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V4L/DVB (13224): pvrusb2: Improve diagnostic info on driver initialization failure
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
d855497e
MI		 3 *
4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21#include <linux/errno.h>
22#include <linux/string.h>
23#include <linux/slab.h>
24#include <linux/firmware.h>
d855497e 25#include <linux/videodev2.h>
32ffa9ae 26#include <media/v4l2-common.h>
75212a02 27#include <media/tuner.h>
d855497e
MI		 28#include "pvrusb2.h"
29#include "pvrusb2-std.h"
30#include "pvrusb2-util.h"
31#include "pvrusb2-hdw.h"
32#include "pvrusb2-i2c-core.h"
d855497e
MI		 33#include "pvrusb2-eeprom.h"
34#include "pvrusb2-hdw-internal.h"
35#include "pvrusb2-encoder.h"
36#include "pvrusb2-debug.h"
8d364363 37#include "pvrusb2-fx2-cmd.h"
5f6dae80 38#include "pvrusb2-wm8775.h"
6f956512 39#include "pvrusb2-video-v4l.h"
634ba268 40#include "pvrusb2-cx2584x-v4l.h"
2a6b627f 41#include "pvrusb2-cs53l32a.h"
76891d65 42#include "pvrusb2-audio.h"
d855497e 43
1bde0289
MI		 44#define TV_MIN_FREQ 55250000L
45#define TV_MAX_FREQ 850000000L
25d8527a 46
83ce57aa
MI		 47/* This defines a minimum interval that the decoder must remain quiet
48 before we are allowed to start it running. */
49#define TIME_MSEC_DECODER_WAIT 50
50
51/* This defines a minimum interval that the encoder must remain quiet
fa98e594
MI		 52 before we are allowed to configure it. I had this originally set to
53 50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
54 things work better when it's set to 100msec. */
55#define TIME_MSEC_ENCODER_WAIT 100
83ce57aa
MI		 56
57/* This defines the minimum interval that the encoder must successfully run
58 before we consider that the encoder has run at least once since its
59 firmware has been loaded. This measurement is in important for cases
60 where we can't do something until we know that the encoder has been run
61 at least once. */
62#define TIME_MSEC_ENCODER_OK 250
63
a0fd1cb1 64static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 65static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e 66
ff699e6b 67static int ctlchg;
ff699e6b 68static int procreload;
d855497e
MI		 69static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
70static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
71static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
ff699e6b 72static int init_pause_msec;
d855497e
MI		 73
74module_param(ctlchg, int, S_IRUGO|S_IWUSR);
75MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
76module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
77MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
d855497e
MI		 78module_param(procreload, int, S_IRUGO|S_IWUSR);
79MODULE_PARM_DESC(procreload,
80 "Attempt init failure recovery with firmware reload");
81module_param_array(tuner, int, NULL, 0444);
82MODULE_PARM_DESC(tuner,"specify installed tuner type");
83module_param_array(video_std, int, NULL, 0444);
84MODULE_PARM_DESC(video_std,"specify initial video standard");
85module_param_array(tolerance, int, NULL, 0444);
86MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
87
6f441ed7
MI		 88/* US Broadcast channel 3 (61.25 MHz), to help with testing */
89static int default_tv_freq = 61250000L;
5a4f5da6
MK		 90/* 104.3 MHz, a usable FM station for my area */
91static int default_radio_freq = 104300000L;
92
93module_param_named(tv_freq, default_tv_freq, int, 0444);
94MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
95module_param_named(radio_freq, default_radio_freq, int, 0444);
96MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
97
d855497e
MI		 98#define PVR2_CTL_WRITE_ENDPOINT 0x01
99#define PVR2_CTL_READ_ENDPOINT 0x81
100
101#define PVR2_GPIO_IN 0x9008
102#define PVR2_GPIO_OUT 0x900c
103#define PVR2_GPIO_DIR 0x9020
104
105#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
106
107#define PVR2_FIRMWARE_ENDPOINT 0x02
108
109/* size of a firmware chunk */
110#define FIRMWARE_CHUNK_SIZE 0x2000
111
edb9dcb8
MI		 112typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
113 struct v4l2_subdev *);
114
115static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
4ecbc28d 116 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
6f956512 117 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
76891d65 118 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
634ba268 119 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
2a6b627f 120 [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
edb9dcb8
MI		 121};
122
e9c64a78
MI		 123static const char *module_names[] = {
124 [PVR2_CLIENT_ID_MSP3400] = "msp3400",
125 [PVR2_CLIENT_ID_CX25840] = "cx25840",
126 [PVR2_CLIENT_ID_SAA7115] = "saa7115",
127 [PVR2_CLIENT_ID_TUNER] = "tuner",
bb65242a 128 [PVR2_CLIENT_ID_DEMOD] = "tuner",
851981a1 129 [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
5f6dae80 130 [PVR2_CLIENT_ID_WM8775] = "wm8775",
e9c64a78
MI		 131};
132
133
134static const unsigned char *module_i2c_addresses[] = {
135 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
bb65242a 136 [PVR2_CLIENT_ID_DEMOD] = "\x43",
1dfe6c77
MI		 137 [PVR2_CLIENT_ID_MSP3400] = "\x40",
138 [PVR2_CLIENT_ID_SAA7115] = "\x21",
ae111f76 139 [PVR2_CLIENT_ID_WM8775] = "\x1b",
0b467014 140 [PVR2_CLIENT_ID_CX25840] = "\x44",
23334a22 141 [PVR2_CLIENT_ID_CS53L32A] = "\x11",
e9c64a78
MI		 142};
143
144
27eab384
MI		 145static const char *ir_scheme_names[] = {
146 [PVR2_IR_SCHEME_NONE] = "none",
147 [PVR2_IR_SCHEME_29XXX] = "29xxx",
148 [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
149 [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
150 [PVR2_IR_SCHEME_ZILOG] = "Zilog",
151};
152
153
b30d2441
MI		 154/* Define the list of additional controls we'll dynamically construct based
155 on query of the cx2341x module. */
156struct pvr2_mpeg_ids {
157 const char *strid;
158 int id;
159};
160static const struct pvr2_mpeg_ids mpeg_ids[] = {
161 {
162 .strid = "audio_layer",
163 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
164 },{
165 .strid = "audio_bitrate",
166 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
167 },{
168 /* Already using audio_mode elsewhere :-( */
169 .strid = "mpeg_audio_mode",
170 .id = V4L2_CID_MPEG_AUDIO_MODE,
171 },{
172 .strid = "mpeg_audio_mode_extension",
173 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
174 },{
175 .strid = "audio_emphasis",
176 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
177 },{
178 .strid = "audio_crc",
179 .id = V4L2_CID_MPEG_AUDIO_CRC,
180 },{
181 .strid = "video_aspect",
182 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
183 },{
184 .strid = "video_b_frames",
185 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
186 },{
187 .strid = "video_gop_size",
188 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
189 },{
190 .strid = "video_gop_closure",
191 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 192 },{
193 .strid = "video_bitrate_mode",
194 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
195 },{
196 .strid = "video_bitrate",
197 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
198 },{
199 .strid = "video_bitrate_peak",
200 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
201 },{
202 .strid = "video_temporal_decimation",
203 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
204 },{
205 .strid = "stream_type",
206 .id = V4L2_CID_MPEG_STREAM_TYPE,
207 },{
208 .strid = "video_spatial_filter_mode",
209 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
210 },{
211 .strid = "video_spatial_filter",
212 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
213 },{
214 .strid = "video_luma_spatial_filter_type",
215 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
216 },{
217 .strid = "video_chroma_spatial_filter_type",
218 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
219 },{
220 .strid = "video_temporal_filter_mode",
221 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
222 },{
223 .strid = "video_temporal_filter",
224 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
225 },{
226 .strid = "video_median_filter_type",
227 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
228 },{
229 .strid = "video_luma_median_filter_top",
230 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
231 },{
232 .strid = "video_luma_median_filter_bottom",
233 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
234 },{
235 .strid = "video_chroma_median_filter_top",
236 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
237 },{
238 .strid = "video_chroma_median_filter_bottom",
239 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
240 }
241};
eca8ebfc 242#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 243
434449f4 244
d855497e 245static const char *control_values_srate[] = {
434449f4
MI		 246 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
247 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
248 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 249};
250
251
d855497e 252
d855497e
MI		 253static const char *control_values_input[] = {
254 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
29bf5b1d 255 [PVR2_CVAL_INPUT_DTV] = "dtv",
d855497e
MI		 256 [PVR2_CVAL_INPUT_RADIO] = "radio",
257 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
258 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
259};
260
261
262static const char *control_values_audiomode[] = {
263 [V4L2_TUNER_MODE_MONO] = "Mono",
264 [V4L2_TUNER_MODE_STEREO] = "Stereo",
265 [V4L2_TUNER_MODE_LANG1] = "Lang1",
266 [V4L2_TUNER_MODE_LANG2] = "Lang2",
267 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
268};
269
270
271static const char *control_values_hsm[] = {
272 [PVR2_CVAL_HSM_FAIL] = "Fail",
273 [PVR2_CVAL_HSM_HIGH] = "High",
274 [PVR2_CVAL_HSM_FULL] = "Full",
275};
276
277
681c7399
MI		 278static const char *pvr2_state_names[] = {
279 [PVR2_STATE_NONE] = "none",
280 [PVR2_STATE_DEAD] = "dead",
281 [PVR2_STATE_COLD] = "cold",
282 [PVR2_STATE_WARM] = "warm",
283 [PVR2_STATE_ERROR] = "error",
284 [PVR2_STATE_READY] = "ready",
285 [PVR2_STATE_RUN] = "run",
d855497e
MI		 286};
287
681c7399 288
694dca2b 289struct pvr2_fx2cmd_descdef {
1c9d10d4
MI		 290 unsigned char id;
291 unsigned char *desc;
292};
293
694dca2b 294static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
1c9d10d4
MI		 295 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
296 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
31335b13 297 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
1c9d10d4
MI		 298 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
299 {FX2CMD_REG_WRITE, "write encoder register"},
300 {FX2CMD_REG_READ, "read encoder register"},
301 {FX2CMD_MEMSEL, "encoder memsel"},
302 {FX2CMD_I2C_WRITE, "i2c write"},
303 {FX2CMD_I2C_READ, "i2c read"},
304 {FX2CMD_GET_USB_SPEED, "get USB speed"},
305 {FX2CMD_STREAMING_ON, "stream on"},
306 {FX2CMD_STREAMING_OFF, "stream off"},
307 {FX2CMD_FWPOST1, "fwpost1"},
308 {FX2CMD_POWER_OFF, "power off"},
309 {FX2CMD_POWER_ON, "power on"},
310 {FX2CMD_DEEP_RESET, "deep reset"},
311 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
312 {FX2CMD_GET_IR_CODE, "get IR code"},
313 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
314 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
315 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
316 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
317 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
318 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
319 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
320};
321
322
1cb03b76 323static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
681c7399
MI		 324static void pvr2_hdw_state_sched(struct pvr2_hdw *);
325static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 326static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399 327static void pvr2_hdw_worker_poll(struct work_struct *work);
681c7399
MI		 328static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
329static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
330static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 331static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 332static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 333static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 334static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
335static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
681c7399
MI		 336static void pvr2_hdw_quiescent_timeout(unsigned long);
337static void pvr2_hdw_encoder_wait_timeout(unsigned long);
d913d630 338static void pvr2_hdw_encoder_run_timeout(unsigned long);
1c9d10d4 339static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
07e337ee
AB		 340static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
341 unsigned int timeout,int probe_fl,
342 void *write_data,unsigned int write_len,
343 void *read_data,unsigned int read_len);
432907f7 344static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
d855497e 345
681c7399
MI		 346
347static void trace_stbit(const char *name,int val)
348{
349 pvr2_trace(PVR2_TRACE_STBITS,
350 "State bit %s <-- %s",
351 name,(val ? "true" : "false"));
352}
353
d855497e
MI		 354static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
355{
356 struct pvr2_hdw *hdw = cptr->hdw;
357 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
358 *vp = hdw->freqTable[hdw->freqProgSlot-1];
359 } else {
360 *vp = 0;
361 }
362 return 0;
363}
364
365static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
366{
367 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 368 unsigned int slotId = hdw->freqProgSlot;
369 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
370 hdw->freqTable[slotId-1] = v;
371 /* Handle side effects correctly - if we're tuned to this
372 slot, then forgot the slot id relation since the stored
373 frequency has been changed. */
374 if (hdw->freqSelector) {
375 if (hdw->freqSlotRadio == slotId) {
376 hdw->freqSlotRadio = 0;
377 }
378 } else {
379 if (hdw->freqSlotTelevision == slotId) {
380 hdw->freqSlotTelevision = 0;
381 }
382 }
d855497e
MI		 383 }
384 return 0;
385}
386
387static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
388{
389 *vp = cptr->hdw->freqProgSlot;
390 return 0;
391}
392
393static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
394{
395 struct pvr2_hdw *hdw = cptr->hdw;
396 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
397 hdw->freqProgSlot = v;
398 }
399 return 0;
400}
401
402static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
403{
1bde0289
MI		 404 struct pvr2_hdw *hdw = cptr->hdw;
405 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 406 return 0;
407}
408
1bde0289 409static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 410{
411 unsigned freq = 0;
412 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 413 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
414 if (slotId > 0) {
415 freq = hdw->freqTable[slotId-1];
416 if (!freq) return 0;
417 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 418 }
1bde0289
MI		 419 if (hdw->freqSelector) {
420 hdw->freqSlotRadio = slotId;
421 } else {
422 hdw->freqSlotTelevision = slotId;
d855497e
MI		 423 }
424 return 0;
425}
426
427static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
428{
1bde0289 429 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 430 return 0;
431}
432
433static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
434{
435 return cptr->hdw->freqDirty != 0;
436}
437
438static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
439{
440 cptr->hdw->freqDirty = 0;
441}
442
443static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
444{
1bde0289 445 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 446 return 0;
447}
448
e784bfb9 449static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
450{
432907f7
MI		 451 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
452 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
453 if (stat != 0) {
432907f7 454 return stat;
e784bfb9 455 }
432907f7 456 *left = cap->bounds.left;
e784bfb9 457 return 0;
458}
459
460static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
461{
432907f7
MI		 462 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
463 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
464 if (stat != 0) {
432907f7
MI		 465 return stat;
466 }
467 *left = cap->bounds.left;
468 if (cap->bounds.width > cptr->hdw->cropw_val) {
432907f7 469 *left += cap->bounds.width - cptr->hdw->cropw_val;
e784bfb9 470 }
471 return 0;
472}
473
474static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
475{
432907f7
MI		 476 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
477 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
478 if (stat != 0) {
432907f7 479 return stat;
e784bfb9 480 }
432907f7 481 *top = cap->bounds.top;
e784bfb9 482 return 0;
483}
484
432907f7 485static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
3ad9fc37 486{
432907f7
MI		 487 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
488 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
489 if (stat != 0) {
432907f7
MI		 490 return stat;
491 }
492 *top = cap->bounds.top;
493 if (cap->bounds.height > cptr->hdw->croph_val) {
432907f7 494 *top += cap->bounds.height - cptr->hdw->croph_val;
3ad9fc37
MI		 495 }
496 return 0;
497}
498
432907f7
MI		 499static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
500{
501 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
502 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
503 if (stat != 0) {
432907f7
MI		 504 return stat;
505 }
506 *val = 0;
507 if (cap->bounds.width > cptr->hdw->cropl_val) {
432907f7
MI		 508 *val = cap->bounds.width - cptr->hdw->cropl_val;
509 }
510 return 0;
511}
512
513static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
514{
515 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
516 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
517 if (stat != 0) {
432907f7
MI		 518 return stat;
519 }
520 *val = 0;
521 if (cap->bounds.height > cptr->hdw->cropt_val) {
432907f7
MI		 522 *val = cap->bounds.height - cptr->hdw->cropt_val;
523 }
524 return 0;
525}
526
527static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
528{
529 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
530 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
531 if (stat != 0) {
432907f7
MI		 532 return stat;
533 }
534 *val = cap->bounds.left;
535 return 0;
536}
537
538static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
539{
540 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
541 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
542 if (stat != 0) {
432907f7
MI		 543 return stat;
544 }
545 *val = cap->bounds.top;
546 return 0;
547}
548
549static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
550{
551 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
552 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
553 if (stat != 0) {
432907f7
MI		 554 return stat;
555 }
556 *val = cap->bounds.width;
557 return 0;
558}
559
560static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
561{
562 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
563 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
564 if (stat != 0) {
432907f7
MI		 565 return stat;
566 }
567 *val = cap->bounds.height;
568 return 0;
569}
570
571static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
572{
573 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
574 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
575 if (stat != 0) {
432907f7
MI		 576 return stat;
577 }
578 *val = cap->defrect.left;
579 return 0;
580}
581
582static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
583{
584 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
585 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
586 if (stat != 0) {
432907f7
MI		 587 return stat;
588 }
589 *val = cap->defrect.top;
590 return 0;
591}
592
593static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
594{
595 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
596 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
597 if (stat != 0) {
432907f7
MI		 598 return stat;
599 }
600 *val = cap->defrect.width;
601 return 0;
602}
603
604static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
605{
606 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
607 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
608 if (stat != 0) {
432907f7
MI		 609 return stat;
610 }
611 *val = cap->defrect.height;
612 return 0;
613}
614
615static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
616{
617 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
618 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
619 if (stat != 0) {
432907f7
MI		 620 return stat;
621 }
622 *val = cap->pixelaspect.numerator;
623 return 0;
624}
625
626static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
627{
628 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
629 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
630 if (stat != 0) {
432907f7
MI		 631 return stat;
632 }
633 *val = cap->pixelaspect.denominator;
634 return 0;
635}
636
637static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
e784bfb9 638{
432907f7
MI		 639 /* Actual maximum depends on the video standard in effect. */
640 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
641 *vp = 480;
e784bfb9 642 } else {
432907f7 643 *vp = 576;
e784bfb9 644 }
645 return 0;
646}
647
3ad9fc37
MI		 648static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
649{
989eb154
MI		 650 /* Actual minimum depends on device digitizer type. */
651 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 652 *vp = 75;
653 } else {
654 *vp = 17;
655 }
656 return 0;
657}
658
1bde0289 659static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 660{
1bde0289
MI		 661 *vp = cptr->hdw->input_val;
662 return 0;
663}
664
29bf5b1d
MI		 665static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
666{
1cb03b76 667 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
29bf5b1d
MI		 668}
669
1bde0289
MI		 670static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
671{
1cb03b76 672 return pvr2_hdw_set_input(cptr->hdw,v);
1bde0289
MI		 673}
674
675static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
676{
677 return cptr->hdw->input_dirty != 0;
678}
679
680static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
681{
682 cptr->hdw->input_dirty = 0;
683}
684
5549f54f 685
25d8527a
PK		 686static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
687{
644afdb9
MI		 688 unsigned long fv;
689 struct pvr2_hdw *hdw = cptr->hdw;
690 if (hdw->tuner_signal_stale) {
a51f5000 691 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 692 }
693 fv = hdw->tuner_signal_info.rangehigh;
694 if (!fv) {
695 /* Safety fallback */
25d8527a 696 *vp = TV_MAX_FREQ;
644afdb9 697 return 0;
25d8527a 698 }
644afdb9
MI		 699 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
700 fv = (fv * 125) / 2;
701 } else {
702 fv = fv * 62500;
703 }
704 *vp = fv;
25d8527a
PK		 705 return 0;
706}
707
708static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
709{
644afdb9
MI		 710 unsigned long fv;
711 struct pvr2_hdw *hdw = cptr->hdw;
712 if (hdw->tuner_signal_stale) {
a51f5000 713 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 714 }
715 fv = hdw->tuner_signal_info.rangelow;
716 if (!fv) {
717 /* Safety fallback */
25d8527a 718 *vp = TV_MIN_FREQ;
644afdb9
MI		 719 return 0;
720 }
721 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
722 fv = (fv * 125) / 2;
723 } else {
724 fv = fv * 62500;
25d8527a 725 }
644afdb9 726 *vp = fv;
25d8527a
PK		 727 return 0;
728}
729
b30d2441
MI		 730static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
731{
732 return cptr->hdw->enc_stale != 0;
733}
734
735static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
736{
737 cptr->hdw->enc_stale = 0;
681c7399 738 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 739}
740
741static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
742{
743 int ret;
744 struct v4l2_ext_controls cs;
745 struct v4l2_ext_control c1;
746 memset(&cs,0,sizeof(cs));
747 memset(&c1,0,sizeof(c1));
748 cs.controls = &c1;
749 cs.count = 1;
750 c1.id = cptr->info->v4l_id;
01f1e44f 751 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 752 VIDIOC_G_EXT_CTRLS);
753 if (ret) return ret;
754 *vp = c1.value;
755 return 0;
756}
757
758static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
759{
760 int ret;
681c7399 761 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 762 struct v4l2_ext_controls cs;
763 struct v4l2_ext_control c1;
764 memset(&cs,0,sizeof(cs));
765 memset(&c1,0,sizeof(c1));
766 cs.controls = &c1;
767 cs.count = 1;
768 c1.id = cptr->info->v4l_id;
769 c1.value = v;
681c7399
MI		 770 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
771 hdw->state_encoder_run, &cs,
b30d2441 772 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 773 if (ret == -EBUSY) {
774 /* Oops. cx2341x is telling us it's not safe to change
775 this control while we're capturing. Make a note of this
776 fact so that the pipeline will be stopped the next time
777 controls are committed. Then go on ahead and store this
778 change anyway. */
779 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
780 0, &cs,
781 VIDIOC_S_EXT_CTRLS);
782 if (!ret) hdw->enc_unsafe_stale = !0;
783 }
b30d2441 784 if (ret) return ret;
681c7399 785 hdw->enc_stale = !0;
b30d2441
MI		 786 return 0;
787}
788
789static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
790{
791 struct v4l2_queryctrl qctrl;
792 struct pvr2_ctl_info *info;
793 qctrl.id = cptr->info->v4l_id;
794 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
795 /* Strip out the const so we can adjust a function pointer. It's
796 OK to do this here because we know this is a dynamically created
797 control, so the underlying storage for the info pointer is (a)
798 private to us, and (b) not in read-only storage. Either we do
799 this or we significantly complicate the underlying control
800 implementation. */
801 info = (struct pvr2_ctl_info *)(cptr->info);
802 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
803 if (info->set_value) {
a0fd1cb1 804 info->set_value = NULL;
b30d2441
MI		 805 }
806 } else {
807 if (!(info->set_value)) {
808 info->set_value = ctrl_cx2341x_set;
809 }
810 }
811 return qctrl.flags;
812}
813
d855497e
MI		 814static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
815{
681c7399
MI		 816 *vp = cptr->hdw->state_pipeline_req;
817 return 0;
818}
819
820static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
821{
822 *vp = cptr->hdw->master_state;
d855497e
MI		 823 return 0;
824}
825
826static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
827{
828 int result = pvr2_hdw_is_hsm(cptr->hdw);
829 *vp = PVR2_CVAL_HSM_FULL;
830 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
831 if (result) *vp = PVR2_CVAL_HSM_HIGH;
832 return 0;
833}
834
835static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
836{
837 *vp = cptr->hdw->std_mask_avail;
838 return 0;
839}
840
841static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
842{
843 struct pvr2_hdw *hdw = cptr->hdw;
844 v4l2_std_id ns;
845 ns = hdw->std_mask_avail;
846 ns = (ns & ~m) | (v & m);
847 if (ns == hdw->std_mask_avail) return 0;
848 hdw->std_mask_avail = ns;
849 pvr2_hdw_internal_set_std_avail(hdw);
850 pvr2_hdw_internal_find_stdenum(hdw);
851 return 0;
852}
853
854static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
855 char *bufPtr,unsigned int bufSize,
856 unsigned int *len)
857{
858 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
859 return 0;
860}
861
862static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
863 const char *bufPtr,unsigned int bufSize,
864 int *mskp,int *valp)
865{
866 int ret;
867 v4l2_std_id id;
868 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
869 if (ret < 0) return ret;
870 if (mskp) *mskp = id;
871 if (valp) *valp = id;
872 return 0;
873}
874
875static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
876{
877 *vp = cptr->hdw->std_mask_cur;
878 return 0;
879}
880
881static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
882{
883 struct pvr2_hdw *hdw = cptr->hdw;
884 v4l2_std_id ns;
885 ns = hdw->std_mask_cur;
886 ns = (ns & ~m) | (v & m);
887 if (ns == hdw->std_mask_cur) return 0;
888 hdw->std_mask_cur = ns;
889 hdw->std_dirty = !0;
890 pvr2_hdw_internal_find_stdenum(hdw);
891 return 0;
892}
893
894static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
895{
896 return cptr->hdw->std_dirty != 0;
897}
898
899static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
900{
901 cptr->hdw->std_dirty = 0;
902}
903
904static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
905{
18103c57 906 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 907 pvr2_hdw_status_poll(hdw);
18103c57
MI		 908 *vp = hdw->tuner_signal_info.signal;
909 return 0;
910}
911
912static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
913{
914 int val = 0;
915 unsigned int subchan;
916 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 917 pvr2_hdw_status_poll(hdw);
18103c57
MI		 918 subchan = hdw->tuner_signal_info.rxsubchans;
919 if (subchan & V4L2_TUNER_SUB_MONO) {
920 val |= (1 << V4L2_TUNER_MODE_MONO);
921 }
922 if (subchan & V4L2_TUNER_SUB_STEREO) {
923 val |= (1 << V4L2_TUNER_MODE_STEREO);
924 }
925 if (subchan & V4L2_TUNER_SUB_LANG1) {
926 val |= (1 << V4L2_TUNER_MODE_LANG1);
927 }
928 if (subchan & V4L2_TUNER_SUB_LANG2) {
929 val |= (1 << V4L2_TUNER_MODE_LANG2);
930 }
931 *vp = val;
d855497e
MI		 932 return 0;
933}
934
d855497e
MI		 935
936static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
937{
938 struct pvr2_hdw *hdw = cptr->hdw;
939 if (v < 0) return -EINVAL;
940 if (v > hdw->std_enum_cnt) return -EINVAL;
941 hdw->std_enum_cur = v;
942 if (!v) return 0;
943 v--;
944 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
945 hdw->std_mask_cur = hdw->std_defs[v].id;
946 hdw->std_dirty = !0;
947 return 0;
948}
949
950
951static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
952{
953 *vp = cptr->hdw->std_enum_cur;
954 return 0;
955}
956
957
958static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
959{
960 return cptr->hdw->std_dirty != 0;
961}
962
963
964static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
965{
966 cptr->hdw->std_dirty = 0;
967}
968
969
970#define DEFINT(vmin,vmax) \
971 .type = pvr2_ctl_int, \
972 .def.type_int.min_value = vmin, \
973 .def.type_int.max_value = vmax
974
975#define DEFENUM(tab) \
976 .type = pvr2_ctl_enum, \
27c7b710 977 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 978 .def.type_enum.value_names = tab
979
33213963
MI		 980#define DEFBOOL \
981 .type = pvr2_ctl_bool
982
d855497e
MI		 983#define DEFMASK(msk,tab) \
984 .type = pvr2_ctl_bitmask, \
985 .def.type_bitmask.valid_bits = msk, \
986 .def.type_bitmask.bit_names = tab
987
988#define DEFREF(vname) \
989 .set_value = ctrl_set_##vname, \
990 .get_value = ctrl_get_##vname, \
991 .is_dirty = ctrl_isdirty_##vname, \
992 .clear_dirty = ctrl_cleardirty_##vname
993
994
995#define VCREATE_FUNCS(vname) \
996static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
997{*vp = cptr->hdw->vname##_val; return 0;} \
998static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
999{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
1000static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
1001{return cptr->hdw->vname##_dirty != 0;} \
1002static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
1003{cptr->hdw->vname##_dirty = 0;}
1004
1005VCREATE_FUNCS(brightness)
1006VCREATE_FUNCS(contrast)
1007VCREATE_FUNCS(saturation)
1008VCREATE_FUNCS(hue)
1009VCREATE_FUNCS(volume)
1010VCREATE_FUNCS(balance)
1011VCREATE_FUNCS(bass)
1012VCREATE_FUNCS(treble)
1013VCREATE_FUNCS(mute)
e784bfb9 1014VCREATE_FUNCS(cropl)
1015VCREATE_FUNCS(cropt)
1016VCREATE_FUNCS(cropw)
1017VCREATE_FUNCS(croph)
c05c0462
MI		 1018VCREATE_FUNCS(audiomode)
1019VCREATE_FUNCS(res_hor)
1020VCREATE_FUNCS(res_ver)
d855497e 1021VCREATE_FUNCS(srate)
d855497e 1022
d855497e
MI		 1023/* Table definition of all controls which can be manipulated */
1024static const struct pvr2_ctl_info control_defs[] = {
1025 {
1026 .v4l_id = V4L2_CID_BRIGHTNESS,
1027 .desc = "Brightness",
1028 .name = "brightness",
1029 .default_value = 128,
1030 DEFREF(brightness),
1031 DEFINT(0,255),
1032 },{
1033 .v4l_id = V4L2_CID_CONTRAST,
1034 .desc = "Contrast",
1035 .name = "contrast",
1036 .default_value = 68,
1037 DEFREF(contrast),
1038 DEFINT(0,127),
1039 },{
1040 .v4l_id = V4L2_CID_SATURATION,
1041 .desc = "Saturation",
1042 .name = "saturation",
1043 .default_value = 64,
1044 DEFREF(saturation),
1045 DEFINT(0,127),
1046 },{
1047 .v4l_id = V4L2_CID_HUE,
1048 .desc = "Hue",
1049 .name = "hue",
1050 .default_value = 0,
1051 DEFREF(hue),
1052 DEFINT(-128,127),
1053 },{
1054 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1055 .desc = "Volume",
1056 .name = "volume",
139eecf9 1057 .default_value = 62000,
d855497e
MI		 1058 DEFREF(volume),
1059 DEFINT(0,65535),
1060 },{
1061 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1062 .desc = "Balance",
1063 .name = "balance",
1064 .default_value = 0,
1065 DEFREF(balance),
1066 DEFINT(-32768,32767),
1067 },{
1068 .v4l_id = V4L2_CID_AUDIO_BASS,
1069 .desc = "Bass",
1070 .name = "bass",
1071 .default_value = 0,
1072 DEFREF(bass),
1073 DEFINT(-32768,32767),
1074 },{
1075 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1076 .desc = "Treble",
1077 .name = "treble",
1078 .default_value = 0,
1079 DEFREF(treble),
1080 DEFINT(-32768,32767),
1081 },{
1082 .v4l_id = V4L2_CID_AUDIO_MUTE,
1083 .desc = "Mute",
1084 .name = "mute",
1085 .default_value = 0,
1086 DEFREF(mute),
33213963 1087 DEFBOOL,
e784bfb9 1088 }, {
432907f7 1089 .desc = "Capture crop left margin",
e784bfb9 1090 .name = "crop_left",
1091 .internal_id = PVR2_CID_CROPL,
1092 .default_value = 0,
1093 DEFREF(cropl),
1094 DEFINT(-129, 340),
1095 .get_min_value = ctrl_cropl_min_get,
1096 .get_max_value = ctrl_cropl_max_get,
432907f7 1097 .get_def_value = ctrl_get_cropcapdl,
e784bfb9 1098 }, {
432907f7 1099 .desc = "Capture crop top margin",
e784bfb9 1100 .name = "crop_top",
1101 .internal_id = PVR2_CID_CROPT,
1102 .default_value = 0,
1103 DEFREF(cropt),
1104 DEFINT(-35, 544),
1105 .get_min_value = ctrl_cropt_min_get,
1106 .get_max_value = ctrl_cropt_max_get,
432907f7 1107 .get_def_value = ctrl_get_cropcapdt,
e784bfb9 1108 }, {
432907f7 1109 .desc = "Capture crop width",
e784bfb9 1110 .name = "crop_width",
1111 .internal_id = PVR2_CID_CROPW,
1112 .default_value = 720,
1113 DEFREF(cropw),
432907f7
MI		 1114 .get_max_value = ctrl_cropw_max_get,
1115 .get_def_value = ctrl_get_cropcapdw,
e784bfb9 1116 }, {
432907f7 1117 .desc = "Capture crop height",
e784bfb9 1118 .name = "crop_height",
1119 .internal_id = PVR2_CID_CROPH,
1120 .default_value = 480,
1121 DEFREF(croph),
432907f7
MI		 1122 .get_max_value = ctrl_croph_max_get,
1123 .get_def_value = ctrl_get_cropcapdh,
1124 }, {
1125 .desc = "Capture capability pixel aspect numerator",
1126 .name = "cropcap_pixel_numerator",
1127 .internal_id = PVR2_CID_CROPCAPPAN,
1128 .get_value = ctrl_get_cropcappan,
1129 }, {
1130 .desc = "Capture capability pixel aspect denominator",
1131 .name = "cropcap_pixel_denominator",
1132 .internal_id = PVR2_CID_CROPCAPPAD,
1133 .get_value = ctrl_get_cropcappad,
1134 }, {
1135 .desc = "Capture capability bounds top",
1136 .name = "cropcap_bounds_top",
1137 .internal_id = PVR2_CID_CROPCAPBT,
1138 .get_value = ctrl_get_cropcapbt,
1139 }, {
1140 .desc = "Capture capability bounds left",
1141 .name = "cropcap_bounds_left",
1142 .internal_id = PVR2_CID_CROPCAPBL,
1143 .get_value = ctrl_get_cropcapbl,
1144 }, {
1145 .desc = "Capture capability bounds width",
1146 .name = "cropcap_bounds_width",
1147 .internal_id = PVR2_CID_CROPCAPBW,
1148 .get_value = ctrl_get_cropcapbw,
1149 }, {
1150 .desc = "Capture capability bounds height",
1151 .name = "cropcap_bounds_height",
1152 .internal_id = PVR2_CID_CROPCAPBH,
1153 .get_value = ctrl_get_cropcapbh,
c05c0462
MI		 1154 },{
1155 .desc = "Video Source",
1156 .name = "input",
1157 .internal_id = PVR2_CID_INPUT,
1158 .default_value = PVR2_CVAL_INPUT_TV,
29bf5b1d 1159 .check_value = ctrl_check_input,
c05c0462
MI		 1160 DEFREF(input),
1161 DEFENUM(control_values_input),
1162 },{
1163 .desc = "Audio Mode",
1164 .name = "audio_mode",
1165 .internal_id = PVR2_CID_AUDIOMODE,
1166 .default_value = V4L2_TUNER_MODE_STEREO,
1167 DEFREF(audiomode),
1168 DEFENUM(control_values_audiomode),
1169 },{
1170 .desc = "Horizontal capture resolution",
1171 .name = "resolution_hor",
1172 .internal_id = PVR2_CID_HRES,
1173 .default_value = 720,
1174 DEFREF(res_hor),
3ad9fc37 1175 DEFINT(19,720),
c05c0462
MI		 1176 },{
1177 .desc = "Vertical capture resolution",
1178 .name = "resolution_ver",
1179 .internal_id = PVR2_CID_VRES,
1180 .default_value = 480,
1181 DEFREF(res_ver),
3ad9fc37
MI		 1182 DEFINT(17,576),
1183 /* Hook in check for video standard and adjust maximum
1184 depending on the standard. */
1185 .get_max_value = ctrl_vres_max_get,
1186 .get_min_value = ctrl_vres_min_get,
d855497e 1187 },{
b30d2441 1188 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 1189 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1190 .desc = "Audio Sampling Frequency",
d855497e 1191 .name = "srate",
d855497e
MI		 1192 DEFREF(srate),
1193 DEFENUM(control_values_srate),
d855497e
MI		 1194 },{
1195 .desc = "Tuner Frequency (Hz)",
1196 .name = "frequency",
1197 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 1198 .default_value = 0,
d855497e
MI		 1199 .set_value = ctrl_freq_set,
1200 .get_value = ctrl_freq_get,
1201 .is_dirty = ctrl_freq_is_dirty,
1202 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 1203 DEFINT(0,0),
25d8527a
PK		 1204 /* Hook in check for input value (tv/radio) and adjust
1205 max/min values accordingly */
1206 .get_max_value = ctrl_freq_max_get,
1207 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1208 },{
1209 .desc = "Channel",
1210 .name = "channel",
1211 .set_value = ctrl_channel_set,
1212 .get_value = ctrl_channel_get,
1213 DEFINT(0,FREQTABLE_SIZE),
1214 },{
1215 .desc = "Channel Program Frequency",
1216 .name = "freq_table_value",
1217 .set_value = ctrl_channelfreq_set,
1218 .get_value = ctrl_channelfreq_get,
644afdb9 1219 DEFINT(0,0),
1bde0289
MI		 1220 /* Hook in check for input value (tv/radio) and adjust
1221 max/min values accordingly */
1bde0289
MI		 1222 .get_max_value = ctrl_freq_max_get,
1223 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1224 },{
1225 .desc = "Channel Program ID",
1226 .name = "freq_table_channel",
1227 .set_value = ctrl_channelprog_set,
1228 .get_value = ctrl_channelprog_get,
1229 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 1230 },{
1231 .desc = "Streaming Enabled",
1232 .name = "streaming_enabled",
1233 .get_value = ctrl_streamingenabled_get,
33213963 1234 DEFBOOL,
d855497e
MI		 1235 },{
1236 .desc = "USB Speed",
1237 .name = "usb_speed",
1238 .get_value = ctrl_hsm_get,
1239 DEFENUM(control_values_hsm),
681c7399
MI		 1240 },{
1241 .desc = "Master State",
1242 .name = "master_state",
1243 .get_value = ctrl_masterstate_get,
1244 DEFENUM(pvr2_state_names),
d855497e
MI		 1245 },{
1246 .desc = "Signal Present",
1247 .name = "signal_present",
1248 .get_value = ctrl_signal_get,
18103c57
MI		 1249 DEFINT(0,65535),
1250 },{
1251 .desc = "Audio Modes Present",
1252 .name = "audio_modes_present",
1253 .get_value = ctrl_audio_modes_present_get,
1254 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1255 v4l. Nothing outside of this module cares about this,
1256 but I reuse it in order to also reuse the
1257 control_values_audiomode string table. */
1258 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1259 (1 << V4L2_TUNER_MODE_STEREO)|
1260 (1 << V4L2_TUNER_MODE_LANG1)|
1261 (1 << V4L2_TUNER_MODE_LANG2)),
1262 control_values_audiomode),
d855497e
MI		 1263 },{
1264 .desc = "Video Standards Available Mask",
1265 .name = "video_standard_mask_available",
1266 .internal_id = PVR2_CID_STDAVAIL,
1267 .skip_init = !0,
1268 .get_value = ctrl_stdavail_get,
1269 .set_value = ctrl_stdavail_set,
1270 .val_to_sym = ctrl_std_val_to_sym,
1271 .sym_to_val = ctrl_std_sym_to_val,
1272 .type = pvr2_ctl_bitmask,
1273 },{
1274 .desc = "Video Standards In Use Mask",
1275 .name = "video_standard_mask_active",
1276 .internal_id = PVR2_CID_STDCUR,
1277 .skip_init = !0,
1278 .get_value = ctrl_stdcur_get,
1279 .set_value = ctrl_stdcur_set,
1280 .is_dirty = ctrl_stdcur_is_dirty,
1281 .clear_dirty = ctrl_stdcur_clear_dirty,
1282 .val_to_sym = ctrl_std_val_to_sym,
1283 .sym_to_val = ctrl_std_sym_to_val,
1284 .type = pvr2_ctl_bitmask,
d855497e
MI		 1285 },{
1286 .desc = "Video Standard Name",
1287 .name = "video_standard",
1288 .internal_id = PVR2_CID_STDENUM,
1289 .skip_init = !0,
1290 .get_value = ctrl_stdenumcur_get,
1291 .set_value = ctrl_stdenumcur_set,
1292 .is_dirty = ctrl_stdenumcur_is_dirty,
1293 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1294 .type = pvr2_ctl_enum,
1295 }
1296};
1297
eca8ebfc 1298#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 1299
1300
1301const char *pvr2_config_get_name(enum pvr2_config cfg)
1302{
1303 switch (cfg) {
1304 case pvr2_config_empty: return "empty";
1305 case pvr2_config_mpeg: return "mpeg";
1306 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 1307 case pvr2_config_pcm: return "pcm";
1308 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 1309 }
1310 return "<unknown>";
1311}
1312
1313
1314struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1315{
1316 return hdw->usb_dev;
1317}
1318
1319
1320unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1321{
1322 return hdw->serial_number;
1323}
1324
31a18547
MI		 1325
1326const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1327{
1328 return hdw->bus_info;
1329}
1330
1331
13a88797
MI		 1332const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1333{
1334 return hdw->identifier;
1335}
1336
1337
1bde0289
MI		 1338unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1339{
1340 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1341}
1342
1343/* Set the currently tuned frequency and account for all possible
1344 driver-core side effects of this action. */
f55a8712 1345static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1bde0289 1346{
7c74e57e 1347 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 1348 if (hdw->freqSelector) {
1349 /* Swing over to radio frequency selection */
1350 hdw->freqSelector = 0;
1351 hdw->freqDirty = !0;
1352 }
1bde0289
MI		 1353 if (hdw->freqValRadio != val) {
1354 hdw->freqValRadio = val;
1355 hdw->freqSlotRadio = 0;
7c74e57e 1356 hdw->freqDirty = !0;
1bde0289 1357 }
7c74e57e 1358 } else {
1bde0289
MI		 1359 if (!(hdw->freqSelector)) {
1360 /* Swing over to television frequency selection */
1361 hdw->freqSelector = 1;
1362 hdw->freqDirty = !0;
1363 }
1bde0289
MI		 1364 if (hdw->freqValTelevision != val) {
1365 hdw->freqValTelevision = val;
1366 hdw->freqSlotTelevision = 0;
7c74e57e 1367 hdw->freqDirty = !0;
1bde0289 1368 }
1bde0289
MI		 1369 }
1370}
1371
d855497e
MI		 1372int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1373{
1374 return hdw->unit_number;
1375}
1376
1377
1378/* Attempt to locate one of the given set of files. Messages are logged
1379 appropriate to what has been found. The return value will be 0 or
1380 greater on success (it will be the index of the file name found) and
1381 fw_entry will be filled in. Otherwise a negative error is returned on
1382 failure. If the return value is -ENOENT then no viable firmware file
1383 could be located. */
1384static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1385 const struct firmware **fw_entry,
1386 const char *fwtypename,
1387 unsigned int fwcount,
1388 const char *fwnames[])
1389{
1390 unsigned int idx;
1391 int ret = -EINVAL;
1392 for (idx = 0; idx < fwcount; idx++) {
1393 ret = request_firmware(fw_entry,
1394 fwnames[idx],
1395 &hdw->usb_dev->dev);
1396 if (!ret) {
1397 trace_firmware("Located %s firmware: %s;"
1398 " uploading...",
1399 fwtypename,
1400 fwnames[idx]);
1401 return idx;
1402 }
1403 if (ret == -ENOENT) continue;
1404 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1405 "request_firmware fatal error with code=%d",ret);
1406 return ret;
1407 }
1408 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1409 "***WARNING***"
1410 " Device %s firmware"
1411 " seems to be missing.",
1412 fwtypename);
1413 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1414 "Did you install the pvrusb2 firmware files"
1415 " in their proper location?");
1416 if (fwcount == 1) {
1417 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1418 "request_firmware unable to locate %s file %s",
1419 fwtypename,fwnames[0]);
1420 } else {
1421 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1422 "request_firmware unable to locate"
1423 " one of the following %s files:",
1424 fwtypename);
1425 for (idx = 0; idx < fwcount; idx++) {
1426 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1427 "request_firmware: Failed to find %s",
1428 fwnames[idx]);
1429 }
1430 }
1431 return ret;
1432}
1433
1434
1435/*
1436 * pvr2_upload_firmware1().
1437 *
1438 * Send the 8051 firmware to the device. After the upload, arrange for
1439 * device to re-enumerate.
1440 *
1441 * NOTE : the pointer to the firmware data given by request_firmware()
1442 * is not suitable for an usb transaction.
1443 *
1444 */
07e337ee 1445static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1446{
a0fd1cb1 1447 const struct firmware *fw_entry = NULL;
d855497e
MI		 1448 void *fw_ptr;
1449 unsigned int pipe;
1450 int ret;
1451 u16 address;
1d643a37 1452
989eb154 1453 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1454 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1455 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1456 "Connected device type defines"
1457 " no firmware to upload; ignoring firmware");
1458 return -ENOTTY;
1d643a37
MI		 1459 }
1460
d855497e
MI		 1461 hdw->fw1_state = FW1_STATE_FAILED; // default result
1462
1463 trace_firmware("pvr2_upload_firmware1");
1464
1465 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1466 hdw->hdw_desc->fx2_firmware.cnt,
1467 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1468 if (ret < 0) {
1469 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1470 return ret;
1471 }
1472
d855497e
MI		 1473 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1474
1475 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1476
1477 if (fw_entry->size != 0x2000){
1478 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1479 release_firmware(fw_entry);
1480 return -ENOMEM;
1481 }
1482
1483 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1484 if (fw_ptr == NULL){
1485 release_firmware(fw_entry);
1486 return -ENOMEM;
1487 }
1488
1489 /* We have to hold the CPU during firmware upload. */
1490 pvr2_hdw_cpureset_assert(hdw,1);
1491
1492 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1493 chunk. */
1494
1495 ret = 0;
1496 for(address = 0; address < fw_entry->size; address += 0x800) {
1497 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1498 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1499 0, fw_ptr, 0x800, HZ);
1500 }
1501
1502 trace_firmware("Upload done, releasing device's CPU");
1503
1504 /* Now release the CPU. It will disconnect and reconnect later. */
1505 pvr2_hdw_cpureset_assert(hdw,0);
1506
1507 kfree(fw_ptr);
1508 release_firmware(fw_entry);
1509
1510 trace_firmware("Upload done (%d bytes sent)",ret);
1511
1512 /* We should have written 8192 bytes */
1513 if (ret == 8192) {
1514 hdw->fw1_state = FW1_STATE_RELOAD;
1515 return 0;
1516 }
1517
1518 return -EIO;
1519}
1520
1521
1522/*
1523 * pvr2_upload_firmware2()
1524 *
1525 * This uploads encoder firmware on endpoint 2.
1526 *
1527 */
1528
1529int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1530{
a0fd1cb1 1531 const struct firmware *fw_entry = NULL;
d855497e 1532 void *fw_ptr;
90060d32 1533 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1534 int actual_length;
1535 int ret = 0;
1536 int fwidx;
1537 static const char *fw_files[] = {
1538 CX2341X_FIRM_ENC_FILENAME,
1539 };
1540
989eb154 1541 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1542 return 0;
1543 }
1544
d855497e
MI		 1545 trace_firmware("pvr2_upload_firmware2");
1546
1547 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1548 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1549 if (ret < 0) return ret;
1550 fwidx = ret;
1551 ret = 0;
b30d2441
MI		 1552 /* Since we're about to completely reinitialize the encoder,
1553 invalidate our cached copy of its configuration state. Next
1554 time we configure the encoder, then we'll fully configure it. */
1555 hdw->enc_cur_valid = 0;
d855497e 1556
d913d630
MI		 1557 /* Encoder is about to be reset so note that as far as we're
1558 concerned now, the encoder has never been run. */
1559 del_timer_sync(&hdw->encoder_run_timer);
1560 if (hdw->state_encoder_runok) {
1561 hdw->state_encoder_runok = 0;
1562 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1563 }
1564
d855497e
MI		 1565 /* First prepare firmware loading */
1566 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1567 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1568 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1569 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1570 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1571 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1572 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1573 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1574 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1575 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1576 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1577 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1578 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1579 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1580 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1581 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1c9d10d4
MI		 1582 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1583 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1584
1585 if (ret) {
1586 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1587 "firmware2 upload prep failed, ret=%d",ret);
1588 release_firmware(fw_entry);
21684ba9 1589 goto done;
d855497e
MI		 1590 }
1591
1592 /* Now send firmware */
1593
1594 fw_len = fw_entry->size;
1595
90060d32 1596 if (fw_len % sizeof(u32)) {
d855497e
MI		 1597 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1598 "size of %s firmware"
48dc30a1 1599 " must be a multiple of %zu bytes",
90060d32 1600 fw_files[fwidx],sizeof(u32));
d855497e 1601 release_firmware(fw_entry);
21684ba9
MI		 1602 ret = -EINVAL;
1603 goto done;
d855497e
MI		 1604 }
1605
1606 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1607 if (fw_ptr == NULL){
1608 release_firmware(fw_entry);
1609 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1610 "failed to allocate memory for firmware2 upload");
21684ba9
MI		 1611 ret = -ENOMEM;
1612 goto done;
d855497e
MI		 1613 }
1614
1615 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1616
90060d32
MI		 1617 fw_done = 0;
1618 for (fw_done = 0; fw_done < fw_len;) {
1619 bcnt = fw_len - fw_done;
1620 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1621 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1622 /* Usbsnoop log shows that we must swap bytes... */
5f33df14
MI		 1623 /* Some background info: The data being swapped here is a
1624 firmware image destined for the mpeg encoder chip that
1625 lives at the other end of a USB endpoint. The encoder
1626 chip always talks in 32 bit chunks and its storage is
1627 organized into 32 bit words. However from the file
1628 system to the encoder chip everything is purely a byte
1629 stream. The firmware file's contents are always 32 bit
1630 swapped from what the encoder expects. Thus the need
1631 always exists to swap the bytes regardless of the endian
1632 type of the host processor and therefore swab32() makes
1633 the most sense. */
90060d32 1634 for (icnt = 0; icnt < bcnt/4 ; icnt++)
513edce6 1635 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
90060d32
MI		 1636
1637 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1638 &actual_length, HZ);
90060d32
MI		 1639 ret |= (actual_length != bcnt);
1640 if (ret) break;
1641 fw_done += bcnt;
d855497e
MI		 1642 }
1643
1644 trace_firmware("upload of %s : %i / %i ",
1645 fw_files[fwidx],fw_done,fw_len);
1646
1647 kfree(fw_ptr);
1648 release_firmware(fw_entry);
1649
1650 if (ret) {
1651 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1652 "firmware2 upload transfer failure");
21684ba9 1653 goto done;
d855497e
MI		 1654 }
1655
1656 /* Finish upload */
1657
1658 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1659 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1c9d10d4 1660 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1661
1662 if (ret) {
1663 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1664 "firmware2 upload post-proc failure");
d855497e 1665 }
21684ba9
MI		 1666
1667 done:
1df59f0b
MI		 1668 if (hdw->hdw_desc->signal_routing_scheme ==
1669 PVR2_ROUTING_SCHEME_GOTVIEW) {
1670 /* Ensure that GPIO 11 is set to output for GOTVIEW
1671 hardware. */
1672 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1673 }
d855497e
MI		 1674 return ret;
1675}
1676
1677
681c7399
MI		 1678static const char *pvr2_get_state_name(unsigned int st)
1679{
1680 if (st < ARRAY_SIZE(pvr2_state_names)) {
1681 return pvr2_state_names[st];
d855497e 1682 }
681c7399 1683 return "???";
d855497e
MI		 1684}
1685
681c7399 1686static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1687{
af78e16b
MI		 1688 /* Even though we really only care about the video decoder chip at
1689 this point, we'll broadcast stream on/off to all sub-devices
1690 anyway, just in case somebody else wants to hear the
1691 command... */
e260508d
MI		 1692 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1693 (enablefl ? "on" : "off"));
af78e16b
MI		 1694 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1695 if (hdw->decoder_client_id) {
1696 /* We get here if the encoder has been noticed. Otherwise
1697 we'll issue a warning to the user (which should
1698 normally never happen). */
1699 return 0;
1700 }
1701 if (!hdw->flag_decoder_missed) {
1702 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1703 "WARNING: No decoder present");
1704 hdw->flag_decoder_missed = !0;
1705 trace_stbit("flag_decoder_missed",
1706 hdw->flag_decoder_missed);
1707 }
1708 return -EIO;
d855497e
MI		 1709}
1710
1711
681c7399 1712int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1713{
681c7399 1714 return hdw->master_state;
d855497e
MI		 1715}
1716
1717
681c7399 1718static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1719{
681c7399
MI		 1720 if (!hdw->flag_tripped) return 0;
1721 hdw->flag_tripped = 0;
1722 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1723 "Clearing driver error statuss");
1724 return !0;
d855497e
MI		 1725}
1726
1727
681c7399 1728int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1729{
681c7399 1730 int fl;
d855497e 1731 LOCK_TAKE(hdw->big_lock); do {
681c7399 1732 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1733 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1734 if (fl) pvr2_hdw_state_sched(hdw);
1735 return 0;
d855497e
MI		 1736}
1737
1738
d855497e
MI		 1739
1740
1741int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1742{
681c7399 1743 return hdw->state_pipeline_req != 0;
d855497e
MI		 1744}
1745
1746
1747int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1748{
681c7399 1749 int ret,st;
d855497e 1750 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1751 pvr2_hdw_untrip_unlocked(hdw);
1752 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1753 hdw->state_pipeline_req = enable_flag != 0;
1754 pvr2_trace(PVR2_TRACE_START_STOP,
1755 "/*--TRACE_STREAM--*/ %s",
1756 enable_flag ? "enable" : "disable");
1757 }
1758 pvr2_hdw_state_sched(hdw);
d855497e 1759 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1760 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1761 if (enable_flag) {
1762 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1763 if (st != PVR2_STATE_READY) return -EIO;
1764 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1765 }
1766 }
d855497e
MI		 1767 return 0;
1768}
1769
1770
1771int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1772{
681c7399 1773 int fl;
d855497e 1774 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1775 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1776 hdw->desired_stream_type = config;
1777 hdw->state_pipeline_config = 0;
1778 trace_stbit("state_pipeline_config",
1779 hdw->state_pipeline_config);
1780 pvr2_hdw_state_sched(hdw);
1781 }
d855497e 1782 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1783 if (fl) return 0;
1784 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1785}
1786
1787
1788static int get_default_tuner_type(struct pvr2_hdw *hdw)
1789{
1790 int unit_number = hdw->unit_number;
1791 int tp = -1;
1792 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1793 tp = tuner[unit_number];
1794 }
1795 if (tp < 0) return -EINVAL;
1796 hdw->tuner_type = tp;
aaf7884d 1797 hdw->tuner_updated = !0;
d855497e
MI		 1798 return 0;
1799}
1800
1801
1802static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1803{
1804 int unit_number = hdw->unit_number;
1805 int tp = 0;
1806 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1807 tp = video_std[unit_number];
6a540254 1808 if (tp) return tp;
d855497e 1809 }
6a540254 1810 return 0;
d855497e
MI		 1811}
1812
1813
1814static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1815{
1816 int unit_number = hdw->unit_number;
1817 int tp = 0;
1818 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1819 tp = tolerance[unit_number];
1820 }
1821 return tp;
1822}
1823
1824
1825static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1826{
1827 /* Try a harmless request to fetch the eeprom's address over
1828 endpoint 1. See what happens. Only the full FX2 image can
1829 respond to this. If this probe fails then likely the FX2
1830 firmware needs be loaded. */
1831 int result;
1832 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1833 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1834 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1835 hdw->cmd_buffer,1,
1836 hdw->cmd_buffer,1);
1837 if (result < 0) break;
1838 } while(0); LOCK_GIVE(hdw->ctl_lock);
1839 if (result) {
1840 pvr2_trace(PVR2_TRACE_INIT,
1841 "Probe of device endpoint 1 result status %d",
1842 result);
1843 } else {
1844 pvr2_trace(PVR2_TRACE_INIT,
1845 "Probe of device endpoint 1 succeeded");
1846 }
1847 return result == 0;
1848}
1849
9f66d4ea
MI		 1850struct pvr2_std_hack {
1851 v4l2_std_id pat; /* Pattern to match */
1852 v4l2_std_id msk; /* Which bits we care about */
1853 v4l2_std_id std; /* What additional standards or default to set */
1854};
1855
1856/* This data structure labels specific combinations of standards from
1857 tveeprom that we'll try to recognize. If we recognize one, then assume
1858 a specified default standard to use. This is here because tveeprom only
1859 tells us about available standards not the intended default standard (if
1860 any) for the device in question. We guess the default based on what has
1861 been reported as available. Note that this is only for guessing a
1862 default - which can always be overridden explicitly - and if the user
1863 has otherwise named a default then that default will always be used in
1864 place of this table. */
ebff0330 1865static const struct pvr2_std_hack std_eeprom_maps[] = {
9f66d4ea
MI		 1866 { /* PAL(B/G) */
1867 .pat = V4L2_STD_B|V4L2_STD_GH,
1868 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1869 },
1870 { /* NTSC(M) */
1871 .pat = V4L2_STD_MN,
1872 .std = V4L2_STD_NTSC_M,
1873 },
1874 { /* PAL(I) */
1875 .pat = V4L2_STD_PAL_I,
1876 .std = V4L2_STD_PAL_I,
1877 },
1878 { /* SECAM(L/L') */
1879 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1880 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1881 },
1882 { /* PAL(D/D1/K) */
1883 .pat = V4L2_STD_DK,
ea2562d9 1884 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
9f66d4ea
MI		 1885 },
1886};
1887
d855497e
MI		 1888static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1889{
1890 char buf[40];
1891 unsigned int bcnt;
3d290bdb 1892 v4l2_std_id std1,std2,std3;
d855497e
MI		 1893
1894 std1 = get_default_standard(hdw);
3d290bdb 1895 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
d855497e
MI		 1896
1897 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1898 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1899 "Supported video standard(s) reported available"
1900 " in hardware: %.*s",
d855497e
MI		 1901 bcnt,buf);
1902
1903 hdw->std_mask_avail = hdw->std_mask_eeprom;
1904
3d290bdb 1905 std2 = (std1|std3) & ~hdw->std_mask_avail;
d855497e
MI		 1906 if (std2) {
1907 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1908 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1909 "Expanding supported video standards"
1910 " to include: %.*s",
1911 bcnt,buf);
1912 hdw->std_mask_avail |= std2;
1913 }
1914
1915 pvr2_hdw_internal_set_std_avail(hdw);
1916
1917 if (std1) {
1918 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1919 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1920 "Initial video standard forced to %.*s",
1921 bcnt,buf);
1922 hdw->std_mask_cur = std1;
1923 hdw->std_dirty = !0;
1924 pvr2_hdw_internal_find_stdenum(hdw);
1925 return;
1926 }
3d290bdb
MI		 1927 if (std3) {
1928 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1929 pvr2_trace(PVR2_TRACE_STD,
1930 "Initial video standard"
1931 " (determined by device type): %.*s",bcnt,buf);
1932 hdw->std_mask_cur = std3;
1933 hdw->std_dirty = !0;
1934 pvr2_hdw_internal_find_stdenum(hdw);
1935 return;
1936 }
d855497e 1937
9f66d4ea
MI		 1938 {
1939 unsigned int idx;
1940 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1941 if (std_eeprom_maps[idx].msk ?
1942 ((std_eeprom_maps[idx].pat ^
1943 hdw->std_mask_eeprom) &
1944 std_eeprom_maps[idx].msk) :
1945 (std_eeprom_maps[idx].pat !=
1946 hdw->std_mask_eeprom)) continue;
1947 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1948 std_eeprom_maps[idx].std);
56585386 1949 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1950 "Initial video standard guessed as %.*s",
1951 bcnt,buf);
1952 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1953 hdw->std_dirty = !0;
1954 pvr2_hdw_internal_find_stdenum(hdw);
1955 return;
1956 }
1957 }
1958
d855497e
MI		 1959 if (hdw->std_enum_cnt > 1) {
1960 // Autoselect the first listed standard
1961 hdw->std_enum_cur = 1;
1962 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1963 hdw->std_dirty = !0;
56585386 1964 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1965 "Initial video standard auto-selected to %s",
1966 hdw->std_defs[hdw->std_enum_cur-1].name);
1967 return;
1968 }
1969
0885ba1d 1970 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1971 "Unable to select a viable initial video standard");
1972}
1973
1974
e9c64a78
MI		 1975static unsigned int pvr2_copy_i2c_addr_list(
1976 unsigned short *dst, const unsigned char *src,
1977 unsigned int dst_max)
1978{
3ab8d295 1979 unsigned int cnt = 0;
e9c64a78
MI		 1980 if (!src) return 0;
1981 while (src[cnt] && (cnt + 1) < dst_max) {
1982 dst[cnt] = src[cnt];
1983 cnt++;
1984 }
1985 dst[cnt] = I2C_CLIENT_END;
1986 return cnt;
1987}
1988
1989
e17d787c
MI		 1990static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
1991{
1992 /*
1993 Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
1994 for cx25840 causes that module to correctly set up its video
1995 scaling. This is really a problem in the cx25840 module itself,
1996 but we work around it here. The problem has not been seen in
1997 ivtv because there VBI is supported and set up. We don't do VBI
1998 here (at least not yet) and thus we never attempted to even set
1999 it up.
2000 */
2001 struct v4l2_format fmt;
2002 if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
2003 /* We're not using a cx25840 so don't enable the hack */
2004 return;
2005 }
2006
2007 pvr2_trace(PVR2_TRACE_INIT,
2008 "Module ID %u:"
2009 " Executing cx25840 VBI hack",
2010 hdw->decoder_client_id);
2011 memset(&fmt, 0, sizeof(fmt));
2012 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2013 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
2014 video, s_fmt, &fmt);
2015}
2016
2017
1ab5e74f
MI		 2018static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
2019 const struct pvr2_device_client_desc *cd)
e9c64a78
MI		 2020{
2021 const char *fname;
2022 unsigned char mid;
2023 struct v4l2_subdev *sd;
2024 unsigned int i2ccnt;
2025 const unsigned char *p;
2026 /* Arbitrary count - max # i2c addresses we will probe */
2027 unsigned short i2caddr[25];
2028
2029 mid = cd->module_id;
2030 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2031 if (!fname) {
2032 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
27108147
MI		 2033 "Module ID %u for device %s has no name?"
2034 " The driver might have a configuration problem.",
e9c64a78
MI		 2035 mid,
2036 hdw->hdw_desc->description);
1ab5e74f 2037 return -EINVAL;
e9c64a78 2038 }
bd14d4f8
MI		 2039 pvr2_trace(PVR2_TRACE_INIT,
2040 "Module ID %u (%s) for device %s being loaded...",
2041 mid, fname,
2042 hdw->hdw_desc->description);
e9c64a78
MI		 2043
2044 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2045 ARRAY_SIZE(i2caddr));
2046 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2047 module_i2c_addresses[mid] : NULL) != NULL)) {
2048 /* Second chance: Try default i2c address list */
2049 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2050 ARRAY_SIZE(i2caddr));
bd14d4f8
MI		 2051 if (i2ccnt) {
2052 pvr2_trace(PVR2_TRACE_INIT,
2053 "Module ID %u:"
2054 " Using default i2c address list",
2055 mid);
2056 }
e9c64a78
MI		 2057 }
2058
2059 if (!i2ccnt) {
2060 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f 2061 "Module ID %u (%s) for device %s:"
27108147
MI		 2062 " No i2c addresses."
2063 " The driver might have a configuration problem.",
1ab5e74f
MI		 2064 mid, fname, hdw->hdw_desc->description);
2065 return -EINVAL;
e9c64a78
MI		 2066 }
2067
53dacb15
HV		 2068 /* Note how the 2nd and 3rd arguments are the same for
2069 * v4l2_i2c_new_subdev(). Why?
e9c64a78
MI		 2070 * Well the 2nd argument is the module name to load, while the 3rd
2071 * argument is documented in the framework as being the "chipid" -
2072 * and every other place where I can find examples of this, the
2073 * "chipid" appears to just be the module name again. So here we
2074 * just do the same thing. */
2075 if (i2ccnt == 1) {
bd14d4f8
MI		 2076 pvr2_trace(PVR2_TRACE_INIT,
2077 "Module ID %u:"
2078 " Setting up with specified i2c address 0x%x",
2079 mid, i2caddr[0]);
e6574f2f 2080 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
e9c64a78 2081 fname, fname,
53dacb15 2082 i2caddr[0], NULL);
e9c64a78 2083 } else {
bd14d4f8
MI		 2084 pvr2_trace(PVR2_TRACE_INIT,
2085 "Module ID %u:"
2086 " Setting up with address probe list",
2087 mid);
53dacb15 2088 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
e9c64a78 2089 fname, fname,
53dacb15 2090 0, i2caddr);
e9c64a78
MI		 2091 }
2092
446dfdc6
MI		 2093 if (!sd) {
2094 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
27108147
MI		 2095 "Module ID %u (%s) for device %s failed to load."
2096 " Possible missing sub-device kernel module or"
2097 " initialization failure within module.",
1ab5e74f
MI		 2098 mid, fname, hdw->hdw_desc->description);
2099 return -EIO;
446dfdc6
MI		 2100 }
2101
2102 /* Tag this sub-device instance with the module ID we know about.
2103 In other places we'll use that tag to determine if the instance
2104 requires special handling. */
2105 sd->grp_id = mid;
2106
bd14d4f8 2107 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
a932f507 2108
e9c64a78 2109
00e5f736
MI		 2110 /* client-specific setup... */
2111 switch (mid) {
2112 case PVR2_CLIENT_ID_CX25840:
00e5f736
MI		 2113 case PVR2_CLIENT_ID_SAA7115:
2114 hdw->decoder_client_id = mid;
2115 break;
2116 default: break;
2117 }
1ab5e74f
MI		 2118
2119 return 0;
e9c64a78
MI		 2120}
2121
2122
2123static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2124{
2125 unsigned int idx;
2126 const struct pvr2_string_table *cm;
2127 const struct pvr2_device_client_table *ct;
1ab5e74f 2128 int okFl = !0;
e9c64a78
MI		 2129
2130 cm = &hdw->hdw_desc->client_modules;
2131 for (idx = 0; idx < cm->cnt; idx++) {
2132 request_module(cm->lst[idx]);
2133 }
2134
2135 ct = &hdw->hdw_desc->client_table;
2136 for (idx = 0; idx < ct->cnt; idx++) {
bd14d4f8 2137 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
e9c64a78 2138 }
27108147
MI		 2139 if (!okFl) {
2140 hdw->flag_modulefail = !0;
2141 pvr2_hdw_render_useless(hdw);
2142 }
e9c64a78
MI		 2143}
2144
2145
d855497e
MI		 2146static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2147{
2148 int ret;
2149 unsigned int idx;
2150 struct pvr2_ctrl *cptr;
2151 int reloadFl = 0;
989eb154 2152 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 2153 if (!reloadFl) {
2154 reloadFl =
2155 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2156 == 0);
2157 if (reloadFl) {
2158 pvr2_trace(PVR2_TRACE_INIT,
2159 "USB endpoint config looks strange"
2160 "; possibly firmware needs to be"
2161 " loaded");
2162 }
d855497e 2163 }
1d643a37
MI		 2164 if (!reloadFl) {
2165 reloadFl = !pvr2_hdw_check_firmware(hdw);
2166 if (reloadFl) {
2167 pvr2_trace(PVR2_TRACE_INIT,
2168 "Check for FX2 firmware failed"
2169 "; possibly firmware needs to be"
2170 " loaded");
2171 }
d855497e 2172 }
1d643a37
MI		 2173 if (reloadFl) {
2174 if (pvr2_upload_firmware1(hdw) != 0) {
2175 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2176 "Failure uploading firmware1");
2177 }
2178 return;
d855497e 2179 }
d855497e
MI		 2180 }
2181 hdw->fw1_state = FW1_STATE_OK;
2182
d855497e
MI		 2183 if (!pvr2_hdw_dev_ok(hdw)) return;
2184
27764726
MI		 2185 hdw->force_dirty = !0;
2186
989eb154 2187 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 2188 pvr2_hdw_cmd_powerup(hdw);
2189 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 2190 }
2191
31335b13 2192 /* Take the IR chip out of reset, if appropriate */
27eab384 2193 if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
31335b13
MI		 2194 pvr2_issue_simple_cmd(hdw,
2195 FX2CMD_HCW_ZILOG_RESET |
2196 (1 << 8) |
2197 ((0) << 16));
2198 }
2199
d855497e
MI		 2200 // This step MUST happen after the earlier powerup step.
2201 pvr2_i2c_core_init(hdw);
2202 if (!pvr2_hdw_dev_ok(hdw)) return;
2203
e9c64a78 2204 pvr2_hdw_load_modules(hdw);
1ab5e74f 2205 if (!pvr2_hdw_dev_ok(hdw)) return;
e9c64a78 2206
cc26b076 2207 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
5c6cb4e2 2208
c05c0462 2209 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 2210 cptr = hdw->controls + idx;
2211 if (cptr->info->skip_init) continue;
2212 if (!cptr->info->set_value) continue;
2213 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2214 }
2215
e17d787c
MI		 2216 pvr2_hdw_cx25840_vbi_hack(hdw);
2217
1bde0289
MI		 2218 /* Set up special default values for the television and radio
2219 frequencies here. It's not really important what these defaults
2220 are, but I set them to something usable in the Chicago area just
2221 to make driver testing a little easier. */
2222
5a4f5da6
MK		 2223 hdw->freqValTelevision = default_tv_freq;
2224 hdw->freqValRadio = default_radio_freq;
1bde0289 2225
d855497e
MI		 2226 // Do not use pvr2_reset_ctl_endpoints() here. It is not
2227 // thread-safe against the normal pvr2_send_request() mechanism.
2228 // (We should make it thread safe).
2229
aaf7884d
MI		 2230 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2231 ret = pvr2_hdw_get_eeprom_addr(hdw);
d855497e 2232 if (!pvr2_hdw_dev_ok(hdw)) return;
aaf7884d
MI		 2233 if (ret < 0) {
2234 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2235 "Unable to determine location of eeprom,"
2236 " skipping");
2237 } else {
2238 hdw->eeprom_addr = ret;
2239 pvr2_eeprom_analyze(hdw);
2240 if (!pvr2_hdw_dev_ok(hdw)) return;
2241 }
2242 } else {
2243 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2244 hdw->tuner_updated = !0;
2245 hdw->std_mask_eeprom = V4L2_STD_ALL;
d855497e
MI		 2246 }
2247
13a88797
MI		 2248 if (hdw->serial_number) {
2249 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2250 "sn-%lu", hdw->serial_number);
2251 } else if (hdw->unit_number >= 0) {
2252 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2253 "unit-%c",
2254 hdw->unit_number + 'a');
2255 } else {
2256 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2257 "unit-??");
2258 }
2259 hdw->identifier[idx] = 0;
2260
d855497e
MI		 2261 pvr2_hdw_setup_std(hdw);
2262
2263 if (!get_default_tuner_type(hdw)) {
2264 pvr2_trace(PVR2_TRACE_INIT,
2265 "pvr2_hdw_setup: Tuner type overridden to %d",
2266 hdw->tuner_type);
2267 }
2268
d855497e
MI		 2269
2270 if (!pvr2_hdw_dev_ok(hdw)) return;
2271
1df59f0b
MI		 2272 if (hdw->hdw_desc->signal_routing_scheme ==
2273 PVR2_ROUTING_SCHEME_GOTVIEW) {
2274 /* Ensure that GPIO 11 is set to output for GOTVIEW
2275 hardware. */
2276 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2277 }
2278
681c7399 2279 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 2280
2281 hdw->vid_stream = pvr2_stream_create();
2282 if (!pvr2_hdw_dev_ok(hdw)) return;
2283 pvr2_trace(PVR2_TRACE_INIT,
2284 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2285 if (hdw->vid_stream) {
2286 idx = get_default_error_tolerance(hdw);
2287 if (idx) {
2288 pvr2_trace(PVR2_TRACE_INIT,
2289 "pvr2_hdw_setup: video stream %p"
2290 " setting tolerance %u",
2291 hdw->vid_stream,idx);
2292 }
2293 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2294 PVR2_VID_ENDPOINT,idx);
2295 }
2296
2297 if (!pvr2_hdw_dev_ok(hdw)) return;
2298
d855497e 2299 hdw->flag_init_ok = !0;
681c7399
MI		 2300
2301 pvr2_hdw_state_sched(hdw);
d855497e
MI		 2302}
2303
2304
681c7399
MI		 2305/* Set up the structure and attempt to put the device into a usable state.
2306 This can be a time-consuming operation, which is why it is not done
2307 internally as part of the create() step. */
2308static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 2309{
2310 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 2311 do {
d855497e
MI		 2312 pvr2_hdw_setup_low(hdw);
2313 pvr2_trace(PVR2_TRACE_INIT,
2314 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 2315 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 2316 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 2317 if (hdw->flag_init_ok) {
d855497e
MI		 2318 pvr2_trace(
2319 PVR2_TRACE_INFO,
2320 "Device initialization"
2321 " completed successfully.");
2322 break;
2323 }
2324 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2325 pvr2_trace(
2326 PVR2_TRACE_INFO,
2327 "Device microcontroller firmware"
2328 " (re)loaded; it should now reset"
2329 " and reconnect.");
2330 break;
2331 }
2332 pvr2_trace(
2333 PVR2_TRACE_ERROR_LEGS,
2334 "Device initialization was not successful.");
2335 if (hdw->fw1_state == FW1_STATE_MISSING) {
2336 pvr2_trace(
2337 PVR2_TRACE_ERROR_LEGS,
2338 "Giving up since device"
2339 " microcontroller firmware"
2340 " appears to be missing.");
2341 break;
2342 }
2343 }
27108147
MI		 2344 if (hdw->flag_modulefail) {
2345 pvr2_trace(
2346 PVR2_TRACE_ERROR_LEGS,
2347 "***WARNING*** pvrusb2 driver initialization"
2348 " failed due to the failure of one or more"
2349 " sub-device kernel modules.");
2350 pvr2_trace(
2351 PVR2_TRACE_ERROR_LEGS,
2352 "You need to resolve the failing condition"
2353 " before this driver can function. There"
2354 " should be some earlier messages giving more"
2355 " information about the problem.");
2356 }
d855497e
MI		 2357 if (procreload) {
2358 pvr2_trace(
2359 PVR2_TRACE_ERROR_LEGS,
2360 "Attempting pvrusb2 recovery by reloading"
2361 " primary firmware.");
2362 pvr2_trace(
2363 PVR2_TRACE_ERROR_LEGS,
2364 "If this works, device should disconnect"
2365 " and reconnect in a sane state.");
2366 hdw->fw1_state = FW1_STATE_UNKNOWN;
2367 pvr2_upload_firmware1(hdw);
2368 } else {
2369 pvr2_trace(
2370 PVR2_TRACE_ERROR_LEGS,
2371 "***WARNING*** pvrusb2 device hardware"
2372 " appears to be jammed"
2373 " and I can't clear it.");
2374 pvr2_trace(
2375 PVR2_TRACE_ERROR_LEGS,
2376 "You might need to power cycle"
2377 " the pvrusb2 device"
2378 " in order to recover.");
2379 }
681c7399 2380 } while (0);
d855497e 2381 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 2382}
2383
2384
c4a8828d
MI		 2385/* Perform second stage initialization. Set callback pointer first so that
2386 we can avoid a possible initialization race (if the kernel thread runs
2387 before the callback has been set). */
794b1607
MI		 2388int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2389 void (*callback_func)(void *),
2390 void *callback_data)
c4a8828d
MI		 2391{
2392 LOCK_TAKE(hdw->big_lock); do {
97f26ff6
MI		 2393 if (hdw->flag_disconnected) {
2394 /* Handle a race here: If we're already
2395 disconnected by this point, then give up. If we
2396 get past this then we'll remain connected for
2397 the duration of initialization since the entire
2398 initialization sequence is now protected by the
2399 big_lock. */
2400 break;
2401 }
c4a8828d
MI		 2402 hdw->state_data = callback_data;
2403 hdw->state_func = callback_func;
97f26ff6 2404 pvr2_hdw_setup(hdw);
c4a8828d 2405 } while (0); LOCK_GIVE(hdw->big_lock);
794b1607 2406 return hdw->flag_init_ok;
c4a8828d
MI		 2407}
2408
2409
2410/* Create, set up, and return a structure for interacting with the
2411 underlying hardware. */
d855497e
MI		 2412struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2413 const struct usb_device_id *devid)
2414{
7fb20fa3 2415 unsigned int idx,cnt1,cnt2,m;
fe15f136 2416 struct pvr2_hdw *hdw = NULL;
d855497e
MI		 2417 int valid_std_mask;
2418 struct pvr2_ctrl *cptr;
b72b7bf5 2419 struct usb_device *usb_dev;
989eb154 2420 const struct pvr2_device_desc *hdw_desc;
d855497e 2421 __u8 ifnum;
b30d2441
MI		 2422 struct v4l2_queryctrl qctrl;
2423 struct pvr2_ctl_info *ciptr;
d855497e 2424
b72b7bf5
MI		 2425 usb_dev = interface_to_usbdev(intf);
2426
d130fa8a 2427 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
d855497e 2428
fe15f136
MI		 2429 if (hdw_desc == NULL) {
2430 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2431 " No device description pointer,"
2432 " unable to continue.");
2433 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2434 " please contact Mike Isely <isely@pobox.com>"
2435 " to get it included in the driver\n");
2436 goto fail;
2437 }
2438
ca545f7c 2439 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 2440 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 2441 hdw,hdw_desc->description);
d855497e 2442 if (!hdw) goto fail;
681c7399
MI		 2443
2444 init_timer(&hdw->quiescent_timer);
2445 hdw->quiescent_timer.data = (unsigned long)hdw;
2446 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2447
2448 init_timer(&hdw->encoder_wait_timer);
2449 hdw->encoder_wait_timer.data = (unsigned long)hdw;
2450 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2451
d913d630
MI		 2452 init_timer(&hdw->encoder_run_timer);
2453 hdw->encoder_run_timer.data = (unsigned long)hdw;
2454 hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2455
681c7399
MI		 2456 hdw->master_state = PVR2_STATE_DEAD;
2457
2458 init_waitqueue_head(&hdw->state_wait_data);
2459
18103c57 2460 hdw->tuner_signal_stale = !0;
b30d2441 2461 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 2462
7fb20fa3
MI		 2463 /* Calculate which inputs are OK */
2464 m = 0;
2465 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
e8f5bacf
MI		 2466 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2467 m |= 1 << PVR2_CVAL_INPUT_DTV;
2468 }
7fb20fa3
MI		 2469 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2470 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2471 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2472 hdw->input_avail_mask = m;
1cb03b76 2473 hdw->input_allowed_mask = hdw->input_avail_mask;
7fb20fa3 2474
62433e31
MI		 2475 /* If not a hybrid device, pathway_state never changes. So
2476 initialize it here to what it should forever be. */
2477 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2478 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2479 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2480 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2481 }
2482
c05c0462 2483 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 2484 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 2485 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 2486 GFP_KERNEL);
2487 if (!hdw->controls) goto fail;
989eb154 2488 hdw->hdw_desc = hdw_desc;
27eab384 2489 hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
c05c0462
MI		 2490 for (idx = 0; idx < hdw->control_cnt; idx++) {
2491 cptr = hdw->controls + idx;
2492 cptr->hdw = hdw;
2493 }
d855497e
MI		 2494 for (idx = 0; idx < 32; idx++) {
2495 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2496 }
c05c0462 2497 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 2498 cptr = hdw->controls + idx;
d855497e
MI		 2499 cptr->info = control_defs+idx;
2500 }
dbc40a0e
MI		 2501
2502 /* Ensure that default input choice is a valid one. */
2503 m = hdw->input_avail_mask;
2504 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2505 if (!((1 << idx) & m)) continue;
2506 hdw->input_val = idx;
2507 break;
2508 }
2509
b30d2441 2510 /* Define and configure additional controls from cx2341x module. */
ca545f7c 2511 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 2512 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2513 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 2514 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2515 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2516 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2517 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2518 ciptr->name = mpeg_ids[idx].strid;
2519 ciptr->v4l_id = mpeg_ids[idx].id;
2520 ciptr->skip_init = !0;
2521 ciptr->get_value = ctrl_cx2341x_get;
2522 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2523 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2524 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2525 qctrl.id = ciptr->v4l_id;
2526 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2527 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2528 ciptr->set_value = ctrl_cx2341x_set;
2529 }
2530 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2531 PVR2_CTLD_INFO_DESC_SIZE);
2532 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2533 ciptr->default_value = qctrl.default_value;
2534 switch (qctrl.type) {
2535 default:
2536 case V4L2_CTRL_TYPE_INTEGER:
2537 ciptr->type = pvr2_ctl_int;
2538 ciptr->def.type_int.min_value = qctrl.minimum;
2539 ciptr->def.type_int.max_value = qctrl.maximum;
2540 break;
2541 case V4L2_CTRL_TYPE_BOOLEAN:
2542 ciptr->type = pvr2_ctl_bool;
2543 break;
2544 case V4L2_CTRL_TYPE_MENU:
2545 ciptr->type = pvr2_ctl_enum;
2546 ciptr->def.type_enum.value_names =
e0e31cdb
HV		 2547 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2548 ciptr->v4l_id);
b30d2441
MI		 2549 for (cnt1 = 0;
2550 ciptr->def.type_enum.value_names[cnt1] != NULL;
2551 cnt1++) { }
2552 ciptr->def.type_enum.count = cnt1;
2553 break;
2554 }
2555 cptr->info = ciptr;
2556 }
d855497e
MI		 2557
2558 // Initialize video standard enum dynamic control
2559 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2560 if (cptr) {
2561 memcpy(&hdw->std_info_enum,cptr->info,
2562 sizeof(hdw->std_info_enum));
2563 cptr->info = &hdw->std_info_enum;
2564
2565 }
2566 // Initialize control data regarding video standard masks
2567 valid_std_mask = pvr2_std_get_usable();
2568 for (idx = 0; idx < 32; idx++) {
2569 if (!(valid_std_mask & (1 << idx))) continue;
2570 cnt1 = pvr2_std_id_to_str(
2571 hdw->std_mask_names[idx],
2572 sizeof(hdw->std_mask_names[idx])-1,
2573 1 << idx);
2574 hdw->std_mask_names[idx][cnt1] = 0;
2575 }
2576 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2577 if (cptr) {
2578 memcpy(&hdw->std_info_avail,cptr->info,
2579 sizeof(hdw->std_info_avail));
2580 cptr->info = &hdw->std_info_avail;
2581 hdw->std_info_avail.def.type_bitmask.bit_names =
2582 hdw->std_mask_ptrs;
2583 hdw->std_info_avail.def.type_bitmask.valid_bits =
2584 valid_std_mask;
2585 }
2586 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2587 if (cptr) {
2588 memcpy(&hdw->std_info_cur,cptr->info,
2589 sizeof(hdw->std_info_cur));
2590 cptr->info = &hdw->std_info_cur;
2591 hdw->std_info_cur.def.type_bitmask.bit_names =
2592 hdw->std_mask_ptrs;
2593 hdw->std_info_avail.def.type_bitmask.valid_bits =
2594 valid_std_mask;
2595 }
2596
432907f7 2597 hdw->cropcap_stale = !0;
d855497e
MI		 2598 hdw->eeprom_addr = -1;
2599 hdw->unit_number = -1;
8079384e
MI		 2600 hdw->v4l_minor_number_video = -1;
2601 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 2602 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 2603 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2604 if (!hdw->ctl_write_buffer) goto fail;
2605 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2606 if (!hdw->ctl_read_buffer) goto fail;
2607 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2608 if (!hdw->ctl_write_urb) goto fail;
2609 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2610 if (!hdw->ctl_read_urb) goto fail;
2611
70ad6383 2612 if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
b72b7bf5
MI		 2613 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2614 "Error registering with v4l core, giving up");
2615 goto fail;
2616 }
8df0c87c 2617 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2618 for (idx = 0; idx < PVR_NUM; idx++) {
2619 if (unit_pointers[idx]) continue;
2620 hdw->unit_number = idx;
2621 unit_pointers[idx] = hdw;
2622 break;
2623 }
8df0c87c 2624 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 2625
2626 cnt1 = 0;
2627 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2628 cnt1 += cnt2;
2629 if (hdw->unit_number >= 0) {
2630 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2631 ('a' + hdw->unit_number));
2632 cnt1 += cnt2;
2633 }
2634 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2635 hdw->name[cnt1] = 0;
2636
681c7399
MI		 2637 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2638 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
681c7399 2639
d855497e
MI		 2640 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2641 hdw->unit_number,hdw->name);
2642
2643 hdw->tuner_type = -1;
2644 hdw->flag_ok = !0;
d855497e
MI		 2645
2646 hdw->usb_intf = intf;
b72b7bf5 2647 hdw->usb_dev = usb_dev;
d855497e 2648
87e3495c 2649 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
31a18547 2650
d855497e
MI		 2651 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2652 usb_set_interface(hdw->usb_dev,ifnum,0);
2653
2654 mutex_init(&hdw->ctl_lock_mutex);
2655 mutex_init(&hdw->big_lock_mutex);
2656
2657 return hdw;
2658 fail:
2659 if (hdw) {
681c7399 2660 del_timer_sync(&hdw->quiescent_timer);
d913d630 2661 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 2662 del_timer_sync(&hdw->encoder_wait_timer);
2663 if (hdw->workqueue) {
2664 flush_workqueue(hdw->workqueue);
2665 destroy_workqueue(hdw->workqueue);
2666 hdw->workqueue = NULL;
2667 }
5e55d2ce
MK		 2668 usb_free_urb(hdw->ctl_read_urb);
2669 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2670 kfree(hdw->ctl_read_buffer);
2671 kfree(hdw->ctl_write_buffer);
2672 kfree(hdw->controls);
2673 kfree(hdw->mpeg_ctrl_info);
681c7399
MI		 2674 kfree(hdw->std_defs);
2675 kfree(hdw->std_enum_names);
d855497e
MI		 2676 kfree(hdw);
2677 }
a0fd1cb1 2678 return NULL;
d855497e
MI		 2679}
2680
2681
2682/* Remove _all_ associations between this driver and the underlying USB
2683 layer. */
07e337ee 2684static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2685{
2686 if (hdw->flag_disconnected) return;
2687 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2688 if (hdw->ctl_read_urb) {
2689 usb_kill_urb(hdw->ctl_read_urb);
2690 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2691 hdw->ctl_read_urb = NULL;
d855497e
MI		 2692 }
2693 if (hdw->ctl_write_urb) {
2694 usb_kill_urb(hdw->ctl_write_urb);
2695 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2696 hdw->ctl_write_urb = NULL;
d855497e
MI		 2697 }
2698 if (hdw->ctl_read_buffer) {
2699 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2700 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2701 }
2702 if (hdw->ctl_write_buffer) {
2703 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2704 hdw->ctl_write_buffer = NULL;
d855497e 2705 }
d855497e 2706 hdw->flag_disconnected = !0;
b72b7bf5
MI		 2707 /* If we don't do this, then there will be a dangling struct device
2708 reference to our disappearing device persisting inside the V4L
2709 core... */
dc070bcc 2710 v4l2_device_disconnect(&hdw->v4l2_dev);
a0fd1cb1
MI		 2711 hdw->usb_dev = NULL;
2712 hdw->usb_intf = NULL;
681c7399 2713 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2714}
2715
2716
2717/* Destroy hardware interaction structure */
2718void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2719{
401c27ce 2720 if (!hdw) return;
d855497e 2721 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2722 if (hdw->workqueue) {
2723 flush_workqueue(hdw->workqueue);
2724 destroy_workqueue(hdw->workqueue);
2725 hdw->workqueue = NULL;
2726 }
8f59100a 2727 del_timer_sync(&hdw->quiescent_timer);
d913d630 2728 del_timer_sync(&hdw->encoder_run_timer);
8f59100a 2729 del_timer_sync(&hdw->encoder_wait_timer);
d855497e
MI		 2730 if (hdw->fw_buffer) {
2731 kfree(hdw->fw_buffer);
a0fd1cb1 2732 hdw->fw_buffer = NULL;
d855497e
MI		 2733 }
2734 if (hdw->vid_stream) {
2735 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2736 hdw->vid_stream = NULL;
d855497e 2737 }
d855497e 2738 pvr2_i2c_core_done(hdw);
b72b7bf5 2739 v4l2_device_unregister(&hdw->v4l2_dev);
d855497e 2740 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2741 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2742 if ((hdw->unit_number >= 0) &&
2743 (hdw->unit_number < PVR_NUM) &&
2744 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2745 unit_pointers[hdw->unit_number] = NULL;
d855497e 2746 }
8df0c87c 2747 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2748 kfree(hdw->controls);
2749 kfree(hdw->mpeg_ctrl_info);
2750 kfree(hdw->std_defs);
2751 kfree(hdw->std_enum_names);
d855497e
MI		 2752 kfree(hdw);
2753}
2754
2755
d855497e
MI		 2756int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2757{
2758 return (hdw && hdw->flag_ok);
2759}
2760
2761
2762/* Called when hardware has been unplugged */
2763void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2764{
2765 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2766 LOCK_TAKE(hdw->big_lock);
2767 LOCK_TAKE(hdw->ctl_lock);
2768 pvr2_hdw_remove_usb_stuff(hdw);
2769 LOCK_GIVE(hdw->ctl_lock);
2770 LOCK_GIVE(hdw->big_lock);
2771}
2772
2773
2774// Attempt to autoselect an appropriate value for std_enum_cur given
2775// whatever is currently in std_mask_cur
07e337ee 2776static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2777{
2778 unsigned int idx;
2779 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2780 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2781 hdw->std_enum_cur = idx;
2782 return;
2783 }
2784 }
2785 hdw->std_enum_cur = 0;
2786}
2787
2788
2789// Calculate correct set of enumerated standards based on currently known
2790// set of available standards bits.
07e337ee 2791static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2792{
2793 struct v4l2_standard *newstd;
2794 unsigned int std_cnt;
2795 unsigned int idx;
2796
2797 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2798
2799 if (hdw->std_defs) {
2800 kfree(hdw->std_defs);
a0fd1cb1 2801 hdw->std_defs = NULL;
d855497e
MI		 2802 }
2803 hdw->std_enum_cnt = 0;
2804 if (hdw->std_enum_names) {
2805 kfree(hdw->std_enum_names);
a0fd1cb1 2806 hdw->std_enum_names = NULL;
d855497e
MI		 2807 }
2808
2809 if (!std_cnt) {
2810 pvr2_trace(
2811 PVR2_TRACE_ERROR_LEGS,
2812 "WARNING: Failed to identify any viable standards");
2813 }
2814 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2815 hdw->std_enum_names[0] = "none";
2816 for (idx = 0; idx < std_cnt; idx++) {
2817 hdw->std_enum_names[idx+1] =
2818 newstd[idx].name;
2819 }
2820 // Set up the dynamic control for this standard
2821 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2822 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2823 hdw->std_defs = newstd;
2824 hdw->std_enum_cnt = std_cnt+1;
2825 hdw->std_enum_cur = 0;
2826 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2827}
2828
2829
2830int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2831 struct v4l2_standard *std,
2832 unsigned int idx)
2833{
2834 int ret = -EINVAL;
2835 if (!idx) return ret;
2836 LOCK_TAKE(hdw->big_lock); do {
2837 if (idx >= hdw->std_enum_cnt) break;
2838 idx--;
2839 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2840 ret = 0;
2841 } while (0); LOCK_GIVE(hdw->big_lock);
2842 return ret;
2843}
2844
2845
2846/* Get the number of defined controls */
2847unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2848{
c05c0462 2849 return hdw->control_cnt;
d855497e
MI		 2850}
2851
2852
2853/* Retrieve a control handle given its index (0..count-1) */
2854struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2855 unsigned int idx)
2856{
a0fd1cb1 2857 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2858 return hdw->controls + idx;
2859}
2860
2861
2862/* Retrieve a control handle given its index (0..count-1) */
2863struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2864 unsigned int ctl_id)
2865{
2866 struct pvr2_ctrl *cptr;
2867 unsigned int idx;
2868 int i;
2869
2870 /* This could be made a lot more efficient, but for now... */
c05c0462 2871 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2872 cptr = hdw->controls + idx;
2873 i = cptr->info->internal_id;
2874 if (i && (i == ctl_id)) return cptr;
2875 }
a0fd1cb1 2876 return NULL;
d855497e
MI		 2877}
2878
2879
a761f431 2880/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2881struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2882{
2883 struct pvr2_ctrl *cptr;
2884 unsigned int idx;
2885 int i;
2886
2887 /* This could be made a lot more efficient, but for now... */
c05c0462 2888 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2889 cptr = hdw->controls + idx;
2890 i = cptr->info->v4l_id;
2891 if (i && (i == ctl_id)) return cptr;
2892 }
a0fd1cb1 2893 return NULL;
d855497e
MI		 2894}
2895
2896
a761f431
MI		 2897/* Given a V4L ID for its immediate predecessor, retrieve the control
2898 structure associated with it. */
2899struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2900 unsigned int ctl_id)
2901{
2902 struct pvr2_ctrl *cptr,*cp2;
2903 unsigned int idx;
2904 int i;
2905
2906 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2907 cp2 = NULL;
a761f431
MI		 2908 for (idx = 0; idx < hdw->control_cnt; idx++) {
2909 cptr = hdw->controls + idx;
2910 i = cptr->info->v4l_id;
2911 if (!i) continue;
2912 if (i <= ctl_id) continue;
2913 if (cp2 && (cp2->info->v4l_id < i)) continue;
2914 cp2 = cptr;
2915 }
2916 return cp2;
a0fd1cb1 2917 return NULL;
a761f431
MI		 2918}
2919
2920
d855497e
MI		 2921static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2922{
2923 switch (tp) {
2924 case pvr2_ctl_int: return "integer";
2925 case pvr2_ctl_enum: return "enum";
33213963 2926 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2927 case pvr2_ctl_bitmask: return "bitmask";
2928 }
2929 return "";
2930}
2931
2932
2641df36
MI		 2933static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2934 const char *name, int val)
2935{
2936 struct v4l2_control ctrl;
2937 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2938 memset(&ctrl, 0, sizeof(ctrl));
2939 ctrl.id = id;
2940 ctrl.value = val;
2941 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2942}
2943
2944#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
27764726 2945 if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \
2641df36
MI		 2946 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2947 }
2948
5ceaad14 2949/* Execute whatever commands are required to update the state of all the
2641df36 2950 sub-devices so that they match our current control values. */
5ceaad14
MI		 2951static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2952{
edb9dcb8
MI		 2953 struct v4l2_subdev *sd;
2954 unsigned int id;
2955 pvr2_subdev_update_func fp;
2956
75212a02
MI		 2957 pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2958
27764726 2959 if (hdw->tuner_updated || hdw->force_dirty) {
75212a02
MI		 2960 struct tuner_setup setup;
2961 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2962 hdw->tuner_type);
2963 if (((int)(hdw->tuner_type)) >= 0) {
fcd62cf7 2964 memset(&setup, 0, sizeof(setup));
75212a02
MI		 2965 setup.addr = ADDR_UNSET;
2966 setup.type = hdw->tuner_type;
2967 setup.mode_mask = T_RADIO | T_ANALOG_TV;
2968 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2969 tuner, s_type_addr, &setup);
2970 }
2971 }
2972
27764726 2973 if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
b481880b 2974 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2641df36
MI		 2975 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2976 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2977 tuner, s_radio);
2978 } else {
2979 v4l2_std_id vs;
2980 vs = hdw->std_mask_cur;
2981 v4l2_device_call_all(&hdw->v4l2_dev, 0,
f41737ec 2982 core, s_std, vs);
a6862da2 2983 pvr2_hdw_cx25840_vbi_hack(hdw);
2641df36
MI		 2984 }
2985 hdw->tuner_signal_stale = !0;
2986 hdw->cropcap_stale = !0;
2987 }
2988
2989 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2990 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2991 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2992 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2993 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2994 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2995 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2996 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2997 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2998
27764726 2999 if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2641df36
MI		 3000 struct v4l2_tuner vt;
3001 memset(&vt, 0, sizeof(vt));
3002 vt.audmode = hdw->audiomode_val;
3003 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
3004 }
3005
27764726 3006 if (hdw->freqDirty || hdw->force_dirty) {
2641df36
MI		 3007 unsigned long fv;
3008 struct v4l2_frequency freq;
3009 fv = pvr2_hdw_get_cur_freq(hdw);
3010 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
3011 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
3012 memset(&freq, 0, sizeof(freq));
3013 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
3014 /* ((fv * 1000) / 62500) */
3015 freq.frequency = (fv * 2) / 125;
3016 } else {
3017 freq.frequency = fv / 62500;
3018 }
3019 /* tuner-core currently doesn't seem to care about this, but
3020 let's set it anyway for completeness. */
3021 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3022 freq.type = V4L2_TUNER_RADIO;
3023 } else {
3024 freq.type = V4L2_TUNER_ANALOG_TV;
3025 }
3026 freq.tuner = 0;
3027 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
3028 s_frequency, &freq);
3029 }
3030
27764726 3031 if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
2641df36
MI		 3032 struct v4l2_format fmt;
3033 memset(&fmt, 0, sizeof(fmt));
3034 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
3035 fmt.fmt.pix.width = hdw->res_hor_val;
3036 fmt.fmt.pix.height = hdw->res_ver_val;
7dfdf1ee 3037 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
2641df36
MI		 3038 fmt.fmt.pix.width, fmt.fmt.pix.height);
3039 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
3040 }
3041
27764726 3042 if (hdw->srate_dirty || hdw->force_dirty) {
01c59df8
MI		 3043 u32 val;
3044 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3045 hdw->srate_val);
3046 switch (hdw->srate_val) {
3047 default:
3048 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3049 val = 48000;
3050 break;
3051 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3052 val = 44100;
3053 break;
3054 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3055 val = 32000;
3056 break;
3057 }
3058 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3059 audio, s_clock_freq, val);
3060 }
3061
2641df36
MI		 3062 /* Unable to set crop parameters; there is apparently no equivalent
3063 for VIDIOC_S_CROP */
3064
edb9dcb8
MI		 3065 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3066 id = sd->grp_id;
3067 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3068 fp = pvr2_module_update_functions[id];
3069 if (!fp) continue;
3070 (*fp)(hdw, sd);
3071 }
2641df36 3072
27764726 3073 if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
2641df36
MI		 3074 pvr2_hdw_status_poll(hdw);
3075 }
5ceaad14
MI		 3076}
3077
3078
681c7399
MI		 3079/* Figure out if we need to commit control changes. If so, mark internal
3080 state flags to indicate this fact and return true. Otherwise do nothing
3081 else and return false. */
3082static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 3083{
d855497e
MI		 3084 unsigned int idx;
3085 struct pvr2_ctrl *cptr;
3086 int value;
27764726 3087 int commit_flag = hdw->force_dirty;
d855497e
MI		 3088 char buf[100];
3089 unsigned int bcnt,ccnt;
3090
c05c0462 3091 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e 3092 cptr = hdw->controls + idx;
5fa1247a 3093 if (!cptr->info->is_dirty) continue;
d855497e 3094 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 3095 commit_flag = !0;
d855497e 3096
fe23a280 3097 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 3098 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3099 cptr->info->name);
3100 value = 0;
3101 cptr->info->get_value(cptr,&value);
3102 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3103 buf+bcnt,
3104 sizeof(buf)-bcnt,&ccnt);
3105 bcnt += ccnt;
3106 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3107 get_ctrl_typename(cptr->info->type));
3108 pvr2_trace(PVR2_TRACE_CTL,
3109 "/*--TRACE_COMMIT--*/ %.*s",
3110 bcnt,buf);
3111 }
3112
3113 if (!commit_flag) {
3114 /* Nothing has changed */
3115 return 0;
3116 }
3117
681c7399
MI		 3118 hdw->state_pipeline_config = 0;
3119 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3120 pvr2_hdw_state_sched(hdw);
3121
3122 return !0;
3123}
3124
3125
3126/* Perform all operations needed to commit all control changes. This must
3127 be performed in synchronization with the pipeline state and is thus
3128 expected to be called as part of the driver's worker thread. Return
3129 true if commit successful, otherwise return false to indicate that
3130 commit isn't possible at this time. */
3131static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3132{
3133 unsigned int idx;
3134 struct pvr2_ctrl *cptr;
3135 int disruptive_change;
3136
ab062fe3
MI		 3137 /* Handle some required side effects when the video standard is
3138 changed.... */
d855497e 3139 if (hdw->std_dirty) {
d855497e 3140 int nvres;
00528d9c 3141 int gop_size;
d855497e
MI		 3142 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3143 nvres = 480;
00528d9c 3144 gop_size = 15;
d855497e
MI		 3145 } else {
3146 nvres = 576;
00528d9c 3147 gop_size = 12;
d855497e 3148 }
00528d9c
MI		 3149 /* Rewrite the vertical resolution to be appropriate to the
3150 video standard that has been selected. */
d855497e
MI		 3151 if (nvres != hdw->res_ver_val) {
3152 hdw->res_ver_val = nvres;
3153 hdw->res_ver_dirty = !0;
3154 }
00528d9c
MI		 3155 /* Rewrite the GOP size to be appropriate to the video
3156 standard that has been selected. */
3157 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3158 struct v4l2_ext_controls cs;
3159 struct v4l2_ext_control c1;
3160 memset(&cs, 0, sizeof(cs));
3161 memset(&c1, 0, sizeof(c1));
3162 cs.controls = &c1;
3163 cs.count = 1;
3164 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3165 c1.value = gop_size;
3166 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3167 VIDIOC_S_EXT_CTRLS);
3168 }
d855497e
MI		 3169 }
3170
38d9a2cf 3171 if (hdw->input_dirty && hdw->state_pathway_ok &&
62433e31
MI		 3172 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3173 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3174 hdw->pathway_state)) {
3175 /* Change of mode being asked for... */
3176 hdw->state_pathway_ok = 0;
e9db1ff2 3177 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 3178 }
3179 if (!hdw->state_pathway_ok) {
3180 /* Can't commit anything until pathway is ok. */
3181 return 0;
3182 }
e784bfb9 3183 /* The broadcast decoder can only scale down, so if
3184 * res_*_dirty && crop window < output format ==> enlarge crop.
3185 *
3186 * The mpeg encoder receives fields of res_hor_val dots and
3187 * res_ver_val halflines. Limits: hor<=720, ver<=576.
3188 */
3189 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3190 hdw->cropw_val = hdw->res_hor_val;
3191 hdw->cropw_dirty = !0;
3192 } else if (hdw->cropw_dirty) {
3193 hdw->res_hor_dirty = !0; /* must rescale */
3194 hdw->res_hor_val = min(720, hdw->cropw_val);
3195 }
3196 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3197 hdw->croph_val = hdw->res_ver_val;
3198 hdw->croph_dirty = !0;
3199 } else if (hdw->croph_dirty) {
3200 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3201 hdw->res_ver_dirty = !0;
3202 hdw->res_ver_val = min(nvres, hdw->croph_val);
3203 }
3204
681c7399
MI		 3205 /* If any of the below has changed, then we can't do the update
3206 while the pipeline is running. Pipeline must be paused first
3207 and decoder -> encoder connection be made quiescent before we
3208 can proceed. */
3209 disruptive_change =
3210 (hdw->std_dirty ||
3211 hdw->enc_unsafe_stale ||
3212 hdw->srate_dirty ||
3213 hdw->res_ver_dirty ||
3214 hdw->res_hor_dirty ||
755879c6
MI		 3215 hdw->cropw_dirty ||
3216 hdw->croph_dirty ||
681c7399
MI		 3217 hdw->input_dirty ||
3218 (hdw->active_stream_type != hdw->desired_stream_type));
3219 if (disruptive_change && !hdw->state_pipeline_idle) {
3220 /* Pipeline is not idle; we can't proceed. Arrange to
3221 cause pipeline to stop so that we can try this again
3222 later.... */
3223 hdw->state_pipeline_pause = !0;
3224 return 0;
275b2e28
PK		 3225 }
3226
b30d2441
MI		 3227 if (hdw->srate_dirty) {
3228 /* Write new sample rate into control structure since
3229 * the master copy is stale. We must track srate
3230 * separate from the mpeg control structure because
3231 * other logic also uses this value. */
3232 struct v4l2_ext_controls cs;
3233 struct v4l2_ext_control c1;
3234 memset(&cs,0,sizeof(cs));
3235 memset(&c1,0,sizeof(c1));
3236 cs.controls = &c1;
3237 cs.count = 1;
3238 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3239 c1.value = hdw->srate_val;
01f1e44f 3240 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 3241 }
c05c0462 3242
681c7399
MI		 3243 if (hdw->active_stream_type != hdw->desired_stream_type) {
3244 /* Handle any side effects of stream config here */
3245 hdw->active_stream_type = hdw->desired_stream_type;
3246 }
3247
1df59f0b
MI		 3248 if (hdw->hdw_desc->signal_routing_scheme ==
3249 PVR2_ROUTING_SCHEME_GOTVIEW) {
3250 u32 b;
3251 /* Handle GOTVIEW audio switching */
3252 pvr2_hdw_gpio_get_out(hdw,&b);
3253 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3254 /* Set GPIO 11 */
3255 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3256 } else {
3257 /* Clear GPIO 11 */
3258 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3259 }
3260 }
3261
e68a619a
MI		 3262 /* Check and update state for all sub-devices. */
3263 pvr2_subdev_update(hdw);
3264
75212a02 3265 hdw->tuner_updated = 0;
27764726 3266 hdw->force_dirty = 0;
5ceaad14
MI		 3267 for (idx = 0; idx < hdw->control_cnt; idx++) {
3268 cptr = hdw->controls + idx;
3269 if (!cptr->info->clear_dirty) continue;
3270 cptr->info->clear_dirty(cptr);
3271 }
3272
62433e31
MI		 3273 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3274 hdw->state_encoder_run) {
3275 /* If encoder isn't running or it can't be touched, then
3276 this will get worked out later when we start the
3277 encoder. */
681c7399
MI		 3278 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3279 }
d855497e 3280
681c7399 3281 hdw->state_pipeline_config = !0;
432907f7
MI		 3282 /* Hardware state may have changed in a way to cause the cropping
3283 capabilities to have changed. So mark it stale, which will
3284 cause a later re-fetch. */
681c7399
MI		 3285 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3286 return !0;
d855497e
MI		 3287}
3288
3289
3290int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3291{
681c7399
MI		 3292 int fl;
3293 LOCK_TAKE(hdw->big_lock);
3294 fl = pvr2_hdw_commit_setup(hdw);
3295 LOCK_GIVE(hdw->big_lock);
3296 if (!fl) return 0;
3297 return pvr2_hdw_wait(hdw,0);
3298}
3299
3300
681c7399 3301static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 3302{
681c7399
MI		 3303 int fl = 0;
3304 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 3305 LOCK_TAKE(hdw->big_lock); do {
681c7399 3306 fl = pvr2_hdw_state_eval(hdw);
d855497e 3307 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 3308 if (fl && hdw->state_func) {
3309 hdw->state_func(hdw->state_data);
3310 }
d855497e
MI		 3311}
3312
3313
681c7399 3314static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 3315{
681c7399
MI		 3316 return wait_event_interruptible(
3317 hdw->state_wait_data,
3318 (hdw->state_stale == 0) &&
3319 (!state || (hdw->master_state != state)));
3320}
3321
3322
d855497e
MI		 3323/* Return name for this driver instance */
3324const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3325{
3326 return hdw->name;
3327}
3328
3329
78a47101
MI		 3330const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3331{
3332 return hdw->hdw_desc->description;
3333}
3334
3335
3336const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3337{
3338 return hdw->hdw_desc->shortname;
3339}
3340
3341
d855497e
MI		 3342int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3343{
3344 int result;
3345 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3346 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 3347 result = pvr2_send_request(hdw,
3348 hdw->cmd_buffer,1,
3349 hdw->cmd_buffer,1);
3350 if (result < 0) break;
3351 result = (hdw->cmd_buffer[0] != 0);
3352 } while(0); LOCK_GIVE(hdw->ctl_lock);
3353 return result;
3354}
3355
3356
18103c57
MI		 3357/* Execute poll of tuner status */
3358void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 3359{
d855497e 3360 LOCK_TAKE(hdw->big_lock); do {
a51f5000 3361 pvr2_hdw_status_poll(hdw);
d855497e 3362 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 3363}
3364
3365
432907f7
MI		 3366static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3367{
3368 if (!hdw->cropcap_stale) {
432907f7
MI		 3369 return 0;
3370 }
a51f5000 3371 pvr2_hdw_status_poll(hdw);
432907f7 3372 if (hdw->cropcap_stale) {
432907f7
MI		 3373 return -EIO;
3374 }
3375 return 0;
3376}
3377
3378
3379/* Return information about cropping capabilities */
3380int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3381{
3382 int stat = 0;
3383 LOCK_TAKE(hdw->big_lock);
3384 stat = pvr2_hdw_check_cropcap(hdw);
3385 if (!stat) {
432907f7
MI		 3386 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3387 }
3388 LOCK_GIVE(hdw->big_lock);
3389 return stat;
3390}
3391
3392
18103c57
MI		 3393/* Return information about the tuner */
3394int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3395{
3396 LOCK_TAKE(hdw->big_lock); do {
3397 if (hdw->tuner_signal_stale) {
a51f5000 3398 pvr2_hdw_status_poll(hdw);
18103c57
MI		 3399 }
3400 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3401 } while (0); LOCK_GIVE(hdw->big_lock);
3402 return 0;
d855497e
MI		 3403}
3404
3405
3406/* Get handle to video output stream */
3407struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3408{
3409 return hp->vid_stream;
3410}
3411
3412
3413void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3414{
4f1a3e5b 3415 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e 3416 LOCK_TAKE(hdw->big_lock); do {
4f1a3e5b 3417 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
ed3261a8 3418 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
b30d2441 3419 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 3420 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 3421 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 3422 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 3423 } while (0); LOCK_GIVE(hdw->big_lock);
3424}
3425
4db666cc
MI		 3426
3427/* Grab EEPROM contents, needed for direct method. */
3428#define EEPROM_SIZE 8192
3429#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3430static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3431{
3432 struct i2c_msg msg[2];
3433 u8 *eeprom;
3434 u8 iadd[2];
3435 u8 addr;
3436 u16 eepromSize;
3437 unsigned int offs;
3438 int ret;
3439 int mode16 = 0;
3440 unsigned pcnt,tcnt;
3441 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3442 if (!eeprom) {
3443 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3444 "Failed to allocate memory"
3445 " required to read eeprom");
3446 return NULL;
3447 }
3448
3449 trace_eeprom("Value for eeprom addr from controller was 0x%x",
3450 hdw->eeprom_addr);
3451 addr = hdw->eeprom_addr;
3452 /* Seems that if the high bit is set, then the *real* eeprom
3453 address is shifted right now bit position (noticed this in
3454 newer PVR USB2 hardware) */
3455 if (addr & 0x80) addr >>= 1;
3456
3457 /* FX2 documentation states that a 16bit-addressed eeprom is
3458 expected if the I2C address is an odd number (yeah, this is
3459 strange but it's what they do) */
3460 mode16 = (addr & 1);
3461 eepromSize = (mode16 ? EEPROM_SIZE : 256);
3462 trace_eeprom("Examining %d byte eeprom at location 0x%x"
3463 " using %d bit addressing",eepromSize,addr,
3464 mode16 ? 16 : 8);
3465
3466 msg[0].addr = addr;
3467 msg[0].flags = 0;
3468 msg[0].len = mode16 ? 2 : 1;
3469 msg[0].buf = iadd;
3470 msg[1].addr = addr;
3471 msg[1].flags = I2C_M_RD;
3472
3473 /* We have to do the actual eeprom data fetch ourselves, because
3474 (1) we're only fetching part of the eeprom, and (2) if we were
3475 getting the whole thing our I2C driver can't grab it in one
3476 pass - which is what tveeprom is otherwise going to attempt */
3477 memset(eeprom,0,EEPROM_SIZE);
3478 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3479 pcnt = 16;
3480 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3481 offs = tcnt + (eepromSize - EEPROM_SIZE);
3482 if (mode16) {
3483 iadd[0] = offs >> 8;
3484 iadd[1] = offs;
3485 } else {
3486 iadd[0] = offs;
3487 }
3488 msg[1].len = pcnt;
3489 msg[1].buf = eeprom+tcnt;
3490 if ((ret = i2c_transfer(&hdw->i2c_adap,
3491 msg,ARRAY_SIZE(msg))) != 2) {
3492 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3493 "eeprom fetch set offs err=%d",ret);
3494 kfree(eeprom);
3495 return NULL;
3496 }
3497 }
3498 return eeprom;
3499}
3500
3501
3502void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3503 int prom_flag,
3504 int enable_flag)
d855497e
MI		 3505{
3506 int ret;
3507 u16 address;
3508 unsigned int pipe;
3509 LOCK_TAKE(hdw->big_lock); do {
5fa1247a 3510 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
d855497e
MI		 3511
3512 if (!enable_flag) {
3513 pvr2_trace(PVR2_TRACE_FIRMWARE,
3514 "Cleaning up after CPU firmware fetch");
3515 kfree(hdw->fw_buffer);
a0fd1cb1 3516 hdw->fw_buffer = NULL;
d855497e 3517 hdw->fw_size = 0;
4db666cc
MI		 3518 if (hdw->fw_cpu_flag) {
3519 /* Now release the CPU. It will disconnect
3520 and reconnect later. */
3521 pvr2_hdw_cpureset_assert(hdw,0);
3522 }
d855497e
MI		 3523 break;
3524 }
3525
4db666cc
MI		 3526 hdw->fw_cpu_flag = (prom_flag == 0);
3527 if (hdw->fw_cpu_flag) {
3528 pvr2_trace(PVR2_TRACE_FIRMWARE,
3529 "Preparing to suck out CPU firmware");
3530 hdw->fw_size = 0x2000;
3531 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3532 if (!hdw->fw_buffer) {
3533 hdw->fw_size = 0;
3534 break;
3535 }
d855497e 3536
4db666cc
MI		 3537 /* We have to hold the CPU during firmware upload. */
3538 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 3539
4db666cc
MI		 3540 /* download the firmware from address 0000-1fff in 2048
3541 (=0x800) bytes chunk. */
d855497e 3542
4db666cc
MI		 3543 pvr2_trace(PVR2_TRACE_FIRMWARE,
3544 "Grabbing CPU firmware");
3545 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3546 for(address = 0; address < hdw->fw_size;
3547 address += 0x800) {
3548 ret = usb_control_msg(hdw->usb_dev,pipe,
3549 0xa0,0xc0,
3550 address,0,
3551 hdw->fw_buffer+address,
3552 0x800,HZ);
3553 if (ret < 0) break;
3554 }
d855497e 3555
4db666cc
MI		 3556 pvr2_trace(PVR2_TRACE_FIRMWARE,
3557 "Done grabbing CPU firmware");
3558 } else {
3559 pvr2_trace(PVR2_TRACE_FIRMWARE,
3560 "Sucking down EEPROM contents");
3561 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3562 if (!hdw->fw_buffer) {
3563 pvr2_trace(PVR2_TRACE_FIRMWARE,
3564 "EEPROM content suck failed.");
3565 break;
3566 }
3567 hdw->fw_size = EEPROM_SIZE;
3568 pvr2_trace(PVR2_TRACE_FIRMWARE,
3569 "Done sucking down EEPROM contents");
3570 }
d855497e
MI		 3571
3572 } while (0); LOCK_GIVE(hdw->big_lock);
3573}
3574
3575
3576/* Return true if we're in a mode for retrieval CPU firmware */
3577int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3578{
5fa1247a 3579 return hdw->fw_buffer != NULL;
d855497e
MI		 3580}
3581
3582
3583int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3584 char *buf,unsigned int cnt)
3585{
3586 int ret = -EINVAL;
3587 LOCK_TAKE(hdw->big_lock); do {
3588 if (!buf) break;
3589 if (!cnt) break;
3590
3591 if (!hdw->fw_buffer) {
3592 ret = -EIO;
3593 break;
3594 }
3595
3596 if (offs >= hdw->fw_size) {
3597 pvr2_trace(PVR2_TRACE_FIRMWARE,
3598 "Read firmware data offs=%d EOF",
3599 offs);
3600 ret = 0;
3601 break;
3602 }
3603
3604 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3605
3606 memcpy(buf,hdw->fw_buffer+offs,cnt);
3607
3608 pvr2_trace(PVR2_TRACE_FIRMWARE,
3609 "Read firmware data offs=%d cnt=%d",
3610 offs,cnt);
3611 ret = cnt;
3612 } while (0); LOCK_GIVE(hdw->big_lock);
3613
3614 return ret;
3615}
3616
3617
fd5a75fe 3618int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 3619 enum pvr2_v4l_type index)
d855497e 3620{
fd5a75fe 3621 switch (index) {
8079384e
MI		 3622 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3623 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3624 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 3625 default: return -1;
3626 }
d855497e
MI		 3627}
3628
3629
2fdf3d9c 3630/* Store a v4l minor device number */
fd5a75fe 3631void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 3632 enum pvr2_v4l_type index,int v)
d855497e 3633{
fd5a75fe 3634 switch (index) {
8079384e
MI		 3635 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3636 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3637 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 3638 default: break;
3639 }
d855497e
MI		 3640}
3641
3642
7d12e780 3643static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 3644{
3645 struct pvr2_hdw *hdw = urb->context;
3646 hdw->ctl_write_pend_flag = 0;
3647 if (hdw->ctl_read_pend_flag) return;
3648 complete(&hdw->ctl_done);
3649}
3650
3651
7d12e780 3652static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 3653{
3654 struct pvr2_hdw *hdw = urb->context;
3655 hdw->ctl_read_pend_flag = 0;
3656 if (hdw->ctl_write_pend_flag) return;
3657 complete(&hdw->ctl_done);
3658}
3659
3660
3661static void pvr2_ctl_timeout(unsigned long data)
3662{
3663 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3664 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3665 hdw->ctl_timeout_flag = !0;
5e55d2ce 3666 if (hdw->ctl_write_pend_flag)
d855497e 3667 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 3668 if (hdw->ctl_read_pend_flag)
d855497e 3669 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 3670 }
3671}
3672
3673
e61b6fc5
MI		 3674/* Issue a command and get a response from the device. This extended
3675 version includes a probe flag (which if set means that device errors
3676 should not be logged or treated as fatal) and a timeout in jiffies.
3677 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 3678static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3679 unsigned int timeout,int probe_fl,
3680 void *write_data,unsigned int write_len,
3681 void *read_data,unsigned int read_len)
d855497e
MI		 3682{
3683 unsigned int idx;
3684 int status = 0;
3685 struct timer_list timer;
3686 if (!hdw->ctl_lock_held) {
3687 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3688 "Attempted to execute control transfer"
3689 " without lock!!");
3690 return -EDEADLK;
3691 }
681c7399 3692 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 3693 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3694 "Attempted to execute control transfer"
3695 " when device not ok");
3696 return -EIO;
3697 }
3698 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3699 if (!probe_fl) {
3700 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3701 "Attempted to execute control transfer"
3702 " when USB is disconnected");
3703 }
3704 return -ENOTTY;
3705 }
3706
3707 /* Ensure that we have sane parameters */
3708 if (!write_data) write_len = 0;
3709 if (!read_data) read_len = 0;
3710 if (write_len > PVR2_CTL_BUFFSIZE) {
3711 pvr2_trace(
3712 PVR2_TRACE_ERROR_LEGS,
3713 "Attempted to execute %d byte"
3714 " control-write transfer (limit=%d)",
3715 write_len,PVR2_CTL_BUFFSIZE);
3716 return -EINVAL;
3717 }
3718 if (read_len > PVR2_CTL_BUFFSIZE) {
3719 pvr2_trace(
3720 PVR2_TRACE_ERROR_LEGS,
3721 "Attempted to execute %d byte"
3722 " control-read transfer (limit=%d)",
3723 write_len,PVR2_CTL_BUFFSIZE);
3724 return -EINVAL;
3725 }
3726 if ((!write_len) && (!read_len)) {
3727 pvr2_trace(
3728 PVR2_TRACE_ERROR_LEGS,
3729 "Attempted to execute null control transfer?");
3730 return -EINVAL;
3731 }
3732
3733
3734 hdw->cmd_debug_state = 1;
3735 if (write_len) {
3736 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3737 } else {
3738 hdw->cmd_debug_code = 0;
3739 }
3740 hdw->cmd_debug_write_len = write_len;
3741 hdw->cmd_debug_read_len = read_len;
3742
3743 /* Initialize common stuff */
3744 init_completion(&hdw->ctl_done);
3745 hdw->ctl_timeout_flag = 0;
3746 hdw->ctl_write_pend_flag = 0;
3747 hdw->ctl_read_pend_flag = 0;
3748 init_timer(&timer);
3749 timer.expires = jiffies + timeout;
3750 timer.data = (unsigned long)hdw;
3751 timer.function = pvr2_ctl_timeout;
3752
3753 if (write_len) {
3754 hdw->cmd_debug_state = 2;
3755 /* Transfer write data to internal buffer */
3756 for (idx = 0; idx < write_len; idx++) {
3757 hdw->ctl_write_buffer[idx] =
3758 ((unsigned char *)write_data)[idx];
3759 }
3760 /* Initiate a write request */
3761 usb_fill_bulk_urb(hdw->ctl_write_urb,
3762 hdw->usb_dev,
3763 usb_sndbulkpipe(hdw->usb_dev,
3764 PVR2_CTL_WRITE_ENDPOINT),
3765 hdw->ctl_write_buffer,
3766 write_len,
3767 pvr2_ctl_write_complete,
3768 hdw);
3769 hdw->ctl_write_urb->actual_length = 0;
3770 hdw->ctl_write_pend_flag = !0;
3771 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3772 if (status < 0) {
3773 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3774 "Failed to submit write-control"
3775 " URB status=%d",status);
3776 hdw->ctl_write_pend_flag = 0;
3777 goto done;
3778 }
3779 }
3780
3781 if (read_len) {
3782 hdw->cmd_debug_state = 3;
3783 memset(hdw->ctl_read_buffer,0x43,read_len);
3784 /* Initiate a read request */
3785 usb_fill_bulk_urb(hdw->ctl_read_urb,
3786 hdw->usb_dev,
3787 usb_rcvbulkpipe(hdw->usb_dev,
3788 PVR2_CTL_READ_ENDPOINT),
3789 hdw->ctl_read_buffer,
3790 read_len,
3791 pvr2_ctl_read_complete,
3792 hdw);
3793 hdw->ctl_read_urb->actual_length = 0;
3794 hdw->ctl_read_pend_flag = !0;
3795 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3796 if (status < 0) {
3797 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3798 "Failed to submit read-control"
3799 " URB status=%d",status);
3800 hdw->ctl_read_pend_flag = 0;
3801 goto done;
3802 }
3803 }
3804
3805 /* Start timer */
3806 add_timer(&timer);
3807
3808 /* Now wait for all I/O to complete */
3809 hdw->cmd_debug_state = 4;
3810 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3811 wait_for_completion(&hdw->ctl_done);
3812 }
3813 hdw->cmd_debug_state = 5;
3814
3815 /* Stop timer */
3816 del_timer_sync(&timer);
3817
3818 hdw->cmd_debug_state = 6;
3819 status = 0;
3820
3821 if (hdw->ctl_timeout_flag) {
3822 status = -ETIMEDOUT;
3823 if (!probe_fl) {
3824 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3825 "Timed out control-write");
3826 }
3827 goto done;
3828 }
3829
3830 if (write_len) {
3831 /* Validate results of write request */
3832 if ((hdw->ctl_write_urb->status != 0) &&
3833 (hdw->ctl_write_urb->status != -ENOENT) &&
3834 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3835 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3836 /* USB subsystem is reporting some kind of failure
3837 on the write */
3838 status = hdw->ctl_write_urb->status;
3839 if (!probe_fl) {
3840 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3841 "control-write URB failure,"
3842 " status=%d",
3843 status);
3844 }
3845 goto done;
3846 }
3847 if (hdw->ctl_write_urb->actual_length < write_len) {
3848 /* Failed to write enough data */
3849 status = -EIO;
3850 if (!probe_fl) {
3851 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3852 "control-write URB short,"
3853 " expected=%d got=%d",
3854 write_len,
3855 hdw->ctl_write_urb->actual_length);
3856 }
3857 goto done;
3858 }
3859 }
3860 if (read_len) {
3861 /* Validate results of read request */
3862 if ((hdw->ctl_read_urb->status != 0) &&
3863 (hdw->ctl_read_urb->status != -ENOENT) &&
3864 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3865 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3866 /* USB subsystem is reporting some kind of failure
3867 on the read */
3868 status = hdw->ctl_read_urb->status;
3869 if (!probe_fl) {
3870 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3871 "control-read URB failure,"
3872 " status=%d",
3873 status);
3874 }
3875 goto done;
3876 }
3877 if (hdw->ctl_read_urb->actual_length < read_len) {
3878 /* Failed to read enough data */
3879 status = -EIO;
3880 if (!probe_fl) {
3881 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3882 "control-read URB short,"
3883 " expected=%d got=%d",
3884 read_len,
3885 hdw->ctl_read_urb->actual_length);
3886 }
3887 goto done;
3888 }
3889 /* Transfer retrieved data out from internal buffer */
3890 for (idx = 0; idx < read_len; idx++) {
3891 ((unsigned char *)read_data)[idx] =
3892 hdw->ctl_read_buffer[idx];
3893 }
3894 }
3895
3896 done:
3897
3898 hdw->cmd_debug_state = 0;
3899 if ((status < 0) && (!probe_fl)) {
681c7399 3900 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3901 }
3902 return status;
3903}
3904
3905
3906int pvr2_send_request(struct pvr2_hdw *hdw,
3907 void *write_data,unsigned int write_len,
3908 void *read_data,unsigned int read_len)
3909{
3910 return pvr2_send_request_ex(hdw,HZ*4,0,
3911 write_data,write_len,
3912 read_data,read_len);
3913}
3914
1c9d10d4
MI		 3915
3916static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3917{
3918 int ret;
3919 unsigned int cnt = 1;
3920 unsigned int args = 0;
3921 LOCK_TAKE(hdw->ctl_lock);
3922 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3923 args = (cmdcode >> 8) & 0xffu;
3924 args = (args > 2) ? 2 : args;
3925 if (args) {
3926 cnt += args;
3927 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3928 if (args > 1) {
3929 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3930 }
3931 }
3932 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3933 unsigned int idx;
3934 unsigned int ccnt,bcnt;
3935 char tbuf[50];
3936 cmdcode &= 0xffu;
3937 bcnt = 0;
3938 ccnt = scnprintf(tbuf+bcnt,
3939 sizeof(tbuf)-bcnt,
3940 "Sending FX2 command 0x%x",cmdcode);
3941 bcnt += ccnt;
3942 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3943 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3944 ccnt = scnprintf(tbuf+bcnt,
3945 sizeof(tbuf)-bcnt,
3946 " \"%s\"",
3947 pvr2_fx2cmd_desc[idx].desc);
3948 bcnt += ccnt;
3949 break;
3950 }
3951 }
3952 if (args) {
3953 ccnt = scnprintf(tbuf+bcnt,
3954 sizeof(tbuf)-bcnt,
3955 " (%u",hdw->cmd_buffer[1]);
3956 bcnt += ccnt;
3957 if (args > 1) {
3958 ccnt = scnprintf(tbuf+bcnt,
3959 sizeof(tbuf)-bcnt,
3960 ",%u",hdw->cmd_buffer[2]);
3961 bcnt += ccnt;
3962 }
3963 ccnt = scnprintf(tbuf+bcnt,
3964 sizeof(tbuf)-bcnt,
3965 ")");
3966 bcnt += ccnt;
3967 }
3968 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3969 }
3970 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3971 LOCK_GIVE(hdw->ctl_lock);
3972 return ret;
3973}
3974
3975
d855497e
MI		 3976int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3977{
3978 int ret;
3979
3980 LOCK_TAKE(hdw->ctl_lock);
3981
8d364363 3982 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 3983 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3984 hdw->cmd_buffer[5] = 0;
3985 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3986 hdw->cmd_buffer[7] = reg & 0xff;
3987
3988
3989 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3990
3991 LOCK_GIVE(hdw->ctl_lock);
3992
3993 return ret;
3994}
3995
3996
07e337ee 3997static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 3998{
3999 int ret = 0;
4000
4001 LOCK_TAKE(hdw->ctl_lock);
4002
8d364363 4003 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 4004 hdw->cmd_buffer[1] = 0;
4005 hdw->cmd_buffer[2] = 0;
4006 hdw->cmd_buffer[3] = 0;
4007 hdw->cmd_buffer[4] = 0;
4008 hdw->cmd_buffer[5] = 0;
4009 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4010 hdw->cmd_buffer[7] = reg & 0xff;
4011
4012 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
4013 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
4014
4015 LOCK_GIVE(hdw->ctl_lock);
4016
4017 return ret;
4018}
4019
4020
681c7399 4021void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 4022{
4023 if (!hdw->flag_ok) return;
681c7399
MI		 4024 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4025 "Device being rendered inoperable");
d855497e 4026 if (hdw->vid_stream) {
a0fd1cb1 4027 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 4028 }
681c7399
MI		 4029 hdw->flag_ok = 0;
4030 trace_stbit("flag_ok",hdw->flag_ok);
4031 pvr2_hdw_state_sched(hdw);
d855497e
MI		 4032}
4033
4034
4035void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4036{
4037 int ret;
4038 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 4039 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
011b15df 4040 if (ret == 0) {
d855497e
MI		 4041 ret = usb_reset_device(hdw->usb_dev);
4042 usb_unlock_device(hdw->usb_dev);
4043 } else {
4044 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4045 "Failed to lock USB device ret=%d",ret);
4046 }
4047 if (init_pause_msec) {
4048 pvr2_trace(PVR2_TRACE_INFO,
4049 "Waiting %u msec for hardware to settle",
4050 init_pause_msec);
4051 msleep(init_pause_msec);
4052 }
4053
4054}
4055
4056
4057void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4058{
4059 char da[1];
4060 unsigned int pipe;
4061 int ret;
4062
4063 if (!hdw->usb_dev) return;
4064
4065 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4066
4067 da[0] = val ? 0x01 : 0x00;
4068
4069 /* Write the CPUCS register on the 8051. The lsb of the register
4070 is the reset bit; a 1 asserts reset while a 0 clears it. */
4071 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4072 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4073 if (ret < 0) {
4074 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4075 "cpureset_assert(%d) error=%d",val,ret);
4076 pvr2_hdw_render_useless(hdw);
4077 }
4078}
4079
4080
4081int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4082{
1c9d10d4 4083 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
d855497e
MI		 4084}
4085
4086
e1edb19a
MK		 4087int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4088{
1c9d10d4 4089 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
e1edb19a
MK		 4090}
4091
1c9d10d4 4092
e1edb19a
MK		 4093int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4094{
1c9d10d4 4095 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
e1edb19a
MK		 4096}
4097
d855497e
MI		 4098
4099int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4100{
af78e16b
MI		 4101 pvr2_trace(PVR2_TRACE_INIT,
4102 "Requesting decoder reset");
af78e16b
MI		 4103 if (hdw->decoder_client_id) {
4104 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4105 core, reset, 0);
e17d787c 4106 pvr2_hdw_cx25840_vbi_hack(hdw);
af78e16b 4107 return 0;
d855497e 4108 }
d855497e 4109 pvr2_trace(PVR2_TRACE_INIT,
af78e16b
MI		 4110 "Unable to reset decoder: nothing attached");
4111 return -ENOTTY;
d855497e
MI		 4112}
4113
4114
62433e31 4115static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
84147f3d 4116{
1c9d10d4
MI		 4117 hdw->flag_ok = !0;
4118 return pvr2_issue_simple_cmd(hdw,
4119 FX2CMD_HCW_DEMOD_RESETIN |
4120 (1 << 8) |
4121 ((onoff ? 1 : 0) << 16));
84147f3d
MI		 4122}
4123
84147f3d 4124
62433e31 4125static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
84147f3d 4126{
1c9d10d4
MI		 4127 hdw->flag_ok = !0;
4128 return pvr2_issue_simple_cmd(hdw,(onoff ?
4129 FX2CMD_ONAIR_DTV_POWER_ON :
4130 FX2CMD_ONAIR_DTV_POWER_OFF));
84147f3d
MI		 4131}
4132
62433e31
MI		 4133
4134static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4135 int onoff)
84147f3d 4136{
1c9d10d4
MI		 4137 return pvr2_issue_simple_cmd(hdw,(onoff ?
4138 FX2CMD_ONAIR_DTV_STREAMING_ON :
4139 FX2CMD_ONAIR_DTV_STREAMING_OFF));
84147f3d
MI		 4140}
4141
62433e31
MI		 4142
4143static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4144{
4145 int cmode;
4146 /* Compare digital/analog desired setting with current setting. If
4147 they don't match, fix it... */
4148 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4149 if (cmode == hdw->pathway_state) {
4150 /* They match; nothing to do */
4151 return;
4152 }
4153
4154 switch (hdw->hdw_desc->digital_control_scheme) {
4155 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4156 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4157 if (cmode == PVR2_PATHWAY_ANALOG) {
4158 /* If moving to analog mode, also force the decoder
4159 to reset. If no decoder is attached, then it's
4160 ok to ignore this because if/when the decoder
4161 attaches, it will reset itself at that time. */
4162 pvr2_hdw_cmd_decoder_reset(hdw);
4163 }
4164 break;
4165 case PVR2_DIGITAL_SCHEME_ONAIR:
4166 /* Supposedly we should always have the power on whether in
4167 digital or analog mode. But for now do what appears to
4168 work... */
bb0c2fe0 4169 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
62433e31
MI		 4170 break;
4171 default: break;
4172 }
4173
1b9c18c5 4174 pvr2_hdw_untrip_unlocked(hdw);
62433e31
MI		 4175 hdw->pathway_state = cmode;
4176}
4177
4178
e9b59f6e 4179static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
c55a97d7
MI		 4180{
4181 /* change some GPIO data
4182 *
4183 * note: bit d7 of dir appears to control the LED,
4184 * so we shut it off here.
4185 *
c55a97d7 4186 */
40381cb0 4187 if (onoff) {
c55a97d7 4188 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
40381cb0 4189 } else {
c55a97d7 4190 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
40381cb0 4191 }
c55a97d7 4192 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
40381cb0 4193}
c55a97d7 4194
40381cb0
MI		 4195
4196typedef void (*led_method_func)(struct pvr2_hdw *,int);
4197
4198static led_method_func led_methods[] = {
4199 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4200};
4201
4202
4203/* Toggle LED */
4204static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4205{
4206 unsigned int scheme_id;
4207 led_method_func fp;
4208
4209 if ((!onoff) == (!hdw->led_on)) return;
4210
4211 hdw->led_on = onoff != 0;
4212
4213 scheme_id = hdw->hdw_desc->led_scheme;
4214 if (scheme_id < ARRAY_SIZE(led_methods)) {
4215 fp = led_methods[scheme_id];
4216 } else {
4217 fp = NULL;
4218 }
4219
4220 if (fp) (*fp)(hdw,onoff);
c55a97d7
MI		 4221}
4222
4223
e61b6fc5 4224/* Stop / start video stream transport */
07e337ee 4225static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e 4226{
bb0c2fe0
MI		 4227 int ret;
4228
4229 /* If we're in analog mode, then just issue the usual analog
4230 command. */
4231 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4232 return pvr2_issue_simple_cmd(hdw,
4233 (runFl ?
4234 FX2CMD_STREAMING_ON :
4235 FX2CMD_STREAMING_OFF));
4236 /*Note: Not reached */
4237 }
4238
4239 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4240 /* Whoops, we don't know what mode we're in... */
4241 return -EINVAL;
4242 }
4243
4244 /* To get here we have to be in digital mode. The mechanism here
4245 is unfortunately different for different vendors. So we switch
4246 on the device's digital scheme attribute in order to figure out
4247 what to do. */
4248 switch (hdw->hdw_desc->digital_control_scheme) {
4249 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4250 return pvr2_issue_simple_cmd(hdw,
4251 (runFl ?
4252 FX2CMD_HCW_DTV_STREAMING_ON :
4253 FX2CMD_HCW_DTV_STREAMING_OFF));
4254 case PVR2_DIGITAL_SCHEME_ONAIR:
4255 ret = pvr2_issue_simple_cmd(hdw,
4256 (runFl ?
4257 FX2CMD_STREAMING_ON :
4258 FX2CMD_STREAMING_OFF));
4259 if (ret) return ret;
4260 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4261 default:
4262 return -EINVAL;
62433e31 4263 }
d855497e
MI		 4264}
4265
4266
62433e31
MI		 4267/* Evaluate whether or not state_pathway_ok can change */
4268static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4269{
4270 if (hdw->state_pathway_ok) {
4271 /* Nothing to do if pathway is already ok */
4272 return 0;
4273 }
4274 if (!hdw->state_pipeline_idle) {
4275 /* Not allowed to change anything if pipeline is not idle */
4276 return 0;
4277 }
4278 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4279 hdw->state_pathway_ok = !0;
e9db1ff2 4280 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 4281 return !0;
4282}
4283
4284
681c7399
MI		 4285/* Evaluate whether or not state_encoder_ok can change */
4286static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4287{
4288 if (hdw->state_encoder_ok) return 0;
4289 if (hdw->flag_tripped) return 0;
4290 if (hdw->state_encoder_run) return 0;
4291 if (hdw->state_encoder_config) return 0;
4292 if (hdw->state_decoder_run) return 0;
4293 if (hdw->state_usbstream_run) return 0;
72998b71
MI		 4294 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4295 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4296 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4297 return 0;
4298 }
4299
681c7399
MI		 4300 if (pvr2_upload_firmware2(hdw) < 0) {
4301 hdw->flag_tripped = !0;
4302 trace_stbit("flag_tripped",hdw->flag_tripped);
4303 return !0;
4304 }
4305 hdw->state_encoder_ok = !0;
4306 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4307 return !0;
4308}
4309
4310
4311/* Evaluate whether or not state_encoder_config can change */
4312static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4313{
4314 if (hdw->state_encoder_config) {
4315 if (hdw->state_encoder_ok) {
4316 if (hdw->state_pipeline_req &&
4317 !hdw->state_pipeline_pause) return 0;
4318 }
4319 hdw->state_encoder_config = 0;
4320 hdw->state_encoder_waitok = 0;
4321 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4322 /* paranoia - solve race if timer just completed */
4323 del_timer_sync(&hdw->encoder_wait_timer);
4324 } else {
62433e31
MI		 4325 if (!hdw->state_pathway_ok ||
4326 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4327 !hdw->state_encoder_ok ||
681c7399
MI		 4328 !hdw->state_pipeline_idle ||
4329 hdw->state_pipeline_pause ||
4330 !hdw->state_pipeline_req ||
4331 !hdw->state_pipeline_config) {
4332 /* We must reset the enforced wait interval if
4333 anything has happened that might have disturbed
4334 the encoder. This should be a rare case. */
4335 if (timer_pending(&hdw->encoder_wait_timer)) {
4336 del_timer_sync(&hdw->encoder_wait_timer);
4337 }
4338 if (hdw->state_encoder_waitok) {
4339 /* Must clear the state - therefore we did
4340 something to a state bit and must also
4341 return true. */
4342 hdw->state_encoder_waitok = 0;
4343 trace_stbit("state_encoder_waitok",
4344 hdw->state_encoder_waitok);
4345 return !0;
4346 }
4347 return 0;
4348 }
4349 if (!hdw->state_encoder_waitok) {
4350 if (!timer_pending(&hdw->encoder_wait_timer)) {
4351 /* waitok flag wasn't set and timer isn't
4352 running. Check flag once more to avoid
4353 a race then start the timer. This is
4354 the point when we measure out a minimal
4355 quiet interval before doing something to
4356 the encoder. */
4357 if (!hdw->state_encoder_waitok) {
4358 hdw->encoder_wait_timer.expires =
83ce57aa
MI		 4359 jiffies +
4360 (HZ * TIME_MSEC_ENCODER_WAIT
4361 / 1000);
681c7399
MI		 4362 add_timer(&hdw->encoder_wait_timer);
4363 }
4364 }
4365 /* We can't continue until we know we have been
4366 quiet for the interval measured by this
4367 timer. */
4368 return 0;
4369 }
4370 pvr2_encoder_configure(hdw);
4371 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4372 }
4373 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4374 return !0;
4375}
4376
4377
d913d630
MI		 4378/* Return true if the encoder should not be running. */
4379static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4380{
4381 if (!hdw->state_encoder_ok) {
4382 /* Encoder isn't healthy at the moment, so stop it. */
4383 return !0;
4384 }
4385 if (!hdw->state_pathway_ok) {
4386 /* Mode is not understood at the moment (i.e. it wants to
4387 change), so encoder must be stopped. */
4388 return !0;
4389 }
4390
4391 switch (hdw->pathway_state) {
4392 case PVR2_PATHWAY_ANALOG:
4393 if (!hdw->state_decoder_run) {
4394 /* We're in analog mode and the decoder is not
4395 running; thus the encoder should be stopped as
4396 well. */
4397 return !0;
4398 }
4399 break;
4400 case PVR2_PATHWAY_DIGITAL:
4401 if (hdw->state_encoder_runok) {
4402 /* This is a funny case. We're in digital mode so
4403 really the encoder should be stopped. However
4404 if it really is running, only kill it after
4405 runok has been set. This gives a chance for the
4406 onair quirk to function (encoder must run
4407 briefly first, at least once, before onair
4408 digital streaming can work). */
4409 return !0;
4410 }
4411 break;
4412 default:
4413 /* Unknown mode; so encoder should be stopped. */
4414 return !0;
4415 }
4416
4417 /* If we get here, we haven't found a reason to stop the
4418 encoder. */
4419 return 0;
4420}
4421
4422
4423/* Return true if the encoder should be running. */
4424static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4425{
4426 if (!hdw->state_encoder_ok) {
4427 /* Don't run the encoder if it isn't healthy... */
4428 return 0;
4429 }
4430 if (!hdw->state_pathway_ok) {
4431 /* Don't run the encoder if we don't (yet) know what mode
4432 we need to be in... */
4433 return 0;
4434 }
4435
4436 switch (hdw->pathway_state) {
4437 case PVR2_PATHWAY_ANALOG:
4438 if (hdw->state_decoder_run) {
4439 /* In analog mode, if the decoder is running, then
4440 run the encoder. */
4441 return !0;
4442 }
4443 break;
4444 case PVR2_PATHWAY_DIGITAL:
4445 if ((hdw->hdw_desc->digital_control_scheme ==
4446 PVR2_DIGITAL_SCHEME_ONAIR) &&
4447 !hdw->state_encoder_runok) {
4448 /* This is a quirk. OnAir hardware won't stream
4449 digital until the encoder has been run at least
4450 once, for a minimal period of time (empiricially
4451 measured to be 1/4 second). So if we're on
4452 OnAir hardware and the encoder has never been
4453 run at all, then start the encoder. Normal
4454 state machine logic in the driver will
4455 automatically handle the remaining bits. */
4456 return !0;
4457 }
4458 break;
4459 default:
4460 /* For completeness (unknown mode; encoder won't run ever) */
4461 break;
4462 }
4463 /* If we get here, then we haven't found any reason to run the
4464 encoder, so don't run it. */
4465 return 0;
4466}
4467
4468
681c7399
MI		 4469/* Evaluate whether or not state_encoder_run can change */
4470static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4471{
4472 if (hdw->state_encoder_run) {
d913d630 4473 if (!state_check_disable_encoder_run(hdw)) return 0;
681c7399 4474 if (hdw->state_encoder_ok) {
d913d630 4475 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 4476 if (pvr2_encoder_stop(hdw) < 0) return !0;
4477 }
4478 hdw->state_encoder_run = 0;
4479 } else {
d913d630 4480 if (!state_check_enable_encoder_run(hdw)) return 0;
681c7399
MI		 4481 if (pvr2_encoder_start(hdw) < 0) return !0;
4482 hdw->state_encoder_run = !0;
d913d630
MI		 4483 if (!hdw->state_encoder_runok) {
4484 hdw->encoder_run_timer.expires =
83ce57aa 4485 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
d913d630
MI		 4486 add_timer(&hdw->encoder_run_timer);
4487 }
681c7399
MI		 4488 }
4489 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4490 return !0;
4491}
4492
4493
4494/* Timeout function for quiescent timer. */
4495static void pvr2_hdw_quiescent_timeout(unsigned long data)
4496{
4497 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4498 hdw->state_decoder_quiescent = !0;
4499 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4500 hdw->state_stale = !0;
4501 queue_work(hdw->workqueue,&hdw->workpoll);
4502}
4503
4504
4505/* Timeout function for encoder wait timer. */
4506static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4507{
4508 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4509 hdw->state_encoder_waitok = !0;
4510 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4511 hdw->state_stale = !0;
4512 queue_work(hdw->workqueue,&hdw->workpoll);
4513}
4514
4515
d913d630
MI		 4516/* Timeout function for encoder run timer. */
4517static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4518{
4519 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4520 if (!hdw->state_encoder_runok) {
4521 hdw->state_encoder_runok = !0;
4522 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4523 hdw->state_stale = !0;
4524 queue_work(hdw->workqueue,&hdw->workpoll);
4525 }
4526}
4527
4528
681c7399
MI		 4529/* Evaluate whether or not state_decoder_run can change */
4530static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4531{
4532 if (hdw->state_decoder_run) {
4533 if (hdw->state_encoder_ok) {
4534 if (hdw->state_pipeline_req &&
62433e31
MI		 4535 !hdw->state_pipeline_pause &&
4536 hdw->state_pathway_ok) return 0;
681c7399
MI		 4537 }
4538 if (!hdw->flag_decoder_missed) {
4539 pvr2_decoder_enable(hdw,0);
4540 }
4541 hdw->state_decoder_quiescent = 0;
4542 hdw->state_decoder_run = 0;
4543 /* paranoia - solve race if timer just completed */
4544 del_timer_sync(&hdw->quiescent_timer);
4545 } else {
4546 if (!hdw->state_decoder_quiescent) {
4547 if (!timer_pending(&hdw->quiescent_timer)) {
4548 /* We don't do something about the
4549 quiescent timer until right here because
4550 we also want to catch cases where the
4551 decoder was already not running (like
4552 after initialization) as opposed to
4553 knowing that we had just stopped it.
4554 The second flag check is here to cover a
4555 race - the timer could have run and set
4556 this flag just after the previous check
4557 but before we did the pending check. */
4558 if (!hdw->state_decoder_quiescent) {
4559 hdw->quiescent_timer.expires =
83ce57aa
MI		 4560 jiffies +
4561 (HZ * TIME_MSEC_DECODER_WAIT
4562 / 1000);
681c7399
MI		 4563 add_timer(&hdw->quiescent_timer);
4564 }
4565 }
4566 /* Don't allow decoder to start again until it has
4567 been quiesced first. This little detail should
4568 hopefully further stabilize the encoder. */
4569 return 0;
4570 }
62433e31
MI		 4571 if (!hdw->state_pathway_ok ||
4572 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4573 !hdw->state_pipeline_req ||
681c7399
MI		 4574 hdw->state_pipeline_pause ||
4575 !hdw->state_pipeline_config ||
4576 !hdw->state_encoder_config ||
4577 !hdw->state_encoder_ok) return 0;
4578 del_timer_sync(&hdw->quiescent_timer);
4579 if (hdw->flag_decoder_missed) return 0;
4580 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4581 hdw->state_decoder_quiescent = 0;
4582 hdw->state_decoder_run = !0;
4583 }
4584 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4585 trace_stbit("state_decoder_run",hdw->state_decoder_run);
4586 return !0;
4587}
4588
4589
4590/* Evaluate whether or not state_usbstream_run can change */
4591static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4592{
4593 if (hdw->state_usbstream_run) {
72998b71 4594 int fl = !0;
62433e31 4595 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
72998b71
MI		 4596 fl = (hdw->state_encoder_ok &&
4597 hdw->state_encoder_run);
4598 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4599 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4600 fl = hdw->state_encoder_ok;
4601 }
4602 if (fl &&
4603 hdw->state_pipeline_req &&
4604 !hdw->state_pipeline_pause &&
4605 hdw->state_pathway_ok) {
4606 return 0;
681c7399
MI		 4607 }
4608 pvr2_hdw_cmd_usbstream(hdw,0);
4609 hdw->state_usbstream_run = 0;
4610 } else {
62433e31
MI		 4611 if (!hdw->state_pipeline_req ||
4612 hdw->state_pipeline_pause ||
4613 !hdw->state_pathway_ok) return 0;
4614 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4615 if (!hdw->state_encoder_ok ||
4616 !hdw->state_encoder_run) return 0;
72998b71
MI		 4617 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4618 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4619 if (!hdw->state_encoder_ok) return 0;
d913d630
MI		 4620 if (hdw->state_encoder_run) return 0;
4621 if (hdw->hdw_desc->digital_control_scheme ==
4622 PVR2_DIGITAL_SCHEME_ONAIR) {
4623 /* OnAir digital receivers won't stream
4624 unless the analog encoder has run first.
4625 Why? I have no idea. But don't even
4626 try until we know the analog side is
4627 known to have run. */
4628 if (!hdw->state_encoder_runok) return 0;
4629 }
62433e31 4630 }
681c7399
MI		 4631 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4632 hdw->state_usbstream_run = !0;
4633 }
4634 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4635 return !0;
4636}
4637
4638
4639/* Attempt to configure pipeline, if needed */
4640static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4641{
4642 if (hdw->state_pipeline_config ||
4643 hdw->state_pipeline_pause) return 0;
4644 pvr2_hdw_commit_execute(hdw);
4645 return !0;
4646}
4647
4648
4649/* Update pipeline idle and pipeline pause tracking states based on other
4650 inputs. This must be called whenever the other relevant inputs have
4651 changed. */
4652static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4653{
4654 unsigned int st;
4655 int updatedFl = 0;
4656 /* Update pipeline state */
4657 st = !(hdw->state_encoder_run ||
4658 hdw->state_decoder_run ||
4659 hdw->state_usbstream_run ||
4660 (!hdw->state_decoder_quiescent));
4661 if (!st != !hdw->state_pipeline_idle) {
4662 hdw->state_pipeline_idle = st;
4663 updatedFl = !0;
4664 }
4665 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4666 hdw->state_pipeline_pause = 0;
4667 updatedFl = !0;
4668 }
4669 return updatedFl;
4670}
4671
4672
4673typedef int (*state_eval_func)(struct pvr2_hdw *);
4674
4675/* Set of functions to be run to evaluate various states in the driver. */
ebff0330 4676static const state_eval_func eval_funcs[] = {
62433e31 4677 state_eval_pathway_ok,
681c7399
MI		 4678 state_eval_pipeline_config,
4679 state_eval_encoder_ok,
4680 state_eval_encoder_config,
4681 state_eval_decoder_run,
4682 state_eval_encoder_run,
4683 state_eval_usbstream_run,
4684};
4685
4686
4687/* Process various states and return true if we did anything interesting. */
4688static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4689{
4690 unsigned int i;
4691 int state_updated = 0;
4692 int check_flag;
4693
4694 if (!hdw->state_stale) return 0;
4695 if ((hdw->fw1_state != FW1_STATE_OK) ||
4696 !hdw->flag_ok) {
4697 hdw->state_stale = 0;
4698 return !0;
4699 }
4700 /* This loop is the heart of the entire driver. It keeps trying to
4701 evaluate various bits of driver state until nothing changes for
4702 one full iteration. Each "bit of state" tracks some global
4703 aspect of the driver, e.g. whether decoder should run, if
4704 pipeline is configured, usb streaming is on, etc. We separately
4705 evaluate each of those questions based on other driver state to
4706 arrive at the correct running configuration. */
4707 do {
4708 check_flag = 0;
4709 state_update_pipeline_state(hdw);
4710 /* Iterate over each bit of state */
4711 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4712 if ((*eval_funcs[i])(hdw)) {
4713 check_flag = !0;
4714 state_updated = !0;
4715 state_update_pipeline_state(hdw);
4716 }
4717 }
4718 } while (check_flag && hdw->flag_ok);
4719 hdw->state_stale = 0;
4720 trace_stbit("state_stale",hdw->state_stale);
4721 return state_updated;
4722}
4723
4724
1cb03b76
MI		 4725static unsigned int print_input_mask(unsigned int msk,
4726 char *buf,unsigned int acnt)
4727{
4728 unsigned int idx,ccnt;
4729 unsigned int tcnt = 0;
4730 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4731 if (!((1 << idx) & msk)) continue;
4732 ccnt = scnprintf(buf+tcnt,
4733 acnt-tcnt,
4734 "%s%s",
4735 (tcnt ? ", " : ""),
4736 control_values_input[idx]);
4737 tcnt += ccnt;
4738 }
4739 return tcnt;
4740}
4741
4742
62433e31
MI		 4743static const char *pvr2_pathway_state_name(int id)
4744{
4745 switch (id) {
4746 case PVR2_PATHWAY_ANALOG: return "analog";
4747 case PVR2_PATHWAY_DIGITAL: return "digital";
4748 default: return "unknown";
4749 }
4750}
4751
4752
681c7399
MI		 4753static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4754 char *buf,unsigned int acnt)
4755{
4756 switch (which) {
4757 case 0:
4758 return scnprintf(
4759 buf,acnt,
e9db1ff2 4760 "driver:%s%s%s%s%s <mode=%s>",
681c7399
MI		 4761 (hdw->flag_ok ? " <ok>" : " <fail>"),
4762 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4763 (hdw->flag_disconnected ? " <disconnected>" :
4764 " <connected>"),
4765 (hdw->flag_tripped ? " <tripped>" : ""),
62433e31
MI		 4766 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4767 pvr2_pathway_state_name(hdw->pathway_state));
4768
681c7399
MI		 4769 case 1:
4770 return scnprintf(
4771 buf,acnt,
4772 "pipeline:%s%s%s%s",
4773 (hdw->state_pipeline_idle ? " <idle>" : ""),
4774 (hdw->state_pipeline_config ?
4775 " <configok>" : " <stale>"),
4776 (hdw->state_pipeline_req ? " <req>" : ""),
4777 (hdw->state_pipeline_pause ? " <pause>" : ""));
4778 case 2:
4779 return scnprintf(
4780 buf,acnt,
62433e31 4781 "worker:%s%s%s%s%s%s%s",
681c7399
MI		 4782 (hdw->state_decoder_run ?
4783 " <decode:run>" :
4784 (hdw->state_decoder_quiescent ?
4785 "" : " <decode:stop>")),
4786 (hdw->state_decoder_quiescent ?
4787 " <decode:quiescent>" : ""),
4788 (hdw->state_encoder_ok ?
4789 "" : " <encode:init>"),
4790 (hdw->state_encoder_run ?
d913d630
MI		 4791 (hdw->state_encoder_runok ?
4792 " <encode:run>" :
4793 " <encode:firstrun>") :
4794 (hdw->state_encoder_runok ?
4795 " <encode:stop>" :
4796 " <encode:virgin>")),
681c7399
MI		 4797 (hdw->state_encoder_config ?
4798 " <encode:configok>" :
4799 (hdw->state_encoder_waitok ?
b9a37d91 4800 "" : " <encode:waitok>")),
681c7399 4801 (hdw->state_usbstream_run ?
62433e31
MI		 4802 " <usb:run>" : " <usb:stop>"),
4803 (hdw->state_pathway_ok ?
e9db1ff2 4804 " <pathway:ok>" : ""));
681c7399
MI		 4805 case 3:
4806 return scnprintf(
4807 buf,acnt,
4808 "state: %s",
4809 pvr2_get_state_name(hdw->master_state));
ad0992e9 4810 case 4: {
1cb03b76
MI		 4811 unsigned int tcnt = 0;
4812 unsigned int ccnt;
4813
4814 ccnt = scnprintf(buf,
4815 acnt,
4816 "Hardware supported inputs: ");
4817 tcnt += ccnt;
4818 tcnt += print_input_mask(hdw->input_avail_mask,
4819 buf+tcnt,
4820 acnt-tcnt);
4821 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4822 ccnt = scnprintf(buf+tcnt,
4823 acnt-tcnt,
4824 "; allowed inputs: ");
4825 tcnt += ccnt;
4826 tcnt += print_input_mask(hdw->input_allowed_mask,
4827 buf+tcnt,
4828 acnt-tcnt);
4829 }
4830 return tcnt;
4831 }
4832 case 5: {
ad0992e9
MI		 4833 struct pvr2_stream_stats stats;
4834 if (!hdw->vid_stream) break;
4835 pvr2_stream_get_stats(hdw->vid_stream,
4836 &stats,
4837 0);
4838 return scnprintf(
4839 buf,acnt,
4840 "Bytes streamed=%u"
4841 " URBs: queued=%u idle=%u ready=%u"
4842 " processed=%u failed=%u",
4843 stats.bytes_processed,
4844 stats.buffers_in_queue,
4845 stats.buffers_in_idle,
4846 stats.buffers_in_ready,
4847 stats.buffers_processed,
4848 stats.buffers_failed);
4849 }
27eab384
MI		 4850 case 6: {
4851 unsigned int id = hdw->ir_scheme_active;
4852 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4853 (id >= ARRAY_SIZE(ir_scheme_names) ?
4854 "?" : ir_scheme_names[id]));
4855 }
2eb563b7
MI		 4856 default: break;
4857 }
4858 return 0;
4859}
4860
4861
4862/* Generate report containing info about attached sub-devices and attached
4863 i2c clients, including an indication of which attached i2c clients are
4864 actually sub-devices. */
4865static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4866 char *buf, unsigned int acnt)
4867{
4868 struct v4l2_subdev *sd;
4869 unsigned int tcnt = 0;
4870 unsigned int ccnt;
4871 struct i2c_client *client;
2eb563b7
MI		 4872 const char *p;
4873 unsigned int id;
4874
fa7ce764 4875 ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
2eb563b7
MI		 4876 tcnt += ccnt;
4877 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4878 id = sd->grp_id;
4879 p = NULL;
4880 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4881 if (p) {
fa7ce764 4882 ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s:", p);
2eb563b7
MI		 4883 tcnt += ccnt;
4884 } else {
4885 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
fa7ce764 4886 " (unknown id=%u):", id);
2eb563b7
MI		 4887 tcnt += ccnt;
4888 }
fa7ce764
JD		 4889 client = v4l2_get_subdevdata(sd);
4890 if (client) {
4891 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4892 " %s @ %02x\n", client->name,
4893 client->addr);
4894 tcnt += ccnt;
4895 } else {
4896 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4897 " no i2c client\n");
4898 tcnt += ccnt;
858f910e 4899 }
681c7399 4900 }
2eb563b7 4901 return tcnt;
681c7399
MI		 4902}
4903
4904
4905unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4906 char *buf,unsigned int acnt)
4907{
4908 unsigned int bcnt,ccnt,idx;
4909 bcnt = 0;
4910 LOCK_TAKE(hdw->big_lock);
4911 for (idx = 0; ; idx++) {
4912 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4913 if (!ccnt) break;
4914 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4915 if (!acnt) break;
4916 buf[0] = '\n'; ccnt = 1;
4917 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4918 }
2eb563b7
MI		 4919 ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4920 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
681c7399
MI		 4921 LOCK_GIVE(hdw->big_lock);
4922 return bcnt;
4923}
4924
4925
4926static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4927{
2eb563b7
MI		 4928 char buf[256];
4929 unsigned int idx, ccnt;
4930 unsigned int lcnt, ucnt;
681c7399
MI		 4931
4932 for (idx = 0; ; idx++) {
4933 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4934 if (!ccnt) break;
4935 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4936 }
2eb563b7
MI		 4937 ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
4938 ucnt = 0;
4939 while (ucnt < ccnt) {
4940 lcnt = 0;
4941 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4942 lcnt++;
4943 }
4944 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4945 ucnt += lcnt + 1;
4946 }
681c7399
MI		 4947}
4948
4949
4950/* Evaluate and update the driver's current state, taking various actions
4951 as appropriate for the update. */
4952static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4953{
4954 unsigned int st;
4955 int state_updated = 0;
4956 int callback_flag = 0;
1b9c18c5 4957 int analog_mode;
681c7399
MI		 4958
4959 pvr2_trace(PVR2_TRACE_STBITS,
4960 "Drive state check START");
4961 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4962 pvr2_hdw_state_log_state(hdw);
4963 }
4964
4965 /* Process all state and get back over disposition */
4966 state_updated = pvr2_hdw_state_update(hdw);
4967
1b9c18c5
MI		 4968 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4969
681c7399
MI		 4970 /* Update master state based upon all other states. */
4971 if (!hdw->flag_ok) {
4972 st = PVR2_STATE_DEAD;
4973 } else if (hdw->fw1_state != FW1_STATE_OK) {
4974 st = PVR2_STATE_COLD;
72998b71
MI		 4975 } else if ((analog_mode ||
4976 hdw->hdw_desc->flag_digital_requires_cx23416) &&
4977 !hdw->state_encoder_ok) {
681c7399 4978 st = PVR2_STATE_WARM;
1b9c18c5
MI		 4979 } else if (hdw->flag_tripped ||
4980 (analog_mode && hdw->flag_decoder_missed)) {
681c7399 4981 st = PVR2_STATE_ERROR;
62433e31 4982 } else if (hdw->state_usbstream_run &&
1b9c18c5 4983 (!analog_mode ||
62433e31 4984 (hdw->state_encoder_run && hdw->state_decoder_run))) {
681c7399
MI		 4985 st = PVR2_STATE_RUN;
4986 } else {
4987 st = PVR2_STATE_READY;
4988 }
4989 if (hdw->master_state != st) {
4990 pvr2_trace(PVR2_TRACE_STATE,
4991 "Device state change from %s to %s",
4992 pvr2_get_state_name(hdw->master_state),
4993 pvr2_get_state_name(st));
40381cb0 4994 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
681c7399
MI		 4995 hdw->master_state = st;
4996 state_updated = !0;
4997 callback_flag = !0;
4998 }
4999 if (state_updated) {
5000 /* Trigger anyone waiting on any state changes here. */
5001 wake_up(&hdw->state_wait_data);
5002 }
5003
5004 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5005 pvr2_hdw_state_log_state(hdw);
5006 }
5007 pvr2_trace(PVR2_TRACE_STBITS,
5008 "Drive state check DONE callback=%d",callback_flag);
5009
5010 return callback_flag;
5011}
5012
5013
5014/* Cause kernel thread to check / update driver state */
5015static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
5016{
5017 if (hdw->state_stale) return;
5018 hdw->state_stale = !0;
5019 trace_stbit("state_stale",hdw->state_stale);
5020 queue_work(hdw->workqueue,&hdw->workpoll);
5021}
5022
5023
d855497e
MI		 5024int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
5025{
5026 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5027}
5028
5029
5030int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5031{
5032 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5033}
5034
5035
5036int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5037{
5038 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5039}
5040
5041
5042int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5043{
5044 u32 cval,nval;
5045 int ret;
5046 if (~msk) {
5047 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5048 if (ret) return ret;
5049 nval = (cval & ~msk) | (val & msk);
5050 pvr2_trace(PVR2_TRACE_GPIO,
5051 "GPIO direction changing 0x%x:0x%x"
5052 " from 0x%x to 0x%x",
5053 msk,val,cval,nval);
5054 } else {
5055 nval = val;
5056 pvr2_trace(PVR2_TRACE_GPIO,
5057 "GPIO direction changing to 0x%x",nval);
5058 }
5059 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5060}
5061
5062
5063int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5064{
5065 u32 cval,nval;
5066 int ret;
5067 if (~msk) {
5068 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5069 if (ret) return ret;
5070 nval = (cval & ~msk) | (val & msk);
5071 pvr2_trace(PVR2_TRACE_GPIO,
5072 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5073 msk,val,cval,nval);
5074 } else {
5075 nval = val;
5076 pvr2_trace(PVR2_TRACE_GPIO,
5077 "GPIO output changing to 0x%x",nval);
5078 }
5079 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5080}
5081
5082
a51f5000
MI		 5083void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5084{
40f07111
MI		 5085 struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5086 memset(vtp, 0, sizeof(*vtp));
2641df36 5087 hdw->tuner_signal_stale = 0;
40f07111
MI		 5088 /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5089 using v4l2-subdev - therefore we can't support that AT ALL right
5090 now. (Of course, no sub-drivers seem to implement it either.
5091 But now it's a a chicken and egg problem...) */
5092 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5093 &hdw->tuner_signal_info);
2641df36 5094 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
40f07111
MI		 5095 " type=%u strength=%u audio=0x%x cap=0x%x"
5096 " low=%u hi=%u",
5097 vtp->type,
5098 vtp->signal, vtp->rxsubchans, vtp->capability,
5099 vtp->rangelow, vtp->rangehigh);
2641df36
MI		 5100
5101 /* We have to do this to avoid getting into constant polling if
5102 there's nobody to answer a poll of cropcap info. */
5103 hdw->cropcap_stale = 0;
a51f5000
MI		 5104}
5105
5106
7fb20fa3
MI		 5107unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5108{
5109 return hdw->input_avail_mask;
5110}
5111
5112
1cb03b76
MI		 5113unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5114{
5115 return hdw->input_allowed_mask;
5116}
5117
5118
5119static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5120{
5121 if (hdw->input_val != v) {
5122 hdw->input_val = v;
5123 hdw->input_dirty = !0;
5124 }
5125
5126 /* Handle side effects - if we switch to a mode that needs the RF
5127 tuner, then select the right frequency choice as well and mark
5128 it dirty. */
5129 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5130 hdw->freqSelector = 0;
5131 hdw->freqDirty = !0;
5132 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5133 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5134 hdw->freqSelector = 1;
5135 hdw->freqDirty = !0;
5136 }
5137 return 0;
5138}
5139
5140
5141int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5142 unsigned int change_mask,
5143 unsigned int change_val)
5144{
5145 int ret = 0;
5146 unsigned int nv,m,idx;
5147 LOCK_TAKE(hdw->big_lock);
5148 do {
5149 nv = hdw->input_allowed_mask & ~change_mask;
5150 nv |= (change_val & change_mask);
5151 nv &= hdw->input_avail_mask;
5152 if (!nv) {
5153 /* No legal modes left; return error instead. */
5154 ret = -EPERM;
5155 break;
5156 }
5157 hdw->input_allowed_mask = nv;
5158 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5159 /* Current mode is still in the allowed mask, so
5160 we're done. */
5161 break;
5162 }
5163 /* Select and switch to a mode that is still in the allowed
5164 mask */
5165 if (!hdw->input_allowed_mask) {
5166 /* Nothing legal; give up */
5167 break;
5168 }
5169 m = hdw->input_allowed_mask;
5170 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5171 if (!((1 << idx) & m)) continue;
5172 pvr2_hdw_set_input(hdw,idx);
5173 break;
5174 }
5175 } while (0);
5176 LOCK_GIVE(hdw->big_lock);
5177 return ret;
5178}
5179
5180
e61b6fc5 5181/* Find I2C address of eeprom */
07e337ee 5182static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 5183{
5184 int result;
5185 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 5186 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 5187 result = pvr2_send_request(hdw,
5188 hdw->cmd_buffer,1,
5189 hdw->cmd_buffer,1);
5190 if (result < 0) break;
5191 result = hdw->cmd_buffer[0];
5192 } while(0); LOCK_GIVE(hdw->ctl_lock);
5193 return result;
5194}
5195
5196
32ffa9ae 5197int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
aecde8b5
HV		 5198 struct v4l2_dbg_match *match, u64 reg_id,
5199 int setFl, u64 *val_ptr)
32ffa9ae
MI		 5200{
5201#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 5202 struct v4l2_dbg_register req;
6d98816f
MI		 5203 int stat = 0;
5204 int okFl = 0;
32ffa9ae 5205
201f5c9c
MI		 5206 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5207
aecde8b5 5208 req.match = *match;
32ffa9ae
MI		 5209 req.reg = reg_id;
5210 if (setFl) req.val = *val_ptr;
d8f5b9ba
MI		 5211 /* It would be nice to know if a sub-device answered the request */
5212 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5213 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 5214 if (okFl) {
5215 return stat;
5216 }
32ffa9ae
MI		 5217 return -EINVAL;
5218#else
5219 return -ENOSYS;
5220#endif
5221}
5222
5223
d855497e
MI		 5224/*
5225 Stuff for Emacs to see, in order to encourage consistent editing style:
5226 *** Local Variables: ***
5227 *** mode: c ***
5228 *** fill-column: 75 ***
5229 *** tab-width: 8 ***
5230 *** c-basic-offset: 8 ***
5231 *** End: ***
5232 */
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