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V4L/DVB (11194): pvrusb2: Implement mechanism to force a full sub-device update
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
d855497e
MI		 3 *
4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21#include <linux/errno.h>
22#include <linux/string.h>
23#include <linux/slab.h>
24#include <linux/firmware.h>
d855497e 25#include <linux/videodev2.h>
32ffa9ae 26#include <media/v4l2-common.h>
75212a02 27#include <media/tuner.h>
d855497e
MI		 28#include "pvrusb2.h"
29#include "pvrusb2-std.h"
30#include "pvrusb2-util.h"
31#include "pvrusb2-hdw.h"
32#include "pvrusb2-i2c-core.h"
59af3367 33#include "pvrusb2-i2c-track.h"
d855497e
MI		 34#include "pvrusb2-tuner.h"
35#include "pvrusb2-eeprom.h"
36#include "pvrusb2-hdw-internal.h"
37#include "pvrusb2-encoder.h"
38#include "pvrusb2-debug.h"
8d364363 39#include "pvrusb2-fx2-cmd.h"
5f6dae80 40#include "pvrusb2-wm8775.h"
6f956512 41#include "pvrusb2-video-v4l.h"
634ba268 42#include "pvrusb2-cx2584x-v4l.h"
76891d65 43#include "pvrusb2-audio.h"
d855497e 44
1bde0289
MI		 45#define TV_MIN_FREQ 55250000L
46#define TV_MAX_FREQ 850000000L
25d8527a 47
83ce57aa
MI		 48/* This defines a minimum interval that the decoder must remain quiet
49 before we are allowed to start it running. */
50#define TIME_MSEC_DECODER_WAIT 50
51
52/* This defines a minimum interval that the encoder must remain quiet
fa98e594
MI		 53 before we are allowed to configure it. I had this originally set to
54 50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
55 things work better when it's set to 100msec. */
56#define TIME_MSEC_ENCODER_WAIT 100
83ce57aa
MI		 57
58/* This defines the minimum interval that the encoder must successfully run
59 before we consider that the encoder has run at least once since its
60 firmware has been loaded. This measurement is in important for cases
61 where we can't do something until we know that the encoder has been run
62 at least once. */
63#define TIME_MSEC_ENCODER_OK 250
64
a0fd1cb1 65static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 66static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e 67
ff699e6b 68static int ctlchg;
ff699e6b 69static int procreload;
d855497e
MI		 70static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
71static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
72static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
ff699e6b 73static int init_pause_msec;
d855497e
MI		 74
75module_param(ctlchg, int, S_IRUGO|S_IWUSR);
76MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
77module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
78MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
d855497e
MI		 79module_param(procreload, int, S_IRUGO|S_IWUSR);
80MODULE_PARM_DESC(procreload,
81 "Attempt init failure recovery with firmware reload");
82module_param_array(tuner, int, NULL, 0444);
83MODULE_PARM_DESC(tuner,"specify installed tuner type");
84module_param_array(video_std, int, NULL, 0444);
85MODULE_PARM_DESC(video_std,"specify initial video standard");
86module_param_array(tolerance, int, NULL, 0444);
87MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
88
5a4f5da6
MK		 89/* US Broadcast channel 7 (175.25 MHz) */
90static int default_tv_freq = 175250000L;
91/* 104.3 MHz, a usable FM station for my area */
92static int default_radio_freq = 104300000L;
93
94module_param_named(tv_freq, default_tv_freq, int, 0444);
95MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
96module_param_named(radio_freq, default_radio_freq, int, 0444);
97MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
98
d855497e
MI		 99#define PVR2_CTL_WRITE_ENDPOINT 0x01
100#define PVR2_CTL_READ_ENDPOINT 0x81
101
102#define PVR2_GPIO_IN 0x9008
103#define PVR2_GPIO_OUT 0x900c
104#define PVR2_GPIO_DIR 0x9020
105
106#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
107
108#define PVR2_FIRMWARE_ENDPOINT 0x02
109
110/* size of a firmware chunk */
111#define FIRMWARE_CHUNK_SIZE 0x2000
112
edb9dcb8
MI		 113typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
114 struct v4l2_subdev *);
115
116static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
4ecbc28d 117 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
6f956512 118 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
76891d65 119 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
634ba268 120 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
edb9dcb8
MI		 121};
122
e9c64a78
MI		 123static const char *module_names[] = {
124 [PVR2_CLIENT_ID_MSP3400] = "msp3400",
125 [PVR2_CLIENT_ID_CX25840] = "cx25840",
126 [PVR2_CLIENT_ID_SAA7115] = "saa7115",
127 [PVR2_CLIENT_ID_TUNER] = "tuner",
128 [PVR2_CLIENT_ID_CS53132A] = "cs53132a",
5f6dae80 129 [PVR2_CLIENT_ID_WM8775] = "wm8775",
e9c64a78
MI		 130};
131
132
133static const unsigned char *module_i2c_addresses[] = {
134 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
ae111f76 135 [PVR2_CLIENT_ID_WM8775] = "\x1b",
0b467014 136 [PVR2_CLIENT_ID_CX25840] = "\x44",
e9c64a78
MI		 137};
138
139
b30d2441
MI		 140/* Define the list of additional controls we'll dynamically construct based
141 on query of the cx2341x module. */
142struct pvr2_mpeg_ids {
143 const char *strid;
144 int id;
145};
146static const struct pvr2_mpeg_ids mpeg_ids[] = {
147 {
148 .strid = "audio_layer",
149 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
150 },{
151 .strid = "audio_bitrate",
152 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
153 },{
154 /* Already using audio_mode elsewhere :-( */
155 .strid = "mpeg_audio_mode",
156 .id = V4L2_CID_MPEG_AUDIO_MODE,
157 },{
158 .strid = "mpeg_audio_mode_extension",
159 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
160 },{
161 .strid = "audio_emphasis",
162 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
163 },{
164 .strid = "audio_crc",
165 .id = V4L2_CID_MPEG_AUDIO_CRC,
166 },{
167 .strid = "video_aspect",
168 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
169 },{
170 .strid = "video_b_frames",
171 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
172 },{
173 .strid = "video_gop_size",
174 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
175 },{
176 .strid = "video_gop_closure",
177 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 178 },{
179 .strid = "video_bitrate_mode",
180 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
181 },{
182 .strid = "video_bitrate",
183 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
184 },{
185 .strid = "video_bitrate_peak",
186 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
187 },{
188 .strid = "video_temporal_decimation",
189 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
190 },{
191 .strid = "stream_type",
192 .id = V4L2_CID_MPEG_STREAM_TYPE,
193 },{
194 .strid = "video_spatial_filter_mode",
195 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
196 },{
197 .strid = "video_spatial_filter",
198 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
199 },{
200 .strid = "video_luma_spatial_filter_type",
201 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
202 },{
203 .strid = "video_chroma_spatial_filter_type",
204 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
205 },{
206 .strid = "video_temporal_filter_mode",
207 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
208 },{
209 .strid = "video_temporal_filter",
210 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
211 },{
212 .strid = "video_median_filter_type",
213 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
214 },{
215 .strid = "video_luma_median_filter_top",
216 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
217 },{
218 .strid = "video_luma_median_filter_bottom",
219 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
220 },{
221 .strid = "video_chroma_median_filter_top",
222 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
223 },{
224 .strid = "video_chroma_median_filter_bottom",
225 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
226 }
227};
eca8ebfc 228#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 229
434449f4 230
d855497e 231static const char *control_values_srate[] = {
434449f4
MI		 232 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
233 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
234 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 235};
236
237
d855497e 238
d855497e
MI		 239static const char *control_values_input[] = {
240 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
29bf5b1d 241 [PVR2_CVAL_INPUT_DTV] = "dtv",
d855497e
MI		 242 [PVR2_CVAL_INPUT_RADIO] = "radio",
243 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
244 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
245};
246
247
248static const char *control_values_audiomode[] = {
249 [V4L2_TUNER_MODE_MONO] = "Mono",
250 [V4L2_TUNER_MODE_STEREO] = "Stereo",
251 [V4L2_TUNER_MODE_LANG1] = "Lang1",
252 [V4L2_TUNER_MODE_LANG2] = "Lang2",
253 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
254};
255
256
257static const char *control_values_hsm[] = {
258 [PVR2_CVAL_HSM_FAIL] = "Fail",
259 [PVR2_CVAL_HSM_HIGH] = "High",
260 [PVR2_CVAL_HSM_FULL] = "Full",
261};
262
263
681c7399
MI		 264static const char *pvr2_state_names[] = {
265 [PVR2_STATE_NONE] = "none",
266 [PVR2_STATE_DEAD] = "dead",
267 [PVR2_STATE_COLD] = "cold",
268 [PVR2_STATE_WARM] = "warm",
269 [PVR2_STATE_ERROR] = "error",
270 [PVR2_STATE_READY] = "ready",
271 [PVR2_STATE_RUN] = "run",
d855497e
MI		 272};
273
681c7399 274
694dca2b 275struct pvr2_fx2cmd_descdef {
1c9d10d4
MI		 276 unsigned char id;
277 unsigned char *desc;
278};
279
694dca2b 280static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
1c9d10d4
MI		 281 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
282 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
31335b13 283 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
1c9d10d4
MI		 284 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
285 {FX2CMD_REG_WRITE, "write encoder register"},
286 {FX2CMD_REG_READ, "read encoder register"},
287 {FX2CMD_MEMSEL, "encoder memsel"},
288 {FX2CMD_I2C_WRITE, "i2c write"},
289 {FX2CMD_I2C_READ, "i2c read"},
290 {FX2CMD_GET_USB_SPEED, "get USB speed"},
291 {FX2CMD_STREAMING_ON, "stream on"},
292 {FX2CMD_STREAMING_OFF, "stream off"},
293 {FX2CMD_FWPOST1, "fwpost1"},
294 {FX2CMD_POWER_OFF, "power off"},
295 {FX2CMD_POWER_ON, "power on"},
296 {FX2CMD_DEEP_RESET, "deep reset"},
297 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
298 {FX2CMD_GET_IR_CODE, "get IR code"},
299 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
300 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
301 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
302 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
303 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
304 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
305 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
306};
307
308
1cb03b76 309static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
681c7399
MI		 310static void pvr2_hdw_state_sched(struct pvr2_hdw *);
311static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 312static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399
MI		 313static void pvr2_hdw_worker_i2c(struct work_struct *work);
314static void pvr2_hdw_worker_poll(struct work_struct *work);
681c7399
MI		 315static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
316static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
317static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 318static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 319static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 320static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 321static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
322static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
681c7399
MI		 323static void pvr2_hdw_quiescent_timeout(unsigned long);
324static void pvr2_hdw_encoder_wait_timeout(unsigned long);
d913d630 325static void pvr2_hdw_encoder_run_timeout(unsigned long);
1c9d10d4 326static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
07e337ee
AB		 327static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
328 unsigned int timeout,int probe_fl,
329 void *write_data,unsigned int write_len,
330 void *read_data,unsigned int read_len);
432907f7 331static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
d855497e 332
681c7399
MI		 333
334static void trace_stbit(const char *name,int val)
335{
336 pvr2_trace(PVR2_TRACE_STBITS,
337 "State bit %s <-- %s",
338 name,(val ? "true" : "false"));
339}
340
d855497e
MI		 341static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
342{
343 struct pvr2_hdw *hdw = cptr->hdw;
344 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
345 *vp = hdw->freqTable[hdw->freqProgSlot-1];
346 } else {
347 *vp = 0;
348 }
349 return 0;
350}
351
352static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
353{
354 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 355 unsigned int slotId = hdw->freqProgSlot;
356 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
357 hdw->freqTable[slotId-1] = v;
358 /* Handle side effects correctly - if we're tuned to this
359 slot, then forgot the slot id relation since the stored
360 frequency has been changed. */
361 if (hdw->freqSelector) {
362 if (hdw->freqSlotRadio == slotId) {
363 hdw->freqSlotRadio = 0;
364 }
365 } else {
366 if (hdw->freqSlotTelevision == slotId) {
367 hdw->freqSlotTelevision = 0;
368 }
369 }
d855497e
MI		 370 }
371 return 0;
372}
373
374static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
375{
376 *vp = cptr->hdw->freqProgSlot;
377 return 0;
378}
379
380static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
381{
382 struct pvr2_hdw *hdw = cptr->hdw;
383 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
384 hdw->freqProgSlot = v;
385 }
386 return 0;
387}
388
389static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
390{
1bde0289
MI		 391 struct pvr2_hdw *hdw = cptr->hdw;
392 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 393 return 0;
394}
395
1bde0289 396static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 397{
398 unsigned freq = 0;
399 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 400 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
401 if (slotId > 0) {
402 freq = hdw->freqTable[slotId-1];
403 if (!freq) return 0;
404 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 405 }
1bde0289
MI		 406 if (hdw->freqSelector) {
407 hdw->freqSlotRadio = slotId;
408 } else {
409 hdw->freqSlotTelevision = slotId;
d855497e
MI		 410 }
411 return 0;
412}
413
414static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
415{
1bde0289 416 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 417 return 0;
418}
419
420static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
421{
422 return cptr->hdw->freqDirty != 0;
423}
424
425static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
426{
427 cptr->hdw->freqDirty = 0;
428}
429
430static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
431{
1bde0289 432 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 433 return 0;
434}
435
e784bfb9 436static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
437{
432907f7
MI		 438 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
439 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
440 if (stat != 0) {
432907f7 441 return stat;
e784bfb9 442 }
432907f7 443 *left = cap->bounds.left;
e784bfb9 444 return 0;
445}
446
447static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
448{
432907f7
MI		 449 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
450 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
451 if (stat != 0) {
432907f7
MI		 452 return stat;
453 }
454 *left = cap->bounds.left;
455 if (cap->bounds.width > cptr->hdw->cropw_val) {
432907f7 456 *left += cap->bounds.width - cptr->hdw->cropw_val;
e784bfb9 457 }
458 return 0;
459}
460
461static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
462{
432907f7
MI		 463 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
464 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
465 if (stat != 0) {
432907f7 466 return stat;
e784bfb9 467 }
432907f7 468 *top = cap->bounds.top;
e784bfb9 469 return 0;
470}
471
432907f7 472static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
3ad9fc37 473{
432907f7
MI		 474 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
475 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
476 if (stat != 0) {
432907f7
MI		 477 return stat;
478 }
479 *top = cap->bounds.top;
480 if (cap->bounds.height > cptr->hdw->croph_val) {
432907f7 481 *top += cap->bounds.height - cptr->hdw->croph_val;
3ad9fc37
MI		 482 }
483 return 0;
484}
485
432907f7
MI		 486static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
487{
488 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
489 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
490 if (stat != 0) {
432907f7
MI		 491 return stat;
492 }
493 *val = 0;
494 if (cap->bounds.width > cptr->hdw->cropl_val) {
432907f7
MI		 495 *val = cap->bounds.width - cptr->hdw->cropl_val;
496 }
497 return 0;
498}
499
500static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
501{
502 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
503 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
504 if (stat != 0) {
432907f7
MI		 505 return stat;
506 }
507 *val = 0;
508 if (cap->bounds.height > cptr->hdw->cropt_val) {
432907f7
MI		 509 *val = cap->bounds.height - cptr->hdw->cropt_val;
510 }
511 return 0;
512}
513
514static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
515{
516 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
517 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
518 if (stat != 0) {
432907f7
MI		 519 return stat;
520 }
521 *val = cap->bounds.left;
522 return 0;
523}
524
525static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
526{
527 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
528 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
529 if (stat != 0) {
432907f7
MI		 530 return stat;
531 }
532 *val = cap->bounds.top;
533 return 0;
534}
535
536static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
537{
538 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
539 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
540 if (stat != 0) {
432907f7
MI		 541 return stat;
542 }
543 *val = cap->bounds.width;
544 return 0;
545}
546
547static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
548{
549 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
550 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
551 if (stat != 0) {
432907f7
MI		 552 return stat;
553 }
554 *val = cap->bounds.height;
555 return 0;
556}
557
558static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
559{
560 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
561 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
562 if (stat != 0) {
432907f7
MI		 563 return stat;
564 }
565 *val = cap->defrect.left;
566 return 0;
567}
568
569static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
570{
571 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
572 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
573 if (stat != 0) {
432907f7
MI		 574 return stat;
575 }
576 *val = cap->defrect.top;
577 return 0;
578}
579
580static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
581{
582 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
583 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
584 if (stat != 0) {
432907f7
MI		 585 return stat;
586 }
587 *val = cap->defrect.width;
588 return 0;
589}
590
591static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
592{
593 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
594 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
595 if (stat != 0) {
432907f7
MI		 596 return stat;
597 }
598 *val = cap->defrect.height;
599 return 0;
600}
601
602static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
603{
604 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
605 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
606 if (stat != 0) {
432907f7
MI		 607 return stat;
608 }
609 *val = cap->pixelaspect.numerator;
610 return 0;
611}
612
613static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
614{
615 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
616 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
617 if (stat != 0) {
432907f7
MI		 618 return stat;
619 }
620 *val = cap->pixelaspect.denominator;
621 return 0;
622}
623
624static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
e784bfb9 625{
432907f7
MI		 626 /* Actual maximum depends on the video standard in effect. */
627 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
628 *vp = 480;
e784bfb9 629 } else {
432907f7 630 *vp = 576;
e784bfb9 631 }
632 return 0;
633}
634
3ad9fc37
MI		 635static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
636{
989eb154
MI		 637 /* Actual minimum depends on device digitizer type. */
638 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 639 *vp = 75;
640 } else {
641 *vp = 17;
642 }
643 return 0;
644}
645
1bde0289 646static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 647{
1bde0289
MI		 648 *vp = cptr->hdw->input_val;
649 return 0;
650}
651
29bf5b1d
MI		 652static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
653{
1cb03b76 654 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
29bf5b1d
MI		 655}
656
1bde0289
MI		 657static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
658{
1cb03b76 659 return pvr2_hdw_set_input(cptr->hdw,v);
1bde0289
MI		 660}
661
662static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
663{
664 return cptr->hdw->input_dirty != 0;
665}
666
667static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
668{
669 cptr->hdw->input_dirty = 0;
670}
671
5549f54f 672
25d8527a
PK		 673static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
674{
644afdb9
MI		 675 unsigned long fv;
676 struct pvr2_hdw *hdw = cptr->hdw;
677 if (hdw->tuner_signal_stale) {
a51f5000 678 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 679 }
680 fv = hdw->tuner_signal_info.rangehigh;
681 if (!fv) {
682 /* Safety fallback */
25d8527a 683 *vp = TV_MAX_FREQ;
644afdb9 684 return 0;
25d8527a 685 }
644afdb9
MI		 686 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
687 fv = (fv * 125) / 2;
688 } else {
689 fv = fv * 62500;
690 }
691 *vp = fv;
25d8527a
PK		 692 return 0;
693}
694
695static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
696{
644afdb9
MI		 697 unsigned long fv;
698 struct pvr2_hdw *hdw = cptr->hdw;
699 if (hdw->tuner_signal_stale) {
a51f5000 700 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 701 }
702 fv = hdw->tuner_signal_info.rangelow;
703 if (!fv) {
704 /* Safety fallback */
25d8527a 705 *vp = TV_MIN_FREQ;
644afdb9
MI		 706 return 0;
707 }
708 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
709 fv = (fv * 125) / 2;
710 } else {
711 fv = fv * 62500;
25d8527a 712 }
644afdb9 713 *vp = fv;
25d8527a
PK		 714 return 0;
715}
716
b30d2441
MI		 717static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
718{
719 return cptr->hdw->enc_stale != 0;
720}
721
722static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
723{
724 cptr->hdw->enc_stale = 0;
681c7399 725 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 726}
727
728static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
729{
730 int ret;
731 struct v4l2_ext_controls cs;
732 struct v4l2_ext_control c1;
733 memset(&cs,0,sizeof(cs));
734 memset(&c1,0,sizeof(c1));
735 cs.controls = &c1;
736 cs.count = 1;
737 c1.id = cptr->info->v4l_id;
01f1e44f 738 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 739 VIDIOC_G_EXT_CTRLS);
740 if (ret) return ret;
741 *vp = c1.value;
742 return 0;
743}
744
745static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
746{
747 int ret;
681c7399 748 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 749 struct v4l2_ext_controls cs;
750 struct v4l2_ext_control c1;
751 memset(&cs,0,sizeof(cs));
752 memset(&c1,0,sizeof(c1));
753 cs.controls = &c1;
754 cs.count = 1;
755 c1.id = cptr->info->v4l_id;
756 c1.value = v;
681c7399
MI		 757 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
758 hdw->state_encoder_run, &cs,
b30d2441 759 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 760 if (ret == -EBUSY) {
761 /* Oops. cx2341x is telling us it's not safe to change
762 this control while we're capturing. Make a note of this
763 fact so that the pipeline will be stopped the next time
764 controls are committed. Then go on ahead and store this
765 change anyway. */
766 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
767 0, &cs,
768 VIDIOC_S_EXT_CTRLS);
769 if (!ret) hdw->enc_unsafe_stale = !0;
770 }
b30d2441 771 if (ret) return ret;
681c7399 772 hdw->enc_stale = !0;
b30d2441
MI		 773 return 0;
774}
775
776static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
777{
778 struct v4l2_queryctrl qctrl;
779 struct pvr2_ctl_info *info;
780 qctrl.id = cptr->info->v4l_id;
781 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
782 /* Strip out the const so we can adjust a function pointer. It's
783 OK to do this here because we know this is a dynamically created
784 control, so the underlying storage for the info pointer is (a)
785 private to us, and (b) not in read-only storage. Either we do
786 this or we significantly complicate the underlying control
787 implementation. */
788 info = (struct pvr2_ctl_info *)(cptr->info);
789 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
790 if (info->set_value) {
a0fd1cb1 791 info->set_value = NULL;
b30d2441
MI		 792 }
793 } else {
794 if (!(info->set_value)) {
795 info->set_value = ctrl_cx2341x_set;
796 }
797 }
798 return qctrl.flags;
799}
800
d855497e
MI		 801static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
802{
681c7399
MI		 803 *vp = cptr->hdw->state_pipeline_req;
804 return 0;
805}
806
807static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
808{
809 *vp = cptr->hdw->master_state;
d855497e
MI		 810 return 0;
811}
812
813static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
814{
815 int result = pvr2_hdw_is_hsm(cptr->hdw);
816 *vp = PVR2_CVAL_HSM_FULL;
817 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
818 if (result) *vp = PVR2_CVAL_HSM_HIGH;
819 return 0;
820}
821
822static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
823{
824 *vp = cptr->hdw->std_mask_avail;
825 return 0;
826}
827
828static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
829{
830 struct pvr2_hdw *hdw = cptr->hdw;
831 v4l2_std_id ns;
832 ns = hdw->std_mask_avail;
833 ns = (ns & ~m) | (v & m);
834 if (ns == hdw->std_mask_avail) return 0;
835 hdw->std_mask_avail = ns;
836 pvr2_hdw_internal_set_std_avail(hdw);
837 pvr2_hdw_internal_find_stdenum(hdw);
838 return 0;
839}
840
841static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
842 char *bufPtr,unsigned int bufSize,
843 unsigned int *len)
844{
845 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
846 return 0;
847}
848
849static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
850 const char *bufPtr,unsigned int bufSize,
851 int *mskp,int *valp)
852{
853 int ret;
854 v4l2_std_id id;
855 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
856 if (ret < 0) return ret;
857 if (mskp) *mskp = id;
858 if (valp) *valp = id;
859 return 0;
860}
861
862static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
863{
864 *vp = cptr->hdw->std_mask_cur;
865 return 0;
866}
867
868static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
869{
870 struct pvr2_hdw *hdw = cptr->hdw;
871 v4l2_std_id ns;
872 ns = hdw->std_mask_cur;
873 ns = (ns & ~m) | (v & m);
874 if (ns == hdw->std_mask_cur) return 0;
875 hdw->std_mask_cur = ns;
876 hdw->std_dirty = !0;
877 pvr2_hdw_internal_find_stdenum(hdw);
878 return 0;
879}
880
881static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
882{
883 return cptr->hdw->std_dirty != 0;
884}
885
886static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
887{
888 cptr->hdw->std_dirty = 0;
889}
890
891static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
892{
18103c57 893 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 894 pvr2_hdw_status_poll(hdw);
18103c57
MI		 895 *vp = hdw->tuner_signal_info.signal;
896 return 0;
897}
898
899static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
900{
901 int val = 0;
902 unsigned int subchan;
903 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 904 pvr2_hdw_status_poll(hdw);
18103c57
MI		 905 subchan = hdw->tuner_signal_info.rxsubchans;
906 if (subchan & V4L2_TUNER_SUB_MONO) {
907 val |= (1 << V4L2_TUNER_MODE_MONO);
908 }
909 if (subchan & V4L2_TUNER_SUB_STEREO) {
910 val |= (1 << V4L2_TUNER_MODE_STEREO);
911 }
912 if (subchan & V4L2_TUNER_SUB_LANG1) {
913 val |= (1 << V4L2_TUNER_MODE_LANG1);
914 }
915 if (subchan & V4L2_TUNER_SUB_LANG2) {
916 val |= (1 << V4L2_TUNER_MODE_LANG2);
917 }
918 *vp = val;
d855497e
MI		 919 return 0;
920}
921
d855497e
MI		 922
923static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
924{
925 struct pvr2_hdw *hdw = cptr->hdw;
926 if (v < 0) return -EINVAL;
927 if (v > hdw->std_enum_cnt) return -EINVAL;
928 hdw->std_enum_cur = v;
929 if (!v) return 0;
930 v--;
931 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
932 hdw->std_mask_cur = hdw->std_defs[v].id;
933 hdw->std_dirty = !0;
934 return 0;
935}
936
937
938static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
939{
940 *vp = cptr->hdw->std_enum_cur;
941 return 0;
942}
943
944
945static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
946{
947 return cptr->hdw->std_dirty != 0;
948}
949
950
951static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
952{
953 cptr->hdw->std_dirty = 0;
954}
955
956
957#define DEFINT(vmin,vmax) \
958 .type = pvr2_ctl_int, \
959 .def.type_int.min_value = vmin, \
960 .def.type_int.max_value = vmax
961
962#define DEFENUM(tab) \
963 .type = pvr2_ctl_enum, \
27c7b710 964 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 965 .def.type_enum.value_names = tab
966
33213963
MI		 967#define DEFBOOL \
968 .type = pvr2_ctl_bool
969
d855497e
MI		 970#define DEFMASK(msk,tab) \
971 .type = pvr2_ctl_bitmask, \
972 .def.type_bitmask.valid_bits = msk, \
973 .def.type_bitmask.bit_names = tab
974
975#define DEFREF(vname) \
976 .set_value = ctrl_set_##vname, \
977 .get_value = ctrl_get_##vname, \
978 .is_dirty = ctrl_isdirty_##vname, \
979 .clear_dirty = ctrl_cleardirty_##vname
980
981
982#define VCREATE_FUNCS(vname) \
983static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
984{*vp = cptr->hdw->vname##_val; return 0;} \
985static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
986{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
987static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
988{return cptr->hdw->vname##_dirty != 0;} \
989static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
990{cptr->hdw->vname##_dirty = 0;}
991
992VCREATE_FUNCS(brightness)
993VCREATE_FUNCS(contrast)
994VCREATE_FUNCS(saturation)
995VCREATE_FUNCS(hue)
996VCREATE_FUNCS(volume)
997VCREATE_FUNCS(balance)
998VCREATE_FUNCS(bass)
999VCREATE_FUNCS(treble)
1000VCREATE_FUNCS(mute)
e784bfb9 1001VCREATE_FUNCS(cropl)
1002VCREATE_FUNCS(cropt)
1003VCREATE_FUNCS(cropw)
1004VCREATE_FUNCS(croph)
c05c0462
MI		 1005VCREATE_FUNCS(audiomode)
1006VCREATE_FUNCS(res_hor)
1007VCREATE_FUNCS(res_ver)
d855497e 1008VCREATE_FUNCS(srate)
d855497e 1009
d855497e
MI		 1010/* Table definition of all controls which can be manipulated */
1011static const struct pvr2_ctl_info control_defs[] = {
1012 {
1013 .v4l_id = V4L2_CID_BRIGHTNESS,
1014 .desc = "Brightness",
1015 .name = "brightness",
1016 .default_value = 128,
1017 DEFREF(brightness),
1018 DEFINT(0,255),
1019 },{
1020 .v4l_id = V4L2_CID_CONTRAST,
1021 .desc = "Contrast",
1022 .name = "contrast",
1023 .default_value = 68,
1024 DEFREF(contrast),
1025 DEFINT(0,127),
1026 },{
1027 .v4l_id = V4L2_CID_SATURATION,
1028 .desc = "Saturation",
1029 .name = "saturation",
1030 .default_value = 64,
1031 DEFREF(saturation),
1032 DEFINT(0,127),
1033 },{
1034 .v4l_id = V4L2_CID_HUE,
1035 .desc = "Hue",
1036 .name = "hue",
1037 .default_value = 0,
1038 DEFREF(hue),
1039 DEFINT(-128,127),
1040 },{
1041 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1042 .desc = "Volume",
1043 .name = "volume",
139eecf9 1044 .default_value = 62000,
d855497e
MI		 1045 DEFREF(volume),
1046 DEFINT(0,65535),
1047 },{
1048 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1049 .desc = "Balance",
1050 .name = "balance",
1051 .default_value = 0,
1052 DEFREF(balance),
1053 DEFINT(-32768,32767),
1054 },{
1055 .v4l_id = V4L2_CID_AUDIO_BASS,
1056 .desc = "Bass",
1057 .name = "bass",
1058 .default_value = 0,
1059 DEFREF(bass),
1060 DEFINT(-32768,32767),
1061 },{
1062 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1063 .desc = "Treble",
1064 .name = "treble",
1065 .default_value = 0,
1066 DEFREF(treble),
1067 DEFINT(-32768,32767),
1068 },{
1069 .v4l_id = V4L2_CID_AUDIO_MUTE,
1070 .desc = "Mute",
1071 .name = "mute",
1072 .default_value = 0,
1073 DEFREF(mute),
33213963 1074 DEFBOOL,
e784bfb9 1075 }, {
432907f7 1076 .desc = "Capture crop left margin",
e784bfb9 1077 .name = "crop_left",
1078 .internal_id = PVR2_CID_CROPL,
1079 .default_value = 0,
1080 DEFREF(cropl),
1081 DEFINT(-129, 340),
1082 .get_min_value = ctrl_cropl_min_get,
1083 .get_max_value = ctrl_cropl_max_get,
432907f7 1084 .get_def_value = ctrl_get_cropcapdl,
e784bfb9 1085 }, {
432907f7 1086 .desc = "Capture crop top margin",
e784bfb9 1087 .name = "crop_top",
1088 .internal_id = PVR2_CID_CROPT,
1089 .default_value = 0,
1090 DEFREF(cropt),
1091 DEFINT(-35, 544),
1092 .get_min_value = ctrl_cropt_min_get,
1093 .get_max_value = ctrl_cropt_max_get,
432907f7 1094 .get_def_value = ctrl_get_cropcapdt,
e784bfb9 1095 }, {
432907f7 1096 .desc = "Capture crop width",
e784bfb9 1097 .name = "crop_width",
1098 .internal_id = PVR2_CID_CROPW,
1099 .default_value = 720,
1100 DEFREF(cropw),
432907f7
MI		 1101 .get_max_value = ctrl_cropw_max_get,
1102 .get_def_value = ctrl_get_cropcapdw,
e784bfb9 1103 }, {
432907f7 1104 .desc = "Capture crop height",
e784bfb9 1105 .name = "crop_height",
1106 .internal_id = PVR2_CID_CROPH,
1107 .default_value = 480,
1108 DEFREF(croph),
432907f7
MI		 1109 .get_max_value = ctrl_croph_max_get,
1110 .get_def_value = ctrl_get_cropcapdh,
1111 }, {
1112 .desc = "Capture capability pixel aspect numerator",
1113 .name = "cropcap_pixel_numerator",
1114 .internal_id = PVR2_CID_CROPCAPPAN,
1115 .get_value = ctrl_get_cropcappan,
1116 }, {
1117 .desc = "Capture capability pixel aspect denominator",
1118 .name = "cropcap_pixel_denominator",
1119 .internal_id = PVR2_CID_CROPCAPPAD,
1120 .get_value = ctrl_get_cropcappad,
1121 }, {
1122 .desc = "Capture capability bounds top",
1123 .name = "cropcap_bounds_top",
1124 .internal_id = PVR2_CID_CROPCAPBT,
1125 .get_value = ctrl_get_cropcapbt,
1126 }, {
1127 .desc = "Capture capability bounds left",
1128 .name = "cropcap_bounds_left",
1129 .internal_id = PVR2_CID_CROPCAPBL,
1130 .get_value = ctrl_get_cropcapbl,
1131 }, {
1132 .desc = "Capture capability bounds width",
1133 .name = "cropcap_bounds_width",
1134 .internal_id = PVR2_CID_CROPCAPBW,
1135 .get_value = ctrl_get_cropcapbw,
1136 }, {
1137 .desc = "Capture capability bounds height",
1138 .name = "cropcap_bounds_height",
1139 .internal_id = PVR2_CID_CROPCAPBH,
1140 .get_value = ctrl_get_cropcapbh,
c05c0462
MI		 1141 },{
1142 .desc = "Video Source",
1143 .name = "input",
1144 .internal_id = PVR2_CID_INPUT,
1145 .default_value = PVR2_CVAL_INPUT_TV,
29bf5b1d 1146 .check_value = ctrl_check_input,
c05c0462
MI		 1147 DEFREF(input),
1148 DEFENUM(control_values_input),
1149 },{
1150 .desc = "Audio Mode",
1151 .name = "audio_mode",
1152 .internal_id = PVR2_CID_AUDIOMODE,
1153 .default_value = V4L2_TUNER_MODE_STEREO,
1154 DEFREF(audiomode),
1155 DEFENUM(control_values_audiomode),
1156 },{
1157 .desc = "Horizontal capture resolution",
1158 .name = "resolution_hor",
1159 .internal_id = PVR2_CID_HRES,
1160 .default_value = 720,
1161 DEFREF(res_hor),
3ad9fc37 1162 DEFINT(19,720),
c05c0462
MI		 1163 },{
1164 .desc = "Vertical capture resolution",
1165 .name = "resolution_ver",
1166 .internal_id = PVR2_CID_VRES,
1167 .default_value = 480,
1168 DEFREF(res_ver),
3ad9fc37
MI		 1169 DEFINT(17,576),
1170 /* Hook in check for video standard and adjust maximum
1171 depending on the standard. */
1172 .get_max_value = ctrl_vres_max_get,
1173 .get_min_value = ctrl_vres_min_get,
d855497e 1174 },{
b30d2441 1175 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 1176 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1177 .desc = "Audio Sampling Frequency",
d855497e 1178 .name = "srate",
d855497e
MI		 1179 DEFREF(srate),
1180 DEFENUM(control_values_srate),
d855497e
MI		 1181 },{
1182 .desc = "Tuner Frequency (Hz)",
1183 .name = "frequency",
1184 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 1185 .default_value = 0,
d855497e
MI		 1186 .set_value = ctrl_freq_set,
1187 .get_value = ctrl_freq_get,
1188 .is_dirty = ctrl_freq_is_dirty,
1189 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 1190 DEFINT(0,0),
25d8527a
PK		 1191 /* Hook in check for input value (tv/radio) and adjust
1192 max/min values accordingly */
1193 .get_max_value = ctrl_freq_max_get,
1194 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1195 },{
1196 .desc = "Channel",
1197 .name = "channel",
1198 .set_value = ctrl_channel_set,
1199 .get_value = ctrl_channel_get,
1200 DEFINT(0,FREQTABLE_SIZE),
1201 },{
1202 .desc = "Channel Program Frequency",
1203 .name = "freq_table_value",
1204 .set_value = ctrl_channelfreq_set,
1205 .get_value = ctrl_channelfreq_get,
644afdb9 1206 DEFINT(0,0),
1bde0289
MI		 1207 /* Hook in check for input value (tv/radio) and adjust
1208 max/min values accordingly */
1bde0289
MI		 1209 .get_max_value = ctrl_freq_max_get,
1210 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1211 },{
1212 .desc = "Channel Program ID",
1213 .name = "freq_table_channel",
1214 .set_value = ctrl_channelprog_set,
1215 .get_value = ctrl_channelprog_get,
1216 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 1217 },{
1218 .desc = "Streaming Enabled",
1219 .name = "streaming_enabled",
1220 .get_value = ctrl_streamingenabled_get,
33213963 1221 DEFBOOL,
d855497e
MI		 1222 },{
1223 .desc = "USB Speed",
1224 .name = "usb_speed",
1225 .get_value = ctrl_hsm_get,
1226 DEFENUM(control_values_hsm),
681c7399
MI		 1227 },{
1228 .desc = "Master State",
1229 .name = "master_state",
1230 .get_value = ctrl_masterstate_get,
1231 DEFENUM(pvr2_state_names),
d855497e
MI		 1232 },{
1233 .desc = "Signal Present",
1234 .name = "signal_present",
1235 .get_value = ctrl_signal_get,
18103c57
MI		 1236 DEFINT(0,65535),
1237 },{
1238 .desc = "Audio Modes Present",
1239 .name = "audio_modes_present",
1240 .get_value = ctrl_audio_modes_present_get,
1241 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1242 v4l. Nothing outside of this module cares about this,
1243 but I reuse it in order to also reuse the
1244 control_values_audiomode string table. */
1245 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1246 (1 << V4L2_TUNER_MODE_STEREO)|
1247 (1 << V4L2_TUNER_MODE_LANG1)|
1248 (1 << V4L2_TUNER_MODE_LANG2)),
1249 control_values_audiomode),
d855497e
MI		 1250 },{
1251 .desc = "Video Standards Available Mask",
1252 .name = "video_standard_mask_available",
1253 .internal_id = PVR2_CID_STDAVAIL,
1254 .skip_init = !0,
1255 .get_value = ctrl_stdavail_get,
1256 .set_value = ctrl_stdavail_set,
1257 .val_to_sym = ctrl_std_val_to_sym,
1258 .sym_to_val = ctrl_std_sym_to_val,
1259 .type = pvr2_ctl_bitmask,
1260 },{
1261 .desc = "Video Standards In Use Mask",
1262 .name = "video_standard_mask_active",
1263 .internal_id = PVR2_CID_STDCUR,
1264 .skip_init = !0,
1265 .get_value = ctrl_stdcur_get,
1266 .set_value = ctrl_stdcur_set,
1267 .is_dirty = ctrl_stdcur_is_dirty,
1268 .clear_dirty = ctrl_stdcur_clear_dirty,
1269 .val_to_sym = ctrl_std_val_to_sym,
1270 .sym_to_val = ctrl_std_sym_to_val,
1271 .type = pvr2_ctl_bitmask,
d855497e
MI		 1272 },{
1273 .desc = "Video Standard Name",
1274 .name = "video_standard",
1275 .internal_id = PVR2_CID_STDENUM,
1276 .skip_init = !0,
1277 .get_value = ctrl_stdenumcur_get,
1278 .set_value = ctrl_stdenumcur_set,
1279 .is_dirty = ctrl_stdenumcur_is_dirty,
1280 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1281 .type = pvr2_ctl_enum,
1282 }
1283};
1284
eca8ebfc 1285#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 1286
1287
1288const char *pvr2_config_get_name(enum pvr2_config cfg)
1289{
1290 switch (cfg) {
1291 case pvr2_config_empty: return "empty";
1292 case pvr2_config_mpeg: return "mpeg";
1293 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 1294 case pvr2_config_pcm: return "pcm";
1295 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 1296 }
1297 return "<unknown>";
1298}
1299
1300
1301struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1302{
1303 return hdw->usb_dev;
1304}
1305
1306
1307unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1308{
1309 return hdw->serial_number;
1310}
1311
31a18547
MI		 1312
1313const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1314{
1315 return hdw->bus_info;
1316}
1317
1318
13a88797
MI		 1319const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1320{
1321 return hdw->identifier;
1322}
1323
1324
1bde0289
MI		 1325unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1326{
1327 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1328}
1329
1330/* Set the currently tuned frequency and account for all possible
1331 driver-core side effects of this action. */
f55a8712 1332static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1bde0289 1333{
7c74e57e 1334 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 1335 if (hdw->freqSelector) {
1336 /* Swing over to radio frequency selection */
1337 hdw->freqSelector = 0;
1338 hdw->freqDirty = !0;
1339 }
1bde0289
MI		 1340 if (hdw->freqValRadio != val) {
1341 hdw->freqValRadio = val;
1342 hdw->freqSlotRadio = 0;
7c74e57e 1343 hdw->freqDirty = !0;
1bde0289 1344 }
7c74e57e 1345 } else {
1bde0289
MI		 1346 if (!(hdw->freqSelector)) {
1347 /* Swing over to television frequency selection */
1348 hdw->freqSelector = 1;
1349 hdw->freqDirty = !0;
1350 }
1bde0289
MI		 1351 if (hdw->freqValTelevision != val) {
1352 hdw->freqValTelevision = val;
1353 hdw->freqSlotTelevision = 0;
7c74e57e 1354 hdw->freqDirty = !0;
1bde0289 1355 }
1bde0289
MI		 1356 }
1357}
1358
d855497e
MI		 1359int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1360{
1361 return hdw->unit_number;
1362}
1363
1364
1365/* Attempt to locate one of the given set of files. Messages are logged
1366 appropriate to what has been found. The return value will be 0 or
1367 greater on success (it will be the index of the file name found) and
1368 fw_entry will be filled in. Otherwise a negative error is returned on
1369 failure. If the return value is -ENOENT then no viable firmware file
1370 could be located. */
1371static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1372 const struct firmware **fw_entry,
1373 const char *fwtypename,
1374 unsigned int fwcount,
1375 const char *fwnames[])
1376{
1377 unsigned int idx;
1378 int ret = -EINVAL;
1379 for (idx = 0; idx < fwcount; idx++) {
1380 ret = request_firmware(fw_entry,
1381 fwnames[idx],
1382 &hdw->usb_dev->dev);
1383 if (!ret) {
1384 trace_firmware("Located %s firmware: %s;"
1385 " uploading...",
1386 fwtypename,
1387 fwnames[idx]);
1388 return idx;
1389 }
1390 if (ret == -ENOENT) continue;
1391 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1392 "request_firmware fatal error with code=%d",ret);
1393 return ret;
1394 }
1395 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1396 "***WARNING***"
1397 " Device %s firmware"
1398 " seems to be missing.",
1399 fwtypename);
1400 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1401 "Did you install the pvrusb2 firmware files"
1402 " in their proper location?");
1403 if (fwcount == 1) {
1404 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1405 "request_firmware unable to locate %s file %s",
1406 fwtypename,fwnames[0]);
1407 } else {
1408 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1409 "request_firmware unable to locate"
1410 " one of the following %s files:",
1411 fwtypename);
1412 for (idx = 0; idx < fwcount; idx++) {
1413 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1414 "request_firmware: Failed to find %s",
1415 fwnames[idx]);
1416 }
1417 }
1418 return ret;
1419}
1420
1421
1422/*
1423 * pvr2_upload_firmware1().
1424 *
1425 * Send the 8051 firmware to the device. After the upload, arrange for
1426 * device to re-enumerate.
1427 *
1428 * NOTE : the pointer to the firmware data given by request_firmware()
1429 * is not suitable for an usb transaction.
1430 *
1431 */
07e337ee 1432static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1433{
a0fd1cb1 1434 const struct firmware *fw_entry = NULL;
d855497e
MI		 1435 void *fw_ptr;
1436 unsigned int pipe;
1437 int ret;
1438 u16 address;
1d643a37 1439
989eb154 1440 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1441 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1442 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1443 "Connected device type defines"
1444 " no firmware to upload; ignoring firmware");
1445 return -ENOTTY;
1d643a37
MI		 1446 }
1447
d855497e
MI		 1448 hdw->fw1_state = FW1_STATE_FAILED; // default result
1449
1450 trace_firmware("pvr2_upload_firmware1");
1451
1452 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1453 hdw->hdw_desc->fx2_firmware.cnt,
1454 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1455 if (ret < 0) {
1456 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1457 return ret;
1458 }
1459
1460 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1461 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1462
1463 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1464
1465 if (fw_entry->size != 0x2000){
1466 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1467 release_firmware(fw_entry);
1468 return -ENOMEM;
1469 }
1470
1471 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1472 if (fw_ptr == NULL){
1473 release_firmware(fw_entry);
1474 return -ENOMEM;
1475 }
1476
1477 /* We have to hold the CPU during firmware upload. */
1478 pvr2_hdw_cpureset_assert(hdw,1);
1479
1480 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1481 chunk. */
1482
1483 ret = 0;
1484 for(address = 0; address < fw_entry->size; address += 0x800) {
1485 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1486 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1487 0, fw_ptr, 0x800, HZ);
1488 }
1489
1490 trace_firmware("Upload done, releasing device's CPU");
1491
1492 /* Now release the CPU. It will disconnect and reconnect later. */
1493 pvr2_hdw_cpureset_assert(hdw,0);
1494
1495 kfree(fw_ptr);
1496 release_firmware(fw_entry);
1497
1498 trace_firmware("Upload done (%d bytes sent)",ret);
1499
1500 /* We should have written 8192 bytes */
1501 if (ret == 8192) {
1502 hdw->fw1_state = FW1_STATE_RELOAD;
1503 return 0;
1504 }
1505
1506 return -EIO;
1507}
1508
1509
1510/*
1511 * pvr2_upload_firmware2()
1512 *
1513 * This uploads encoder firmware on endpoint 2.
1514 *
1515 */
1516
1517int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1518{
a0fd1cb1 1519 const struct firmware *fw_entry = NULL;
d855497e 1520 void *fw_ptr;
90060d32 1521 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1522 int actual_length;
1523 int ret = 0;
1524 int fwidx;
1525 static const char *fw_files[] = {
1526 CX2341X_FIRM_ENC_FILENAME,
1527 };
1528
989eb154 1529 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1530 return 0;
1531 }
1532
d855497e
MI		 1533 trace_firmware("pvr2_upload_firmware2");
1534
1535 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1536 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1537 if (ret < 0) return ret;
1538 fwidx = ret;
1539 ret = 0;
b30d2441
MI		 1540 /* Since we're about to completely reinitialize the encoder,
1541 invalidate our cached copy of its configuration state. Next
1542 time we configure the encoder, then we'll fully configure it. */
1543 hdw->enc_cur_valid = 0;
d855497e 1544
d913d630
MI		 1545 /* Encoder is about to be reset so note that as far as we're
1546 concerned now, the encoder has never been run. */
1547 del_timer_sync(&hdw->encoder_run_timer);
1548 if (hdw->state_encoder_runok) {
1549 hdw->state_encoder_runok = 0;
1550 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1551 }
1552
d855497e
MI		 1553 /* First prepare firmware loading */
1554 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1555 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1556 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1557 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1558 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1559 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1560 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1561 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1562 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1563 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1564 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1565 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1566 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1567 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1568 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1569 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1c9d10d4
MI		 1570 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1571 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1572
1573 if (ret) {
1574 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1575 "firmware2 upload prep failed, ret=%d",ret);
1576 release_firmware(fw_entry);
21684ba9 1577 goto done;
d855497e
MI		 1578 }
1579
1580 /* Now send firmware */
1581
1582 fw_len = fw_entry->size;
1583
90060d32 1584 if (fw_len % sizeof(u32)) {
d855497e
MI		 1585 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1586 "size of %s firmware"
48dc30a1 1587 " must be a multiple of %zu bytes",
90060d32 1588 fw_files[fwidx],sizeof(u32));
d855497e 1589 release_firmware(fw_entry);
21684ba9
MI		 1590 ret = -EINVAL;
1591 goto done;
d855497e
MI		 1592 }
1593
1594 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1595 if (fw_ptr == NULL){
1596 release_firmware(fw_entry);
1597 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1598 "failed to allocate memory for firmware2 upload");
21684ba9
MI		 1599 ret = -ENOMEM;
1600 goto done;
d855497e
MI		 1601 }
1602
1603 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1604
90060d32
MI		 1605 fw_done = 0;
1606 for (fw_done = 0; fw_done < fw_len;) {
1607 bcnt = fw_len - fw_done;
1608 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1609 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1610 /* Usbsnoop log shows that we must swap bytes... */
5f33df14
MI		 1611 /* Some background info: The data being swapped here is a
1612 firmware image destined for the mpeg encoder chip that
1613 lives at the other end of a USB endpoint. The encoder
1614 chip always talks in 32 bit chunks and its storage is
1615 organized into 32 bit words. However from the file
1616 system to the encoder chip everything is purely a byte
1617 stream. The firmware file's contents are always 32 bit
1618 swapped from what the encoder expects. Thus the need
1619 always exists to swap the bytes regardless of the endian
1620 type of the host processor and therefore swab32() makes
1621 the most sense. */
90060d32 1622 for (icnt = 0; icnt < bcnt/4 ; icnt++)
513edce6 1623 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
90060d32
MI		 1624
1625 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1626 &actual_length, HZ);
90060d32
MI		 1627 ret |= (actual_length != bcnt);
1628 if (ret) break;
1629 fw_done += bcnt;
d855497e
MI		 1630 }
1631
1632 trace_firmware("upload of %s : %i / %i ",
1633 fw_files[fwidx],fw_done,fw_len);
1634
1635 kfree(fw_ptr);
1636 release_firmware(fw_entry);
1637
1638 if (ret) {
1639 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1640 "firmware2 upload transfer failure");
21684ba9 1641 goto done;
d855497e
MI		 1642 }
1643
1644 /* Finish upload */
1645
1646 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1647 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1c9d10d4 1648 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1649
1650 if (ret) {
1651 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1652 "firmware2 upload post-proc failure");
d855497e 1653 }
21684ba9
MI		 1654
1655 done:
1df59f0b
MI		 1656 if (hdw->hdw_desc->signal_routing_scheme ==
1657 PVR2_ROUTING_SCHEME_GOTVIEW) {
1658 /* Ensure that GPIO 11 is set to output for GOTVIEW
1659 hardware. */
1660 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1661 }
d855497e
MI		 1662 return ret;
1663}
1664
1665
681c7399
MI		 1666static const char *pvr2_get_state_name(unsigned int st)
1667{
1668 if (st < ARRAY_SIZE(pvr2_state_names)) {
1669 return pvr2_state_names[st];
d855497e 1670 }
681c7399 1671 return "???";
d855497e
MI		 1672}
1673
681c7399 1674static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1675{
af78e16b
MI		 1676 if (hdw->decoder_ctrl) {
1677 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt, enablefl);
1678 return 0;
681c7399 1679 }
af78e16b
MI		 1680 /* Even though we really only care about the video decoder chip at
1681 this point, we'll broadcast stream on/off to all sub-devices
1682 anyway, just in case somebody else wants to hear the
1683 command... */
e260508d
MI		 1684 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1685 (enablefl ? "on" : "off"));
af78e16b
MI		 1686 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1687 if (hdw->decoder_client_id) {
1688 /* We get here if the encoder has been noticed. Otherwise
1689 we'll issue a warning to the user (which should
1690 normally never happen). */
1691 return 0;
1692 }
1693 if (!hdw->flag_decoder_missed) {
1694 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1695 "WARNING: No decoder present");
1696 hdw->flag_decoder_missed = !0;
1697 trace_stbit("flag_decoder_missed",
1698 hdw->flag_decoder_missed);
1699 }
1700 return -EIO;
d855497e
MI		 1701}
1702
1703
681c7399 1704void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
d855497e 1705{
681c7399
MI		 1706 if (hdw->decoder_ctrl == ptr) return;
1707 hdw->decoder_ctrl = ptr;
1708 if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1709 hdw->flag_decoder_missed = 0;
1710 trace_stbit("flag_decoder_missed",
1711 hdw->flag_decoder_missed);
1712 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1713 "Decoder has appeared");
1714 pvr2_hdw_state_sched(hdw);
1715 }
d855497e
MI		 1716}
1717
1718
681c7399 1719int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1720{
681c7399 1721 return hdw->master_state;
d855497e
MI		 1722}
1723
1724
681c7399 1725static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1726{
681c7399
MI		 1727 if (!hdw->flag_tripped) return 0;
1728 hdw->flag_tripped = 0;
1729 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1730 "Clearing driver error statuss");
1731 return !0;
d855497e
MI		 1732}
1733
1734
681c7399 1735int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1736{
681c7399 1737 int fl;
d855497e 1738 LOCK_TAKE(hdw->big_lock); do {
681c7399 1739 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1740 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1741 if (fl) pvr2_hdw_state_sched(hdw);
1742 return 0;
d855497e
MI		 1743}
1744
1745
d855497e
MI		 1746
1747
1748int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1749{
681c7399 1750 return hdw->state_pipeline_req != 0;
d855497e
MI		 1751}
1752
1753
1754int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1755{
681c7399 1756 int ret,st;
d855497e 1757 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1758 pvr2_hdw_untrip_unlocked(hdw);
1759 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1760 hdw->state_pipeline_req = enable_flag != 0;
1761 pvr2_trace(PVR2_TRACE_START_STOP,
1762 "/*--TRACE_STREAM--*/ %s",
1763 enable_flag ? "enable" : "disable");
1764 }
1765 pvr2_hdw_state_sched(hdw);
d855497e 1766 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1767 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1768 if (enable_flag) {
1769 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1770 if (st != PVR2_STATE_READY) return -EIO;
1771 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1772 }
1773 }
d855497e
MI		 1774 return 0;
1775}
1776
1777
1778int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1779{
681c7399 1780 int fl;
d855497e 1781 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1782 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1783 hdw->desired_stream_type = config;
1784 hdw->state_pipeline_config = 0;
1785 trace_stbit("state_pipeline_config",
1786 hdw->state_pipeline_config);
1787 pvr2_hdw_state_sched(hdw);
1788 }
d855497e 1789 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1790 if (fl) return 0;
1791 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1792}
1793
1794
1795static int get_default_tuner_type(struct pvr2_hdw *hdw)
1796{
1797 int unit_number = hdw->unit_number;
1798 int tp = -1;
1799 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1800 tp = tuner[unit_number];
1801 }
1802 if (tp < 0) return -EINVAL;
1803 hdw->tuner_type = tp;
aaf7884d 1804 hdw->tuner_updated = !0;
d855497e
MI		 1805 return 0;
1806}
1807
1808
1809static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1810{
1811 int unit_number = hdw->unit_number;
1812 int tp = 0;
1813 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1814 tp = video_std[unit_number];
6a540254 1815 if (tp) return tp;
d855497e 1816 }
6a540254 1817 return 0;
d855497e
MI		 1818}
1819
1820
1821static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1822{
1823 int unit_number = hdw->unit_number;
1824 int tp = 0;
1825 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1826 tp = tolerance[unit_number];
1827 }
1828 return tp;
1829}
1830
1831
1832static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1833{
1834 /* Try a harmless request to fetch the eeprom's address over
1835 endpoint 1. See what happens. Only the full FX2 image can
1836 respond to this. If this probe fails then likely the FX2
1837 firmware needs be loaded. */
1838 int result;
1839 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1840 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1841 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1842 hdw->cmd_buffer,1,
1843 hdw->cmd_buffer,1);
1844 if (result < 0) break;
1845 } while(0); LOCK_GIVE(hdw->ctl_lock);
1846 if (result) {
1847 pvr2_trace(PVR2_TRACE_INIT,
1848 "Probe of device endpoint 1 result status %d",
1849 result);
1850 } else {
1851 pvr2_trace(PVR2_TRACE_INIT,
1852 "Probe of device endpoint 1 succeeded");
1853 }
1854 return result == 0;
1855}
1856
9f66d4ea
MI		 1857struct pvr2_std_hack {
1858 v4l2_std_id pat; /* Pattern to match */
1859 v4l2_std_id msk; /* Which bits we care about */
1860 v4l2_std_id std; /* What additional standards or default to set */
1861};
1862
1863/* This data structure labels specific combinations of standards from
1864 tveeprom that we'll try to recognize. If we recognize one, then assume
1865 a specified default standard to use. This is here because tveeprom only
1866 tells us about available standards not the intended default standard (if
1867 any) for the device in question. We guess the default based on what has
1868 been reported as available. Note that this is only for guessing a
1869 default - which can always be overridden explicitly - and if the user
1870 has otherwise named a default then that default will always be used in
1871 place of this table. */
ebff0330 1872static const struct pvr2_std_hack std_eeprom_maps[] = {
9f66d4ea
MI		 1873 { /* PAL(B/G) */
1874 .pat = V4L2_STD_B|V4L2_STD_GH,
1875 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1876 },
1877 { /* NTSC(M) */
1878 .pat = V4L2_STD_MN,
1879 .std = V4L2_STD_NTSC_M,
1880 },
1881 { /* PAL(I) */
1882 .pat = V4L2_STD_PAL_I,
1883 .std = V4L2_STD_PAL_I,
1884 },
1885 { /* SECAM(L/L') */
1886 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1887 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1888 },
1889 { /* PAL(D/D1/K) */
1890 .pat = V4L2_STD_DK,
ea2562d9 1891 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
9f66d4ea
MI		 1892 },
1893};
1894
d855497e
MI		 1895static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1896{
1897 char buf[40];
1898 unsigned int bcnt;
3d290bdb 1899 v4l2_std_id std1,std2,std3;
d855497e
MI		 1900
1901 std1 = get_default_standard(hdw);
3d290bdb 1902 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
d855497e
MI		 1903
1904 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1905 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1906 "Supported video standard(s) reported available"
1907 " in hardware: %.*s",
d855497e
MI		 1908 bcnt,buf);
1909
1910 hdw->std_mask_avail = hdw->std_mask_eeprom;
1911
3d290bdb 1912 std2 = (std1|std3) & ~hdw->std_mask_avail;
d855497e
MI		 1913 if (std2) {
1914 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1915 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1916 "Expanding supported video standards"
1917 " to include: %.*s",
1918 bcnt,buf);
1919 hdw->std_mask_avail |= std2;
1920 }
1921
1922 pvr2_hdw_internal_set_std_avail(hdw);
1923
1924 if (std1) {
1925 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1926 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1927 "Initial video standard forced to %.*s",
1928 bcnt,buf);
1929 hdw->std_mask_cur = std1;
1930 hdw->std_dirty = !0;
1931 pvr2_hdw_internal_find_stdenum(hdw);
1932 return;
1933 }
3d290bdb
MI		 1934 if (std3) {
1935 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1936 pvr2_trace(PVR2_TRACE_STD,
1937 "Initial video standard"
1938 " (determined by device type): %.*s",bcnt,buf);
1939 hdw->std_mask_cur = std3;
1940 hdw->std_dirty = !0;
1941 pvr2_hdw_internal_find_stdenum(hdw);
1942 return;
1943 }
d855497e 1944
9f66d4ea
MI		 1945 {
1946 unsigned int idx;
1947 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1948 if (std_eeprom_maps[idx].msk ?
1949 ((std_eeprom_maps[idx].pat ^
1950 hdw->std_mask_eeprom) &
1951 std_eeprom_maps[idx].msk) :
1952 (std_eeprom_maps[idx].pat !=
1953 hdw->std_mask_eeprom)) continue;
1954 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1955 std_eeprom_maps[idx].std);
56585386 1956 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1957 "Initial video standard guessed as %.*s",
1958 bcnt,buf);
1959 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1960 hdw->std_dirty = !0;
1961 pvr2_hdw_internal_find_stdenum(hdw);
1962 return;
1963 }
1964 }
1965
d855497e
MI		 1966 if (hdw->std_enum_cnt > 1) {
1967 // Autoselect the first listed standard
1968 hdw->std_enum_cur = 1;
1969 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1970 hdw->std_dirty = !0;
56585386 1971 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1972 "Initial video standard auto-selected to %s",
1973 hdw->std_defs[hdw->std_enum_cur-1].name);
1974 return;
1975 }
1976
0885ba1d 1977 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1978 "Unable to select a viable initial video standard");
1979}
1980
1981
e9c64a78
MI		 1982static unsigned int pvr2_copy_i2c_addr_list(
1983 unsigned short *dst, const unsigned char *src,
1984 unsigned int dst_max)
1985{
3ab8d295 1986 unsigned int cnt = 0;
e9c64a78
MI		 1987 if (!src) return 0;
1988 while (src[cnt] && (cnt + 1) < dst_max) {
1989 dst[cnt] = src[cnt];
1990 cnt++;
1991 }
1992 dst[cnt] = I2C_CLIENT_END;
1993 return cnt;
1994}
1995
1996
1ab5e74f
MI		 1997static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1998 const struct pvr2_device_client_desc *cd)
e9c64a78
MI		 1999{
2000 const char *fname;
2001 unsigned char mid;
2002 struct v4l2_subdev *sd;
2003 unsigned int i2ccnt;
2004 const unsigned char *p;
2005 /* Arbitrary count - max # i2c addresses we will probe */
2006 unsigned short i2caddr[25];
2007
2008 mid = cd->module_id;
2009 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2010 if (!fname) {
2011 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f 2012 "Module ID %u for device %s has no name",
e9c64a78
MI		 2013 mid,
2014 hdw->hdw_desc->description);
1ab5e74f 2015 return -EINVAL;
e9c64a78 2016 }
bd14d4f8
MI		 2017 pvr2_trace(PVR2_TRACE_INIT,
2018 "Module ID %u (%s) for device %s being loaded...",
2019 mid, fname,
2020 hdw->hdw_desc->description);
e9c64a78
MI		 2021
2022 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2023 ARRAY_SIZE(i2caddr));
2024 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2025 module_i2c_addresses[mid] : NULL) != NULL)) {
2026 /* Second chance: Try default i2c address list */
2027 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2028 ARRAY_SIZE(i2caddr));
bd14d4f8
MI		 2029 if (i2ccnt) {
2030 pvr2_trace(PVR2_TRACE_INIT,
2031 "Module ID %u:"
2032 " Using default i2c address list",
2033 mid);
2034 }
e9c64a78
MI		 2035 }
2036
2037 if (!i2ccnt) {
2038 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f
MI		 2039 "Module ID %u (%s) for device %s:"
2040 " No i2c addresses",
2041 mid, fname, hdw->hdw_desc->description);
2042 return -EINVAL;
e9c64a78
MI		 2043 }
2044
2045 /* Note how the 2nd and 3rd arguments are the same for both
2046 * v4l2_i2c_new_subdev() and v4l2_i2c_new_probed_subdev(). Why?
2047 * Well the 2nd argument is the module name to load, while the 3rd
2048 * argument is documented in the framework as being the "chipid" -
2049 * and every other place where I can find examples of this, the
2050 * "chipid" appears to just be the module name again. So here we
2051 * just do the same thing. */
0db85568 2052 hdw->i2c_adap.class = 0;
e9c64a78 2053 if (i2ccnt == 1) {
bd14d4f8
MI		 2054 pvr2_trace(PVR2_TRACE_INIT,
2055 "Module ID %u:"
2056 " Setting up with specified i2c address 0x%x",
2057 mid, i2caddr[0]);
e9c64a78
MI		 2058 sd = v4l2_i2c_new_subdev(&hdw->i2c_adap,
2059 fname, fname,
2060 i2caddr[0]);
2061 } else {
bd14d4f8
MI		 2062 pvr2_trace(PVR2_TRACE_INIT,
2063 "Module ID %u:"
2064 " Setting up with address probe list",
2065 mid);
e9c64a78
MI		 2066 sd = v4l2_i2c_new_probed_subdev(&hdw->i2c_adap,
2067 fname, fname,
2068 i2caddr);
2069 }
0db85568 2070 hdw->i2c_adap.class = I2C_CLASS_TV_ANALOG;
e9c64a78 2071
446dfdc6
MI		 2072 if (!sd) {
2073 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f
MI		 2074 "Module ID %u (%s) for device %s failed to load",
2075 mid, fname, hdw->hdw_desc->description);
2076 return -EIO;
446dfdc6
MI		 2077 }
2078
2079 /* Tag this sub-device instance with the module ID we know about.
2080 In other places we'll use that tag to determine if the instance
2081 requires special handling. */
2082 sd->grp_id = mid;
2083
a932f507
MI		 2084 /* If we have both old and new i2c layers enabled, make sure that
2085 old layer isn't also tracking this module. This is a debugging
2086 aid, in normal situations there's no reason for both mechanisms
2087 to be enabled. */
2088 pvr2_i2c_untrack_subdev(hdw, sd);
bd14d4f8 2089 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
a932f507 2090
e9c64a78 2091
00e5f736
MI		 2092 /* client-specific setup... */
2093 switch (mid) {
2094 case PVR2_CLIENT_ID_CX25840:
2095 hdw->decoder_client_id = mid;
2096 {
2097 /*
2098 Mike Isely <isely@pobox.com> 19-Nov-2006 - This
2099 bit of nuttiness for cx25840 causes that module
2100 to correctly set up its video scaling. This is
2101 really a problem in the cx25840 module itself,
2102 but we work around it here. The problem has not
2103 been seen in ivtv because there VBI is supported
2104 and set up. We don't do VBI here (at least not
2105 yet) and thus we never attempted to even set it
2106 up.
2107 */
2108 struct v4l2_format fmt;
bd14d4f8
MI		 2109 pvr2_trace(PVR2_TRACE_INIT,
2110 "Module ID %u:"
2111 " Executing cx25840 VBI hack",
2112 mid);
00e5f736
MI		 2113 memset(&fmt, 0, sizeof(fmt));
2114 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2115 v4l2_device_call_all(&hdw->v4l2_dev, mid,
2116 video, s_fmt, &fmt);
2117 }
2118 break;
2119 case PVR2_CLIENT_ID_SAA7115:
2120 hdw->decoder_client_id = mid;
2121 break;
2122 default: break;
2123 }
1ab5e74f
MI		 2124
2125 return 0;
e9c64a78
MI		 2126}
2127
2128
2129static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2130{
2131 unsigned int idx;
2132 const struct pvr2_string_table *cm;
2133 const struct pvr2_device_client_table *ct;
1ab5e74f 2134 int okFl = !0;
e9c64a78
MI		 2135
2136 cm = &hdw->hdw_desc->client_modules;
2137 for (idx = 0; idx < cm->cnt; idx++) {
2138 request_module(cm->lst[idx]);
2139 }
2140
2141 ct = &hdw->hdw_desc->client_table;
2142 for (idx = 0; idx < ct->cnt; idx++) {
bd14d4f8 2143 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
e9c64a78 2144 }
1ab5e74f 2145 if (!okFl) pvr2_hdw_render_useless(hdw);
e9c64a78
MI		 2146}
2147
2148
d855497e
MI		 2149static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2150{
2151 int ret;
2152 unsigned int idx;
2153 struct pvr2_ctrl *cptr;
2154 int reloadFl = 0;
989eb154 2155 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 2156 if (!reloadFl) {
2157 reloadFl =
2158 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2159 == 0);
2160 if (reloadFl) {
2161 pvr2_trace(PVR2_TRACE_INIT,
2162 "USB endpoint config looks strange"
2163 "; possibly firmware needs to be"
2164 " loaded");
2165 }
d855497e 2166 }
1d643a37
MI		 2167 if (!reloadFl) {
2168 reloadFl = !pvr2_hdw_check_firmware(hdw);
2169 if (reloadFl) {
2170 pvr2_trace(PVR2_TRACE_INIT,
2171 "Check for FX2 firmware failed"
2172 "; possibly firmware needs to be"
2173 " loaded");
2174 }
d855497e 2175 }
1d643a37
MI		 2176 if (reloadFl) {
2177 if (pvr2_upload_firmware1(hdw) != 0) {
2178 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2179 "Failure uploading firmware1");
2180 }
2181 return;
d855497e 2182 }
d855497e
MI		 2183 }
2184 hdw->fw1_state = FW1_STATE_OK;
2185
d855497e
MI		 2186 if (!pvr2_hdw_dev_ok(hdw)) return;
2187
27764726
MI		 2188 hdw->force_dirty = !0;
2189
989eb154 2190 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 2191 pvr2_hdw_cmd_powerup(hdw);
2192 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 2193 }
2194
31335b13
MI		 2195 /* Take the IR chip out of reset, if appropriate */
2196 if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
2197 pvr2_issue_simple_cmd(hdw,
2198 FX2CMD_HCW_ZILOG_RESET |
2199 (1 << 8) |
2200 ((0) << 16));
2201 }
2202
d855497e 2203 // This step MUST happen after the earlier powerup step.
59af3367 2204 pvr2_i2c_track_init(hdw);
d855497e
MI		 2205 pvr2_i2c_core_init(hdw);
2206 if (!pvr2_hdw_dev_ok(hdw)) return;
2207
e9c64a78 2208 pvr2_hdw_load_modules(hdw);
1ab5e74f 2209 if (!pvr2_hdw_dev_ok(hdw)) return;
e9c64a78 2210
c05c0462 2211 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 2212 cptr = hdw->controls + idx;
2213 if (cptr->info->skip_init) continue;
2214 if (!cptr->info->set_value) continue;
2215 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2216 }
2217
1bde0289
MI		 2218 /* Set up special default values for the television and radio
2219 frequencies here. It's not really important what these defaults
2220 are, but I set them to something usable in the Chicago area just
2221 to make driver testing a little easier. */
2222
5a4f5da6
MK		 2223 hdw->freqValTelevision = default_tv_freq;
2224 hdw->freqValRadio = default_radio_freq;
1bde0289 2225
d855497e
MI		 2226 // Do not use pvr2_reset_ctl_endpoints() here. It is not
2227 // thread-safe against the normal pvr2_send_request() mechanism.
2228 // (We should make it thread safe).
2229
aaf7884d
MI		 2230 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2231 ret = pvr2_hdw_get_eeprom_addr(hdw);
d855497e 2232 if (!pvr2_hdw_dev_ok(hdw)) return;
aaf7884d
MI		 2233 if (ret < 0) {
2234 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2235 "Unable to determine location of eeprom,"
2236 " skipping");
2237 } else {
2238 hdw->eeprom_addr = ret;
2239 pvr2_eeprom_analyze(hdw);
2240 if (!pvr2_hdw_dev_ok(hdw)) return;
2241 }
2242 } else {
2243 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2244 hdw->tuner_updated = !0;
2245 hdw->std_mask_eeprom = V4L2_STD_ALL;
d855497e
MI		 2246 }
2247
13a88797
MI		 2248 if (hdw->serial_number) {
2249 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2250 "sn-%lu", hdw->serial_number);
2251 } else if (hdw->unit_number >= 0) {
2252 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2253 "unit-%c",
2254 hdw->unit_number + 'a');
2255 } else {
2256 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2257 "unit-??");
2258 }
2259 hdw->identifier[idx] = 0;
2260
d855497e
MI		 2261 pvr2_hdw_setup_std(hdw);
2262
2263 if (!get_default_tuner_type(hdw)) {
2264 pvr2_trace(PVR2_TRACE_INIT,
2265 "pvr2_hdw_setup: Tuner type overridden to %d",
2266 hdw->tuner_type);
2267 }
2268
d855497e 2269 pvr2_i2c_core_check_stale(hdw);
d855497e
MI		 2270
2271 if (!pvr2_hdw_dev_ok(hdw)) return;
2272
1df59f0b
MI		 2273 if (hdw->hdw_desc->signal_routing_scheme ==
2274 PVR2_ROUTING_SCHEME_GOTVIEW) {
2275 /* Ensure that GPIO 11 is set to output for GOTVIEW
2276 hardware. */
2277 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2278 }
2279
681c7399 2280 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 2281
2282 hdw->vid_stream = pvr2_stream_create();
2283 if (!pvr2_hdw_dev_ok(hdw)) return;
2284 pvr2_trace(PVR2_TRACE_INIT,
2285 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2286 if (hdw->vid_stream) {
2287 idx = get_default_error_tolerance(hdw);
2288 if (idx) {
2289 pvr2_trace(PVR2_TRACE_INIT,
2290 "pvr2_hdw_setup: video stream %p"
2291 " setting tolerance %u",
2292 hdw->vid_stream,idx);
2293 }
2294 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2295 PVR2_VID_ENDPOINT,idx);
2296 }
2297
2298 if (!pvr2_hdw_dev_ok(hdw)) return;
2299
d855497e 2300 hdw->flag_init_ok = !0;
681c7399
MI		 2301
2302 pvr2_hdw_state_sched(hdw);
d855497e
MI		 2303}
2304
2305
681c7399
MI		 2306/* Set up the structure and attempt to put the device into a usable state.
2307 This can be a time-consuming operation, which is why it is not done
2308 internally as part of the create() step. */
2309static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 2310{
2311 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 2312 do {
d855497e
MI		 2313 pvr2_hdw_setup_low(hdw);
2314 pvr2_trace(PVR2_TRACE_INIT,
2315 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 2316 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 2317 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 2318 if (hdw->flag_init_ok) {
d855497e
MI		 2319 pvr2_trace(
2320 PVR2_TRACE_INFO,
2321 "Device initialization"
2322 " completed successfully.");
2323 break;
2324 }
2325 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2326 pvr2_trace(
2327 PVR2_TRACE_INFO,
2328 "Device microcontroller firmware"
2329 " (re)loaded; it should now reset"
2330 " and reconnect.");
2331 break;
2332 }
2333 pvr2_trace(
2334 PVR2_TRACE_ERROR_LEGS,
2335 "Device initialization was not successful.");
2336 if (hdw->fw1_state == FW1_STATE_MISSING) {
2337 pvr2_trace(
2338 PVR2_TRACE_ERROR_LEGS,
2339 "Giving up since device"
2340 " microcontroller firmware"
2341 " appears to be missing.");
2342 break;
2343 }
2344 }
2345 if (procreload) {
2346 pvr2_trace(
2347 PVR2_TRACE_ERROR_LEGS,
2348 "Attempting pvrusb2 recovery by reloading"
2349 " primary firmware.");
2350 pvr2_trace(
2351 PVR2_TRACE_ERROR_LEGS,
2352 "If this works, device should disconnect"
2353 " and reconnect in a sane state.");
2354 hdw->fw1_state = FW1_STATE_UNKNOWN;
2355 pvr2_upload_firmware1(hdw);
2356 } else {
2357 pvr2_trace(
2358 PVR2_TRACE_ERROR_LEGS,
2359 "***WARNING*** pvrusb2 device hardware"
2360 " appears to be jammed"
2361 " and I can't clear it.");
2362 pvr2_trace(
2363 PVR2_TRACE_ERROR_LEGS,
2364 "You might need to power cycle"
2365 " the pvrusb2 device"
2366 " in order to recover.");
2367 }
681c7399 2368 } while (0);
d855497e 2369 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 2370}
2371
2372
c4a8828d
MI		 2373/* Perform second stage initialization. Set callback pointer first so that
2374 we can avoid a possible initialization race (if the kernel thread runs
2375 before the callback has been set). */
794b1607
MI		 2376int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2377 void (*callback_func)(void *),
2378 void *callback_data)
c4a8828d
MI		 2379{
2380 LOCK_TAKE(hdw->big_lock); do {
97f26ff6
MI		 2381 if (hdw->flag_disconnected) {
2382 /* Handle a race here: If we're already
2383 disconnected by this point, then give up. If we
2384 get past this then we'll remain connected for
2385 the duration of initialization since the entire
2386 initialization sequence is now protected by the
2387 big_lock. */
2388 break;
2389 }
c4a8828d
MI		 2390 hdw->state_data = callback_data;
2391 hdw->state_func = callback_func;
97f26ff6 2392 pvr2_hdw_setup(hdw);
c4a8828d 2393 } while (0); LOCK_GIVE(hdw->big_lock);
794b1607 2394 return hdw->flag_init_ok;
c4a8828d
MI		 2395}
2396
2397
2398/* Create, set up, and return a structure for interacting with the
2399 underlying hardware. */
d855497e
MI		 2400struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2401 const struct usb_device_id *devid)
2402{
7fb20fa3 2403 unsigned int idx,cnt1,cnt2,m;
fe15f136 2404 struct pvr2_hdw *hdw = NULL;
d855497e
MI		 2405 int valid_std_mask;
2406 struct pvr2_ctrl *cptr;
b72b7bf5 2407 struct usb_device *usb_dev;
989eb154 2408 const struct pvr2_device_desc *hdw_desc;
d855497e 2409 __u8 ifnum;
b30d2441
MI		 2410 struct v4l2_queryctrl qctrl;
2411 struct pvr2_ctl_info *ciptr;
d855497e 2412
b72b7bf5
MI		 2413 usb_dev = interface_to_usbdev(intf);
2414
d130fa8a 2415 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
d855497e 2416
fe15f136
MI		 2417 if (hdw_desc == NULL) {
2418 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2419 " No device description pointer,"
2420 " unable to continue.");
2421 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2422 " please contact Mike Isely <isely@pobox.com>"
2423 " to get it included in the driver\n");
2424 goto fail;
2425 }
2426
ca545f7c 2427 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 2428 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 2429 hdw,hdw_desc->description);
d855497e 2430 if (!hdw) goto fail;
681c7399
MI		 2431
2432 init_timer(&hdw->quiescent_timer);
2433 hdw->quiescent_timer.data = (unsigned long)hdw;
2434 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2435
2436 init_timer(&hdw->encoder_wait_timer);
2437 hdw->encoder_wait_timer.data = (unsigned long)hdw;
2438 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2439
d913d630
MI		 2440 init_timer(&hdw->encoder_run_timer);
2441 hdw->encoder_run_timer.data = (unsigned long)hdw;
2442 hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2443
681c7399
MI		 2444 hdw->master_state = PVR2_STATE_DEAD;
2445
2446 init_waitqueue_head(&hdw->state_wait_data);
2447
18103c57 2448 hdw->tuner_signal_stale = !0;
b30d2441 2449 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 2450
7fb20fa3
MI		 2451 /* Calculate which inputs are OK */
2452 m = 0;
2453 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
e8f5bacf
MI		 2454 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2455 m |= 1 << PVR2_CVAL_INPUT_DTV;
2456 }
7fb20fa3
MI		 2457 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2458 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2459 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2460 hdw->input_avail_mask = m;
1cb03b76 2461 hdw->input_allowed_mask = hdw->input_avail_mask;
7fb20fa3 2462
62433e31
MI		 2463 /* If not a hybrid device, pathway_state never changes. So
2464 initialize it here to what it should forever be. */
2465 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2466 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2467 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2468 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2469 }
2470
c05c0462 2471 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 2472 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 2473 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 2474 GFP_KERNEL);
2475 if (!hdw->controls) goto fail;
989eb154 2476 hdw->hdw_desc = hdw_desc;
c05c0462
MI		 2477 for (idx = 0; idx < hdw->control_cnt; idx++) {
2478 cptr = hdw->controls + idx;
2479 cptr->hdw = hdw;
2480 }
d855497e
MI		 2481 for (idx = 0; idx < 32; idx++) {
2482 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2483 }
c05c0462 2484 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 2485 cptr = hdw->controls + idx;
d855497e
MI		 2486 cptr->info = control_defs+idx;
2487 }
dbc40a0e
MI		 2488
2489 /* Ensure that default input choice is a valid one. */
2490 m = hdw->input_avail_mask;
2491 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2492 if (!((1 << idx) & m)) continue;
2493 hdw->input_val = idx;
2494 break;
2495 }
2496
b30d2441 2497 /* Define and configure additional controls from cx2341x module. */
ca545f7c 2498 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 2499 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2500 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 2501 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2502 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2503 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2504 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2505 ciptr->name = mpeg_ids[idx].strid;
2506 ciptr->v4l_id = mpeg_ids[idx].id;
2507 ciptr->skip_init = !0;
2508 ciptr->get_value = ctrl_cx2341x_get;
2509 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2510 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2511 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2512 qctrl.id = ciptr->v4l_id;
2513 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2514 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2515 ciptr->set_value = ctrl_cx2341x_set;
2516 }
2517 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2518 PVR2_CTLD_INFO_DESC_SIZE);
2519 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2520 ciptr->default_value = qctrl.default_value;
2521 switch (qctrl.type) {
2522 default:
2523 case V4L2_CTRL_TYPE_INTEGER:
2524 ciptr->type = pvr2_ctl_int;
2525 ciptr->def.type_int.min_value = qctrl.minimum;
2526 ciptr->def.type_int.max_value = qctrl.maximum;
2527 break;
2528 case V4L2_CTRL_TYPE_BOOLEAN:
2529 ciptr->type = pvr2_ctl_bool;
2530 break;
2531 case V4L2_CTRL_TYPE_MENU:
2532 ciptr->type = pvr2_ctl_enum;
2533 ciptr->def.type_enum.value_names =
e0e31cdb
HV		 2534 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2535 ciptr->v4l_id);
b30d2441
MI		 2536 for (cnt1 = 0;
2537 ciptr->def.type_enum.value_names[cnt1] != NULL;
2538 cnt1++) { }
2539 ciptr->def.type_enum.count = cnt1;
2540 break;
2541 }
2542 cptr->info = ciptr;
2543 }
d855497e
MI		 2544
2545 // Initialize video standard enum dynamic control
2546 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2547 if (cptr) {
2548 memcpy(&hdw->std_info_enum,cptr->info,
2549 sizeof(hdw->std_info_enum));
2550 cptr->info = &hdw->std_info_enum;
2551
2552 }
2553 // Initialize control data regarding video standard masks
2554 valid_std_mask = pvr2_std_get_usable();
2555 for (idx = 0; idx < 32; idx++) {
2556 if (!(valid_std_mask & (1 << idx))) continue;
2557 cnt1 = pvr2_std_id_to_str(
2558 hdw->std_mask_names[idx],
2559 sizeof(hdw->std_mask_names[idx])-1,
2560 1 << idx);
2561 hdw->std_mask_names[idx][cnt1] = 0;
2562 }
2563 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2564 if (cptr) {
2565 memcpy(&hdw->std_info_avail,cptr->info,
2566 sizeof(hdw->std_info_avail));
2567 cptr->info = &hdw->std_info_avail;
2568 hdw->std_info_avail.def.type_bitmask.bit_names =
2569 hdw->std_mask_ptrs;
2570 hdw->std_info_avail.def.type_bitmask.valid_bits =
2571 valid_std_mask;
2572 }
2573 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2574 if (cptr) {
2575 memcpy(&hdw->std_info_cur,cptr->info,
2576 sizeof(hdw->std_info_cur));
2577 cptr->info = &hdw->std_info_cur;
2578 hdw->std_info_cur.def.type_bitmask.bit_names =
2579 hdw->std_mask_ptrs;
2580 hdw->std_info_avail.def.type_bitmask.valid_bits =
2581 valid_std_mask;
2582 }
2583
432907f7 2584 hdw->cropcap_stale = !0;
d855497e
MI		 2585 hdw->eeprom_addr = -1;
2586 hdw->unit_number = -1;
8079384e
MI		 2587 hdw->v4l_minor_number_video = -1;
2588 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 2589 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 2590 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2591 if (!hdw->ctl_write_buffer) goto fail;
2592 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2593 if (!hdw->ctl_read_buffer) goto fail;
2594 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2595 if (!hdw->ctl_write_urb) goto fail;
2596 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2597 if (!hdw->ctl_read_urb) goto fail;
2598
b72b7bf5
MI		 2599 if (v4l2_device_register(&usb_dev->dev, &hdw->v4l2_dev) != 0) {
2600 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2601 "Error registering with v4l core, giving up");
2602 goto fail;
2603 }
8df0c87c 2604 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2605 for (idx = 0; idx < PVR_NUM; idx++) {
2606 if (unit_pointers[idx]) continue;
2607 hdw->unit_number = idx;
2608 unit_pointers[idx] = hdw;
2609 break;
2610 }
8df0c87c 2611 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 2612
2613 cnt1 = 0;
2614 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2615 cnt1 += cnt2;
2616 if (hdw->unit_number >= 0) {
2617 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2618 ('a' + hdw->unit_number));
2619 cnt1 += cnt2;
2620 }
2621 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2622 hdw->name[cnt1] = 0;
2623
681c7399
MI		 2624 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2625 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2626 INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
681c7399 2627
d855497e
MI		 2628 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2629 hdw->unit_number,hdw->name);
2630
2631 hdw->tuner_type = -1;
2632 hdw->flag_ok = !0;
d855497e
MI		 2633
2634 hdw->usb_intf = intf;
b72b7bf5 2635 hdw->usb_dev = usb_dev;
d855497e 2636
87e3495c 2637 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
31a18547 2638
d855497e
MI		 2639 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2640 usb_set_interface(hdw->usb_dev,ifnum,0);
2641
2642 mutex_init(&hdw->ctl_lock_mutex);
2643 mutex_init(&hdw->big_lock_mutex);
2644
2645 return hdw;
2646 fail:
2647 if (hdw) {
681c7399 2648 del_timer_sync(&hdw->quiescent_timer);
d913d630 2649 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 2650 del_timer_sync(&hdw->encoder_wait_timer);
2651 if (hdw->workqueue) {
2652 flush_workqueue(hdw->workqueue);
2653 destroy_workqueue(hdw->workqueue);
2654 hdw->workqueue = NULL;
2655 }
5e55d2ce
MK		 2656 usb_free_urb(hdw->ctl_read_urb);
2657 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2658 kfree(hdw->ctl_read_buffer);
2659 kfree(hdw->ctl_write_buffer);
2660 kfree(hdw->controls);
2661 kfree(hdw->mpeg_ctrl_info);
681c7399
MI		 2662 kfree(hdw->std_defs);
2663 kfree(hdw->std_enum_names);
d855497e
MI		 2664 kfree(hdw);
2665 }
a0fd1cb1 2666 return NULL;
d855497e
MI		 2667}
2668
2669
2670/* Remove _all_ associations between this driver and the underlying USB
2671 layer. */
07e337ee 2672static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2673{
2674 if (hdw->flag_disconnected) return;
2675 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2676 if (hdw->ctl_read_urb) {
2677 usb_kill_urb(hdw->ctl_read_urb);
2678 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2679 hdw->ctl_read_urb = NULL;
d855497e
MI		 2680 }
2681 if (hdw->ctl_write_urb) {
2682 usb_kill_urb(hdw->ctl_write_urb);
2683 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2684 hdw->ctl_write_urb = NULL;
d855497e
MI		 2685 }
2686 if (hdw->ctl_read_buffer) {
2687 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2688 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2689 }
2690 if (hdw->ctl_write_buffer) {
2691 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2692 hdw->ctl_write_buffer = NULL;
d855497e 2693 }
d855497e 2694 hdw->flag_disconnected = !0;
b72b7bf5
MI		 2695 /* If we don't do this, then there will be a dangling struct device
2696 reference to our disappearing device persisting inside the V4L
2697 core... */
2698 if (hdw->v4l2_dev.dev) {
2699 dev_set_drvdata(hdw->v4l2_dev.dev, NULL);
2700 hdw->v4l2_dev.dev = NULL;
2701 }
a0fd1cb1
MI		 2702 hdw->usb_dev = NULL;
2703 hdw->usb_intf = NULL;
681c7399 2704 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2705}
2706
2707
2708/* Destroy hardware interaction structure */
2709void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2710{
401c27ce 2711 if (!hdw) return;
d855497e 2712 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2713 if (hdw->workqueue) {
2714 flush_workqueue(hdw->workqueue);
2715 destroy_workqueue(hdw->workqueue);
2716 hdw->workqueue = NULL;
2717 }
8f59100a 2718 del_timer_sync(&hdw->quiescent_timer);
d913d630 2719 del_timer_sync(&hdw->encoder_run_timer);
8f59100a 2720 del_timer_sync(&hdw->encoder_wait_timer);
d855497e
MI		 2721 if (hdw->fw_buffer) {
2722 kfree(hdw->fw_buffer);
a0fd1cb1 2723 hdw->fw_buffer = NULL;
d855497e
MI		 2724 }
2725 if (hdw->vid_stream) {
2726 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2727 hdw->vid_stream = NULL;
d855497e 2728 }
d855497e
MI		 2729 if (hdw->decoder_ctrl) {
2730 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2731 }
2732 pvr2_i2c_core_done(hdw);
59af3367 2733 pvr2_i2c_track_done(hdw);
b72b7bf5 2734 v4l2_device_unregister(&hdw->v4l2_dev);
d855497e 2735 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2736 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2737 if ((hdw->unit_number >= 0) &&
2738 (hdw->unit_number < PVR_NUM) &&
2739 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2740 unit_pointers[hdw->unit_number] = NULL;
d855497e 2741 }
8df0c87c 2742 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2743 kfree(hdw->controls);
2744 kfree(hdw->mpeg_ctrl_info);
2745 kfree(hdw->std_defs);
2746 kfree(hdw->std_enum_names);
d855497e
MI		 2747 kfree(hdw);
2748}
2749
2750
d855497e
MI		 2751int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2752{
2753 return (hdw && hdw->flag_ok);
2754}
2755
2756
2757/* Called when hardware has been unplugged */
2758void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2759{
2760 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2761 LOCK_TAKE(hdw->big_lock);
2762 LOCK_TAKE(hdw->ctl_lock);
2763 pvr2_hdw_remove_usb_stuff(hdw);
2764 LOCK_GIVE(hdw->ctl_lock);
2765 LOCK_GIVE(hdw->big_lock);
2766}
2767
2768
2769// Attempt to autoselect an appropriate value for std_enum_cur given
2770// whatever is currently in std_mask_cur
07e337ee 2771static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2772{
2773 unsigned int idx;
2774 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2775 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2776 hdw->std_enum_cur = idx;
2777 return;
2778 }
2779 }
2780 hdw->std_enum_cur = 0;
2781}
2782
2783
2784// Calculate correct set of enumerated standards based on currently known
2785// set of available standards bits.
07e337ee 2786static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2787{
2788 struct v4l2_standard *newstd;
2789 unsigned int std_cnt;
2790 unsigned int idx;
2791
2792 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2793
2794 if (hdw->std_defs) {
2795 kfree(hdw->std_defs);
a0fd1cb1 2796 hdw->std_defs = NULL;
d855497e
MI		 2797 }
2798 hdw->std_enum_cnt = 0;
2799 if (hdw->std_enum_names) {
2800 kfree(hdw->std_enum_names);
a0fd1cb1 2801 hdw->std_enum_names = NULL;
d855497e
MI		 2802 }
2803
2804 if (!std_cnt) {
2805 pvr2_trace(
2806 PVR2_TRACE_ERROR_LEGS,
2807 "WARNING: Failed to identify any viable standards");
2808 }
2809 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2810 hdw->std_enum_names[0] = "none";
2811 for (idx = 0; idx < std_cnt; idx++) {
2812 hdw->std_enum_names[idx+1] =
2813 newstd[idx].name;
2814 }
2815 // Set up the dynamic control for this standard
2816 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2817 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2818 hdw->std_defs = newstd;
2819 hdw->std_enum_cnt = std_cnt+1;
2820 hdw->std_enum_cur = 0;
2821 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2822}
2823
2824
2825int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2826 struct v4l2_standard *std,
2827 unsigned int idx)
2828{
2829 int ret = -EINVAL;
2830 if (!idx) return ret;
2831 LOCK_TAKE(hdw->big_lock); do {
2832 if (idx >= hdw->std_enum_cnt) break;
2833 idx--;
2834 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2835 ret = 0;
2836 } while (0); LOCK_GIVE(hdw->big_lock);
2837 return ret;
2838}
2839
2840
2841/* Get the number of defined controls */
2842unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2843{
c05c0462 2844 return hdw->control_cnt;
d855497e
MI		 2845}
2846
2847
2848/* Retrieve a control handle given its index (0..count-1) */
2849struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2850 unsigned int idx)
2851{
a0fd1cb1 2852 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2853 return hdw->controls + idx;
2854}
2855
2856
2857/* Retrieve a control handle given its index (0..count-1) */
2858struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2859 unsigned int ctl_id)
2860{
2861 struct pvr2_ctrl *cptr;
2862 unsigned int idx;
2863 int i;
2864
2865 /* This could be made a lot more efficient, but for now... */
c05c0462 2866 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2867 cptr = hdw->controls + idx;
2868 i = cptr->info->internal_id;
2869 if (i && (i == ctl_id)) return cptr;
2870 }
a0fd1cb1 2871 return NULL;
d855497e
MI		 2872}
2873
2874
a761f431 2875/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2876struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2877{
2878 struct pvr2_ctrl *cptr;
2879 unsigned int idx;
2880 int i;
2881
2882 /* This could be made a lot more efficient, but for now... */
c05c0462 2883 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2884 cptr = hdw->controls + idx;
2885 i = cptr->info->v4l_id;
2886 if (i && (i == ctl_id)) return cptr;
2887 }
a0fd1cb1 2888 return NULL;
d855497e
MI		 2889}
2890
2891
a761f431
MI		 2892/* Given a V4L ID for its immediate predecessor, retrieve the control
2893 structure associated with it. */
2894struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2895 unsigned int ctl_id)
2896{
2897 struct pvr2_ctrl *cptr,*cp2;
2898 unsigned int idx;
2899 int i;
2900
2901 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2902 cp2 = NULL;
a761f431
MI		 2903 for (idx = 0; idx < hdw->control_cnt; idx++) {
2904 cptr = hdw->controls + idx;
2905 i = cptr->info->v4l_id;
2906 if (!i) continue;
2907 if (i <= ctl_id) continue;
2908 if (cp2 && (cp2->info->v4l_id < i)) continue;
2909 cp2 = cptr;
2910 }
2911 return cp2;
a0fd1cb1 2912 return NULL;
a761f431
MI		 2913}
2914
2915
d855497e
MI		 2916static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2917{
2918 switch (tp) {
2919 case pvr2_ctl_int: return "integer";
2920 case pvr2_ctl_enum: return "enum";
33213963 2921 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2922 case pvr2_ctl_bitmask: return "bitmask";
2923 }
2924 return "";
2925}
2926
2927
2641df36
MI		 2928static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2929 const char *name, int val)
2930{
2931 struct v4l2_control ctrl;
2932 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2933 memset(&ctrl, 0, sizeof(ctrl));
2934 ctrl.id = id;
2935 ctrl.value = val;
2936 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2937}
2938
2939#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
27764726 2940 if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \
2641df36
MI		 2941 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2942 }
2943
5ceaad14 2944/* Execute whatever commands are required to update the state of all the
2641df36 2945 sub-devices so that they match our current control values. */
5ceaad14
MI		 2946static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2947{
edb9dcb8
MI		 2948 struct v4l2_subdev *sd;
2949 unsigned int id;
2950 pvr2_subdev_update_func fp;
2951
75212a02
MI		 2952 pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2953
27764726 2954 if (hdw->tuner_updated || hdw->force_dirty) {
75212a02
MI		 2955 struct tuner_setup setup;
2956 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2957 hdw->tuner_type);
2958 if (((int)(hdw->tuner_type)) >= 0) {
2959 setup.addr = ADDR_UNSET;
2960 setup.type = hdw->tuner_type;
2961 setup.mode_mask = T_RADIO | T_ANALOG_TV;
2962 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2963 tuner, s_type_addr, &setup);
2964 }
2965 }
2966
27764726 2967 if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
b481880b 2968 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2641df36
MI		 2969 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2970 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2971 tuner, s_radio);
2972 } else {
2973 v4l2_std_id vs;
2974 vs = hdw->std_mask_cur;
2975 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2976 tuner, s_std, vs);
2977 }
2978 hdw->tuner_signal_stale = !0;
2979 hdw->cropcap_stale = !0;
2980 }
2981
2982 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2983 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2984 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2985 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2986 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2987 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2988 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2989 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2990 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2991
27764726 2992 if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2641df36
MI		 2993 struct v4l2_tuner vt;
2994 memset(&vt, 0, sizeof(vt));
2995 vt.audmode = hdw->audiomode_val;
2996 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2997 }
2998
27764726 2999 if (hdw->freqDirty || hdw->force_dirty) {
2641df36
MI		 3000 unsigned long fv;
3001 struct v4l2_frequency freq;
3002 fv = pvr2_hdw_get_cur_freq(hdw);
3003 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
3004 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
3005 memset(&freq, 0, sizeof(freq));
3006 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
3007 /* ((fv * 1000) / 62500) */
3008 freq.frequency = (fv * 2) / 125;
3009 } else {
3010 freq.frequency = fv / 62500;
3011 }
3012 /* tuner-core currently doesn't seem to care about this, but
3013 let's set it anyway for completeness. */
3014 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3015 freq.type = V4L2_TUNER_RADIO;
3016 } else {
3017 freq.type = V4L2_TUNER_ANALOG_TV;
3018 }
3019 freq.tuner = 0;
3020 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
3021 s_frequency, &freq);
3022 }
3023
27764726 3024 if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
2641df36
MI		 3025 struct v4l2_format fmt;
3026 memset(&fmt, 0, sizeof(fmt));
3027 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
3028 fmt.fmt.pix.width = hdw->res_hor_val;
3029 fmt.fmt.pix.height = hdw->res_ver_val;
3030 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_size(%dx%d)",
3031 fmt.fmt.pix.width, fmt.fmt.pix.height);
3032 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
3033 }
3034
27764726 3035 if (hdw->srate_dirty || hdw->force_dirty) {
01c59df8
MI		 3036 u32 val;
3037 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3038 hdw->srate_val);
3039 switch (hdw->srate_val) {
3040 default:
3041 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3042 val = 48000;
3043 break;
3044 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3045 val = 44100;
3046 break;
3047 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3048 val = 32000;
3049 break;
3050 }
3051 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3052 audio, s_clock_freq, val);
3053 }
3054
2641df36
MI		 3055 /* Unable to set crop parameters; there is apparently no equivalent
3056 for VIDIOC_S_CROP */
3057
edb9dcb8
MI		 3058 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3059 id = sd->grp_id;
3060 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3061 fp = pvr2_module_update_functions[id];
3062 if (!fp) continue;
3063 (*fp)(hdw, sd);
3064 }
2641df36 3065
27764726 3066 if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
2641df36
MI		 3067 pvr2_hdw_status_poll(hdw);
3068 }
5ceaad14
MI		 3069}
3070
3071
681c7399
MI		 3072/* Figure out if we need to commit control changes. If so, mark internal
3073 state flags to indicate this fact and return true. Otherwise do nothing
3074 else and return false. */
3075static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 3076{
d855497e
MI		 3077 unsigned int idx;
3078 struct pvr2_ctrl *cptr;
3079 int value;
27764726 3080 int commit_flag = hdw->force_dirty;
d855497e
MI		 3081 char buf[100];
3082 unsigned int bcnt,ccnt;
3083
c05c0462 3084 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e 3085 cptr = hdw->controls + idx;
5fa1247a 3086 if (!cptr->info->is_dirty) continue;
d855497e 3087 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 3088 commit_flag = !0;
d855497e 3089
fe23a280 3090 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 3091 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3092 cptr->info->name);
3093 value = 0;
3094 cptr->info->get_value(cptr,&value);
3095 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3096 buf+bcnt,
3097 sizeof(buf)-bcnt,&ccnt);
3098 bcnt += ccnt;
3099 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3100 get_ctrl_typename(cptr->info->type));
3101 pvr2_trace(PVR2_TRACE_CTL,
3102 "/*--TRACE_COMMIT--*/ %.*s",
3103 bcnt,buf);
3104 }
3105
3106 if (!commit_flag) {
3107 /* Nothing has changed */
3108 return 0;
3109 }
3110
681c7399
MI		 3111 hdw->state_pipeline_config = 0;
3112 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3113 pvr2_hdw_state_sched(hdw);
3114
3115 return !0;
3116}
3117
3118
3119/* Perform all operations needed to commit all control changes. This must
3120 be performed in synchronization with the pipeline state and is thus
3121 expected to be called as part of the driver's worker thread. Return
3122 true if commit successful, otherwise return false to indicate that
3123 commit isn't possible at this time. */
3124static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3125{
3126 unsigned int idx;
3127 struct pvr2_ctrl *cptr;
3128 int disruptive_change;
3129
ab062fe3
MI		 3130 /* Handle some required side effects when the video standard is
3131 changed.... */
d855497e 3132 if (hdw->std_dirty) {
d855497e 3133 int nvres;
00528d9c 3134 int gop_size;
d855497e
MI		 3135 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3136 nvres = 480;
00528d9c 3137 gop_size = 15;
d855497e
MI		 3138 } else {
3139 nvres = 576;
00528d9c 3140 gop_size = 12;
d855497e 3141 }
00528d9c
MI		 3142 /* Rewrite the vertical resolution to be appropriate to the
3143 video standard that has been selected. */
d855497e
MI		 3144 if (nvres != hdw->res_ver_val) {
3145 hdw->res_ver_val = nvres;
3146 hdw->res_ver_dirty = !0;
3147 }
00528d9c
MI		 3148 /* Rewrite the GOP size to be appropriate to the video
3149 standard that has been selected. */
3150 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3151 struct v4l2_ext_controls cs;
3152 struct v4l2_ext_control c1;
3153 memset(&cs, 0, sizeof(cs));
3154 memset(&c1, 0, sizeof(c1));
3155 cs.controls = &c1;
3156 cs.count = 1;
3157 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3158 c1.value = gop_size;
3159 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3160 VIDIOC_S_EXT_CTRLS);
3161 }
d855497e
MI		 3162 }
3163
38d9a2cf 3164 if (hdw->input_dirty && hdw->state_pathway_ok &&
62433e31
MI		 3165 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3166 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3167 hdw->pathway_state)) {
3168 /* Change of mode being asked for... */
3169 hdw->state_pathway_ok = 0;
e9db1ff2 3170 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 3171 }
3172 if (!hdw->state_pathway_ok) {
3173 /* Can't commit anything until pathway is ok. */
3174 return 0;
3175 }
e784bfb9 3176 /* The broadcast decoder can only scale down, so if
3177 * res_*_dirty && crop window < output format ==> enlarge crop.
3178 *
3179 * The mpeg encoder receives fields of res_hor_val dots and
3180 * res_ver_val halflines. Limits: hor<=720, ver<=576.
3181 */
3182 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3183 hdw->cropw_val = hdw->res_hor_val;
3184 hdw->cropw_dirty = !0;
3185 } else if (hdw->cropw_dirty) {
3186 hdw->res_hor_dirty = !0; /* must rescale */
3187 hdw->res_hor_val = min(720, hdw->cropw_val);
3188 }
3189 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3190 hdw->croph_val = hdw->res_ver_val;
3191 hdw->croph_dirty = !0;
3192 } else if (hdw->croph_dirty) {
3193 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3194 hdw->res_ver_dirty = !0;
3195 hdw->res_ver_val = min(nvres, hdw->croph_val);
3196 }
3197
681c7399
MI		 3198 /* If any of the below has changed, then we can't do the update
3199 while the pipeline is running. Pipeline must be paused first
3200 and decoder -> encoder connection be made quiescent before we
3201 can proceed. */
3202 disruptive_change =
3203 (hdw->std_dirty ||
3204 hdw->enc_unsafe_stale ||
3205 hdw->srate_dirty ||
3206 hdw->res_ver_dirty ||
3207 hdw->res_hor_dirty ||
755879c6
MI		 3208 hdw->cropw_dirty ||
3209 hdw->croph_dirty ||
681c7399
MI		 3210 hdw->input_dirty ||
3211 (hdw->active_stream_type != hdw->desired_stream_type));
3212 if (disruptive_change && !hdw->state_pipeline_idle) {
3213 /* Pipeline is not idle; we can't proceed. Arrange to
3214 cause pipeline to stop so that we can try this again
3215 later.... */
3216 hdw->state_pipeline_pause = !0;
3217 return 0;
275b2e28
PK		 3218 }
3219
b30d2441
MI		 3220 if (hdw->srate_dirty) {
3221 /* Write new sample rate into control structure since
3222 * the master copy is stale. We must track srate
3223 * separate from the mpeg control structure because
3224 * other logic also uses this value. */
3225 struct v4l2_ext_controls cs;
3226 struct v4l2_ext_control c1;
3227 memset(&cs,0,sizeof(cs));
3228 memset(&c1,0,sizeof(c1));
3229 cs.controls = &c1;
3230 cs.count = 1;
3231 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3232 c1.value = hdw->srate_val;
01f1e44f 3233 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 3234 }
c05c0462 3235
d855497e
MI		 3236 /* Scan i2c core at this point - before we clear all the dirty
3237 bits. Various parts of the i2c core will notice dirty bits as
3238 appropriate and arrange to broadcast or directly send updates to
3239 the client drivers in order to keep everything in sync */
3240 pvr2_i2c_core_check_stale(hdw);
3241
681c7399
MI		 3242 if (hdw->active_stream_type != hdw->desired_stream_type) {
3243 /* Handle any side effects of stream config here */
3244 hdw->active_stream_type = hdw->desired_stream_type;
3245 }
3246
1df59f0b
MI		 3247 if (hdw->hdw_desc->signal_routing_scheme ==
3248 PVR2_ROUTING_SCHEME_GOTVIEW) {
3249 u32 b;
3250 /* Handle GOTVIEW audio switching */
3251 pvr2_hdw_gpio_get_out(hdw,&b);
3252 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3253 /* Set GPIO 11 */
3254 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3255 } else {
3256 /* Clear GPIO 11 */
3257 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3258 }
3259 }
3260
e68a619a
MI		 3261 /* Check and update state for all sub-devices. */
3262 pvr2_subdev_update(hdw);
3263
75212a02 3264 hdw->tuner_updated = 0;
27764726 3265 hdw->force_dirty = 0;
5ceaad14
MI		 3266 for (idx = 0; idx < hdw->control_cnt; idx++) {
3267 cptr = hdw->controls + idx;
3268 if (!cptr->info->clear_dirty) continue;
3269 cptr->info->clear_dirty(cptr);
3270 }
3271
d855497e
MI		 3272 /* Now execute i2c core update */
3273 pvr2_i2c_core_sync(hdw);
3274
62433e31
MI		 3275 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3276 hdw->state_encoder_run) {
3277 /* If encoder isn't running or it can't be touched, then
3278 this will get worked out later when we start the
3279 encoder. */
681c7399
MI		 3280 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3281 }
d855497e 3282
681c7399 3283 hdw->state_pipeline_config = !0;
432907f7
MI		 3284 /* Hardware state may have changed in a way to cause the cropping
3285 capabilities to have changed. So mark it stale, which will
3286 cause a later re-fetch. */
681c7399
MI		 3287 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3288 return !0;
d855497e
MI		 3289}
3290
3291
3292int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3293{
681c7399
MI		 3294 int fl;
3295 LOCK_TAKE(hdw->big_lock);
3296 fl = pvr2_hdw_commit_setup(hdw);
3297 LOCK_GIVE(hdw->big_lock);
3298 if (!fl) return 0;
3299 return pvr2_hdw_wait(hdw,0);
3300}
3301
3302
3303static void pvr2_hdw_worker_i2c(struct work_struct *work)
3304{
3305 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
d855497e 3306 LOCK_TAKE(hdw->big_lock); do {
681c7399 3307 pvr2_i2c_core_sync(hdw);
d855497e 3308 } while (0); LOCK_GIVE(hdw->big_lock);
d855497e
MI		 3309}
3310
3311
681c7399 3312static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 3313{
681c7399
MI		 3314 int fl = 0;
3315 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 3316 LOCK_TAKE(hdw->big_lock); do {
681c7399 3317 fl = pvr2_hdw_state_eval(hdw);
d855497e 3318 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 3319 if (fl && hdw->state_func) {
3320 hdw->state_func(hdw->state_data);
3321 }
d855497e
MI		 3322}
3323
3324
681c7399 3325static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 3326{
681c7399
MI		 3327 return wait_event_interruptible(
3328 hdw->state_wait_data,
3329 (hdw->state_stale == 0) &&
3330 (!state || (hdw->master_state != state)));
3331}
3332
3333
d855497e
MI		 3334/* Return name for this driver instance */
3335const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3336{
3337 return hdw->name;
3338}
3339
3340
78a47101
MI		 3341const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3342{
3343 return hdw->hdw_desc->description;
3344}
3345
3346
3347const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3348{
3349 return hdw->hdw_desc->shortname;
3350}
3351
3352
d855497e
MI		 3353int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3354{
3355 int result;
3356 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3357 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 3358 result = pvr2_send_request(hdw,
3359 hdw->cmd_buffer,1,
3360 hdw->cmd_buffer,1);
3361 if (result < 0) break;
3362 result = (hdw->cmd_buffer[0] != 0);
3363 } while(0); LOCK_GIVE(hdw->ctl_lock);
3364 return result;
3365}
3366
3367
18103c57
MI		 3368/* Execute poll of tuner status */
3369void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 3370{
d855497e 3371 LOCK_TAKE(hdw->big_lock); do {
a51f5000 3372 pvr2_hdw_status_poll(hdw);
d855497e 3373 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 3374}
3375
3376
432907f7
MI		 3377static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3378{
3379 if (!hdw->cropcap_stale) {
432907f7
MI		 3380 return 0;
3381 }
a51f5000 3382 pvr2_hdw_status_poll(hdw);
432907f7 3383 if (hdw->cropcap_stale) {
432907f7
MI		 3384 return -EIO;
3385 }
3386 return 0;
3387}
3388
3389
3390/* Return information about cropping capabilities */
3391int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3392{
3393 int stat = 0;
3394 LOCK_TAKE(hdw->big_lock);
3395 stat = pvr2_hdw_check_cropcap(hdw);
3396 if (!stat) {
432907f7
MI		 3397 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3398 }
3399 LOCK_GIVE(hdw->big_lock);
3400 return stat;
3401}
3402
3403
18103c57
MI		 3404/* Return information about the tuner */
3405int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3406{
3407 LOCK_TAKE(hdw->big_lock); do {
3408 if (hdw->tuner_signal_stale) {
a51f5000 3409 pvr2_hdw_status_poll(hdw);
18103c57
MI		 3410 }
3411 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3412 } while (0); LOCK_GIVE(hdw->big_lock);
3413 return 0;
d855497e
MI		 3414}
3415
3416
3417/* Get handle to video output stream */
3418struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3419{
3420 return hp->vid_stream;
3421}
3422
3423
3424void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3425{
4f1a3e5b 3426 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e 3427 LOCK_TAKE(hdw->big_lock); do {
4f1a3e5b 3428 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
5ceaad14 3429 hdw->log_requested = !0;
d855497e 3430 pvr2_i2c_core_check_stale(hdw);
d855497e 3431 pvr2_i2c_core_sync(hdw);
a51f5000 3432 hdw->log_requested = 0;
ed3261a8 3433 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
b30d2441 3434 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 3435 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 3436 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 3437 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 3438 } while (0); LOCK_GIVE(hdw->big_lock);
3439}
3440
4db666cc
MI		 3441
3442/* Grab EEPROM contents, needed for direct method. */
3443#define EEPROM_SIZE 8192
3444#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3445static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3446{
3447 struct i2c_msg msg[2];
3448 u8 *eeprom;
3449 u8 iadd[2];
3450 u8 addr;
3451 u16 eepromSize;
3452 unsigned int offs;
3453 int ret;
3454 int mode16 = 0;
3455 unsigned pcnt,tcnt;
3456 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3457 if (!eeprom) {
3458 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3459 "Failed to allocate memory"
3460 " required to read eeprom");
3461 return NULL;
3462 }
3463
3464 trace_eeprom("Value for eeprom addr from controller was 0x%x",
3465 hdw->eeprom_addr);
3466 addr = hdw->eeprom_addr;
3467 /* Seems that if the high bit is set, then the *real* eeprom
3468 address is shifted right now bit position (noticed this in
3469 newer PVR USB2 hardware) */
3470 if (addr & 0x80) addr >>= 1;
3471
3472 /* FX2 documentation states that a 16bit-addressed eeprom is
3473 expected if the I2C address is an odd number (yeah, this is
3474 strange but it's what they do) */
3475 mode16 = (addr & 1);
3476 eepromSize = (mode16 ? EEPROM_SIZE : 256);
3477 trace_eeprom("Examining %d byte eeprom at location 0x%x"
3478 " using %d bit addressing",eepromSize,addr,
3479 mode16 ? 16 : 8);
3480
3481 msg[0].addr = addr;
3482 msg[0].flags = 0;
3483 msg[0].len = mode16 ? 2 : 1;
3484 msg[0].buf = iadd;
3485 msg[1].addr = addr;
3486 msg[1].flags = I2C_M_RD;
3487
3488 /* We have to do the actual eeprom data fetch ourselves, because
3489 (1) we're only fetching part of the eeprom, and (2) if we were
3490 getting the whole thing our I2C driver can't grab it in one
3491 pass - which is what tveeprom is otherwise going to attempt */
3492 memset(eeprom,0,EEPROM_SIZE);
3493 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3494 pcnt = 16;
3495 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3496 offs = tcnt + (eepromSize - EEPROM_SIZE);
3497 if (mode16) {
3498 iadd[0] = offs >> 8;
3499 iadd[1] = offs;
3500 } else {
3501 iadd[0] = offs;
3502 }
3503 msg[1].len = pcnt;
3504 msg[1].buf = eeprom+tcnt;
3505 if ((ret = i2c_transfer(&hdw->i2c_adap,
3506 msg,ARRAY_SIZE(msg))) != 2) {
3507 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3508 "eeprom fetch set offs err=%d",ret);
3509 kfree(eeprom);
3510 return NULL;
3511 }
3512 }
3513 return eeprom;
3514}
3515
3516
3517void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3518 int prom_flag,
3519 int enable_flag)
d855497e
MI		 3520{
3521 int ret;
3522 u16 address;
3523 unsigned int pipe;
3524 LOCK_TAKE(hdw->big_lock); do {
5fa1247a 3525 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
d855497e
MI		 3526
3527 if (!enable_flag) {
3528 pvr2_trace(PVR2_TRACE_FIRMWARE,
3529 "Cleaning up after CPU firmware fetch");
3530 kfree(hdw->fw_buffer);
a0fd1cb1 3531 hdw->fw_buffer = NULL;
d855497e 3532 hdw->fw_size = 0;
4db666cc
MI		 3533 if (hdw->fw_cpu_flag) {
3534 /* Now release the CPU. It will disconnect
3535 and reconnect later. */
3536 pvr2_hdw_cpureset_assert(hdw,0);
3537 }
d855497e
MI		 3538 break;
3539 }
3540
4db666cc
MI		 3541 hdw->fw_cpu_flag = (prom_flag == 0);
3542 if (hdw->fw_cpu_flag) {
3543 pvr2_trace(PVR2_TRACE_FIRMWARE,
3544 "Preparing to suck out CPU firmware");
3545 hdw->fw_size = 0x2000;
3546 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3547 if (!hdw->fw_buffer) {
3548 hdw->fw_size = 0;
3549 break;
3550 }
d855497e 3551
4db666cc
MI		 3552 /* We have to hold the CPU during firmware upload. */
3553 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 3554
4db666cc
MI		 3555 /* download the firmware from address 0000-1fff in 2048
3556 (=0x800) bytes chunk. */
d855497e 3557
4db666cc
MI		 3558 pvr2_trace(PVR2_TRACE_FIRMWARE,
3559 "Grabbing CPU firmware");
3560 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3561 for(address = 0; address < hdw->fw_size;
3562 address += 0x800) {
3563 ret = usb_control_msg(hdw->usb_dev,pipe,
3564 0xa0,0xc0,
3565 address,0,
3566 hdw->fw_buffer+address,
3567 0x800,HZ);
3568 if (ret < 0) break;
3569 }
d855497e 3570
4db666cc
MI		 3571 pvr2_trace(PVR2_TRACE_FIRMWARE,
3572 "Done grabbing CPU firmware");
3573 } else {
3574 pvr2_trace(PVR2_TRACE_FIRMWARE,
3575 "Sucking down EEPROM contents");
3576 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3577 if (!hdw->fw_buffer) {
3578 pvr2_trace(PVR2_TRACE_FIRMWARE,
3579 "EEPROM content suck failed.");
3580 break;
3581 }
3582 hdw->fw_size = EEPROM_SIZE;
3583 pvr2_trace(PVR2_TRACE_FIRMWARE,
3584 "Done sucking down EEPROM contents");
3585 }
d855497e
MI		 3586
3587 } while (0); LOCK_GIVE(hdw->big_lock);
3588}
3589
3590
3591/* Return true if we're in a mode for retrieval CPU firmware */
3592int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3593{
5fa1247a 3594 return hdw->fw_buffer != NULL;
d855497e
MI		 3595}
3596
3597
3598int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3599 char *buf,unsigned int cnt)
3600{
3601 int ret = -EINVAL;
3602 LOCK_TAKE(hdw->big_lock); do {
3603 if (!buf) break;
3604 if (!cnt) break;
3605
3606 if (!hdw->fw_buffer) {
3607 ret = -EIO;
3608 break;
3609 }
3610
3611 if (offs >= hdw->fw_size) {
3612 pvr2_trace(PVR2_TRACE_FIRMWARE,
3613 "Read firmware data offs=%d EOF",
3614 offs);
3615 ret = 0;
3616 break;
3617 }
3618
3619 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3620
3621 memcpy(buf,hdw->fw_buffer+offs,cnt);
3622
3623 pvr2_trace(PVR2_TRACE_FIRMWARE,
3624 "Read firmware data offs=%d cnt=%d",
3625 offs,cnt);
3626 ret = cnt;
3627 } while (0); LOCK_GIVE(hdw->big_lock);
3628
3629 return ret;
3630}
3631
3632
fd5a75fe 3633int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 3634 enum pvr2_v4l_type index)
d855497e 3635{
fd5a75fe 3636 switch (index) {
8079384e
MI		 3637 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3638 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3639 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 3640 default: return -1;
3641 }
d855497e
MI		 3642}
3643
3644
2fdf3d9c 3645/* Store a v4l minor device number */
fd5a75fe 3646void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 3647 enum pvr2_v4l_type index,int v)
d855497e 3648{
fd5a75fe 3649 switch (index) {
8079384e
MI		 3650 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3651 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3652 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 3653 default: break;
3654 }
d855497e
MI		 3655}
3656
3657
7d12e780 3658static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 3659{
3660 struct pvr2_hdw *hdw = urb->context;
3661 hdw->ctl_write_pend_flag = 0;
3662 if (hdw->ctl_read_pend_flag) return;
3663 complete(&hdw->ctl_done);
3664}
3665
3666
7d12e780 3667static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 3668{
3669 struct pvr2_hdw *hdw = urb->context;
3670 hdw->ctl_read_pend_flag = 0;
3671 if (hdw->ctl_write_pend_flag) return;
3672 complete(&hdw->ctl_done);
3673}
3674
3675
3676static void pvr2_ctl_timeout(unsigned long data)
3677{
3678 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3679 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3680 hdw->ctl_timeout_flag = !0;
5e55d2ce 3681 if (hdw->ctl_write_pend_flag)
d855497e 3682 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 3683 if (hdw->ctl_read_pend_flag)
d855497e 3684 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 3685 }
3686}
3687
3688
e61b6fc5
MI		 3689/* Issue a command and get a response from the device. This extended
3690 version includes a probe flag (which if set means that device errors
3691 should not be logged or treated as fatal) and a timeout in jiffies.
3692 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 3693static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3694 unsigned int timeout,int probe_fl,
3695 void *write_data,unsigned int write_len,
3696 void *read_data,unsigned int read_len)
d855497e
MI		 3697{
3698 unsigned int idx;
3699 int status = 0;
3700 struct timer_list timer;
3701 if (!hdw->ctl_lock_held) {
3702 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3703 "Attempted to execute control transfer"
3704 " without lock!!");
3705 return -EDEADLK;
3706 }
681c7399 3707 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 3708 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3709 "Attempted to execute control transfer"
3710 " when device not ok");
3711 return -EIO;
3712 }
3713 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3714 if (!probe_fl) {
3715 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3716 "Attempted to execute control transfer"
3717 " when USB is disconnected");
3718 }
3719 return -ENOTTY;
3720 }
3721
3722 /* Ensure that we have sane parameters */
3723 if (!write_data) write_len = 0;
3724 if (!read_data) read_len = 0;
3725 if (write_len > PVR2_CTL_BUFFSIZE) {
3726 pvr2_trace(
3727 PVR2_TRACE_ERROR_LEGS,
3728 "Attempted to execute %d byte"
3729 " control-write transfer (limit=%d)",
3730 write_len,PVR2_CTL_BUFFSIZE);
3731 return -EINVAL;
3732 }
3733 if (read_len > PVR2_CTL_BUFFSIZE) {
3734 pvr2_trace(
3735 PVR2_TRACE_ERROR_LEGS,
3736 "Attempted to execute %d byte"
3737 " control-read transfer (limit=%d)",
3738 write_len,PVR2_CTL_BUFFSIZE);
3739 return -EINVAL;
3740 }
3741 if ((!write_len) && (!read_len)) {
3742 pvr2_trace(
3743 PVR2_TRACE_ERROR_LEGS,
3744 "Attempted to execute null control transfer?");
3745 return -EINVAL;
3746 }
3747
3748
3749 hdw->cmd_debug_state = 1;
3750 if (write_len) {
3751 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3752 } else {
3753 hdw->cmd_debug_code = 0;
3754 }
3755 hdw->cmd_debug_write_len = write_len;
3756 hdw->cmd_debug_read_len = read_len;
3757
3758 /* Initialize common stuff */
3759 init_completion(&hdw->ctl_done);
3760 hdw->ctl_timeout_flag = 0;
3761 hdw->ctl_write_pend_flag = 0;
3762 hdw->ctl_read_pend_flag = 0;
3763 init_timer(&timer);
3764 timer.expires = jiffies + timeout;
3765 timer.data = (unsigned long)hdw;
3766 timer.function = pvr2_ctl_timeout;
3767
3768 if (write_len) {
3769 hdw->cmd_debug_state = 2;
3770 /* Transfer write data to internal buffer */
3771 for (idx = 0; idx < write_len; idx++) {
3772 hdw->ctl_write_buffer[idx] =
3773 ((unsigned char *)write_data)[idx];
3774 }
3775 /* Initiate a write request */
3776 usb_fill_bulk_urb(hdw->ctl_write_urb,
3777 hdw->usb_dev,
3778 usb_sndbulkpipe(hdw->usb_dev,
3779 PVR2_CTL_WRITE_ENDPOINT),
3780 hdw->ctl_write_buffer,
3781 write_len,
3782 pvr2_ctl_write_complete,
3783 hdw);
3784 hdw->ctl_write_urb->actual_length = 0;
3785 hdw->ctl_write_pend_flag = !0;
3786 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3787 if (status < 0) {
3788 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3789 "Failed to submit write-control"
3790 " URB status=%d",status);
3791 hdw->ctl_write_pend_flag = 0;
3792 goto done;
3793 }
3794 }
3795
3796 if (read_len) {
3797 hdw->cmd_debug_state = 3;
3798 memset(hdw->ctl_read_buffer,0x43,read_len);
3799 /* Initiate a read request */
3800 usb_fill_bulk_urb(hdw->ctl_read_urb,
3801 hdw->usb_dev,
3802 usb_rcvbulkpipe(hdw->usb_dev,
3803 PVR2_CTL_READ_ENDPOINT),
3804 hdw->ctl_read_buffer,
3805 read_len,
3806 pvr2_ctl_read_complete,
3807 hdw);
3808 hdw->ctl_read_urb->actual_length = 0;
3809 hdw->ctl_read_pend_flag = !0;
3810 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3811 if (status < 0) {
3812 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3813 "Failed to submit read-control"
3814 " URB status=%d",status);
3815 hdw->ctl_read_pend_flag = 0;
3816 goto done;
3817 }
3818 }
3819
3820 /* Start timer */
3821 add_timer(&timer);
3822
3823 /* Now wait for all I/O to complete */
3824 hdw->cmd_debug_state = 4;
3825 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3826 wait_for_completion(&hdw->ctl_done);
3827 }
3828 hdw->cmd_debug_state = 5;
3829
3830 /* Stop timer */
3831 del_timer_sync(&timer);
3832
3833 hdw->cmd_debug_state = 6;
3834 status = 0;
3835
3836 if (hdw->ctl_timeout_flag) {
3837 status = -ETIMEDOUT;
3838 if (!probe_fl) {
3839 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3840 "Timed out control-write");
3841 }
3842 goto done;
3843 }
3844
3845 if (write_len) {
3846 /* Validate results of write request */
3847 if ((hdw->ctl_write_urb->status != 0) &&
3848 (hdw->ctl_write_urb->status != -ENOENT) &&
3849 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3850 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3851 /* USB subsystem is reporting some kind of failure
3852 on the write */
3853 status = hdw->ctl_write_urb->status;
3854 if (!probe_fl) {
3855 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3856 "control-write URB failure,"
3857 " status=%d",
3858 status);
3859 }
3860 goto done;
3861 }
3862 if (hdw->ctl_write_urb->actual_length < write_len) {
3863 /* Failed to write enough data */
3864 status = -EIO;
3865 if (!probe_fl) {
3866 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3867 "control-write URB short,"
3868 " expected=%d got=%d",
3869 write_len,
3870 hdw->ctl_write_urb->actual_length);
3871 }
3872 goto done;
3873 }
3874 }
3875 if (read_len) {
3876 /* Validate results of read request */
3877 if ((hdw->ctl_read_urb->status != 0) &&
3878 (hdw->ctl_read_urb->status != -ENOENT) &&
3879 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3880 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3881 /* USB subsystem is reporting some kind of failure
3882 on the read */
3883 status = hdw->ctl_read_urb->status;
3884 if (!probe_fl) {
3885 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3886 "control-read URB failure,"
3887 " status=%d",
3888 status);
3889 }
3890 goto done;
3891 }
3892 if (hdw->ctl_read_urb->actual_length < read_len) {
3893 /* Failed to read enough data */
3894 status = -EIO;
3895 if (!probe_fl) {
3896 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3897 "control-read URB short,"
3898 " expected=%d got=%d",
3899 read_len,
3900 hdw->ctl_read_urb->actual_length);
3901 }
3902 goto done;
3903 }
3904 /* Transfer retrieved data out from internal buffer */
3905 for (idx = 0; idx < read_len; idx++) {
3906 ((unsigned char *)read_data)[idx] =
3907 hdw->ctl_read_buffer[idx];
3908 }
3909 }
3910
3911 done:
3912
3913 hdw->cmd_debug_state = 0;
3914 if ((status < 0) && (!probe_fl)) {
681c7399 3915 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3916 }
3917 return status;
3918}
3919
3920
3921int pvr2_send_request(struct pvr2_hdw *hdw,
3922 void *write_data,unsigned int write_len,
3923 void *read_data,unsigned int read_len)
3924{
3925 return pvr2_send_request_ex(hdw,HZ*4,0,
3926 write_data,write_len,
3927 read_data,read_len);
3928}
3929
1c9d10d4
MI		 3930
3931static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3932{
3933 int ret;
3934 unsigned int cnt = 1;
3935 unsigned int args = 0;
3936 LOCK_TAKE(hdw->ctl_lock);
3937 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3938 args = (cmdcode >> 8) & 0xffu;
3939 args = (args > 2) ? 2 : args;
3940 if (args) {
3941 cnt += args;
3942 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3943 if (args > 1) {
3944 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3945 }
3946 }
3947 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3948 unsigned int idx;
3949 unsigned int ccnt,bcnt;
3950 char tbuf[50];
3951 cmdcode &= 0xffu;
3952 bcnt = 0;
3953 ccnt = scnprintf(tbuf+bcnt,
3954 sizeof(tbuf)-bcnt,
3955 "Sending FX2 command 0x%x",cmdcode);
3956 bcnt += ccnt;
3957 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3958 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3959 ccnt = scnprintf(tbuf+bcnt,
3960 sizeof(tbuf)-bcnt,
3961 " \"%s\"",
3962 pvr2_fx2cmd_desc[idx].desc);
3963 bcnt += ccnt;
3964 break;
3965 }
3966 }
3967 if (args) {
3968 ccnt = scnprintf(tbuf+bcnt,
3969 sizeof(tbuf)-bcnt,
3970 " (%u",hdw->cmd_buffer[1]);
3971 bcnt += ccnt;
3972 if (args > 1) {
3973 ccnt = scnprintf(tbuf+bcnt,
3974 sizeof(tbuf)-bcnt,
3975 ",%u",hdw->cmd_buffer[2]);
3976 bcnt += ccnt;
3977 }
3978 ccnt = scnprintf(tbuf+bcnt,
3979 sizeof(tbuf)-bcnt,
3980 ")");
3981 bcnt += ccnt;
3982 }
3983 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3984 }
3985 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3986 LOCK_GIVE(hdw->ctl_lock);
3987 return ret;
3988}
3989
3990
d855497e
MI		 3991int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3992{
3993 int ret;
3994
3995 LOCK_TAKE(hdw->ctl_lock);
3996
8d364363 3997 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 3998 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3999 hdw->cmd_buffer[5] = 0;
4000 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4001 hdw->cmd_buffer[7] = reg & 0xff;
4002
4003
4004 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
4005
4006 LOCK_GIVE(hdw->ctl_lock);
4007
4008 return ret;
4009}
4010
4011
07e337ee 4012static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 4013{
4014 int ret = 0;
4015
4016 LOCK_TAKE(hdw->ctl_lock);
4017
8d364363 4018 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 4019 hdw->cmd_buffer[1] = 0;
4020 hdw->cmd_buffer[2] = 0;
4021 hdw->cmd_buffer[3] = 0;
4022 hdw->cmd_buffer[4] = 0;
4023 hdw->cmd_buffer[5] = 0;
4024 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4025 hdw->cmd_buffer[7] = reg & 0xff;
4026
4027 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
4028 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
4029
4030 LOCK_GIVE(hdw->ctl_lock);
4031
4032 return ret;
4033}
4034
4035
681c7399 4036void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 4037{
4038 if (!hdw->flag_ok) return;
681c7399
MI		 4039 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4040 "Device being rendered inoperable");
d855497e 4041 if (hdw->vid_stream) {
a0fd1cb1 4042 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 4043 }
681c7399
MI		 4044 hdw->flag_ok = 0;
4045 trace_stbit("flag_ok",hdw->flag_ok);
4046 pvr2_hdw_state_sched(hdw);
d855497e
MI		 4047}
4048
4049
4050void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4051{
4052 int ret;
4053 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 4054 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
011b15df 4055 if (ret == 0) {
d855497e
MI		 4056 ret = usb_reset_device(hdw->usb_dev);
4057 usb_unlock_device(hdw->usb_dev);
4058 } else {
4059 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4060 "Failed to lock USB device ret=%d",ret);
4061 }
4062 if (init_pause_msec) {
4063 pvr2_trace(PVR2_TRACE_INFO,
4064 "Waiting %u msec for hardware to settle",
4065 init_pause_msec);
4066 msleep(init_pause_msec);
4067 }
4068
4069}
4070
4071
4072void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4073{
4074 char da[1];
4075 unsigned int pipe;
4076 int ret;
4077
4078 if (!hdw->usb_dev) return;
4079
4080 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4081
4082 da[0] = val ? 0x01 : 0x00;
4083
4084 /* Write the CPUCS register on the 8051. The lsb of the register
4085 is the reset bit; a 1 asserts reset while a 0 clears it. */
4086 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4087 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4088 if (ret < 0) {
4089 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4090 "cpureset_assert(%d) error=%d",val,ret);
4091 pvr2_hdw_render_useless(hdw);
4092 }
4093}
4094
4095
4096int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4097{
1c9d10d4 4098 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
d855497e
MI		 4099}
4100
4101
e1edb19a
MK		 4102int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4103{
1c9d10d4 4104 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
e1edb19a
MK		 4105}
4106
1c9d10d4 4107
e1edb19a
MK		 4108int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4109{
1c9d10d4 4110 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
e1edb19a
MK		 4111}
4112
d855497e
MI		 4113
4114int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4115{
af78e16b
MI		 4116 pvr2_trace(PVR2_TRACE_INIT,
4117 "Requesting decoder reset");
4118 if (hdw->decoder_ctrl) {
4119 if (!hdw->decoder_ctrl->force_reset) {
4120 pvr2_trace(PVR2_TRACE_INIT,
4121 "Unable to reset decoder: not implemented");
4122 return -ENOTTY;
4123 }
4124 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
4125 return 0;
4126 } else {
d855497e 4127 }
af78e16b
MI		 4128 if (hdw->decoder_client_id) {
4129 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4130 core, reset, 0);
4131 return 0;
d855497e 4132 }
d855497e 4133 pvr2_trace(PVR2_TRACE_INIT,
af78e16b
MI		 4134 "Unable to reset decoder: nothing attached");
4135 return -ENOTTY;
d855497e
MI		 4136}
4137
4138
62433e31 4139static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
84147f3d 4140{
1c9d10d4
MI		 4141 hdw->flag_ok = !0;
4142 return pvr2_issue_simple_cmd(hdw,
4143 FX2CMD_HCW_DEMOD_RESETIN |
4144 (1 << 8) |
4145 ((onoff ? 1 : 0) << 16));
84147f3d
MI		 4146}
4147
84147f3d 4148
62433e31 4149static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
84147f3d 4150{
1c9d10d4
MI		 4151 hdw->flag_ok = !0;
4152 return pvr2_issue_simple_cmd(hdw,(onoff ?
4153 FX2CMD_ONAIR_DTV_POWER_ON :
4154 FX2CMD_ONAIR_DTV_POWER_OFF));
84147f3d
MI		 4155}
4156
62433e31
MI		 4157
4158static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4159 int onoff)
84147f3d 4160{
1c9d10d4
MI		 4161 return pvr2_issue_simple_cmd(hdw,(onoff ?
4162 FX2CMD_ONAIR_DTV_STREAMING_ON :
4163 FX2CMD_ONAIR_DTV_STREAMING_OFF));
84147f3d
MI		 4164}
4165
62433e31
MI		 4166
4167static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4168{
4169 int cmode;
4170 /* Compare digital/analog desired setting with current setting. If
4171 they don't match, fix it... */
4172 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4173 if (cmode == hdw->pathway_state) {
4174 /* They match; nothing to do */
4175 return;
4176 }
4177
4178 switch (hdw->hdw_desc->digital_control_scheme) {
4179 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4180 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4181 if (cmode == PVR2_PATHWAY_ANALOG) {
4182 /* If moving to analog mode, also force the decoder
4183 to reset. If no decoder is attached, then it's
4184 ok to ignore this because if/when the decoder
4185 attaches, it will reset itself at that time. */
4186 pvr2_hdw_cmd_decoder_reset(hdw);
4187 }
4188 break;
4189 case PVR2_DIGITAL_SCHEME_ONAIR:
4190 /* Supposedly we should always have the power on whether in
4191 digital or analog mode. But for now do what appears to
4192 work... */
bb0c2fe0 4193 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
62433e31
MI		 4194 break;
4195 default: break;
4196 }
4197
1b9c18c5 4198 pvr2_hdw_untrip_unlocked(hdw);
62433e31
MI		 4199 hdw->pathway_state = cmode;
4200}
4201
4202
e9b59f6e 4203static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
c55a97d7
MI		 4204{
4205 /* change some GPIO data
4206 *
4207 * note: bit d7 of dir appears to control the LED,
4208 * so we shut it off here.
4209 *
c55a97d7 4210 */
40381cb0 4211 if (onoff) {
c55a97d7 4212 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
40381cb0 4213 } else {
c55a97d7 4214 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
40381cb0 4215 }
c55a97d7 4216 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
40381cb0 4217}
c55a97d7 4218
40381cb0
MI		 4219
4220typedef void (*led_method_func)(struct pvr2_hdw *,int);
4221
4222static led_method_func led_methods[] = {
4223 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4224};
4225
4226
4227/* Toggle LED */
4228static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4229{
4230 unsigned int scheme_id;
4231 led_method_func fp;
4232
4233 if ((!onoff) == (!hdw->led_on)) return;
4234
4235 hdw->led_on = onoff != 0;
4236
4237 scheme_id = hdw->hdw_desc->led_scheme;
4238 if (scheme_id < ARRAY_SIZE(led_methods)) {
4239 fp = led_methods[scheme_id];
4240 } else {
4241 fp = NULL;
4242 }
4243
4244 if (fp) (*fp)(hdw,onoff);
c55a97d7
MI		 4245}
4246
4247
e61b6fc5 4248/* Stop / start video stream transport */
07e337ee 4249static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e 4250{
bb0c2fe0
MI		 4251 int ret;
4252
4253 /* If we're in analog mode, then just issue the usual analog
4254 command. */
4255 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4256 return pvr2_issue_simple_cmd(hdw,
4257 (runFl ?
4258 FX2CMD_STREAMING_ON :
4259 FX2CMD_STREAMING_OFF));
4260 /*Note: Not reached */
4261 }
4262
4263 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4264 /* Whoops, we don't know what mode we're in... */
4265 return -EINVAL;
4266 }
4267
4268 /* To get here we have to be in digital mode. The mechanism here
4269 is unfortunately different for different vendors. So we switch
4270 on the device's digital scheme attribute in order to figure out
4271 what to do. */
4272 switch (hdw->hdw_desc->digital_control_scheme) {
4273 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4274 return pvr2_issue_simple_cmd(hdw,
4275 (runFl ?
4276 FX2CMD_HCW_DTV_STREAMING_ON :
4277 FX2CMD_HCW_DTV_STREAMING_OFF));
4278 case PVR2_DIGITAL_SCHEME_ONAIR:
4279 ret = pvr2_issue_simple_cmd(hdw,
4280 (runFl ?
4281 FX2CMD_STREAMING_ON :
4282 FX2CMD_STREAMING_OFF));
4283 if (ret) return ret;
4284 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4285 default:
4286 return -EINVAL;
62433e31 4287 }
d855497e
MI		 4288}
4289
4290
62433e31
MI		 4291/* Evaluate whether or not state_pathway_ok can change */
4292static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4293{
4294 if (hdw->state_pathway_ok) {
4295 /* Nothing to do if pathway is already ok */
4296 return 0;
4297 }
4298 if (!hdw->state_pipeline_idle) {
4299 /* Not allowed to change anything if pipeline is not idle */
4300 return 0;
4301 }
4302 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4303 hdw->state_pathway_ok = !0;
e9db1ff2 4304 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 4305 return !0;
4306}
4307
4308
681c7399
MI		 4309/* Evaluate whether or not state_encoder_ok can change */
4310static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4311{
4312 if (hdw->state_encoder_ok) return 0;
4313 if (hdw->flag_tripped) return 0;
4314 if (hdw->state_encoder_run) return 0;
4315 if (hdw->state_encoder_config) return 0;
4316 if (hdw->state_decoder_run) return 0;
4317 if (hdw->state_usbstream_run) return 0;
72998b71
MI		 4318 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4319 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4320 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4321 return 0;
4322 }
4323
681c7399
MI		 4324 if (pvr2_upload_firmware2(hdw) < 0) {
4325 hdw->flag_tripped = !0;
4326 trace_stbit("flag_tripped",hdw->flag_tripped);
4327 return !0;
4328 }
4329 hdw->state_encoder_ok = !0;
4330 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4331 return !0;
4332}
4333
4334
4335/* Evaluate whether or not state_encoder_config can change */
4336static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4337{
4338 if (hdw->state_encoder_config) {
4339 if (hdw->state_encoder_ok) {
4340 if (hdw->state_pipeline_req &&
4341 !hdw->state_pipeline_pause) return 0;
4342 }
4343 hdw->state_encoder_config = 0;
4344 hdw->state_encoder_waitok = 0;
4345 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4346 /* paranoia - solve race if timer just completed */
4347 del_timer_sync(&hdw->encoder_wait_timer);
4348 } else {
62433e31
MI		 4349 if (!hdw->state_pathway_ok ||
4350 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4351 !hdw->state_encoder_ok ||
681c7399
MI		 4352 !hdw->state_pipeline_idle ||
4353 hdw->state_pipeline_pause ||
4354 !hdw->state_pipeline_req ||
4355 !hdw->state_pipeline_config) {
4356 /* We must reset the enforced wait interval if
4357 anything has happened that might have disturbed
4358 the encoder. This should be a rare case. */
4359 if (timer_pending(&hdw->encoder_wait_timer)) {
4360 del_timer_sync(&hdw->encoder_wait_timer);
4361 }
4362 if (hdw->state_encoder_waitok) {
4363 /* Must clear the state - therefore we did
4364 something to a state bit and must also
4365 return true. */
4366 hdw->state_encoder_waitok = 0;
4367 trace_stbit("state_encoder_waitok",
4368 hdw->state_encoder_waitok);
4369 return !0;
4370 }
4371 return 0;
4372 }
4373 if (!hdw->state_encoder_waitok) {
4374 if (!timer_pending(&hdw->encoder_wait_timer)) {
4375 /* waitok flag wasn't set and timer isn't
4376 running. Check flag once more to avoid
4377 a race then start the timer. This is
4378 the point when we measure out a minimal
4379 quiet interval before doing something to
4380 the encoder. */
4381 if (!hdw->state_encoder_waitok) {
4382 hdw->encoder_wait_timer.expires =
83ce57aa
MI		 4383 jiffies +
4384 (HZ * TIME_MSEC_ENCODER_WAIT
4385 / 1000);
681c7399
MI		 4386 add_timer(&hdw->encoder_wait_timer);
4387 }
4388 }
4389 /* We can't continue until we know we have been
4390 quiet for the interval measured by this
4391 timer. */
4392 return 0;
4393 }
4394 pvr2_encoder_configure(hdw);
4395 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4396 }
4397 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4398 return !0;
4399}
4400
4401
d913d630
MI		 4402/* Return true if the encoder should not be running. */
4403static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4404{
4405 if (!hdw->state_encoder_ok) {
4406 /* Encoder isn't healthy at the moment, so stop it. */
4407 return !0;
4408 }
4409 if (!hdw->state_pathway_ok) {
4410 /* Mode is not understood at the moment (i.e. it wants to
4411 change), so encoder must be stopped. */
4412 return !0;
4413 }
4414
4415 switch (hdw->pathway_state) {
4416 case PVR2_PATHWAY_ANALOG:
4417 if (!hdw->state_decoder_run) {
4418 /* We're in analog mode and the decoder is not
4419 running; thus the encoder should be stopped as
4420 well. */
4421 return !0;
4422 }
4423 break;
4424 case PVR2_PATHWAY_DIGITAL:
4425 if (hdw->state_encoder_runok) {
4426 /* This is a funny case. We're in digital mode so
4427 really the encoder should be stopped. However
4428 if it really is running, only kill it after
4429 runok has been set. This gives a chance for the
4430 onair quirk to function (encoder must run
4431 briefly first, at least once, before onair
4432 digital streaming can work). */
4433 return !0;
4434 }
4435 break;
4436 default:
4437 /* Unknown mode; so encoder should be stopped. */
4438 return !0;
4439 }
4440
4441 /* If we get here, we haven't found a reason to stop the
4442 encoder. */
4443 return 0;
4444}
4445
4446
4447/* Return true if the encoder should be running. */
4448static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4449{
4450 if (!hdw->state_encoder_ok) {
4451 /* Don't run the encoder if it isn't healthy... */
4452 return 0;
4453 }
4454 if (!hdw->state_pathway_ok) {
4455 /* Don't run the encoder if we don't (yet) know what mode
4456 we need to be in... */
4457 return 0;
4458 }
4459
4460 switch (hdw->pathway_state) {
4461 case PVR2_PATHWAY_ANALOG:
4462 if (hdw->state_decoder_run) {
4463 /* In analog mode, if the decoder is running, then
4464 run the encoder. */
4465 return !0;
4466 }
4467 break;
4468 case PVR2_PATHWAY_DIGITAL:
4469 if ((hdw->hdw_desc->digital_control_scheme ==
4470 PVR2_DIGITAL_SCHEME_ONAIR) &&
4471 !hdw->state_encoder_runok) {
4472 /* This is a quirk. OnAir hardware won't stream
4473 digital until the encoder has been run at least
4474 once, for a minimal period of time (empiricially
4475 measured to be 1/4 second). So if we're on
4476 OnAir hardware and the encoder has never been
4477 run at all, then start the encoder. Normal
4478 state machine logic in the driver will
4479 automatically handle the remaining bits. */
4480 return !0;
4481 }
4482 break;
4483 default:
4484 /* For completeness (unknown mode; encoder won't run ever) */
4485 break;
4486 }
4487 /* If we get here, then we haven't found any reason to run the
4488 encoder, so don't run it. */
4489 return 0;
4490}
4491
4492
681c7399
MI		 4493/* Evaluate whether or not state_encoder_run can change */
4494static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4495{
4496 if (hdw->state_encoder_run) {
d913d630 4497 if (!state_check_disable_encoder_run(hdw)) return 0;
681c7399 4498 if (hdw->state_encoder_ok) {
d913d630 4499 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 4500 if (pvr2_encoder_stop(hdw) < 0) return !0;
4501 }
4502 hdw->state_encoder_run = 0;
4503 } else {
d913d630 4504 if (!state_check_enable_encoder_run(hdw)) return 0;
681c7399
MI		 4505 if (pvr2_encoder_start(hdw) < 0) return !0;
4506 hdw->state_encoder_run = !0;
d913d630
MI		 4507 if (!hdw->state_encoder_runok) {
4508 hdw->encoder_run_timer.expires =
83ce57aa 4509 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
d913d630
MI		 4510 add_timer(&hdw->encoder_run_timer);
4511 }
681c7399
MI		 4512 }
4513 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4514 return !0;
4515}
4516
4517
4518/* Timeout function for quiescent timer. */
4519static void pvr2_hdw_quiescent_timeout(unsigned long data)
4520{
4521 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4522 hdw->state_decoder_quiescent = !0;
4523 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4524 hdw->state_stale = !0;
4525 queue_work(hdw->workqueue,&hdw->workpoll);
4526}
4527
4528
4529/* Timeout function for encoder wait timer. */
4530static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4531{
4532 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4533 hdw->state_encoder_waitok = !0;
4534 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4535 hdw->state_stale = !0;
4536 queue_work(hdw->workqueue,&hdw->workpoll);
4537}
4538
4539
d913d630
MI		 4540/* Timeout function for encoder run timer. */
4541static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4542{
4543 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4544 if (!hdw->state_encoder_runok) {
4545 hdw->state_encoder_runok = !0;
4546 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4547 hdw->state_stale = !0;
4548 queue_work(hdw->workqueue,&hdw->workpoll);
4549 }
4550}
4551
4552
681c7399
MI		 4553/* Evaluate whether or not state_decoder_run can change */
4554static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4555{
4556 if (hdw->state_decoder_run) {
4557 if (hdw->state_encoder_ok) {
4558 if (hdw->state_pipeline_req &&
62433e31
MI		 4559 !hdw->state_pipeline_pause &&
4560 hdw->state_pathway_ok) return 0;
681c7399
MI		 4561 }
4562 if (!hdw->flag_decoder_missed) {
4563 pvr2_decoder_enable(hdw,0);
4564 }
4565 hdw->state_decoder_quiescent = 0;
4566 hdw->state_decoder_run = 0;
4567 /* paranoia - solve race if timer just completed */
4568 del_timer_sync(&hdw->quiescent_timer);
4569 } else {
4570 if (!hdw->state_decoder_quiescent) {
4571 if (!timer_pending(&hdw->quiescent_timer)) {
4572 /* We don't do something about the
4573 quiescent timer until right here because
4574 we also want to catch cases where the
4575 decoder was already not running (like
4576 after initialization) as opposed to
4577 knowing that we had just stopped it.
4578 The second flag check is here to cover a
4579 race - the timer could have run and set
4580 this flag just after the previous check
4581 but before we did the pending check. */
4582 if (!hdw->state_decoder_quiescent) {
4583 hdw->quiescent_timer.expires =
83ce57aa
MI		 4584 jiffies +
4585 (HZ * TIME_MSEC_DECODER_WAIT
4586 / 1000);
681c7399
MI		 4587 add_timer(&hdw->quiescent_timer);
4588 }
4589 }
4590 /* Don't allow decoder to start again until it has
4591 been quiesced first. This little detail should
4592 hopefully further stabilize the encoder. */
4593 return 0;
4594 }
62433e31
MI		 4595 if (!hdw->state_pathway_ok ||
4596 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4597 !hdw->state_pipeline_req ||
681c7399
MI		 4598 hdw->state_pipeline_pause ||
4599 !hdw->state_pipeline_config ||
4600 !hdw->state_encoder_config ||
4601 !hdw->state_encoder_ok) return 0;
4602 del_timer_sync(&hdw->quiescent_timer);
4603 if (hdw->flag_decoder_missed) return 0;
4604 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4605 hdw->state_decoder_quiescent = 0;
4606 hdw->state_decoder_run = !0;
4607 }
4608 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4609 trace_stbit("state_decoder_run",hdw->state_decoder_run);
4610 return !0;
4611}
4612
4613
4614/* Evaluate whether or not state_usbstream_run can change */
4615static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4616{
4617 if (hdw->state_usbstream_run) {
72998b71 4618 int fl = !0;
62433e31 4619 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
72998b71
MI		 4620 fl = (hdw->state_encoder_ok &&
4621 hdw->state_encoder_run);
4622 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4623 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4624 fl = hdw->state_encoder_ok;
4625 }
4626 if (fl &&
4627 hdw->state_pipeline_req &&
4628 !hdw->state_pipeline_pause &&
4629 hdw->state_pathway_ok) {
4630 return 0;
681c7399
MI		 4631 }
4632 pvr2_hdw_cmd_usbstream(hdw,0);
4633 hdw->state_usbstream_run = 0;
4634 } else {
62433e31
MI		 4635 if (!hdw->state_pipeline_req ||
4636 hdw->state_pipeline_pause ||
4637 !hdw->state_pathway_ok) return 0;
4638 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4639 if (!hdw->state_encoder_ok ||
4640 !hdw->state_encoder_run) return 0;
72998b71
MI		 4641 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4642 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4643 if (!hdw->state_encoder_ok) return 0;
d913d630
MI		 4644 if (hdw->state_encoder_run) return 0;
4645 if (hdw->hdw_desc->digital_control_scheme ==
4646 PVR2_DIGITAL_SCHEME_ONAIR) {
4647 /* OnAir digital receivers won't stream
4648 unless the analog encoder has run first.
4649 Why? I have no idea. But don't even
4650 try until we know the analog side is
4651 known to have run. */
4652 if (!hdw->state_encoder_runok) return 0;
4653 }
62433e31 4654 }
681c7399
MI		 4655 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4656 hdw->state_usbstream_run = !0;
4657 }
4658 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4659 return !0;
4660}
4661
4662
4663/* Attempt to configure pipeline, if needed */
4664static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4665{
4666 if (hdw->state_pipeline_config ||
4667 hdw->state_pipeline_pause) return 0;
4668 pvr2_hdw_commit_execute(hdw);
4669 return !0;
4670}
4671
4672
4673/* Update pipeline idle and pipeline pause tracking states based on other
4674 inputs. This must be called whenever the other relevant inputs have
4675 changed. */
4676static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4677{
4678 unsigned int st;
4679 int updatedFl = 0;
4680 /* Update pipeline state */
4681 st = !(hdw->state_encoder_run ||
4682 hdw->state_decoder_run ||
4683 hdw->state_usbstream_run ||
4684 (!hdw->state_decoder_quiescent));
4685 if (!st != !hdw->state_pipeline_idle) {
4686 hdw->state_pipeline_idle = st;
4687 updatedFl = !0;
4688 }
4689 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4690 hdw->state_pipeline_pause = 0;
4691 updatedFl = !0;
4692 }
4693 return updatedFl;
4694}
4695
4696
4697typedef int (*state_eval_func)(struct pvr2_hdw *);
4698
4699/* Set of functions to be run to evaluate various states in the driver. */
ebff0330 4700static const state_eval_func eval_funcs[] = {
62433e31 4701 state_eval_pathway_ok,
681c7399
MI		 4702 state_eval_pipeline_config,
4703 state_eval_encoder_ok,
4704 state_eval_encoder_config,
4705 state_eval_decoder_run,
4706 state_eval_encoder_run,
4707 state_eval_usbstream_run,
4708};
4709
4710
4711/* Process various states and return true if we did anything interesting. */
4712static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4713{
4714 unsigned int i;
4715 int state_updated = 0;
4716 int check_flag;
4717
4718 if (!hdw->state_stale) return 0;
4719 if ((hdw->fw1_state != FW1_STATE_OK) ||
4720 !hdw->flag_ok) {
4721 hdw->state_stale = 0;
4722 return !0;
4723 }
4724 /* This loop is the heart of the entire driver. It keeps trying to
4725 evaluate various bits of driver state until nothing changes for
4726 one full iteration. Each "bit of state" tracks some global
4727 aspect of the driver, e.g. whether decoder should run, if
4728 pipeline is configured, usb streaming is on, etc. We separately
4729 evaluate each of those questions based on other driver state to
4730 arrive at the correct running configuration. */
4731 do {
4732 check_flag = 0;
4733 state_update_pipeline_state(hdw);
4734 /* Iterate over each bit of state */
4735 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4736 if ((*eval_funcs[i])(hdw)) {
4737 check_flag = !0;
4738 state_updated = !0;
4739 state_update_pipeline_state(hdw);
4740 }
4741 }
4742 } while (check_flag && hdw->flag_ok);
4743 hdw->state_stale = 0;
4744 trace_stbit("state_stale",hdw->state_stale);
4745 return state_updated;
4746}
4747
4748
1cb03b76
MI		 4749static unsigned int print_input_mask(unsigned int msk,
4750 char *buf,unsigned int acnt)
4751{
4752 unsigned int idx,ccnt;
4753 unsigned int tcnt = 0;
4754 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4755 if (!((1 << idx) & msk)) continue;
4756 ccnt = scnprintf(buf+tcnt,
4757 acnt-tcnt,
4758 "%s%s",
4759 (tcnt ? ", " : ""),
4760 control_values_input[idx]);
4761 tcnt += ccnt;
4762 }
4763 return tcnt;
4764}
4765
4766
62433e31
MI		 4767static const char *pvr2_pathway_state_name(int id)
4768{
4769 switch (id) {
4770 case PVR2_PATHWAY_ANALOG: return "analog";
4771 case PVR2_PATHWAY_DIGITAL: return "digital";
4772 default: return "unknown";
4773 }
4774}
4775
4776
681c7399
MI		 4777static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4778 char *buf,unsigned int acnt)
4779{
4780 switch (which) {
4781 case 0:
4782 return scnprintf(
4783 buf,acnt,
e9db1ff2 4784 "driver:%s%s%s%s%s <mode=%s>",
681c7399
MI		 4785 (hdw->flag_ok ? " <ok>" : " <fail>"),
4786 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4787 (hdw->flag_disconnected ? " <disconnected>" :
4788 " <connected>"),
4789 (hdw->flag_tripped ? " <tripped>" : ""),
62433e31
MI		 4790 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4791 pvr2_pathway_state_name(hdw->pathway_state));
4792
681c7399
MI		 4793 case 1:
4794 return scnprintf(
4795 buf,acnt,
4796 "pipeline:%s%s%s%s",
4797 (hdw->state_pipeline_idle ? " <idle>" : ""),
4798 (hdw->state_pipeline_config ?
4799 " <configok>" : " <stale>"),
4800 (hdw->state_pipeline_req ? " <req>" : ""),
4801 (hdw->state_pipeline_pause ? " <pause>" : ""));
4802 case 2:
4803 return scnprintf(
4804 buf,acnt,
62433e31 4805 "worker:%s%s%s%s%s%s%s",
681c7399
MI		 4806 (hdw->state_decoder_run ?
4807 " <decode:run>" :
4808 (hdw->state_decoder_quiescent ?
4809 "" : " <decode:stop>")),
4810 (hdw->state_decoder_quiescent ?
4811 " <decode:quiescent>" : ""),
4812 (hdw->state_encoder_ok ?
4813 "" : " <encode:init>"),
4814 (hdw->state_encoder_run ?
d913d630
MI		 4815 (hdw->state_encoder_runok ?
4816 " <encode:run>" :
4817 " <encode:firstrun>") :
4818 (hdw->state_encoder_runok ?
4819 " <encode:stop>" :
4820 " <encode:virgin>")),
681c7399
MI		 4821 (hdw->state_encoder_config ?
4822 " <encode:configok>" :
4823 (hdw->state_encoder_waitok ?
b9a37d91 4824 "" : " <encode:waitok>")),
681c7399 4825 (hdw->state_usbstream_run ?
62433e31
MI		 4826 " <usb:run>" : " <usb:stop>"),
4827 (hdw->state_pathway_ok ?
e9db1ff2 4828 " <pathway:ok>" : ""));
681c7399
MI		 4829 case 3:
4830 return scnprintf(
4831 buf,acnt,
4832 "state: %s",
4833 pvr2_get_state_name(hdw->master_state));
ad0992e9 4834 case 4: {
1cb03b76
MI		 4835 unsigned int tcnt = 0;
4836 unsigned int ccnt;
4837
4838 ccnt = scnprintf(buf,
4839 acnt,
4840 "Hardware supported inputs: ");
4841 tcnt += ccnt;
4842 tcnt += print_input_mask(hdw->input_avail_mask,
4843 buf+tcnt,
4844 acnt-tcnt);
4845 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4846 ccnt = scnprintf(buf+tcnt,
4847 acnt-tcnt,
4848 "; allowed inputs: ");
4849 tcnt += ccnt;
4850 tcnt += print_input_mask(hdw->input_allowed_mask,
4851 buf+tcnt,
4852 acnt-tcnt);
4853 }
4854 return tcnt;
4855 }
4856 case 5: {
ad0992e9
MI		 4857 struct pvr2_stream_stats stats;
4858 if (!hdw->vid_stream) break;
4859 pvr2_stream_get_stats(hdw->vid_stream,
4860 &stats,
4861 0);
4862 return scnprintf(
4863 buf,acnt,
4864 "Bytes streamed=%u"
4865 " URBs: queued=%u idle=%u ready=%u"
4866 " processed=%u failed=%u",
4867 stats.bytes_processed,
4868 stats.buffers_in_queue,
4869 stats.buffers_in_idle,
4870 stats.buffers_in_ready,
4871 stats.buffers_processed,
4872 stats.buffers_failed);
4873 }
858f910e
MI		 4874 case 6: {
4875 struct v4l2_subdev *sd;
4876 unsigned int tcnt = 0;
4877 unsigned int ccnt;
4878 const char *p;
4879 unsigned int id;
4880 ccnt = scnprintf(buf,
4881 acnt,
5f757ddd 4882 "Associated v4l2_subdev drivers:");
858f910e
MI		 4883 tcnt += ccnt;
4884 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4885 id = sd->grp_id;
4886 p = NULL;
4887 if (id < ARRAY_SIZE(module_names)) {
4888 p = module_names[id];
4889 }
5f757ddd
MI		 4890 if (p) {
4891 ccnt = scnprintf(buf + tcnt,
4892 acnt - tcnt,
4893 " %s", p);
4894 } else {
4895 ccnt = scnprintf(buf + tcnt,
4896 acnt - tcnt,
4897 " (unknown id=%u)", id);
4898 }
4899 tcnt += ccnt;
858f910e
MI		 4900 }
4901 return tcnt;
4902 }
681c7399
MI		 4903 default: break;
4904 }
4905 return 0;
4906}
4907
4908
4909unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4910 char *buf,unsigned int acnt)
4911{
4912 unsigned int bcnt,ccnt,idx;
4913 bcnt = 0;
4914 LOCK_TAKE(hdw->big_lock);
4915 for (idx = 0; ; idx++) {
4916 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4917 if (!ccnt) break;
4918 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4919 if (!acnt) break;
4920 buf[0] = '\n'; ccnt = 1;
4921 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4922 }
4923 LOCK_GIVE(hdw->big_lock);
4924 return bcnt;
4925}
4926
4927
4928static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4929{
4930 char buf[128];
4931 unsigned int idx,ccnt;
4932
4933 for (idx = 0; ; idx++) {
4934 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4935 if (!ccnt) break;
4936 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4937 }
4938}
4939
4940
4941/* Evaluate and update the driver's current state, taking various actions
4942 as appropriate for the update. */
4943static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4944{
4945 unsigned int st;
4946 int state_updated = 0;
4947 int callback_flag = 0;
1b9c18c5 4948 int analog_mode;
681c7399
MI		 4949
4950 pvr2_trace(PVR2_TRACE_STBITS,
4951 "Drive state check START");
4952 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4953 pvr2_hdw_state_log_state(hdw);
4954 }
4955
4956 /* Process all state and get back over disposition */
4957 state_updated = pvr2_hdw_state_update(hdw);
4958
1b9c18c5
MI		 4959 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4960
681c7399
MI		 4961 /* Update master state based upon all other states. */
4962 if (!hdw->flag_ok) {
4963 st = PVR2_STATE_DEAD;
4964 } else if (hdw->fw1_state != FW1_STATE_OK) {
4965 st = PVR2_STATE_COLD;
72998b71
MI		 4966 } else if ((analog_mode ||
4967 hdw->hdw_desc->flag_digital_requires_cx23416) &&
4968 !hdw->state_encoder_ok) {
681c7399 4969 st = PVR2_STATE_WARM;
1b9c18c5
MI		 4970 } else if (hdw->flag_tripped ||
4971 (analog_mode && hdw->flag_decoder_missed)) {
681c7399 4972 st = PVR2_STATE_ERROR;
62433e31 4973 } else if (hdw->state_usbstream_run &&
1b9c18c5 4974 (!analog_mode ||
62433e31 4975 (hdw->state_encoder_run && hdw->state_decoder_run))) {
681c7399
MI		 4976 st = PVR2_STATE_RUN;
4977 } else {
4978 st = PVR2_STATE_READY;
4979 }
4980 if (hdw->master_state != st) {
4981 pvr2_trace(PVR2_TRACE_STATE,
4982 "Device state change from %s to %s",
4983 pvr2_get_state_name(hdw->master_state),
4984 pvr2_get_state_name(st));
40381cb0 4985 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
681c7399
MI		 4986 hdw->master_state = st;
4987 state_updated = !0;
4988 callback_flag = !0;
4989 }
4990 if (state_updated) {
4991 /* Trigger anyone waiting on any state changes here. */
4992 wake_up(&hdw->state_wait_data);
4993 }
4994
4995 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4996 pvr2_hdw_state_log_state(hdw);
4997 }
4998 pvr2_trace(PVR2_TRACE_STBITS,
4999 "Drive state check DONE callback=%d",callback_flag);
5000
5001 return callback_flag;
5002}
5003
5004
5005/* Cause kernel thread to check / update driver state */
5006static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
5007{
5008 if (hdw->state_stale) return;
5009 hdw->state_stale = !0;
5010 trace_stbit("state_stale",hdw->state_stale);
5011 queue_work(hdw->workqueue,&hdw->workpoll);
5012}
5013
5014
d855497e
MI		 5015int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
5016{
5017 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5018}
5019
5020
5021int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5022{
5023 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5024}
5025
5026
5027int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5028{
5029 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5030}
5031
5032
5033int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5034{
5035 u32 cval,nval;
5036 int ret;
5037 if (~msk) {
5038 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5039 if (ret) return ret;
5040 nval = (cval & ~msk) | (val & msk);
5041 pvr2_trace(PVR2_TRACE_GPIO,
5042 "GPIO direction changing 0x%x:0x%x"
5043 " from 0x%x to 0x%x",
5044 msk,val,cval,nval);
5045 } else {
5046 nval = val;
5047 pvr2_trace(PVR2_TRACE_GPIO,
5048 "GPIO direction changing to 0x%x",nval);
5049 }
5050 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5051}
5052
5053
5054int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5055{
5056 u32 cval,nval;
5057 int ret;
5058 if (~msk) {
5059 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5060 if (ret) return ret;
5061 nval = (cval & ~msk) | (val & msk);
5062 pvr2_trace(PVR2_TRACE_GPIO,
5063 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5064 msk,val,cval,nval);
5065 } else {
5066 nval = val;
5067 pvr2_trace(PVR2_TRACE_GPIO,
5068 "GPIO output changing to 0x%x",nval);
5069 }
5070 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5071}
5072
5073
a51f5000
MI		 5074void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5075{
40f07111
MI		 5076 struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5077 memset(vtp, 0, sizeof(*vtp));
2641df36 5078 hdw->tuner_signal_stale = 0;
a51f5000 5079 pvr2_i2c_core_status_poll(hdw);
40f07111
MI		 5080 /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5081 using v4l2-subdev - therefore we can't support that AT ALL right
5082 now. (Of course, no sub-drivers seem to implement it either.
5083 But now it's a a chicken and egg problem...) */
5084 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5085 &hdw->tuner_signal_info);
2641df36 5086 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
40f07111
MI		 5087 " type=%u strength=%u audio=0x%x cap=0x%x"
5088 " low=%u hi=%u",
5089 vtp->type,
5090 vtp->signal, vtp->rxsubchans, vtp->capability,
5091 vtp->rangelow, vtp->rangehigh);
2641df36
MI		 5092
5093 /* We have to do this to avoid getting into constant polling if
5094 there's nobody to answer a poll of cropcap info. */
5095 hdw->cropcap_stale = 0;
a51f5000
MI		 5096}
5097
5098
7fb20fa3
MI		 5099unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5100{
5101 return hdw->input_avail_mask;
5102}
5103
5104
1cb03b76
MI		 5105unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5106{
5107 return hdw->input_allowed_mask;
5108}
5109
5110
5111static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5112{
5113 if (hdw->input_val != v) {
5114 hdw->input_val = v;
5115 hdw->input_dirty = !0;
5116 }
5117
5118 /* Handle side effects - if we switch to a mode that needs the RF
5119 tuner, then select the right frequency choice as well and mark
5120 it dirty. */
5121 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5122 hdw->freqSelector = 0;
5123 hdw->freqDirty = !0;
5124 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5125 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5126 hdw->freqSelector = 1;
5127 hdw->freqDirty = !0;
5128 }
5129 return 0;
5130}
5131
5132
5133int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5134 unsigned int change_mask,
5135 unsigned int change_val)
5136{
5137 int ret = 0;
5138 unsigned int nv,m,idx;
5139 LOCK_TAKE(hdw->big_lock);
5140 do {
5141 nv = hdw->input_allowed_mask & ~change_mask;
5142 nv |= (change_val & change_mask);
5143 nv &= hdw->input_avail_mask;
5144 if (!nv) {
5145 /* No legal modes left; return error instead. */
5146 ret = -EPERM;
5147 break;
5148 }
5149 hdw->input_allowed_mask = nv;
5150 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5151 /* Current mode is still in the allowed mask, so
5152 we're done. */
5153 break;
5154 }
5155 /* Select and switch to a mode that is still in the allowed
5156 mask */
5157 if (!hdw->input_allowed_mask) {
5158 /* Nothing legal; give up */
5159 break;
5160 }
5161 m = hdw->input_allowed_mask;
5162 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5163 if (!((1 << idx) & m)) continue;
5164 pvr2_hdw_set_input(hdw,idx);
5165 break;
5166 }
5167 } while (0);
5168 LOCK_GIVE(hdw->big_lock);
5169 return ret;
5170}
5171
5172
e61b6fc5 5173/* Find I2C address of eeprom */
07e337ee 5174static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 5175{
5176 int result;
5177 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 5178 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 5179 result = pvr2_send_request(hdw,
5180 hdw->cmd_buffer,1,
5181 hdw->cmd_buffer,1);
5182 if (result < 0) break;
5183 result = hdw->cmd_buffer[0];
5184 } while(0); LOCK_GIVE(hdw->ctl_lock);
5185 return result;
5186}
5187
5188
32ffa9ae 5189int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
aecde8b5
HV		 5190 struct v4l2_dbg_match *match, u64 reg_id,
5191 int setFl, u64 *val_ptr)
32ffa9ae
MI		 5192{
5193#ifdef CONFIG_VIDEO_ADV_DEBUG
32ffa9ae 5194 struct pvr2_i2c_client *cp;
aecde8b5 5195 struct v4l2_dbg_register req;
6d98816f
MI		 5196 int stat = 0;
5197 int okFl = 0;
32ffa9ae 5198
201f5c9c
MI		 5199 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5200
aecde8b5 5201 req.match = *match;
32ffa9ae
MI		 5202 req.reg = reg_id;
5203 if (setFl) req.val = *val_ptr;
d8f5b9ba
MI		 5204 /* It would be nice to know if a sub-device answered the request */
5205 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5206 if (!setFl) *val_ptr = req.val;
5207 if (!okFl) mutex_lock(&hdw->i2c_list_lock); do {
e77e2c2f 5208 list_for_each_entry(cp, &hdw->i2c_clients, list) {
8481a750
MI		 5209 if (!v4l2_chip_match_i2c_client(
5210 cp->client,
aecde8b5 5211 &req.match)) {
f3d092b8
HV		 5212 continue;
5213 }
32ffa9ae 5214 stat = pvr2_i2c_client_cmd(
52ebc763
TP		 5215 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
5216 VIDIOC_DBG_G_REGISTER),&req);
32ffa9ae 5217 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 5218 okFl = !0;
5219 break;
32ffa9ae
MI		 5220 }
5221 } while (0); mutex_unlock(&hdw->i2c_list_lock);
6d98816f
MI		 5222 if (okFl) {
5223 return stat;
5224 }
32ffa9ae
MI		 5225 return -EINVAL;
5226#else
5227 return -ENOSYS;
5228#endif
5229}
5230
5231
d855497e
MI		 5232/*
5233 Stuff for Emacs to see, in order to encourage consistent editing style:
5234 *** Local Variables: ***
5235 *** mode: c ***
5236 *** fill-column: 75 ***
5237 *** tab-width: 8 ***
5238 *** c-basic-offset: 8 ***
5239 *** End: ***
5240 */
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