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[media] pvrusb2: Fix a few missing default control values, for cropping
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
d855497e
MI		 3 *
4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21#include <linux/errno.h>
22#include <linux/string.h>
23#include <linux/slab.h>
24#include <linux/firmware.h>
d855497e 25#include <linux/videodev2.h>
32ffa9ae 26#include <media/v4l2-common.h>
75212a02 27#include <media/tuner.h>
d855497e
MI		 28#include "pvrusb2.h"
29#include "pvrusb2-std.h"
30#include "pvrusb2-util.h"
31#include "pvrusb2-hdw.h"
32#include "pvrusb2-i2c-core.h"
d855497e
MI		 33#include "pvrusb2-eeprom.h"
34#include "pvrusb2-hdw-internal.h"
35#include "pvrusb2-encoder.h"
36#include "pvrusb2-debug.h"
8d364363 37#include "pvrusb2-fx2-cmd.h"
5f6dae80 38#include "pvrusb2-wm8775.h"
6f956512 39#include "pvrusb2-video-v4l.h"
634ba268 40#include "pvrusb2-cx2584x-v4l.h"
2a6b627f 41#include "pvrusb2-cs53l32a.h"
76891d65 42#include "pvrusb2-audio.h"
d855497e 43
1bde0289
MI		 44#define TV_MIN_FREQ 55250000L
45#define TV_MAX_FREQ 850000000L
25d8527a 46
83ce57aa
MI		 47/* This defines a minimum interval that the decoder must remain quiet
48 before we are allowed to start it running. */
49#define TIME_MSEC_DECODER_WAIT 50
50
6e931375
MI		 51/* This defines a minimum interval that the decoder must be allowed to run
52 before we can safely begin using its streaming output. */
53#define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
54
83ce57aa 55/* This defines a minimum interval that the encoder must remain quiet
91b5b489
MI		 56 before we are allowed to configure it. */
57#define TIME_MSEC_ENCODER_WAIT 50
83ce57aa
MI		 58
59/* This defines the minimum interval that the encoder must successfully run
60 before we consider that the encoder has run at least once since its
61 firmware has been loaded. This measurement is in important for cases
62 where we can't do something until we know that the encoder has been run
63 at least once. */
64#define TIME_MSEC_ENCODER_OK 250
65
a0fd1cb1 66static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 67static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e 68
ff699e6b 69static int ctlchg;
ff699e6b 70static int procreload;
d855497e
MI		 71static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
72static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
73static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
ff699e6b 74static int init_pause_msec;
d855497e
MI		 75
76module_param(ctlchg, int, S_IRUGO|S_IWUSR);
77MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
78module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
79MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
d855497e
MI		 80module_param(procreload, int, S_IRUGO|S_IWUSR);
81MODULE_PARM_DESC(procreload,
82 "Attempt init failure recovery with firmware reload");
83module_param_array(tuner, int, NULL, 0444);
84MODULE_PARM_DESC(tuner,"specify installed tuner type");
85module_param_array(video_std, int, NULL, 0444);
86MODULE_PARM_DESC(video_std,"specify initial video standard");
87module_param_array(tolerance, int, NULL, 0444);
88MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
89
6f441ed7
MI		 90/* US Broadcast channel 3 (61.25 MHz), to help with testing */
91static int default_tv_freq = 61250000L;
5a4f5da6
MK		 92/* 104.3 MHz, a usable FM station for my area */
93static int default_radio_freq = 104300000L;
94
95module_param_named(tv_freq, default_tv_freq, int, 0444);
96MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
97module_param_named(radio_freq, default_radio_freq, int, 0444);
98MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
99
d855497e
MI		 100#define PVR2_CTL_WRITE_ENDPOINT 0x01
101#define PVR2_CTL_READ_ENDPOINT 0x81
102
103#define PVR2_GPIO_IN 0x9008
104#define PVR2_GPIO_OUT 0x900c
105#define PVR2_GPIO_DIR 0x9020
106
107#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
108
109#define PVR2_FIRMWARE_ENDPOINT 0x02
110
111/* size of a firmware chunk */
112#define FIRMWARE_CHUNK_SIZE 0x2000
113
edb9dcb8
MI		 114typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
115 struct v4l2_subdev *);
116
117static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
4ecbc28d 118 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
6f956512 119 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
76891d65 120 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
634ba268 121 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
2a6b627f 122 [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
edb9dcb8
MI		 123};
124
e9c64a78
MI		 125static const char *module_names[] = {
126 [PVR2_CLIENT_ID_MSP3400] = "msp3400",
127 [PVR2_CLIENT_ID_CX25840] = "cx25840",
128 [PVR2_CLIENT_ID_SAA7115] = "saa7115",
129 [PVR2_CLIENT_ID_TUNER] = "tuner",
bb65242a 130 [PVR2_CLIENT_ID_DEMOD] = "tuner",
851981a1 131 [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
5f6dae80 132 [PVR2_CLIENT_ID_WM8775] = "wm8775",
e9c64a78
MI		 133};
134
135
136static const unsigned char *module_i2c_addresses[] = {
137 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
bb65242a 138 [PVR2_CLIENT_ID_DEMOD] = "\x43",
1dfe6c77
MI		 139 [PVR2_CLIENT_ID_MSP3400] = "\x40",
140 [PVR2_CLIENT_ID_SAA7115] = "\x21",
ae111f76 141 [PVR2_CLIENT_ID_WM8775] = "\x1b",
0b467014 142 [PVR2_CLIENT_ID_CX25840] = "\x44",
23334a22 143 [PVR2_CLIENT_ID_CS53L32A] = "\x11",
e9c64a78
MI		 144};
145
146
27eab384
MI		 147static const char *ir_scheme_names[] = {
148 [PVR2_IR_SCHEME_NONE] = "none",
149 [PVR2_IR_SCHEME_29XXX] = "29xxx",
150 [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
151 [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
152 [PVR2_IR_SCHEME_ZILOG] = "Zilog",
153};
154
155
b30d2441
MI		 156/* Define the list of additional controls we'll dynamically construct based
157 on query of the cx2341x module. */
158struct pvr2_mpeg_ids {
159 const char *strid;
160 int id;
161};
162static const struct pvr2_mpeg_ids mpeg_ids[] = {
163 {
164 .strid = "audio_layer",
165 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
166 },{
167 .strid = "audio_bitrate",
168 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
169 },{
170 /* Already using audio_mode elsewhere :-( */
171 .strid = "mpeg_audio_mode",
172 .id = V4L2_CID_MPEG_AUDIO_MODE,
173 },{
174 .strid = "mpeg_audio_mode_extension",
175 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
176 },{
177 .strid = "audio_emphasis",
178 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
179 },{
180 .strid = "audio_crc",
181 .id = V4L2_CID_MPEG_AUDIO_CRC,
182 },{
183 .strid = "video_aspect",
184 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
185 },{
186 .strid = "video_b_frames",
187 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
188 },{
189 .strid = "video_gop_size",
190 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
191 },{
192 .strid = "video_gop_closure",
193 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 194 },{
195 .strid = "video_bitrate_mode",
196 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
197 },{
198 .strid = "video_bitrate",
199 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
200 },{
201 .strid = "video_bitrate_peak",
202 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
203 },{
204 .strid = "video_temporal_decimation",
205 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
206 },{
207 .strid = "stream_type",
208 .id = V4L2_CID_MPEG_STREAM_TYPE,
209 },{
210 .strid = "video_spatial_filter_mode",
211 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
212 },{
213 .strid = "video_spatial_filter",
214 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
215 },{
216 .strid = "video_luma_spatial_filter_type",
217 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
218 },{
219 .strid = "video_chroma_spatial_filter_type",
220 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
221 },{
222 .strid = "video_temporal_filter_mode",
223 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
224 },{
225 .strid = "video_temporal_filter",
226 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
227 },{
228 .strid = "video_median_filter_type",
229 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
230 },{
231 .strid = "video_luma_median_filter_top",
232 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
233 },{
234 .strid = "video_luma_median_filter_bottom",
235 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
236 },{
237 .strid = "video_chroma_median_filter_top",
238 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
239 },{
240 .strid = "video_chroma_median_filter_bottom",
241 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
242 }
243};
eca8ebfc 244#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 245
434449f4 246
d855497e 247static const char *control_values_srate[] = {
434449f4
MI		 248 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
249 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
250 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 251};
252
253
d855497e 254
d855497e
MI		 255static const char *control_values_input[] = {
256 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
29bf5b1d 257 [PVR2_CVAL_INPUT_DTV] = "dtv",
d855497e
MI		 258 [PVR2_CVAL_INPUT_RADIO] = "radio",
259 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
260 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
261};
262
263
264static const char *control_values_audiomode[] = {
265 [V4L2_TUNER_MODE_MONO] = "Mono",
266 [V4L2_TUNER_MODE_STEREO] = "Stereo",
267 [V4L2_TUNER_MODE_LANG1] = "Lang1",
268 [V4L2_TUNER_MODE_LANG2] = "Lang2",
269 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
270};
271
272
273static const char *control_values_hsm[] = {
274 [PVR2_CVAL_HSM_FAIL] = "Fail",
275 [PVR2_CVAL_HSM_HIGH] = "High",
276 [PVR2_CVAL_HSM_FULL] = "Full",
277};
278
279
681c7399
MI		 280static const char *pvr2_state_names[] = {
281 [PVR2_STATE_NONE] = "none",
282 [PVR2_STATE_DEAD] = "dead",
283 [PVR2_STATE_COLD] = "cold",
284 [PVR2_STATE_WARM] = "warm",
285 [PVR2_STATE_ERROR] = "error",
286 [PVR2_STATE_READY] = "ready",
287 [PVR2_STATE_RUN] = "run",
d855497e
MI		 288};
289
681c7399 290
694dca2b 291struct pvr2_fx2cmd_descdef {
1c9d10d4
MI		 292 unsigned char id;
293 unsigned char *desc;
294};
295
694dca2b 296static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
1c9d10d4
MI		 297 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
298 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
31335b13 299 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
1c9d10d4
MI		 300 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
301 {FX2CMD_REG_WRITE, "write encoder register"},
302 {FX2CMD_REG_READ, "read encoder register"},
303 {FX2CMD_MEMSEL, "encoder memsel"},
304 {FX2CMD_I2C_WRITE, "i2c write"},
305 {FX2CMD_I2C_READ, "i2c read"},
306 {FX2CMD_GET_USB_SPEED, "get USB speed"},
307 {FX2CMD_STREAMING_ON, "stream on"},
308 {FX2CMD_STREAMING_OFF, "stream off"},
309 {FX2CMD_FWPOST1, "fwpost1"},
310 {FX2CMD_POWER_OFF, "power off"},
311 {FX2CMD_POWER_ON, "power on"},
312 {FX2CMD_DEEP_RESET, "deep reset"},
313 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
314 {FX2CMD_GET_IR_CODE, "get IR code"},
315 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
316 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
317 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
318 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
319 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
320 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
321 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
322};
323
324
1cb03b76 325static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
681c7399
MI		 326static void pvr2_hdw_state_sched(struct pvr2_hdw *);
327static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 328static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399 329static void pvr2_hdw_worker_poll(struct work_struct *work);
681c7399
MI		 330static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
331static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
332static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 333static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 334static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 335static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 336static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
337static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
681c7399 338static void pvr2_hdw_quiescent_timeout(unsigned long);
6e931375 339static void pvr2_hdw_decoder_stabilization_timeout(unsigned long);
681c7399 340static void pvr2_hdw_encoder_wait_timeout(unsigned long);
d913d630 341static void pvr2_hdw_encoder_run_timeout(unsigned long);
1c9d10d4 342static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
07e337ee
AB		 343static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
344 unsigned int timeout,int probe_fl,
345 void *write_data,unsigned int write_len,
346 void *read_data,unsigned int read_len);
432907f7 347static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
d855497e 348
681c7399
MI		 349
350static void trace_stbit(const char *name,int val)
351{
352 pvr2_trace(PVR2_TRACE_STBITS,
353 "State bit %s <-- %s",
354 name,(val ? "true" : "false"));
355}
356
d855497e
MI		 357static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
358{
359 struct pvr2_hdw *hdw = cptr->hdw;
360 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
361 *vp = hdw->freqTable[hdw->freqProgSlot-1];
362 } else {
363 *vp = 0;
364 }
365 return 0;
366}
367
368static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
369{
370 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 371 unsigned int slotId = hdw->freqProgSlot;
372 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
373 hdw->freqTable[slotId-1] = v;
374 /* Handle side effects correctly - if we're tuned to this
375 slot, then forgot the slot id relation since the stored
376 frequency has been changed. */
377 if (hdw->freqSelector) {
378 if (hdw->freqSlotRadio == slotId) {
379 hdw->freqSlotRadio = 0;
380 }
381 } else {
382 if (hdw->freqSlotTelevision == slotId) {
383 hdw->freqSlotTelevision = 0;
384 }
385 }
d855497e
MI		 386 }
387 return 0;
388}
389
390static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
391{
392 *vp = cptr->hdw->freqProgSlot;
393 return 0;
394}
395
396static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
397{
398 struct pvr2_hdw *hdw = cptr->hdw;
399 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
400 hdw->freqProgSlot = v;
401 }
402 return 0;
403}
404
405static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
406{
1bde0289
MI		 407 struct pvr2_hdw *hdw = cptr->hdw;
408 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 409 return 0;
410}
411
1bde0289 412static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 413{
414 unsigned freq = 0;
415 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 416 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
417 if (slotId > 0) {
418 freq = hdw->freqTable[slotId-1];
419 if (!freq) return 0;
420 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 421 }
1bde0289
MI		 422 if (hdw->freqSelector) {
423 hdw->freqSlotRadio = slotId;
424 } else {
425 hdw->freqSlotTelevision = slotId;
d855497e
MI		 426 }
427 return 0;
428}
429
430static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
431{
1bde0289 432 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 433 return 0;
434}
435
436static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
437{
438 return cptr->hdw->freqDirty != 0;
439}
440
441static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
442{
443 cptr->hdw->freqDirty = 0;
444}
445
446static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
447{
1bde0289 448 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 449 return 0;
450}
451
e784bfb9 452static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
453{
432907f7
MI		 454 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
455 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
456 if (stat != 0) {
432907f7 457 return stat;
e784bfb9 458 }
432907f7 459 *left = cap->bounds.left;
e784bfb9 460 return 0;
461}
462
463static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
464{
432907f7
MI		 465 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
466 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
467 if (stat != 0) {
432907f7
MI		 468 return stat;
469 }
470 *left = cap->bounds.left;
471 if (cap->bounds.width > cptr->hdw->cropw_val) {
432907f7 472 *left += cap->bounds.width - cptr->hdw->cropw_val;
e784bfb9 473 }
474 return 0;
475}
476
477static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
478{
432907f7
MI		 479 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
480 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
481 if (stat != 0) {
432907f7 482 return stat;
e784bfb9 483 }
432907f7 484 *top = cap->bounds.top;
e784bfb9 485 return 0;
486}
487
432907f7 488static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
3ad9fc37 489{
432907f7
MI		 490 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
491 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
492 if (stat != 0) {
432907f7
MI		 493 return stat;
494 }
495 *top = cap->bounds.top;
496 if (cap->bounds.height > cptr->hdw->croph_val) {
432907f7 497 *top += cap->bounds.height - cptr->hdw->croph_val;
3ad9fc37
MI		 498 }
499 return 0;
500}
501
432907f7
MI		 502static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
503{
504 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
505 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
506 if (stat != 0) {
432907f7
MI		 507 return stat;
508 }
509 *val = 0;
510 if (cap->bounds.width > cptr->hdw->cropl_val) {
432907f7
MI		 511 *val = cap->bounds.width - cptr->hdw->cropl_val;
512 }
513 return 0;
514}
515
516static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
517{
518 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
519 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
520 if (stat != 0) {
432907f7
MI		 521 return stat;
522 }
523 *val = 0;
524 if (cap->bounds.height > cptr->hdw->cropt_val) {
432907f7
MI		 525 *val = cap->bounds.height - cptr->hdw->cropt_val;
526 }
527 return 0;
528}
529
530static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
531{
532 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
533 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
534 if (stat != 0) {
432907f7
MI		 535 return stat;
536 }
537 *val = cap->bounds.left;
538 return 0;
539}
540
541static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
542{
543 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
544 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
545 if (stat != 0) {
432907f7
MI		 546 return stat;
547 }
548 *val = cap->bounds.top;
549 return 0;
550}
551
552static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
553{
554 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
555 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
556 if (stat != 0) {
432907f7
MI		 557 return stat;
558 }
559 *val = cap->bounds.width;
560 return 0;
561}
562
563static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
564{
565 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
566 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
567 if (stat != 0) {
432907f7
MI		 568 return stat;
569 }
570 *val = cap->bounds.height;
571 return 0;
572}
573
574static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
575{
576 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
577 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
578 if (stat != 0) {
432907f7
MI		 579 return stat;
580 }
581 *val = cap->defrect.left;
582 return 0;
583}
584
585static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
586{
587 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
588 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
589 if (stat != 0) {
432907f7
MI		 590 return stat;
591 }
592 *val = cap->defrect.top;
593 return 0;
594}
595
596static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
597{
598 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
599 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
600 if (stat != 0) {
432907f7
MI		 601 return stat;
602 }
603 *val = cap->defrect.width;
604 return 0;
605}
606
607static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
608{
609 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
610 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
611 if (stat != 0) {
432907f7
MI		 612 return stat;
613 }
614 *val = cap->defrect.height;
615 return 0;
616}
617
618static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
619{
620 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
621 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
622 if (stat != 0) {
432907f7
MI		 623 return stat;
624 }
625 *val = cap->pixelaspect.numerator;
626 return 0;
627}
628
629static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
630{
631 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
632 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
633 if (stat != 0) {
432907f7
MI		 634 return stat;
635 }
636 *val = cap->pixelaspect.denominator;
637 return 0;
638}
639
640static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
e784bfb9 641{
432907f7
MI		 642 /* Actual maximum depends on the video standard in effect. */
643 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
644 *vp = 480;
e784bfb9 645 } else {
432907f7 646 *vp = 576;
e784bfb9 647 }
648 return 0;
649}
650
3ad9fc37
MI		 651static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
652{
989eb154
MI		 653 /* Actual minimum depends on device digitizer type. */
654 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 655 *vp = 75;
656 } else {
657 *vp = 17;
658 }
659 return 0;
660}
661
1bde0289 662static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 663{
1bde0289
MI		 664 *vp = cptr->hdw->input_val;
665 return 0;
666}
667
29bf5b1d
MI		 668static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
669{
1cb03b76 670 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
29bf5b1d
MI		 671}
672
1bde0289
MI		 673static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
674{
1cb03b76 675 return pvr2_hdw_set_input(cptr->hdw,v);
1bde0289
MI		 676}
677
678static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
679{
680 return cptr->hdw->input_dirty != 0;
681}
682
683static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
684{
685 cptr->hdw->input_dirty = 0;
686}
687
5549f54f 688
25d8527a
PK		 689static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
690{
644afdb9
MI		 691 unsigned long fv;
692 struct pvr2_hdw *hdw = cptr->hdw;
693 if (hdw->tuner_signal_stale) {
a51f5000 694 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 695 }
696 fv = hdw->tuner_signal_info.rangehigh;
697 if (!fv) {
698 /* Safety fallback */
25d8527a 699 *vp = TV_MAX_FREQ;
644afdb9 700 return 0;
25d8527a 701 }
644afdb9
MI		 702 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
703 fv = (fv * 125) / 2;
704 } else {
705 fv = fv * 62500;
706 }
707 *vp = fv;
25d8527a
PK		 708 return 0;
709}
710
711static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
712{
644afdb9
MI		 713 unsigned long fv;
714 struct pvr2_hdw *hdw = cptr->hdw;
715 if (hdw->tuner_signal_stale) {
a51f5000 716 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 717 }
718 fv = hdw->tuner_signal_info.rangelow;
719 if (!fv) {
720 /* Safety fallback */
25d8527a 721 *vp = TV_MIN_FREQ;
644afdb9
MI		 722 return 0;
723 }
724 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
725 fv = (fv * 125) / 2;
726 } else {
727 fv = fv * 62500;
25d8527a 728 }
644afdb9 729 *vp = fv;
25d8527a
PK		 730 return 0;
731}
732
b30d2441
MI		 733static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
734{
735 return cptr->hdw->enc_stale != 0;
736}
737
738static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
739{
740 cptr->hdw->enc_stale = 0;
681c7399 741 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 742}
743
744static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
745{
746 int ret;
747 struct v4l2_ext_controls cs;
748 struct v4l2_ext_control c1;
749 memset(&cs,0,sizeof(cs));
750 memset(&c1,0,sizeof(c1));
751 cs.controls = &c1;
752 cs.count = 1;
753 c1.id = cptr->info->v4l_id;
01f1e44f 754 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 755 VIDIOC_G_EXT_CTRLS);
756 if (ret) return ret;
757 *vp = c1.value;
758 return 0;
759}
760
761static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
762{
763 int ret;
681c7399 764 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 765 struct v4l2_ext_controls cs;
766 struct v4l2_ext_control c1;
767 memset(&cs,0,sizeof(cs));
768 memset(&c1,0,sizeof(c1));
769 cs.controls = &c1;
770 cs.count = 1;
771 c1.id = cptr->info->v4l_id;
772 c1.value = v;
681c7399
MI		 773 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
774 hdw->state_encoder_run, &cs,
b30d2441 775 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 776 if (ret == -EBUSY) {
777 /* Oops. cx2341x is telling us it's not safe to change
778 this control while we're capturing. Make a note of this
779 fact so that the pipeline will be stopped the next time
780 controls are committed. Then go on ahead and store this
781 change anyway. */
782 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
783 0, &cs,
784 VIDIOC_S_EXT_CTRLS);
785 if (!ret) hdw->enc_unsafe_stale = !0;
786 }
b30d2441 787 if (ret) return ret;
681c7399 788 hdw->enc_stale = !0;
b30d2441
MI		 789 return 0;
790}
791
792static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
793{
794 struct v4l2_queryctrl qctrl;
795 struct pvr2_ctl_info *info;
796 qctrl.id = cptr->info->v4l_id;
797 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
798 /* Strip out the const so we can adjust a function pointer. It's
799 OK to do this here because we know this is a dynamically created
800 control, so the underlying storage for the info pointer is (a)
801 private to us, and (b) not in read-only storage. Either we do
802 this or we significantly complicate the underlying control
803 implementation. */
804 info = (struct pvr2_ctl_info *)(cptr->info);
805 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
806 if (info->set_value) {
a0fd1cb1 807 info->set_value = NULL;
b30d2441
MI		 808 }
809 } else {
810 if (!(info->set_value)) {
811 info->set_value = ctrl_cx2341x_set;
812 }
813 }
814 return qctrl.flags;
815}
816
d855497e
MI		 817static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
818{
681c7399
MI		 819 *vp = cptr->hdw->state_pipeline_req;
820 return 0;
821}
822
823static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
824{
825 *vp = cptr->hdw->master_state;
d855497e
MI		 826 return 0;
827}
828
829static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
830{
831 int result = pvr2_hdw_is_hsm(cptr->hdw);
832 *vp = PVR2_CVAL_HSM_FULL;
833 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
834 if (result) *vp = PVR2_CVAL_HSM_HIGH;
835 return 0;
836}
837
838static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
839{
840 *vp = cptr->hdw->std_mask_avail;
841 return 0;
842}
843
844static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
845{
846 struct pvr2_hdw *hdw = cptr->hdw;
847 v4l2_std_id ns;
848 ns = hdw->std_mask_avail;
849 ns = (ns & ~m) | (v & m);
850 if (ns == hdw->std_mask_avail) return 0;
851 hdw->std_mask_avail = ns;
852 pvr2_hdw_internal_set_std_avail(hdw);
853 pvr2_hdw_internal_find_stdenum(hdw);
854 return 0;
855}
856
857static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
858 char *bufPtr,unsigned int bufSize,
859 unsigned int *len)
860{
861 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
862 return 0;
863}
864
865static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
866 const char *bufPtr,unsigned int bufSize,
867 int *mskp,int *valp)
868{
869 int ret;
870 v4l2_std_id id;
871 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
872 if (ret < 0) return ret;
873 if (mskp) *mskp = id;
874 if (valp) *valp = id;
875 return 0;
876}
877
878static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
879{
880 *vp = cptr->hdw->std_mask_cur;
881 return 0;
882}
883
884static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
885{
886 struct pvr2_hdw *hdw = cptr->hdw;
887 v4l2_std_id ns;
888 ns = hdw->std_mask_cur;
889 ns = (ns & ~m) | (v & m);
890 if (ns == hdw->std_mask_cur) return 0;
891 hdw->std_mask_cur = ns;
892 hdw->std_dirty = !0;
893 pvr2_hdw_internal_find_stdenum(hdw);
894 return 0;
895}
896
897static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
898{
899 return cptr->hdw->std_dirty != 0;
900}
901
902static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
903{
904 cptr->hdw->std_dirty = 0;
905}
906
907static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
908{
18103c57 909 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 910 pvr2_hdw_status_poll(hdw);
18103c57
MI		 911 *vp = hdw->tuner_signal_info.signal;
912 return 0;
913}
914
915static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
916{
917 int val = 0;
918 unsigned int subchan;
919 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 920 pvr2_hdw_status_poll(hdw);
18103c57
MI		 921 subchan = hdw->tuner_signal_info.rxsubchans;
922 if (subchan & V4L2_TUNER_SUB_MONO) {
923 val |= (1 << V4L2_TUNER_MODE_MONO);
924 }
925 if (subchan & V4L2_TUNER_SUB_STEREO) {
926 val |= (1 << V4L2_TUNER_MODE_STEREO);
927 }
928 if (subchan & V4L2_TUNER_SUB_LANG1) {
929 val |= (1 << V4L2_TUNER_MODE_LANG1);
930 }
931 if (subchan & V4L2_TUNER_SUB_LANG2) {
932 val |= (1 << V4L2_TUNER_MODE_LANG2);
933 }
934 *vp = val;
d855497e
MI		 935 return 0;
936}
937
d855497e
MI		 938
939static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
940{
941 struct pvr2_hdw *hdw = cptr->hdw;
942 if (v < 0) return -EINVAL;
943 if (v > hdw->std_enum_cnt) return -EINVAL;
944 hdw->std_enum_cur = v;
945 if (!v) return 0;
946 v--;
947 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
948 hdw->std_mask_cur = hdw->std_defs[v].id;
949 hdw->std_dirty = !0;
950 return 0;
951}
952
953
954static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
955{
956 *vp = cptr->hdw->std_enum_cur;
957 return 0;
958}
959
960
961static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
962{
963 return cptr->hdw->std_dirty != 0;
964}
965
966
967static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
968{
969 cptr->hdw->std_dirty = 0;
970}
971
972
973#define DEFINT(vmin,vmax) \
974 .type = pvr2_ctl_int, \
975 .def.type_int.min_value = vmin, \
976 .def.type_int.max_value = vmax
977
978#define DEFENUM(tab) \
979 .type = pvr2_ctl_enum, \
27c7b710 980 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 981 .def.type_enum.value_names = tab
982
33213963
MI		 983#define DEFBOOL \
984 .type = pvr2_ctl_bool
985
d855497e
MI		 986#define DEFMASK(msk,tab) \
987 .type = pvr2_ctl_bitmask, \
988 .def.type_bitmask.valid_bits = msk, \
989 .def.type_bitmask.bit_names = tab
990
991#define DEFREF(vname) \
992 .set_value = ctrl_set_##vname, \
993 .get_value = ctrl_get_##vname, \
994 .is_dirty = ctrl_isdirty_##vname, \
995 .clear_dirty = ctrl_cleardirty_##vname
996
997
998#define VCREATE_FUNCS(vname) \
999static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
1000{*vp = cptr->hdw->vname##_val; return 0;} \
1001static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
1002{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
1003static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
1004{return cptr->hdw->vname##_dirty != 0;} \
1005static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
1006{cptr->hdw->vname##_dirty = 0;}
1007
1008VCREATE_FUNCS(brightness)
1009VCREATE_FUNCS(contrast)
1010VCREATE_FUNCS(saturation)
1011VCREATE_FUNCS(hue)
1012VCREATE_FUNCS(volume)
1013VCREATE_FUNCS(balance)
1014VCREATE_FUNCS(bass)
1015VCREATE_FUNCS(treble)
1016VCREATE_FUNCS(mute)
e784bfb9 1017VCREATE_FUNCS(cropl)
1018VCREATE_FUNCS(cropt)
1019VCREATE_FUNCS(cropw)
1020VCREATE_FUNCS(croph)
c05c0462
MI		 1021VCREATE_FUNCS(audiomode)
1022VCREATE_FUNCS(res_hor)
1023VCREATE_FUNCS(res_ver)
d855497e 1024VCREATE_FUNCS(srate)
d855497e 1025
d855497e
MI		 1026/* Table definition of all controls which can be manipulated */
1027static const struct pvr2_ctl_info control_defs[] = {
1028 {
1029 .v4l_id = V4L2_CID_BRIGHTNESS,
1030 .desc = "Brightness",
1031 .name = "brightness",
1032 .default_value = 128,
1033 DEFREF(brightness),
1034 DEFINT(0,255),
1035 },{
1036 .v4l_id = V4L2_CID_CONTRAST,
1037 .desc = "Contrast",
1038 .name = "contrast",
1039 .default_value = 68,
1040 DEFREF(contrast),
1041 DEFINT(0,127),
1042 },{
1043 .v4l_id = V4L2_CID_SATURATION,
1044 .desc = "Saturation",
1045 .name = "saturation",
1046 .default_value = 64,
1047 DEFREF(saturation),
1048 DEFINT(0,127),
1049 },{
1050 .v4l_id = V4L2_CID_HUE,
1051 .desc = "Hue",
1052 .name = "hue",
1053 .default_value = 0,
1054 DEFREF(hue),
1055 DEFINT(-128,127),
1056 },{
1057 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1058 .desc = "Volume",
1059 .name = "volume",
139eecf9 1060 .default_value = 62000,
d855497e
MI		 1061 DEFREF(volume),
1062 DEFINT(0,65535),
1063 },{
1064 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1065 .desc = "Balance",
1066 .name = "balance",
1067 .default_value = 0,
1068 DEFREF(balance),
1069 DEFINT(-32768,32767),
1070 },{
1071 .v4l_id = V4L2_CID_AUDIO_BASS,
1072 .desc = "Bass",
1073 .name = "bass",
1074 .default_value = 0,
1075 DEFREF(bass),
1076 DEFINT(-32768,32767),
1077 },{
1078 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1079 .desc = "Treble",
1080 .name = "treble",
1081 .default_value = 0,
1082 DEFREF(treble),
1083 DEFINT(-32768,32767),
1084 },{
1085 .v4l_id = V4L2_CID_AUDIO_MUTE,
1086 .desc = "Mute",
1087 .name = "mute",
1088 .default_value = 0,
1089 DEFREF(mute),
33213963 1090 DEFBOOL,
e784bfb9 1091 }, {
432907f7 1092 .desc = "Capture crop left margin",
e784bfb9 1093 .name = "crop_left",
1094 .internal_id = PVR2_CID_CROPL,
1095 .default_value = 0,
1096 DEFREF(cropl),
1097 DEFINT(-129, 340),
1098 .get_min_value = ctrl_cropl_min_get,
1099 .get_max_value = ctrl_cropl_max_get,
432907f7 1100 .get_def_value = ctrl_get_cropcapdl,
e784bfb9 1101 }, {
432907f7 1102 .desc = "Capture crop top margin",
e784bfb9 1103 .name = "crop_top",
1104 .internal_id = PVR2_CID_CROPT,
1105 .default_value = 0,
1106 DEFREF(cropt),
1107 DEFINT(-35, 544),
1108 .get_min_value = ctrl_cropt_min_get,
1109 .get_max_value = ctrl_cropt_max_get,
432907f7 1110 .get_def_value = ctrl_get_cropcapdt,
e784bfb9 1111 }, {
432907f7 1112 .desc = "Capture crop width",
e784bfb9 1113 .name = "crop_width",
1114 .internal_id = PVR2_CID_CROPW,
1115 .default_value = 720,
1116 DEFREF(cropw),
35fa5d4c 1117 DEFINT(0, 864),
432907f7
MI		 1118 .get_max_value = ctrl_cropw_max_get,
1119 .get_def_value = ctrl_get_cropcapdw,
e784bfb9 1120 }, {
432907f7 1121 .desc = "Capture crop height",
e784bfb9 1122 .name = "crop_height",
1123 .internal_id = PVR2_CID_CROPH,
1124 .default_value = 480,
1125 DEFREF(croph),
35fa5d4c 1126 DEFINT(0, 576),
432907f7
MI		 1127 .get_max_value = ctrl_croph_max_get,
1128 .get_def_value = ctrl_get_cropcapdh,
1129 }, {
1130 .desc = "Capture capability pixel aspect numerator",
1131 .name = "cropcap_pixel_numerator",
1132 .internal_id = PVR2_CID_CROPCAPPAN,
1133 .get_value = ctrl_get_cropcappan,
1134 }, {
1135 .desc = "Capture capability pixel aspect denominator",
1136 .name = "cropcap_pixel_denominator",
1137 .internal_id = PVR2_CID_CROPCAPPAD,
1138 .get_value = ctrl_get_cropcappad,
1139 }, {
1140 .desc = "Capture capability bounds top",
1141 .name = "cropcap_bounds_top",
1142 .internal_id = PVR2_CID_CROPCAPBT,
1143 .get_value = ctrl_get_cropcapbt,
1144 }, {
1145 .desc = "Capture capability bounds left",
1146 .name = "cropcap_bounds_left",
1147 .internal_id = PVR2_CID_CROPCAPBL,
1148 .get_value = ctrl_get_cropcapbl,
1149 }, {
1150 .desc = "Capture capability bounds width",
1151 .name = "cropcap_bounds_width",
1152 .internal_id = PVR2_CID_CROPCAPBW,
1153 .get_value = ctrl_get_cropcapbw,
1154 }, {
1155 .desc = "Capture capability bounds height",
1156 .name = "cropcap_bounds_height",
1157 .internal_id = PVR2_CID_CROPCAPBH,
1158 .get_value = ctrl_get_cropcapbh,
c05c0462
MI		 1159 },{
1160 .desc = "Video Source",
1161 .name = "input",
1162 .internal_id = PVR2_CID_INPUT,
1163 .default_value = PVR2_CVAL_INPUT_TV,
29bf5b1d 1164 .check_value = ctrl_check_input,
c05c0462
MI		 1165 DEFREF(input),
1166 DEFENUM(control_values_input),
1167 },{
1168 .desc = "Audio Mode",
1169 .name = "audio_mode",
1170 .internal_id = PVR2_CID_AUDIOMODE,
1171 .default_value = V4L2_TUNER_MODE_STEREO,
1172 DEFREF(audiomode),
1173 DEFENUM(control_values_audiomode),
1174 },{
1175 .desc = "Horizontal capture resolution",
1176 .name = "resolution_hor",
1177 .internal_id = PVR2_CID_HRES,
1178 .default_value = 720,
1179 DEFREF(res_hor),
3ad9fc37 1180 DEFINT(19,720),
c05c0462
MI		 1181 },{
1182 .desc = "Vertical capture resolution",
1183 .name = "resolution_ver",
1184 .internal_id = PVR2_CID_VRES,
1185 .default_value = 480,
1186 DEFREF(res_ver),
3ad9fc37
MI		 1187 DEFINT(17,576),
1188 /* Hook in check for video standard and adjust maximum
1189 depending on the standard. */
1190 .get_max_value = ctrl_vres_max_get,
1191 .get_min_value = ctrl_vres_min_get,
d855497e 1192 },{
b30d2441 1193 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 1194 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1195 .desc = "Audio Sampling Frequency",
d855497e 1196 .name = "srate",
d855497e
MI		 1197 DEFREF(srate),
1198 DEFENUM(control_values_srate),
d855497e
MI		 1199 },{
1200 .desc = "Tuner Frequency (Hz)",
1201 .name = "frequency",
1202 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 1203 .default_value = 0,
d855497e
MI		 1204 .set_value = ctrl_freq_set,
1205 .get_value = ctrl_freq_get,
1206 .is_dirty = ctrl_freq_is_dirty,
1207 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 1208 DEFINT(0,0),
25d8527a
PK		 1209 /* Hook in check for input value (tv/radio) and adjust
1210 max/min values accordingly */
1211 .get_max_value = ctrl_freq_max_get,
1212 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1213 },{
1214 .desc = "Channel",
1215 .name = "channel",
1216 .set_value = ctrl_channel_set,
1217 .get_value = ctrl_channel_get,
1218 DEFINT(0,FREQTABLE_SIZE),
1219 },{
1220 .desc = "Channel Program Frequency",
1221 .name = "freq_table_value",
1222 .set_value = ctrl_channelfreq_set,
1223 .get_value = ctrl_channelfreq_get,
644afdb9 1224 DEFINT(0,0),
1bde0289
MI		 1225 /* Hook in check for input value (tv/radio) and adjust
1226 max/min values accordingly */
1bde0289
MI		 1227 .get_max_value = ctrl_freq_max_get,
1228 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1229 },{
1230 .desc = "Channel Program ID",
1231 .name = "freq_table_channel",
1232 .set_value = ctrl_channelprog_set,
1233 .get_value = ctrl_channelprog_get,
1234 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 1235 },{
1236 .desc = "Streaming Enabled",
1237 .name = "streaming_enabled",
1238 .get_value = ctrl_streamingenabled_get,
33213963 1239 DEFBOOL,
d855497e
MI		 1240 },{
1241 .desc = "USB Speed",
1242 .name = "usb_speed",
1243 .get_value = ctrl_hsm_get,
1244 DEFENUM(control_values_hsm),
681c7399
MI		 1245 },{
1246 .desc = "Master State",
1247 .name = "master_state",
1248 .get_value = ctrl_masterstate_get,
1249 DEFENUM(pvr2_state_names),
d855497e
MI		 1250 },{
1251 .desc = "Signal Present",
1252 .name = "signal_present",
1253 .get_value = ctrl_signal_get,
18103c57
MI		 1254 DEFINT(0,65535),
1255 },{
1256 .desc = "Audio Modes Present",
1257 .name = "audio_modes_present",
1258 .get_value = ctrl_audio_modes_present_get,
1259 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1260 v4l. Nothing outside of this module cares about this,
1261 but I reuse it in order to also reuse the
1262 control_values_audiomode string table. */
1263 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1264 (1 << V4L2_TUNER_MODE_STEREO)|
1265 (1 << V4L2_TUNER_MODE_LANG1)|
1266 (1 << V4L2_TUNER_MODE_LANG2)),
1267 control_values_audiomode),
d855497e
MI		 1268 },{
1269 .desc = "Video Standards Available Mask",
1270 .name = "video_standard_mask_available",
1271 .internal_id = PVR2_CID_STDAVAIL,
1272 .skip_init = !0,
1273 .get_value = ctrl_stdavail_get,
1274 .set_value = ctrl_stdavail_set,
1275 .val_to_sym = ctrl_std_val_to_sym,
1276 .sym_to_val = ctrl_std_sym_to_val,
1277 .type = pvr2_ctl_bitmask,
1278 },{
1279 .desc = "Video Standards In Use Mask",
1280 .name = "video_standard_mask_active",
1281 .internal_id = PVR2_CID_STDCUR,
1282 .skip_init = !0,
1283 .get_value = ctrl_stdcur_get,
1284 .set_value = ctrl_stdcur_set,
1285 .is_dirty = ctrl_stdcur_is_dirty,
1286 .clear_dirty = ctrl_stdcur_clear_dirty,
1287 .val_to_sym = ctrl_std_val_to_sym,
1288 .sym_to_val = ctrl_std_sym_to_val,
1289 .type = pvr2_ctl_bitmask,
d855497e
MI		 1290 },{
1291 .desc = "Video Standard Name",
1292 .name = "video_standard",
1293 .internal_id = PVR2_CID_STDENUM,
1294 .skip_init = !0,
1295 .get_value = ctrl_stdenumcur_get,
1296 .set_value = ctrl_stdenumcur_set,
1297 .is_dirty = ctrl_stdenumcur_is_dirty,
1298 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1299 .type = pvr2_ctl_enum,
1300 }
1301};
1302
eca8ebfc 1303#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 1304
1305
1306const char *pvr2_config_get_name(enum pvr2_config cfg)
1307{
1308 switch (cfg) {
1309 case pvr2_config_empty: return "empty";
1310 case pvr2_config_mpeg: return "mpeg";
1311 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 1312 case pvr2_config_pcm: return "pcm";
1313 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 1314 }
1315 return "<unknown>";
1316}
1317
1318
1319struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1320{
1321 return hdw->usb_dev;
1322}
1323
1324
1325unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1326{
1327 return hdw->serial_number;
1328}
1329
31a18547
MI		 1330
1331const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1332{
1333 return hdw->bus_info;
1334}
1335
1336
13a88797
MI		 1337const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1338{
1339 return hdw->identifier;
1340}
1341
1342
1bde0289
MI		 1343unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1344{
1345 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1346}
1347
1348/* Set the currently tuned frequency and account for all possible
1349 driver-core side effects of this action. */
f55a8712 1350static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1bde0289 1351{
7c74e57e 1352 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 1353 if (hdw->freqSelector) {
1354 /* Swing over to radio frequency selection */
1355 hdw->freqSelector = 0;
1356 hdw->freqDirty = !0;
1357 }
1bde0289
MI		 1358 if (hdw->freqValRadio != val) {
1359 hdw->freqValRadio = val;
1360 hdw->freqSlotRadio = 0;
7c74e57e 1361 hdw->freqDirty = !0;
1bde0289 1362 }
7c74e57e 1363 } else {
1bde0289
MI		 1364 if (!(hdw->freqSelector)) {
1365 /* Swing over to television frequency selection */
1366 hdw->freqSelector = 1;
1367 hdw->freqDirty = !0;
1368 }
1bde0289
MI		 1369 if (hdw->freqValTelevision != val) {
1370 hdw->freqValTelevision = val;
1371 hdw->freqSlotTelevision = 0;
7c74e57e 1372 hdw->freqDirty = !0;
1bde0289 1373 }
1bde0289
MI		 1374 }
1375}
1376
d855497e
MI		 1377int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1378{
1379 return hdw->unit_number;
1380}
1381
1382
1383/* Attempt to locate one of the given set of files. Messages are logged
1384 appropriate to what has been found. The return value will be 0 or
1385 greater on success (it will be the index of the file name found) and
1386 fw_entry will be filled in. Otherwise a negative error is returned on
1387 failure. If the return value is -ENOENT then no viable firmware file
1388 could be located. */
1389static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1390 const struct firmware **fw_entry,
1391 const char *fwtypename,
1392 unsigned int fwcount,
1393 const char *fwnames[])
1394{
1395 unsigned int idx;
1396 int ret = -EINVAL;
1397 for (idx = 0; idx < fwcount; idx++) {
1398 ret = request_firmware(fw_entry,
1399 fwnames[idx],
1400 &hdw->usb_dev->dev);
1401 if (!ret) {
1402 trace_firmware("Located %s firmware: %s;"
1403 " uploading...",
1404 fwtypename,
1405 fwnames[idx]);
1406 return idx;
1407 }
1408 if (ret == -ENOENT) continue;
1409 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1410 "request_firmware fatal error with code=%d",ret);
1411 return ret;
1412 }
1413 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1414 "***WARNING***"
1415 " Device %s firmware"
1416 " seems to be missing.",
1417 fwtypename);
1418 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1419 "Did you install the pvrusb2 firmware files"
1420 " in their proper location?");
1421 if (fwcount == 1) {
1422 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1423 "request_firmware unable to locate %s file %s",
1424 fwtypename,fwnames[0]);
1425 } else {
1426 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1427 "request_firmware unable to locate"
1428 " one of the following %s files:",
1429 fwtypename);
1430 for (idx = 0; idx < fwcount; idx++) {
1431 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1432 "request_firmware: Failed to find %s",
1433 fwnames[idx]);
1434 }
1435 }
1436 return ret;
1437}
1438
1439
1440/*
1441 * pvr2_upload_firmware1().
1442 *
1443 * Send the 8051 firmware to the device. After the upload, arrange for
1444 * device to re-enumerate.
1445 *
1446 * NOTE : the pointer to the firmware data given by request_firmware()
1447 * is not suitable for an usb transaction.
1448 *
1449 */
07e337ee 1450static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1451{
a0fd1cb1 1452 const struct firmware *fw_entry = NULL;
d855497e
MI		 1453 void *fw_ptr;
1454 unsigned int pipe;
9081d901 1455 unsigned int fwsize;
d855497e
MI		 1456 int ret;
1457 u16 address;
1d643a37 1458
989eb154 1459 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1460 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1461 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1462 "Connected device type defines"
1463 " no firmware to upload; ignoring firmware");
1464 return -ENOTTY;
1d643a37
MI		 1465 }
1466
d855497e
MI		 1467 hdw->fw1_state = FW1_STATE_FAILED; // default result
1468
1469 trace_firmware("pvr2_upload_firmware1");
1470
1471 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1472 hdw->hdw_desc->fx2_firmware.cnt,
1473 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1474 if (ret < 0) {
1475 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1476 return ret;
1477 }
1478
d855497e
MI		 1479 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1480
1481 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
9081d901 1482 fwsize = fw_entry->size;
d855497e 1483
9081d901
MI		 1484 if ((fwsize != 0x2000) &&
1485 (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
c21c2db4
MI		 1486 if (hdw->hdw_desc->flag_fx2_16kb) {
1487 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1488 "Wrong fx2 firmware size"
1489 " (expected 8192 or 16384, got %u)",
9081d901 1490 fwsize);
c21c2db4
MI		 1491 } else {
1492 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1493 "Wrong fx2 firmware size"
1494 " (expected 8192, got %u)",
9081d901 1495 fwsize);
c21c2db4 1496 }
d855497e
MI		 1497 release_firmware(fw_entry);
1498 return -ENOMEM;
1499 }
1500
1501 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1502 if (fw_ptr == NULL){
1503 release_firmware(fw_entry);
1504 return -ENOMEM;
1505 }
1506
1507 /* We have to hold the CPU during firmware upload. */
1508 pvr2_hdw_cpureset_assert(hdw,1);
1509
1510 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1511 chunk. */
1512
1513 ret = 0;
9081d901 1514 for (address = 0; address < fwsize; address += 0x800) {
d855497e
MI		 1515 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1516 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1517 0, fw_ptr, 0x800, HZ);
1518 }
1519
1520 trace_firmware("Upload done, releasing device's CPU");
1521
1522 /* Now release the CPU. It will disconnect and reconnect later. */
1523 pvr2_hdw_cpureset_assert(hdw,0);
1524
1525 kfree(fw_ptr);
1526 release_firmware(fw_entry);
1527
1528 trace_firmware("Upload done (%d bytes sent)",ret);
1529
75727460
GF		 1530 /* We should have written fwsize bytes */
1531 if (ret == fwsize) {
d855497e
MI		 1532 hdw->fw1_state = FW1_STATE_RELOAD;
1533 return 0;
1534 }
1535
1536 return -EIO;
1537}
1538
1539
1540/*
1541 * pvr2_upload_firmware2()
1542 *
1543 * This uploads encoder firmware on endpoint 2.
1544 *
1545 */
1546
1547int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1548{
a0fd1cb1 1549 const struct firmware *fw_entry = NULL;
d855497e 1550 void *fw_ptr;
90060d32 1551 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1552 int actual_length;
1553 int ret = 0;
1554 int fwidx;
1555 static const char *fw_files[] = {
1556 CX2341X_FIRM_ENC_FILENAME,
1557 };
1558
989eb154 1559 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1560 return 0;
1561 }
1562
d855497e
MI		 1563 trace_firmware("pvr2_upload_firmware2");
1564
1565 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1566 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1567 if (ret < 0) return ret;
1568 fwidx = ret;
1569 ret = 0;
b30d2441
MI		 1570 /* Since we're about to completely reinitialize the encoder,
1571 invalidate our cached copy of its configuration state. Next
1572 time we configure the encoder, then we'll fully configure it. */
1573 hdw->enc_cur_valid = 0;
d855497e 1574
d913d630
MI		 1575 /* Encoder is about to be reset so note that as far as we're
1576 concerned now, the encoder has never been run. */
1577 del_timer_sync(&hdw->encoder_run_timer);
1578 if (hdw->state_encoder_runok) {
1579 hdw->state_encoder_runok = 0;
1580 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1581 }
1582
d855497e
MI		 1583 /* First prepare firmware loading */
1584 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1585 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1586 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1587 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1588 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1589 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1590 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1591 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1592 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1593 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1594 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1595 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1596 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1597 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1598 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1599 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1c9d10d4
MI		 1600 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1601 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1602
1603 if (ret) {
1604 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1605 "firmware2 upload prep failed, ret=%d",ret);
1606 release_firmware(fw_entry);
21684ba9 1607 goto done;
d855497e
MI		 1608 }
1609
1610 /* Now send firmware */
1611
1612 fw_len = fw_entry->size;
1613
90060d32 1614 if (fw_len % sizeof(u32)) {
d855497e
MI		 1615 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1616 "size of %s firmware"
48dc30a1 1617 " must be a multiple of %zu bytes",
90060d32 1618 fw_files[fwidx],sizeof(u32));
d855497e 1619 release_firmware(fw_entry);
21684ba9
MI		 1620 ret = -EINVAL;
1621 goto done;
d855497e
MI		 1622 }
1623
1624 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1625 if (fw_ptr == NULL){
1626 release_firmware(fw_entry);
1627 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1628 "failed to allocate memory for firmware2 upload");
21684ba9
MI		 1629 ret = -ENOMEM;
1630 goto done;
d855497e
MI		 1631 }
1632
1633 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1634
90060d32
MI		 1635 fw_done = 0;
1636 for (fw_done = 0; fw_done < fw_len;) {
1637 bcnt = fw_len - fw_done;
1638 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1639 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1640 /* Usbsnoop log shows that we must swap bytes... */
5f33df14
MI		 1641 /* Some background info: The data being swapped here is a
1642 firmware image destined for the mpeg encoder chip that
1643 lives at the other end of a USB endpoint. The encoder
1644 chip always talks in 32 bit chunks and its storage is
1645 organized into 32 bit words. However from the file
1646 system to the encoder chip everything is purely a byte
1647 stream. The firmware file's contents are always 32 bit
1648 swapped from what the encoder expects. Thus the need
1649 always exists to swap the bytes regardless of the endian
1650 type of the host processor and therefore swab32() makes
1651 the most sense. */
90060d32 1652 for (icnt = 0; icnt < bcnt/4 ; icnt++)
513edce6 1653 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
90060d32
MI		 1654
1655 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1656 &actual_length, HZ);
90060d32
MI		 1657 ret |= (actual_length != bcnt);
1658 if (ret) break;
1659 fw_done += bcnt;
d855497e
MI		 1660 }
1661
1662 trace_firmware("upload of %s : %i / %i ",
1663 fw_files[fwidx],fw_done,fw_len);
1664
1665 kfree(fw_ptr);
1666 release_firmware(fw_entry);
1667
1668 if (ret) {
1669 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1670 "firmware2 upload transfer failure");
21684ba9 1671 goto done;
d855497e
MI		 1672 }
1673
1674 /* Finish upload */
1675
1676 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1677 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1c9d10d4 1678 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1679
1680 if (ret) {
1681 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1682 "firmware2 upload post-proc failure");
d855497e 1683 }
21684ba9
MI		 1684
1685 done:
1df59f0b
MI		 1686 if (hdw->hdw_desc->signal_routing_scheme ==
1687 PVR2_ROUTING_SCHEME_GOTVIEW) {
1688 /* Ensure that GPIO 11 is set to output for GOTVIEW
1689 hardware. */
1690 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1691 }
d855497e
MI		 1692 return ret;
1693}
1694
1695
681c7399
MI		 1696static const char *pvr2_get_state_name(unsigned int st)
1697{
1698 if (st < ARRAY_SIZE(pvr2_state_names)) {
1699 return pvr2_state_names[st];
d855497e 1700 }
681c7399 1701 return "???";
d855497e
MI		 1702}
1703
681c7399 1704static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1705{
af78e16b
MI		 1706 /* Even though we really only care about the video decoder chip at
1707 this point, we'll broadcast stream on/off to all sub-devices
1708 anyway, just in case somebody else wants to hear the
1709 command... */
e260508d
MI		 1710 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1711 (enablefl ? "on" : "off"));
af78e16b 1712 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
3ccc646b 1713 v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
af78e16b
MI		 1714 if (hdw->decoder_client_id) {
1715 /* We get here if the encoder has been noticed. Otherwise
1716 we'll issue a warning to the user (which should
1717 normally never happen). */
1718 return 0;
1719 }
1720 if (!hdw->flag_decoder_missed) {
1721 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1722 "WARNING: No decoder present");
1723 hdw->flag_decoder_missed = !0;
1724 trace_stbit("flag_decoder_missed",
1725 hdw->flag_decoder_missed);
1726 }
1727 return -EIO;
d855497e
MI		 1728}
1729
1730
681c7399 1731int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1732{
681c7399 1733 return hdw->master_state;
d855497e
MI		 1734}
1735
1736
681c7399 1737static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1738{
681c7399
MI		 1739 if (!hdw->flag_tripped) return 0;
1740 hdw->flag_tripped = 0;
1741 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1742 "Clearing driver error statuss");
1743 return !0;
d855497e
MI		 1744}
1745
1746
681c7399 1747int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1748{
681c7399 1749 int fl;
d855497e 1750 LOCK_TAKE(hdw->big_lock); do {
681c7399 1751 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1752 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1753 if (fl) pvr2_hdw_state_sched(hdw);
1754 return 0;
d855497e
MI		 1755}
1756
1757
d855497e
MI		 1758
1759
1760int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1761{
681c7399 1762 return hdw->state_pipeline_req != 0;
d855497e
MI		 1763}
1764
1765
1766int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1767{
681c7399 1768 int ret,st;
d855497e 1769 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1770 pvr2_hdw_untrip_unlocked(hdw);
1771 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1772 hdw->state_pipeline_req = enable_flag != 0;
1773 pvr2_trace(PVR2_TRACE_START_STOP,
1774 "/*--TRACE_STREAM--*/ %s",
1775 enable_flag ? "enable" : "disable");
1776 }
1777 pvr2_hdw_state_sched(hdw);
d855497e 1778 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1779 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1780 if (enable_flag) {
1781 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1782 if (st != PVR2_STATE_READY) return -EIO;
1783 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1784 }
1785 }
d855497e
MI		 1786 return 0;
1787}
1788
1789
1790int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1791{
681c7399 1792 int fl;
d855497e 1793 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1794 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1795 hdw->desired_stream_type = config;
1796 hdw->state_pipeline_config = 0;
1797 trace_stbit("state_pipeline_config",
1798 hdw->state_pipeline_config);
1799 pvr2_hdw_state_sched(hdw);
1800 }
d855497e 1801 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1802 if (fl) return 0;
1803 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1804}
1805
1806
1807static int get_default_tuner_type(struct pvr2_hdw *hdw)
1808{
1809 int unit_number = hdw->unit_number;
1810 int tp = -1;
1811 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1812 tp = tuner[unit_number];
1813 }
1814 if (tp < 0) return -EINVAL;
1815 hdw->tuner_type = tp;
aaf7884d 1816 hdw->tuner_updated = !0;
d855497e
MI		 1817 return 0;
1818}
1819
1820
1821static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1822{
1823 int unit_number = hdw->unit_number;
1824 int tp = 0;
1825 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1826 tp = video_std[unit_number];
6a540254 1827 if (tp) return tp;
d855497e 1828 }
6a540254 1829 return 0;
d855497e
MI		 1830}
1831
1832
1833static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1834{
1835 int unit_number = hdw->unit_number;
1836 int tp = 0;
1837 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1838 tp = tolerance[unit_number];
1839 }
1840 return tp;
1841}
1842
1843
1844static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1845{
1846 /* Try a harmless request to fetch the eeprom's address over
1847 endpoint 1. See what happens. Only the full FX2 image can
1848 respond to this. If this probe fails then likely the FX2
1849 firmware needs be loaded. */
1850 int result;
1851 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1852 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1853 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1854 hdw->cmd_buffer,1,
1855 hdw->cmd_buffer,1);
1856 if (result < 0) break;
1857 } while(0); LOCK_GIVE(hdw->ctl_lock);
1858 if (result) {
1859 pvr2_trace(PVR2_TRACE_INIT,
1860 "Probe of device endpoint 1 result status %d",
1861 result);
1862 } else {
1863 pvr2_trace(PVR2_TRACE_INIT,
1864 "Probe of device endpoint 1 succeeded");
1865 }
1866 return result == 0;
1867}
1868
9f66d4ea
MI		 1869struct pvr2_std_hack {
1870 v4l2_std_id pat; /* Pattern to match */
1871 v4l2_std_id msk; /* Which bits we care about */
1872 v4l2_std_id std; /* What additional standards or default to set */
1873};
1874
1875/* This data structure labels specific combinations of standards from
1876 tveeprom that we'll try to recognize. If we recognize one, then assume
1877 a specified default standard to use. This is here because tveeprom only
1878 tells us about available standards not the intended default standard (if
1879 any) for the device in question. We guess the default based on what has
1880 been reported as available. Note that this is only for guessing a
1881 default - which can always be overridden explicitly - and if the user
1882 has otherwise named a default then that default will always be used in
1883 place of this table. */
ebff0330 1884static const struct pvr2_std_hack std_eeprom_maps[] = {
9f66d4ea
MI		 1885 { /* PAL(B/G) */
1886 .pat = V4L2_STD_B|V4L2_STD_GH,
1887 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1888 },
1889 { /* NTSC(M) */
1890 .pat = V4L2_STD_MN,
1891 .std = V4L2_STD_NTSC_M,
1892 },
1893 { /* PAL(I) */
1894 .pat = V4L2_STD_PAL_I,
1895 .std = V4L2_STD_PAL_I,
1896 },
1897 { /* SECAM(L/L') */
1898 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1899 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1900 },
1901 { /* PAL(D/D1/K) */
1902 .pat = V4L2_STD_DK,
ea2562d9 1903 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
9f66d4ea
MI		 1904 },
1905};
1906
d855497e
MI		 1907static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1908{
1909 char buf[40];
1910 unsigned int bcnt;
3d290bdb 1911 v4l2_std_id std1,std2,std3;
d855497e
MI		 1912
1913 std1 = get_default_standard(hdw);
3d290bdb 1914 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
d855497e
MI		 1915
1916 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1917 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1918 "Supported video standard(s) reported available"
1919 " in hardware: %.*s",
d855497e
MI		 1920 bcnt,buf);
1921
1922 hdw->std_mask_avail = hdw->std_mask_eeprom;
1923
3d290bdb 1924 std2 = (std1|std3) & ~hdw->std_mask_avail;
d855497e
MI		 1925 if (std2) {
1926 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1927 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1928 "Expanding supported video standards"
1929 " to include: %.*s",
1930 bcnt,buf);
1931 hdw->std_mask_avail |= std2;
1932 }
1933
1934 pvr2_hdw_internal_set_std_avail(hdw);
1935
1936 if (std1) {
1937 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1938 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1939 "Initial video standard forced to %.*s",
1940 bcnt,buf);
1941 hdw->std_mask_cur = std1;
1942 hdw->std_dirty = !0;
1943 pvr2_hdw_internal_find_stdenum(hdw);
1944 return;
1945 }
3d290bdb
MI		 1946 if (std3) {
1947 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1948 pvr2_trace(PVR2_TRACE_STD,
1949 "Initial video standard"
1950 " (determined by device type): %.*s",bcnt,buf);
1951 hdw->std_mask_cur = std3;
1952 hdw->std_dirty = !0;
1953 pvr2_hdw_internal_find_stdenum(hdw);
1954 return;
1955 }
d855497e 1956
9f66d4ea
MI		 1957 {
1958 unsigned int idx;
1959 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1960 if (std_eeprom_maps[idx].msk ?
1961 ((std_eeprom_maps[idx].pat ^
1962 hdw->std_mask_eeprom) &
1963 std_eeprom_maps[idx].msk) :
1964 (std_eeprom_maps[idx].pat !=
1965 hdw->std_mask_eeprom)) continue;
1966 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1967 std_eeprom_maps[idx].std);
56585386 1968 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1969 "Initial video standard guessed as %.*s",
1970 bcnt,buf);
1971 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1972 hdw->std_dirty = !0;
1973 pvr2_hdw_internal_find_stdenum(hdw);
1974 return;
1975 }
1976 }
1977
d855497e
MI		 1978 if (hdw->std_enum_cnt > 1) {
1979 // Autoselect the first listed standard
1980 hdw->std_enum_cur = 1;
1981 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1982 hdw->std_dirty = !0;
56585386 1983 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1984 "Initial video standard auto-selected to %s",
1985 hdw->std_defs[hdw->std_enum_cur-1].name);
1986 return;
1987 }
1988
0885ba1d 1989 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1990 "Unable to select a viable initial video standard");
1991}
1992
1993
e9c64a78
MI		 1994static unsigned int pvr2_copy_i2c_addr_list(
1995 unsigned short *dst, const unsigned char *src,
1996 unsigned int dst_max)
1997{
3ab8d295 1998 unsigned int cnt = 0;
e9c64a78
MI		 1999 if (!src) return 0;
2000 while (src[cnt] && (cnt + 1) < dst_max) {
2001 dst[cnt] = src[cnt];
2002 cnt++;
2003 }
2004 dst[cnt] = I2C_CLIENT_END;
2005 return cnt;
2006}
2007
2008
e17d787c
MI		 2009static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
2010{
2011 /*
2012 Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
2013 for cx25840 causes that module to correctly set up its video
2014 scaling. This is really a problem in the cx25840 module itself,
2015 but we work around it here. The problem has not been seen in
2016 ivtv because there VBI is supported and set up. We don't do VBI
2017 here (at least not yet) and thus we never attempted to even set
2018 it up.
2019 */
2020 struct v4l2_format fmt;
2021 if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
2022 /* We're not using a cx25840 so don't enable the hack */
2023 return;
2024 }
2025
2026 pvr2_trace(PVR2_TRACE_INIT,
2027 "Module ID %u:"
2028 " Executing cx25840 VBI hack",
2029 hdw->decoder_client_id);
2030 memset(&fmt, 0, sizeof(fmt));
2031 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2032 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
09419af3 2033 vbi, s_sliced_fmt, &fmt.fmt.sliced);
e17d787c
MI		 2034}
2035
2036
1ab5e74f
MI		 2037static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
2038 const struct pvr2_device_client_desc *cd)
e9c64a78
MI		 2039{
2040 const char *fname;
2041 unsigned char mid;
2042 struct v4l2_subdev *sd;
2043 unsigned int i2ccnt;
2044 const unsigned char *p;
2045 /* Arbitrary count - max # i2c addresses we will probe */
2046 unsigned short i2caddr[25];
2047
2048 mid = cd->module_id;
2049 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2050 if (!fname) {
2051 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
27108147
MI		 2052 "Module ID %u for device %s has no name?"
2053 " The driver might have a configuration problem.",
e9c64a78
MI		 2054 mid,
2055 hdw->hdw_desc->description);
1ab5e74f 2056 return -EINVAL;
e9c64a78 2057 }
bd14d4f8
MI		 2058 pvr2_trace(PVR2_TRACE_INIT,
2059 "Module ID %u (%s) for device %s being loaded...",
2060 mid, fname,
2061 hdw->hdw_desc->description);
e9c64a78
MI		 2062
2063 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2064 ARRAY_SIZE(i2caddr));
2065 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2066 module_i2c_addresses[mid] : NULL) != NULL)) {
2067 /* Second chance: Try default i2c address list */
2068 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2069 ARRAY_SIZE(i2caddr));
bd14d4f8
MI		 2070 if (i2ccnt) {
2071 pvr2_trace(PVR2_TRACE_INIT,
2072 "Module ID %u:"
2073 " Using default i2c address list",
2074 mid);
2075 }
e9c64a78
MI		 2076 }
2077
2078 if (!i2ccnt) {
2079 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f 2080 "Module ID %u (%s) for device %s:"
27108147
MI		 2081 " No i2c addresses."
2082 " The driver might have a configuration problem.",
1ab5e74f
MI		 2083 mid, fname, hdw->hdw_desc->description);
2084 return -EINVAL;
e9c64a78
MI		 2085 }
2086
e9c64a78 2087 if (i2ccnt == 1) {
bd14d4f8
MI		 2088 pvr2_trace(PVR2_TRACE_INIT,
2089 "Module ID %u:"
2090 " Setting up with specified i2c address 0x%x",
2091 mid, i2caddr[0]);
e6574f2f 2092 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
9a1f8b34 2093 fname, i2caddr[0], NULL);
e9c64a78 2094 } else {
bd14d4f8
MI		 2095 pvr2_trace(PVR2_TRACE_INIT,
2096 "Module ID %u:"
2097 " Setting up with address probe list",
2098 mid);
53dacb15 2099 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
9a1f8b34 2100 fname, 0, i2caddr);
e9c64a78
MI		 2101 }
2102
446dfdc6
MI		 2103 if (!sd) {
2104 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
27108147
MI		 2105 "Module ID %u (%s) for device %s failed to load."
2106 " Possible missing sub-device kernel module or"
2107 " initialization failure within module.",
1ab5e74f
MI		 2108 mid, fname, hdw->hdw_desc->description);
2109 return -EIO;
446dfdc6
MI		 2110 }
2111
2112 /* Tag this sub-device instance with the module ID we know about.
2113 In other places we'll use that tag to determine if the instance
2114 requires special handling. */
2115 sd->grp_id = mid;
2116
bd14d4f8 2117 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
a932f507 2118
e9c64a78 2119
00e5f736
MI		 2120 /* client-specific setup... */
2121 switch (mid) {
2122 case PVR2_CLIENT_ID_CX25840:
00e5f736
MI		 2123 case PVR2_CLIENT_ID_SAA7115:
2124 hdw->decoder_client_id = mid;
2125 break;
2126 default: break;
2127 }
1ab5e74f
MI		 2128
2129 return 0;
e9c64a78
MI		 2130}
2131
2132
2133static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2134{
2135 unsigned int idx;
2136 const struct pvr2_string_table *cm;
2137 const struct pvr2_device_client_table *ct;
1ab5e74f 2138 int okFl = !0;
e9c64a78
MI		 2139
2140 cm = &hdw->hdw_desc->client_modules;
2141 for (idx = 0; idx < cm->cnt; idx++) {
2142 request_module(cm->lst[idx]);
2143 }
2144
2145 ct = &hdw->hdw_desc->client_table;
2146 for (idx = 0; idx < ct->cnt; idx++) {
bd14d4f8 2147 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
e9c64a78 2148 }
27108147
MI		 2149 if (!okFl) {
2150 hdw->flag_modulefail = !0;
2151 pvr2_hdw_render_useless(hdw);
2152 }
e9c64a78
MI		 2153}
2154
2155
d855497e
MI		 2156static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2157{
2158 int ret;
2159 unsigned int idx;
2160 struct pvr2_ctrl *cptr;
2161 int reloadFl = 0;
989eb154 2162 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 2163 if (!reloadFl) {
2164 reloadFl =
2165 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2166 == 0);
2167 if (reloadFl) {
2168 pvr2_trace(PVR2_TRACE_INIT,
2169 "USB endpoint config looks strange"
2170 "; possibly firmware needs to be"
2171 " loaded");
2172 }
d855497e 2173 }
1d643a37
MI		 2174 if (!reloadFl) {
2175 reloadFl = !pvr2_hdw_check_firmware(hdw);
2176 if (reloadFl) {
2177 pvr2_trace(PVR2_TRACE_INIT,
2178 "Check for FX2 firmware failed"
2179 "; possibly firmware needs to be"
2180 " loaded");
2181 }
d855497e 2182 }
1d643a37
MI		 2183 if (reloadFl) {
2184 if (pvr2_upload_firmware1(hdw) != 0) {
2185 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2186 "Failure uploading firmware1");
2187 }
2188 return;
d855497e 2189 }
d855497e
MI		 2190 }
2191 hdw->fw1_state = FW1_STATE_OK;
2192
d855497e
MI		 2193 if (!pvr2_hdw_dev_ok(hdw)) return;
2194
27764726
MI		 2195 hdw->force_dirty = !0;
2196
989eb154 2197 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 2198 pvr2_hdw_cmd_powerup(hdw);
2199 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 2200 }
2201
31335b13 2202 /* Take the IR chip out of reset, if appropriate */
27eab384 2203 if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
31335b13
MI		 2204 pvr2_issue_simple_cmd(hdw,
2205 FX2CMD_HCW_ZILOG_RESET |
2206 (1 << 8) |
2207 ((0) << 16));
2208 }
2209
d855497e
MI		 2210 // This step MUST happen after the earlier powerup step.
2211 pvr2_i2c_core_init(hdw);
2212 if (!pvr2_hdw_dev_ok(hdw)) return;
2213
e9c64a78 2214 pvr2_hdw_load_modules(hdw);
1ab5e74f 2215 if (!pvr2_hdw_dev_ok(hdw)) return;
e9c64a78 2216
cc26b076 2217 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
5c6cb4e2 2218
c05c0462 2219 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 2220 cptr = hdw->controls + idx;
2221 if (cptr->info->skip_init) continue;
2222 if (!cptr->info->set_value) continue;
2223 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2224 }
2225
e17d787c
MI		 2226 pvr2_hdw_cx25840_vbi_hack(hdw);
2227
1bde0289
MI		 2228 /* Set up special default values for the television and radio
2229 frequencies here. It's not really important what these defaults
2230 are, but I set them to something usable in the Chicago area just
2231 to make driver testing a little easier. */
2232
5a4f5da6
MK		 2233 hdw->freqValTelevision = default_tv_freq;
2234 hdw->freqValRadio = default_radio_freq;
1bde0289 2235
d855497e
MI		 2236 // Do not use pvr2_reset_ctl_endpoints() here. It is not
2237 // thread-safe against the normal pvr2_send_request() mechanism.
2238 // (We should make it thread safe).
2239
aaf7884d
MI		 2240 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2241 ret = pvr2_hdw_get_eeprom_addr(hdw);
d855497e 2242 if (!pvr2_hdw_dev_ok(hdw)) return;
aaf7884d
MI		 2243 if (ret < 0) {
2244 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2245 "Unable to determine location of eeprom,"
2246 " skipping");
2247 } else {
2248 hdw->eeprom_addr = ret;
2249 pvr2_eeprom_analyze(hdw);
2250 if (!pvr2_hdw_dev_ok(hdw)) return;
2251 }
2252 } else {
2253 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2254 hdw->tuner_updated = !0;
2255 hdw->std_mask_eeprom = V4L2_STD_ALL;
d855497e
MI		 2256 }
2257
13a88797
MI		 2258 if (hdw->serial_number) {
2259 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2260 "sn-%lu", hdw->serial_number);
2261 } else if (hdw->unit_number >= 0) {
2262 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2263 "unit-%c",
2264 hdw->unit_number + 'a');
2265 } else {
2266 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2267 "unit-??");
2268 }
2269 hdw->identifier[idx] = 0;
2270
d855497e
MI		 2271 pvr2_hdw_setup_std(hdw);
2272
2273 if (!get_default_tuner_type(hdw)) {
2274 pvr2_trace(PVR2_TRACE_INIT,
2275 "pvr2_hdw_setup: Tuner type overridden to %d",
2276 hdw->tuner_type);
2277 }
2278
d855497e
MI		 2279
2280 if (!pvr2_hdw_dev_ok(hdw)) return;
2281
1df59f0b
MI		 2282 if (hdw->hdw_desc->signal_routing_scheme ==
2283 PVR2_ROUTING_SCHEME_GOTVIEW) {
2284 /* Ensure that GPIO 11 is set to output for GOTVIEW
2285 hardware. */
2286 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2287 }
2288
681c7399 2289 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 2290
2291 hdw->vid_stream = pvr2_stream_create();
2292 if (!pvr2_hdw_dev_ok(hdw)) return;
2293 pvr2_trace(PVR2_TRACE_INIT,
2294 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2295 if (hdw->vid_stream) {
2296 idx = get_default_error_tolerance(hdw);
2297 if (idx) {
2298 pvr2_trace(PVR2_TRACE_INIT,
2299 "pvr2_hdw_setup: video stream %p"
2300 " setting tolerance %u",
2301 hdw->vid_stream,idx);
2302 }
2303 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2304 PVR2_VID_ENDPOINT,idx);
2305 }
2306
2307 if (!pvr2_hdw_dev_ok(hdw)) return;
2308
d855497e 2309 hdw->flag_init_ok = !0;
681c7399
MI		 2310
2311 pvr2_hdw_state_sched(hdw);
d855497e
MI		 2312}
2313
2314
681c7399
MI		 2315/* Set up the structure and attempt to put the device into a usable state.
2316 This can be a time-consuming operation, which is why it is not done
2317 internally as part of the create() step. */
2318static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 2319{
2320 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 2321 do {
d855497e
MI		 2322 pvr2_hdw_setup_low(hdw);
2323 pvr2_trace(PVR2_TRACE_INIT,
2324 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 2325 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 2326 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 2327 if (hdw->flag_init_ok) {
d855497e
MI		 2328 pvr2_trace(
2329 PVR2_TRACE_INFO,
2330 "Device initialization"
2331 " completed successfully.");
2332 break;
2333 }
2334 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2335 pvr2_trace(
2336 PVR2_TRACE_INFO,
2337 "Device microcontroller firmware"
2338 " (re)loaded; it should now reset"
2339 " and reconnect.");
2340 break;
2341 }
2342 pvr2_trace(
2343 PVR2_TRACE_ERROR_LEGS,
2344 "Device initialization was not successful.");
2345 if (hdw->fw1_state == FW1_STATE_MISSING) {
2346 pvr2_trace(
2347 PVR2_TRACE_ERROR_LEGS,
2348 "Giving up since device"
2349 " microcontroller firmware"
2350 " appears to be missing.");
2351 break;
2352 }
2353 }
27108147
MI		 2354 if (hdw->flag_modulefail) {
2355 pvr2_trace(
2356 PVR2_TRACE_ERROR_LEGS,
2357 "***WARNING*** pvrusb2 driver initialization"
2358 " failed due to the failure of one or more"
2359 " sub-device kernel modules.");
2360 pvr2_trace(
2361 PVR2_TRACE_ERROR_LEGS,
2362 "You need to resolve the failing condition"
2363 " before this driver can function. There"
2364 " should be some earlier messages giving more"
2365 " information about the problem.");
515ebf79 2366 break;
27108147 2367 }
d855497e
MI		 2368 if (procreload) {
2369 pvr2_trace(
2370 PVR2_TRACE_ERROR_LEGS,
2371 "Attempting pvrusb2 recovery by reloading"
2372 " primary firmware.");
2373 pvr2_trace(
2374 PVR2_TRACE_ERROR_LEGS,
2375 "If this works, device should disconnect"
2376 " and reconnect in a sane state.");
2377 hdw->fw1_state = FW1_STATE_UNKNOWN;
2378 pvr2_upload_firmware1(hdw);
2379 } else {
2380 pvr2_trace(
2381 PVR2_TRACE_ERROR_LEGS,
2382 "***WARNING*** pvrusb2 device hardware"
2383 " appears to be jammed"
2384 " and I can't clear it.");
2385 pvr2_trace(
2386 PVR2_TRACE_ERROR_LEGS,
2387 "You might need to power cycle"
2388 " the pvrusb2 device"
2389 " in order to recover.");
2390 }
681c7399 2391 } while (0);
d855497e 2392 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 2393}
2394
2395
c4a8828d
MI		 2396/* Perform second stage initialization. Set callback pointer first so that
2397 we can avoid a possible initialization race (if the kernel thread runs
2398 before the callback has been set). */
794b1607
MI		 2399int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2400 void (*callback_func)(void *),
2401 void *callback_data)
c4a8828d
MI		 2402{
2403 LOCK_TAKE(hdw->big_lock); do {
97f26ff6
MI		 2404 if (hdw->flag_disconnected) {
2405 /* Handle a race here: If we're already
2406 disconnected by this point, then give up. If we
2407 get past this then we'll remain connected for
2408 the duration of initialization since the entire
2409 initialization sequence is now protected by the
2410 big_lock. */
2411 break;
2412 }
c4a8828d
MI		 2413 hdw->state_data = callback_data;
2414 hdw->state_func = callback_func;
97f26ff6 2415 pvr2_hdw_setup(hdw);
c4a8828d 2416 } while (0); LOCK_GIVE(hdw->big_lock);
794b1607 2417 return hdw->flag_init_ok;
c4a8828d
MI		 2418}
2419
2420
2421/* Create, set up, and return a structure for interacting with the
2422 underlying hardware. */
d855497e
MI		 2423struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2424 const struct usb_device_id *devid)
2425{
7fb20fa3 2426 unsigned int idx,cnt1,cnt2,m;
fe15f136 2427 struct pvr2_hdw *hdw = NULL;
d855497e
MI		 2428 int valid_std_mask;
2429 struct pvr2_ctrl *cptr;
b72b7bf5 2430 struct usb_device *usb_dev;
989eb154 2431 const struct pvr2_device_desc *hdw_desc;
d855497e 2432 __u8 ifnum;
b30d2441
MI		 2433 struct v4l2_queryctrl qctrl;
2434 struct pvr2_ctl_info *ciptr;
d855497e 2435
b72b7bf5
MI		 2436 usb_dev = interface_to_usbdev(intf);
2437
d130fa8a 2438 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
d855497e 2439
fe15f136
MI		 2440 if (hdw_desc == NULL) {
2441 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2442 " No device description pointer,"
2443 " unable to continue.");
2444 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2445 " please contact Mike Isely <isely@pobox.com>"
2446 " to get it included in the driver\n");
2447 goto fail;
2448 }
2449
ca545f7c 2450 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 2451 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 2452 hdw,hdw_desc->description);
e67e376b 2453 pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
00970beb 2454 hdw_desc->description);
8fd04448
MI		 2455 if (hdw_desc->flag_is_experimental) {
2456 pvr2_trace(PVR2_TRACE_INFO, "**********");
2457 pvr2_trace(PVR2_TRACE_INFO,
2458 "WARNING: Support for this device (%s) is"
2459 " experimental.", hdw_desc->description);
2460 pvr2_trace(PVR2_TRACE_INFO,
2461 "Important functionality might not be"
2462 " entirely working.");
2463 pvr2_trace(PVR2_TRACE_INFO,
2464 "Please consider contacting the driver author to"
2465 " help with further stabilization of the driver.");
2466 pvr2_trace(PVR2_TRACE_INFO, "**********");
2467 }
d855497e 2468 if (!hdw) goto fail;
681c7399
MI		 2469
2470 init_timer(&hdw->quiescent_timer);
2471 hdw->quiescent_timer.data = (unsigned long)hdw;
2472 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2473
6e931375
MI		 2474 init_timer(&hdw->decoder_stabilization_timer);
2475 hdw->decoder_stabilization_timer.data = (unsigned long)hdw;
2476 hdw->decoder_stabilization_timer.function =
2477 pvr2_hdw_decoder_stabilization_timeout;
2478
681c7399
MI		 2479 init_timer(&hdw->encoder_wait_timer);
2480 hdw->encoder_wait_timer.data = (unsigned long)hdw;
2481 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2482
d913d630
MI		 2483 init_timer(&hdw->encoder_run_timer);
2484 hdw->encoder_run_timer.data = (unsigned long)hdw;
2485 hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2486
681c7399
MI		 2487 hdw->master_state = PVR2_STATE_DEAD;
2488
2489 init_waitqueue_head(&hdw->state_wait_data);
2490
18103c57 2491 hdw->tuner_signal_stale = !0;
b30d2441 2492 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 2493
7fb20fa3
MI		 2494 /* Calculate which inputs are OK */
2495 m = 0;
2496 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
e8f5bacf
MI		 2497 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2498 m |= 1 << PVR2_CVAL_INPUT_DTV;
2499 }
7fb20fa3
MI		 2500 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2501 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2502 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2503 hdw->input_avail_mask = m;
1cb03b76 2504 hdw->input_allowed_mask = hdw->input_avail_mask;
7fb20fa3 2505
62433e31
MI		 2506 /* If not a hybrid device, pathway_state never changes. So
2507 initialize it here to what it should forever be. */
2508 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2509 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2510 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2511 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2512 }
2513
c05c0462 2514 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 2515 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 2516 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 2517 GFP_KERNEL);
2518 if (!hdw->controls) goto fail;
989eb154 2519 hdw->hdw_desc = hdw_desc;
27eab384 2520 hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
c05c0462
MI		 2521 for (idx = 0; idx < hdw->control_cnt; idx++) {
2522 cptr = hdw->controls + idx;
2523 cptr->hdw = hdw;
2524 }
d855497e
MI		 2525 for (idx = 0; idx < 32; idx++) {
2526 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2527 }
c05c0462 2528 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 2529 cptr = hdw->controls + idx;
d855497e
MI		 2530 cptr->info = control_defs+idx;
2531 }
dbc40a0e
MI		 2532
2533 /* Ensure that default input choice is a valid one. */
2534 m = hdw->input_avail_mask;
2535 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2536 if (!((1 << idx) & m)) continue;
2537 hdw->input_val = idx;
2538 break;
2539 }
2540
b30d2441 2541 /* Define and configure additional controls from cx2341x module. */
ca545f7c 2542 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 2543 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2544 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 2545 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2546 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2547 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2548 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2549 ciptr->name = mpeg_ids[idx].strid;
2550 ciptr->v4l_id = mpeg_ids[idx].id;
2551 ciptr->skip_init = !0;
2552 ciptr->get_value = ctrl_cx2341x_get;
2553 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2554 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2555 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2556 qctrl.id = ciptr->v4l_id;
2557 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2558 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2559 ciptr->set_value = ctrl_cx2341x_set;
2560 }
2561 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2562 PVR2_CTLD_INFO_DESC_SIZE);
2563 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2564 ciptr->default_value = qctrl.default_value;
2565 switch (qctrl.type) {
2566 default:
2567 case V4L2_CTRL_TYPE_INTEGER:
2568 ciptr->type = pvr2_ctl_int;
2569 ciptr->def.type_int.min_value = qctrl.minimum;
2570 ciptr->def.type_int.max_value = qctrl.maximum;
2571 break;
2572 case V4L2_CTRL_TYPE_BOOLEAN:
2573 ciptr->type = pvr2_ctl_bool;
2574 break;
2575 case V4L2_CTRL_TYPE_MENU:
2576 ciptr->type = pvr2_ctl_enum;
2577 ciptr->def.type_enum.value_names =
e0e31cdb
HV		 2578 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2579 ciptr->v4l_id);
b30d2441
MI		 2580 for (cnt1 = 0;
2581 ciptr->def.type_enum.value_names[cnt1] != NULL;
2582 cnt1++) { }
2583 ciptr->def.type_enum.count = cnt1;
2584 break;
2585 }
2586 cptr->info = ciptr;
2587 }
d855497e
MI		 2588
2589 // Initialize video standard enum dynamic control
2590 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2591 if (cptr) {
2592 memcpy(&hdw->std_info_enum,cptr->info,
2593 sizeof(hdw->std_info_enum));
2594 cptr->info = &hdw->std_info_enum;
2595
2596 }
2597 // Initialize control data regarding video standard masks
2598 valid_std_mask = pvr2_std_get_usable();
2599 for (idx = 0; idx < 32; idx++) {
2600 if (!(valid_std_mask & (1 << idx))) continue;
2601 cnt1 = pvr2_std_id_to_str(
2602 hdw->std_mask_names[idx],
2603 sizeof(hdw->std_mask_names[idx])-1,
2604 1 << idx);
2605 hdw->std_mask_names[idx][cnt1] = 0;
2606 }
2607 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2608 if (cptr) {
2609 memcpy(&hdw->std_info_avail,cptr->info,
2610 sizeof(hdw->std_info_avail));
2611 cptr->info = &hdw->std_info_avail;
2612 hdw->std_info_avail.def.type_bitmask.bit_names =
2613 hdw->std_mask_ptrs;
2614 hdw->std_info_avail.def.type_bitmask.valid_bits =
2615 valid_std_mask;
2616 }
2617 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2618 if (cptr) {
2619 memcpy(&hdw->std_info_cur,cptr->info,
2620 sizeof(hdw->std_info_cur));
2621 cptr->info = &hdw->std_info_cur;
2622 hdw->std_info_cur.def.type_bitmask.bit_names =
2623 hdw->std_mask_ptrs;
2624 hdw->std_info_avail.def.type_bitmask.valid_bits =
2625 valid_std_mask;
2626 }
2627
432907f7 2628 hdw->cropcap_stale = !0;
d855497e
MI		 2629 hdw->eeprom_addr = -1;
2630 hdw->unit_number = -1;
8079384e
MI		 2631 hdw->v4l_minor_number_video = -1;
2632 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 2633 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 2634 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2635 if (!hdw->ctl_write_buffer) goto fail;
2636 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2637 if (!hdw->ctl_read_buffer) goto fail;
2638 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2639 if (!hdw->ctl_write_urb) goto fail;
2640 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2641 if (!hdw->ctl_read_urb) goto fail;
2642
70ad6383 2643 if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
b72b7bf5
MI		 2644 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2645 "Error registering with v4l core, giving up");
2646 goto fail;
2647 }
8df0c87c 2648 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2649 for (idx = 0; idx < PVR_NUM; idx++) {
2650 if (unit_pointers[idx]) continue;
2651 hdw->unit_number = idx;
2652 unit_pointers[idx] = hdw;
2653 break;
2654 }
8df0c87c 2655 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 2656
2657 cnt1 = 0;
2658 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2659 cnt1 += cnt2;
2660 if (hdw->unit_number >= 0) {
2661 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2662 ('a' + hdw->unit_number));
2663 cnt1 += cnt2;
2664 }
2665 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2666 hdw->name[cnt1] = 0;
2667
681c7399
MI		 2668 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2669 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
681c7399 2670
d855497e
MI		 2671 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2672 hdw->unit_number,hdw->name);
2673
2674 hdw->tuner_type = -1;
2675 hdw->flag_ok = !0;
d855497e
MI		 2676
2677 hdw->usb_intf = intf;
b72b7bf5 2678 hdw->usb_dev = usb_dev;
d855497e 2679
87e3495c 2680 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
31a18547 2681
d855497e
MI		 2682 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2683 usb_set_interface(hdw->usb_dev,ifnum,0);
2684
2685 mutex_init(&hdw->ctl_lock_mutex);
2686 mutex_init(&hdw->big_lock_mutex);
2687
2688 return hdw;
2689 fail:
2690 if (hdw) {
681c7399 2691 del_timer_sync(&hdw->quiescent_timer);
6e931375 2692 del_timer_sync(&hdw->decoder_stabilization_timer);
d913d630 2693 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 2694 del_timer_sync(&hdw->encoder_wait_timer);
2695 if (hdw->workqueue) {
2696 flush_workqueue(hdw->workqueue);
2697 destroy_workqueue(hdw->workqueue);
2698 hdw->workqueue = NULL;
2699 }
5e55d2ce
MK		 2700 usb_free_urb(hdw->ctl_read_urb);
2701 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2702 kfree(hdw->ctl_read_buffer);
2703 kfree(hdw->ctl_write_buffer);
2704 kfree(hdw->controls);
2705 kfree(hdw->mpeg_ctrl_info);
681c7399
MI		 2706 kfree(hdw->std_defs);
2707 kfree(hdw->std_enum_names);
d855497e
MI		 2708 kfree(hdw);
2709 }
a0fd1cb1 2710 return NULL;
d855497e
MI		 2711}
2712
2713
2714/* Remove _all_ associations between this driver and the underlying USB
2715 layer. */
07e337ee 2716static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2717{
2718 if (hdw->flag_disconnected) return;
2719 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2720 if (hdw->ctl_read_urb) {
2721 usb_kill_urb(hdw->ctl_read_urb);
2722 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2723 hdw->ctl_read_urb = NULL;
d855497e
MI		 2724 }
2725 if (hdw->ctl_write_urb) {
2726 usb_kill_urb(hdw->ctl_write_urb);
2727 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2728 hdw->ctl_write_urb = NULL;
d855497e
MI		 2729 }
2730 if (hdw->ctl_read_buffer) {
2731 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2732 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2733 }
2734 if (hdw->ctl_write_buffer) {
2735 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2736 hdw->ctl_write_buffer = NULL;
d855497e 2737 }
d855497e 2738 hdw->flag_disconnected = !0;
b72b7bf5
MI		 2739 /* If we don't do this, then there will be a dangling struct device
2740 reference to our disappearing device persisting inside the V4L
2741 core... */
dc070bcc 2742 v4l2_device_disconnect(&hdw->v4l2_dev);
a0fd1cb1
MI		 2743 hdw->usb_dev = NULL;
2744 hdw->usb_intf = NULL;
681c7399 2745 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2746}
2747
2748
2749/* Destroy hardware interaction structure */
2750void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2751{
401c27ce 2752 if (!hdw) return;
d855497e 2753 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2754 if (hdw->workqueue) {
2755 flush_workqueue(hdw->workqueue);
2756 destroy_workqueue(hdw->workqueue);
2757 hdw->workqueue = NULL;
2758 }
8f59100a 2759 del_timer_sync(&hdw->quiescent_timer);
6e931375 2760 del_timer_sync(&hdw->decoder_stabilization_timer);
d913d630 2761 del_timer_sync(&hdw->encoder_run_timer);
8f59100a 2762 del_timer_sync(&hdw->encoder_wait_timer);
d855497e
MI		 2763 if (hdw->fw_buffer) {
2764 kfree(hdw->fw_buffer);
a0fd1cb1 2765 hdw->fw_buffer = NULL;
d855497e
MI		 2766 }
2767 if (hdw->vid_stream) {
2768 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2769 hdw->vid_stream = NULL;
d855497e 2770 }
d855497e 2771 pvr2_i2c_core_done(hdw);
b72b7bf5 2772 v4l2_device_unregister(&hdw->v4l2_dev);
d855497e 2773 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2774 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2775 if ((hdw->unit_number >= 0) &&
2776 (hdw->unit_number < PVR_NUM) &&
2777 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2778 unit_pointers[hdw->unit_number] = NULL;
d855497e 2779 }
8df0c87c 2780 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2781 kfree(hdw->controls);
2782 kfree(hdw->mpeg_ctrl_info);
2783 kfree(hdw->std_defs);
2784 kfree(hdw->std_enum_names);
d855497e
MI		 2785 kfree(hdw);
2786}
2787
2788
d855497e
MI		 2789int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2790{
2791 return (hdw && hdw->flag_ok);
2792}
2793
2794
2795/* Called when hardware has been unplugged */
2796void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2797{
2798 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2799 LOCK_TAKE(hdw->big_lock);
2800 LOCK_TAKE(hdw->ctl_lock);
2801 pvr2_hdw_remove_usb_stuff(hdw);
2802 LOCK_GIVE(hdw->ctl_lock);
2803 LOCK_GIVE(hdw->big_lock);
2804}
2805
2806
2807// Attempt to autoselect an appropriate value for std_enum_cur given
2808// whatever is currently in std_mask_cur
07e337ee 2809static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2810{
2811 unsigned int idx;
2812 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2813 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2814 hdw->std_enum_cur = idx;
2815 return;
2816 }
2817 }
2818 hdw->std_enum_cur = 0;
2819}
2820
2821
2822// Calculate correct set of enumerated standards based on currently known
2823// set of available standards bits.
07e337ee 2824static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2825{
2826 struct v4l2_standard *newstd;
2827 unsigned int std_cnt;
2828 unsigned int idx;
2829
2830 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2831
2832 if (hdw->std_defs) {
2833 kfree(hdw->std_defs);
a0fd1cb1 2834 hdw->std_defs = NULL;
d855497e
MI		 2835 }
2836 hdw->std_enum_cnt = 0;
2837 if (hdw->std_enum_names) {
2838 kfree(hdw->std_enum_names);
a0fd1cb1 2839 hdw->std_enum_names = NULL;
d855497e
MI		 2840 }
2841
2842 if (!std_cnt) {
2843 pvr2_trace(
2844 PVR2_TRACE_ERROR_LEGS,
2845 "WARNING: Failed to identify any viable standards");
2846 }
2847 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2848 hdw->std_enum_names[0] = "none";
2849 for (idx = 0; idx < std_cnt; idx++) {
2850 hdw->std_enum_names[idx+1] =
2851 newstd[idx].name;
2852 }
2853 // Set up the dynamic control for this standard
2854 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2855 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2856 hdw->std_defs = newstd;
2857 hdw->std_enum_cnt = std_cnt+1;
2858 hdw->std_enum_cur = 0;
2859 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2860}
2861
2862
2863int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2864 struct v4l2_standard *std,
2865 unsigned int idx)
2866{
2867 int ret = -EINVAL;
2868 if (!idx) return ret;
2869 LOCK_TAKE(hdw->big_lock); do {
2870 if (idx >= hdw->std_enum_cnt) break;
2871 idx--;
2872 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2873 ret = 0;
2874 } while (0); LOCK_GIVE(hdw->big_lock);
2875 return ret;
2876}
2877
2878
2879/* Get the number of defined controls */
2880unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2881{
c05c0462 2882 return hdw->control_cnt;
d855497e
MI		 2883}
2884
2885
2886/* Retrieve a control handle given its index (0..count-1) */
2887struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2888 unsigned int idx)
2889{
a0fd1cb1 2890 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2891 return hdw->controls + idx;
2892}
2893
2894
2895/* Retrieve a control handle given its index (0..count-1) */
2896struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2897 unsigned int ctl_id)
2898{
2899 struct pvr2_ctrl *cptr;
2900 unsigned int idx;
2901 int i;
2902
2903 /* This could be made a lot more efficient, but for now... */
c05c0462 2904 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2905 cptr = hdw->controls + idx;
2906 i = cptr->info->internal_id;
2907 if (i && (i == ctl_id)) return cptr;
2908 }
a0fd1cb1 2909 return NULL;
d855497e
MI		 2910}
2911
2912
a761f431 2913/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2914struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2915{
2916 struct pvr2_ctrl *cptr;
2917 unsigned int idx;
2918 int i;
2919
2920 /* This could be made a lot more efficient, but for now... */
c05c0462 2921 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2922 cptr = hdw->controls + idx;
2923 i = cptr->info->v4l_id;
2924 if (i && (i == ctl_id)) return cptr;
2925 }
a0fd1cb1 2926 return NULL;
d855497e
MI		 2927}
2928
2929
a761f431
MI		 2930/* Given a V4L ID for its immediate predecessor, retrieve the control
2931 structure associated with it. */
2932struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2933 unsigned int ctl_id)
2934{
2935 struct pvr2_ctrl *cptr,*cp2;
2936 unsigned int idx;
2937 int i;
2938
2939 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2940 cp2 = NULL;
a761f431
MI		 2941 for (idx = 0; idx < hdw->control_cnt; idx++) {
2942 cptr = hdw->controls + idx;
2943 i = cptr->info->v4l_id;
2944 if (!i) continue;
2945 if (i <= ctl_id) continue;
2946 if (cp2 && (cp2->info->v4l_id < i)) continue;
2947 cp2 = cptr;
2948 }
2949 return cp2;
a0fd1cb1 2950 return NULL;
a761f431
MI		 2951}
2952
2953
d855497e
MI		 2954static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2955{
2956 switch (tp) {
2957 case pvr2_ctl_int: return "integer";
2958 case pvr2_ctl_enum: return "enum";
33213963 2959 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2960 case pvr2_ctl_bitmask: return "bitmask";
2961 }
2962 return "";
2963}
2964
2965
2641df36
MI		 2966static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2967 const char *name, int val)
2968{
2969 struct v4l2_control ctrl;
2970 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2971 memset(&ctrl, 0, sizeof(ctrl));
2972 ctrl.id = id;
2973 ctrl.value = val;
2974 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2975}
2976
2977#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
27764726 2978 if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \
2641df36
MI		 2979 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2980 }
2981
5ceaad14 2982/* Execute whatever commands are required to update the state of all the
2641df36 2983 sub-devices so that they match our current control values. */
5ceaad14
MI		 2984static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2985{
edb9dcb8
MI		 2986 struct v4l2_subdev *sd;
2987 unsigned int id;
2988 pvr2_subdev_update_func fp;
2989
75212a02
MI		 2990 pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2991
27764726 2992 if (hdw->tuner_updated || hdw->force_dirty) {
75212a02
MI		 2993 struct tuner_setup setup;
2994 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2995 hdw->tuner_type);
2996 if (((int)(hdw->tuner_type)) >= 0) {
fcd62cf7 2997 memset(&setup, 0, sizeof(setup));
75212a02
MI		 2998 setup.addr = ADDR_UNSET;
2999 setup.type = hdw->tuner_type;
3000 setup.mode_mask = T_RADIO | T_ANALOG_TV;
3001 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3002 tuner, s_type_addr, &setup);
3003 }
3004 }
3005
27764726 3006 if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
b481880b 3007 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2641df36
MI		 3008 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3009 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3010 tuner, s_radio);
3011 } else {
3012 v4l2_std_id vs;
3013 vs = hdw->std_mask_cur;
3014 v4l2_device_call_all(&hdw->v4l2_dev, 0,
f41737ec 3015 core, s_std, vs);
a6862da2 3016 pvr2_hdw_cx25840_vbi_hack(hdw);
2641df36
MI		 3017 }
3018 hdw->tuner_signal_stale = !0;
3019 hdw->cropcap_stale = !0;
3020 }
3021
3022 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
3023 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
3024 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
3025 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
3026 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
3027 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
3028 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
3029 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
3030 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
3031
27764726 3032 if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2641df36
MI		 3033 struct v4l2_tuner vt;
3034 memset(&vt, 0, sizeof(vt));
3035 vt.audmode = hdw->audiomode_val;
3036 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
3037 }
3038
27764726 3039 if (hdw->freqDirty || hdw->force_dirty) {
2641df36
MI		 3040 unsigned long fv;
3041 struct v4l2_frequency freq;
3042 fv = pvr2_hdw_get_cur_freq(hdw);
3043 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
3044 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
3045 memset(&freq, 0, sizeof(freq));
3046 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
3047 /* ((fv * 1000) / 62500) */
3048 freq.frequency = (fv * 2) / 125;
3049 } else {
3050 freq.frequency = fv / 62500;
3051 }
3052 /* tuner-core currently doesn't seem to care about this, but
3053 let's set it anyway for completeness. */
3054 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3055 freq.type = V4L2_TUNER_RADIO;
3056 } else {
3057 freq.type = V4L2_TUNER_ANALOG_TV;
3058 }
3059 freq.tuner = 0;
3060 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
3061 s_frequency, &freq);
3062 }
3063
27764726 3064 if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
fa190ee9 3065 struct v4l2_mbus_framefmt fmt;
2641df36 3066 memset(&fmt, 0, sizeof(fmt));
fa190ee9
HV		 3067 fmt.width = hdw->res_hor_val;
3068 fmt.height = hdw->res_ver_val;
3069 fmt.code = V4L2_MBUS_FMT_FIXED;
7dfdf1ee 3070 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
fa190ee9
HV		 3071 fmt.width, fmt.height);
3072 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_mbus_fmt, &fmt);
2641df36
MI		 3073 }
3074
27764726 3075 if (hdw->srate_dirty || hdw->force_dirty) {
01c59df8
MI		 3076 u32 val;
3077 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3078 hdw->srate_val);
3079 switch (hdw->srate_val) {
3080 default:
3081 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3082 val = 48000;
3083 break;
3084 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3085 val = 44100;
3086 break;
3087 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3088 val = 32000;
3089 break;
3090 }
3091 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3092 audio, s_clock_freq, val);
3093 }
3094
2641df36
MI		 3095 /* Unable to set crop parameters; there is apparently no equivalent
3096 for VIDIOC_S_CROP */
3097
edb9dcb8
MI		 3098 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3099 id = sd->grp_id;
3100 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3101 fp = pvr2_module_update_functions[id];
3102 if (!fp) continue;
3103 (*fp)(hdw, sd);
3104 }
2641df36 3105
27764726 3106 if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
2641df36
MI		 3107 pvr2_hdw_status_poll(hdw);
3108 }
5ceaad14
MI		 3109}
3110
3111
681c7399
MI		 3112/* Figure out if we need to commit control changes. If so, mark internal
3113 state flags to indicate this fact and return true. Otherwise do nothing
3114 else and return false. */
3115static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 3116{
d855497e
MI		 3117 unsigned int idx;
3118 struct pvr2_ctrl *cptr;
3119 int value;
27764726 3120 int commit_flag = hdw->force_dirty;
d855497e
MI		 3121 char buf[100];
3122 unsigned int bcnt,ccnt;
3123
c05c0462 3124 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e 3125 cptr = hdw->controls + idx;
5fa1247a 3126 if (!cptr->info->is_dirty) continue;
d855497e 3127 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 3128 commit_flag = !0;
d855497e 3129
fe23a280 3130 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 3131 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3132 cptr->info->name);
3133 value = 0;
3134 cptr->info->get_value(cptr,&value);
3135 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3136 buf+bcnt,
3137 sizeof(buf)-bcnt,&ccnt);
3138 bcnt += ccnt;
3139 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3140 get_ctrl_typename(cptr->info->type));
3141 pvr2_trace(PVR2_TRACE_CTL,
3142 "/*--TRACE_COMMIT--*/ %.*s",
3143 bcnt,buf);
3144 }
3145
3146 if (!commit_flag) {
3147 /* Nothing has changed */
3148 return 0;
3149 }
3150
681c7399
MI		 3151 hdw->state_pipeline_config = 0;
3152 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3153 pvr2_hdw_state_sched(hdw);
3154
3155 return !0;
3156}
3157
3158
3159/* Perform all operations needed to commit all control changes. This must
3160 be performed in synchronization with the pipeline state and is thus
3161 expected to be called as part of the driver's worker thread. Return
3162 true if commit successful, otherwise return false to indicate that
3163 commit isn't possible at this time. */
3164static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3165{
3166 unsigned int idx;
3167 struct pvr2_ctrl *cptr;
3168 int disruptive_change;
3169
9bf98321
MI		 3170 if (hdw->input_dirty && hdw->state_pathway_ok &&
3171 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3172 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3173 hdw->pathway_state)) {
3174 /* Change of mode being asked for... */
3175 hdw->state_pathway_ok = 0;
3176 trace_stbit("state_pathway_ok", hdw->state_pathway_ok);
3177 }
3178 if (!hdw->state_pathway_ok) {
3179 /* Can't commit anything until pathway is ok. */
3180 return 0;
3181 }
3182
ab062fe3
MI		 3183 /* Handle some required side effects when the video standard is
3184 changed.... */
d855497e 3185 if (hdw->std_dirty) {
d855497e 3186 int nvres;
00528d9c 3187 int gop_size;
d855497e
MI		 3188 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3189 nvres = 480;
00528d9c 3190 gop_size = 15;
d855497e
MI		 3191 } else {
3192 nvres = 576;
00528d9c 3193 gop_size = 12;
d855497e 3194 }
00528d9c
MI		 3195 /* Rewrite the vertical resolution to be appropriate to the
3196 video standard that has been selected. */
d855497e
MI		 3197 if (nvres != hdw->res_ver_val) {
3198 hdw->res_ver_val = nvres;
3199 hdw->res_ver_dirty = !0;
3200 }
00528d9c
MI		 3201 /* Rewrite the GOP size to be appropriate to the video
3202 standard that has been selected. */
3203 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3204 struct v4l2_ext_controls cs;
3205 struct v4l2_ext_control c1;
3206 memset(&cs, 0, sizeof(cs));
3207 memset(&c1, 0, sizeof(c1));
3208 cs.controls = &c1;
3209 cs.count = 1;
3210 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3211 c1.value = gop_size;
3212 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3213 VIDIOC_S_EXT_CTRLS);
3214 }
d855497e
MI		 3215 }
3216
e784bfb9 3217 /* The broadcast decoder can only scale down, so if
3218 * res_*_dirty && crop window < output format ==> enlarge crop.
3219 *
3220 * The mpeg encoder receives fields of res_hor_val dots and
3221 * res_ver_val halflines. Limits: hor<=720, ver<=576.
3222 */
3223 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3224 hdw->cropw_val = hdw->res_hor_val;
3225 hdw->cropw_dirty = !0;
3226 } else if (hdw->cropw_dirty) {
3227 hdw->res_hor_dirty = !0; /* must rescale */
3228 hdw->res_hor_val = min(720, hdw->cropw_val);
3229 }
3230 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3231 hdw->croph_val = hdw->res_ver_val;
3232 hdw->croph_dirty = !0;
3233 } else if (hdw->croph_dirty) {
3234 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3235 hdw->res_ver_dirty = !0;
3236 hdw->res_ver_val = min(nvres, hdw->croph_val);
3237 }
3238
681c7399
MI		 3239 /* If any of the below has changed, then we can't do the update
3240 while the pipeline is running. Pipeline must be paused first
3241 and decoder -> encoder connection be made quiescent before we
3242 can proceed. */
3243 disruptive_change =
3244 (hdw->std_dirty ||
3245 hdw->enc_unsafe_stale ||
3246 hdw->srate_dirty ||
3247 hdw->res_ver_dirty ||
3248 hdw->res_hor_dirty ||
755879c6
MI		 3249 hdw->cropw_dirty ||
3250 hdw->croph_dirty ||
681c7399
MI		 3251 hdw->input_dirty ||
3252 (hdw->active_stream_type != hdw->desired_stream_type));
3253 if (disruptive_change && !hdw->state_pipeline_idle) {
3254 /* Pipeline is not idle; we can't proceed. Arrange to
3255 cause pipeline to stop so that we can try this again
3256 later.... */
3257 hdw->state_pipeline_pause = !0;
3258 return 0;
275b2e28
PK		 3259 }
3260
b30d2441
MI		 3261 if (hdw->srate_dirty) {
3262 /* Write new sample rate into control structure since
3263 * the master copy is stale. We must track srate
3264 * separate from the mpeg control structure because
3265 * other logic also uses this value. */
3266 struct v4l2_ext_controls cs;
3267 struct v4l2_ext_control c1;
3268 memset(&cs,0,sizeof(cs));
3269 memset(&c1,0,sizeof(c1));
3270 cs.controls = &c1;
3271 cs.count = 1;
3272 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3273 c1.value = hdw->srate_val;
01f1e44f 3274 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 3275 }
c05c0462 3276
681c7399
MI		 3277 if (hdw->active_stream_type != hdw->desired_stream_type) {
3278 /* Handle any side effects of stream config here */
3279 hdw->active_stream_type = hdw->desired_stream_type;
3280 }
3281
1df59f0b
MI		 3282 if (hdw->hdw_desc->signal_routing_scheme ==
3283 PVR2_ROUTING_SCHEME_GOTVIEW) {
3284 u32 b;
3285 /* Handle GOTVIEW audio switching */
3286 pvr2_hdw_gpio_get_out(hdw,&b);
3287 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3288 /* Set GPIO 11 */
3289 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3290 } else {
3291 /* Clear GPIO 11 */
3292 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3293 }
3294 }
3295
e68a619a
MI		 3296 /* Check and update state for all sub-devices. */
3297 pvr2_subdev_update(hdw);
3298
75212a02 3299 hdw->tuner_updated = 0;
27764726 3300 hdw->force_dirty = 0;
5ceaad14
MI		 3301 for (idx = 0; idx < hdw->control_cnt; idx++) {
3302 cptr = hdw->controls + idx;
3303 if (!cptr->info->clear_dirty) continue;
3304 cptr->info->clear_dirty(cptr);
3305 }
3306
62433e31
MI		 3307 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3308 hdw->state_encoder_run) {
3309 /* If encoder isn't running or it can't be touched, then
3310 this will get worked out later when we start the
3311 encoder. */
681c7399
MI		 3312 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3313 }
d855497e 3314
681c7399 3315 hdw->state_pipeline_config = !0;
432907f7
MI		 3316 /* Hardware state may have changed in a way to cause the cropping
3317 capabilities to have changed. So mark it stale, which will
3318 cause a later re-fetch. */
681c7399
MI		 3319 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3320 return !0;
d855497e
MI		 3321}
3322
3323
3324int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3325{
681c7399
MI		 3326 int fl;
3327 LOCK_TAKE(hdw->big_lock);
3328 fl = pvr2_hdw_commit_setup(hdw);
3329 LOCK_GIVE(hdw->big_lock);
3330 if (!fl) return 0;
3331 return pvr2_hdw_wait(hdw,0);
3332}
3333
3334
681c7399 3335static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 3336{
681c7399
MI		 3337 int fl = 0;
3338 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 3339 LOCK_TAKE(hdw->big_lock); do {
681c7399 3340 fl = pvr2_hdw_state_eval(hdw);
d855497e 3341 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 3342 if (fl && hdw->state_func) {
3343 hdw->state_func(hdw->state_data);
3344 }
d855497e
MI		 3345}
3346
3347
681c7399 3348static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 3349{
681c7399
MI		 3350 return wait_event_interruptible(
3351 hdw->state_wait_data,
3352 (hdw->state_stale == 0) &&
3353 (!state || (hdw->master_state != state)));
3354}
3355
3356
d855497e
MI		 3357/* Return name for this driver instance */
3358const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3359{
3360 return hdw->name;
3361}
3362
3363
78a47101
MI		 3364const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3365{
3366 return hdw->hdw_desc->description;
3367}
3368
3369
3370const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3371{
3372 return hdw->hdw_desc->shortname;
3373}
3374
3375
d855497e
MI		 3376int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3377{
3378 int result;
3379 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3380 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 3381 result = pvr2_send_request(hdw,
3382 hdw->cmd_buffer,1,
3383 hdw->cmd_buffer,1);
3384 if (result < 0) break;
3385 result = (hdw->cmd_buffer[0] != 0);
3386 } while(0); LOCK_GIVE(hdw->ctl_lock);
3387 return result;
3388}
3389
3390
18103c57
MI		 3391/* Execute poll of tuner status */
3392void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 3393{
d855497e 3394 LOCK_TAKE(hdw->big_lock); do {
a51f5000 3395 pvr2_hdw_status_poll(hdw);
d855497e 3396 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 3397}
3398
3399
432907f7
MI		 3400static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3401{
3402 if (!hdw->cropcap_stale) {
432907f7
MI		 3403 return 0;
3404 }
a51f5000 3405 pvr2_hdw_status_poll(hdw);
432907f7 3406 if (hdw->cropcap_stale) {
432907f7
MI		 3407 return -EIO;
3408 }
3409 return 0;
3410}
3411
3412
3413/* Return information about cropping capabilities */
3414int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3415{
3416 int stat = 0;
3417 LOCK_TAKE(hdw->big_lock);
3418 stat = pvr2_hdw_check_cropcap(hdw);
3419 if (!stat) {
432907f7
MI		 3420 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3421 }
3422 LOCK_GIVE(hdw->big_lock);
3423 return stat;
3424}
3425
3426
18103c57
MI		 3427/* Return information about the tuner */
3428int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3429{
3430 LOCK_TAKE(hdw->big_lock); do {
3431 if (hdw->tuner_signal_stale) {
a51f5000 3432 pvr2_hdw_status_poll(hdw);
18103c57
MI		 3433 }
3434 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3435 } while (0); LOCK_GIVE(hdw->big_lock);
3436 return 0;
d855497e
MI		 3437}
3438
3439
3440/* Get handle to video output stream */
3441struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3442{
3443 return hp->vid_stream;
3444}
3445
3446
3447void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3448{
4f1a3e5b 3449 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e 3450 LOCK_TAKE(hdw->big_lock); do {
4f1a3e5b 3451 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
ed3261a8 3452 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
b30d2441 3453 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 3454 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 3455 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 3456 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 3457 } while (0); LOCK_GIVE(hdw->big_lock);
3458}
3459
4db666cc
MI		 3460
3461/* Grab EEPROM contents, needed for direct method. */
3462#define EEPROM_SIZE 8192
3463#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3464static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3465{
3466 struct i2c_msg msg[2];
3467 u8 *eeprom;
3468 u8 iadd[2];
3469 u8 addr;
3470 u16 eepromSize;
3471 unsigned int offs;
3472 int ret;
3473 int mode16 = 0;
3474 unsigned pcnt,tcnt;
3475 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3476 if (!eeprom) {
3477 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3478 "Failed to allocate memory"
3479 " required to read eeprom");
3480 return NULL;
3481 }
3482
3483 trace_eeprom("Value for eeprom addr from controller was 0x%x",
3484 hdw->eeprom_addr);
3485 addr = hdw->eeprom_addr;
3486 /* Seems that if the high bit is set, then the *real* eeprom
3487 address is shifted right now bit position (noticed this in
3488 newer PVR USB2 hardware) */
3489 if (addr & 0x80) addr >>= 1;
3490
3491 /* FX2 documentation states that a 16bit-addressed eeprom is
3492 expected if the I2C address is an odd number (yeah, this is
3493 strange but it's what they do) */
3494 mode16 = (addr & 1);
3495 eepromSize = (mode16 ? EEPROM_SIZE : 256);
3496 trace_eeprom("Examining %d byte eeprom at location 0x%x"
3497 " using %d bit addressing",eepromSize,addr,
3498 mode16 ? 16 : 8);
3499
3500 msg[0].addr = addr;
3501 msg[0].flags = 0;
3502 msg[0].len = mode16 ? 2 : 1;
3503 msg[0].buf = iadd;
3504 msg[1].addr = addr;
3505 msg[1].flags = I2C_M_RD;
3506
3507 /* We have to do the actual eeprom data fetch ourselves, because
3508 (1) we're only fetching part of the eeprom, and (2) if we were
3509 getting the whole thing our I2C driver can't grab it in one
3510 pass - which is what tveeprom is otherwise going to attempt */
3511 memset(eeprom,0,EEPROM_SIZE);
3512 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3513 pcnt = 16;
3514 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3515 offs = tcnt + (eepromSize - EEPROM_SIZE);
3516 if (mode16) {
3517 iadd[0] = offs >> 8;
3518 iadd[1] = offs;
3519 } else {
3520 iadd[0] = offs;
3521 }
3522 msg[1].len = pcnt;
3523 msg[1].buf = eeprom+tcnt;
3524 if ((ret = i2c_transfer(&hdw->i2c_adap,
3525 msg,ARRAY_SIZE(msg))) != 2) {
3526 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3527 "eeprom fetch set offs err=%d",ret);
3528 kfree(eeprom);
3529 return NULL;
3530 }
3531 }
3532 return eeprom;
3533}
3534
3535
3536void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
568efaa2 3537 int mode,
4db666cc 3538 int enable_flag)
d855497e
MI		 3539{
3540 int ret;
3541 u16 address;
3542 unsigned int pipe;
3543 LOCK_TAKE(hdw->big_lock); do {
5fa1247a 3544 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
d855497e
MI		 3545
3546 if (!enable_flag) {
3547 pvr2_trace(PVR2_TRACE_FIRMWARE,
3548 "Cleaning up after CPU firmware fetch");
3549 kfree(hdw->fw_buffer);
a0fd1cb1 3550 hdw->fw_buffer = NULL;
d855497e 3551 hdw->fw_size = 0;
4db666cc
MI		 3552 if (hdw->fw_cpu_flag) {
3553 /* Now release the CPU. It will disconnect
3554 and reconnect later. */
3555 pvr2_hdw_cpureset_assert(hdw,0);
3556 }
d855497e
MI		 3557 break;
3558 }
3559
568efaa2 3560 hdw->fw_cpu_flag = (mode != 2);
4db666cc 3561 if (hdw->fw_cpu_flag) {
568efaa2 3562 hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
4db666cc 3563 pvr2_trace(PVR2_TRACE_FIRMWARE,
568efaa2
MI		 3564 "Preparing to suck out CPU firmware"
3565 " (size=%u)", hdw->fw_size);
4db666cc
MI		 3566 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3567 if (!hdw->fw_buffer) {
3568 hdw->fw_size = 0;
3569 break;
3570 }
d855497e 3571
4db666cc
MI		 3572 /* We have to hold the CPU during firmware upload. */
3573 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 3574
4db666cc
MI		 3575 /* download the firmware from address 0000-1fff in 2048
3576 (=0x800) bytes chunk. */
d855497e 3577
4db666cc
MI		 3578 pvr2_trace(PVR2_TRACE_FIRMWARE,
3579 "Grabbing CPU firmware");
3580 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3581 for(address = 0; address < hdw->fw_size;
3582 address += 0x800) {
3583 ret = usb_control_msg(hdw->usb_dev,pipe,
3584 0xa0,0xc0,
3585 address,0,
3586 hdw->fw_buffer+address,
3587 0x800,HZ);
3588 if (ret < 0) break;
3589 }
d855497e 3590
4db666cc
MI		 3591 pvr2_trace(PVR2_TRACE_FIRMWARE,
3592 "Done grabbing CPU firmware");
3593 } else {
3594 pvr2_trace(PVR2_TRACE_FIRMWARE,
3595 "Sucking down EEPROM contents");
3596 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3597 if (!hdw->fw_buffer) {
3598 pvr2_trace(PVR2_TRACE_FIRMWARE,
3599 "EEPROM content suck failed.");
3600 break;
3601 }
3602 hdw->fw_size = EEPROM_SIZE;
3603 pvr2_trace(PVR2_TRACE_FIRMWARE,
3604 "Done sucking down EEPROM contents");
3605 }
d855497e
MI		 3606
3607 } while (0); LOCK_GIVE(hdw->big_lock);
3608}
3609
3610
3611/* Return true if we're in a mode for retrieval CPU firmware */
3612int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3613{
5fa1247a 3614 return hdw->fw_buffer != NULL;
d855497e
MI		 3615}
3616
3617
3618int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3619 char *buf,unsigned int cnt)
3620{
3621 int ret = -EINVAL;
3622 LOCK_TAKE(hdw->big_lock); do {
3623 if (!buf) break;
3624 if (!cnt) break;
3625
3626 if (!hdw->fw_buffer) {
3627 ret = -EIO;
3628 break;
3629 }
3630
3631 if (offs >= hdw->fw_size) {
3632 pvr2_trace(PVR2_TRACE_FIRMWARE,
3633 "Read firmware data offs=%d EOF",
3634 offs);
3635 ret = 0;
3636 break;
3637 }
3638
3639 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3640
3641 memcpy(buf,hdw->fw_buffer+offs,cnt);
3642
3643 pvr2_trace(PVR2_TRACE_FIRMWARE,
3644 "Read firmware data offs=%d cnt=%d",
3645 offs,cnt);
3646 ret = cnt;
3647 } while (0); LOCK_GIVE(hdw->big_lock);
3648
3649 return ret;
3650}
3651
3652
fd5a75fe 3653int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 3654 enum pvr2_v4l_type index)
d855497e 3655{
fd5a75fe 3656 switch (index) {
8079384e
MI		 3657 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3658 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3659 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 3660 default: return -1;
3661 }
d855497e
MI		 3662}
3663
3664
2fdf3d9c 3665/* Store a v4l minor device number */
fd5a75fe 3666void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 3667 enum pvr2_v4l_type index,int v)
d855497e 3668{
fd5a75fe 3669 switch (index) {
8079384e
MI		 3670 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3671 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3672 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 3673 default: break;
3674 }
d855497e
MI		 3675}
3676
3677
7d12e780 3678static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 3679{
3680 struct pvr2_hdw *hdw = urb->context;
3681 hdw->ctl_write_pend_flag = 0;
3682 if (hdw->ctl_read_pend_flag) return;
3683 complete(&hdw->ctl_done);
3684}
3685
3686
7d12e780 3687static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 3688{
3689 struct pvr2_hdw *hdw = urb->context;
3690 hdw->ctl_read_pend_flag = 0;
3691 if (hdw->ctl_write_pend_flag) return;
3692 complete(&hdw->ctl_done);
3693}
3694
3695
3696static void pvr2_ctl_timeout(unsigned long data)
3697{
3698 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3699 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3700 hdw->ctl_timeout_flag = !0;
5e55d2ce 3701 if (hdw->ctl_write_pend_flag)
d855497e 3702 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 3703 if (hdw->ctl_read_pend_flag)
d855497e 3704 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 3705 }
3706}
3707
3708
e61b6fc5
MI		 3709/* Issue a command and get a response from the device. This extended
3710 version includes a probe flag (which if set means that device errors
3711 should not be logged or treated as fatal) and a timeout in jiffies.
3712 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 3713static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3714 unsigned int timeout,int probe_fl,
3715 void *write_data,unsigned int write_len,
3716 void *read_data,unsigned int read_len)
d855497e
MI		 3717{
3718 unsigned int idx;
3719 int status = 0;
3720 struct timer_list timer;
3721 if (!hdw->ctl_lock_held) {
3722 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3723 "Attempted to execute control transfer"
3724 " without lock!!");
3725 return -EDEADLK;
3726 }
681c7399 3727 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 3728 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3729 "Attempted to execute control transfer"
3730 " when device not ok");
3731 return -EIO;
3732 }
3733 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3734 if (!probe_fl) {
3735 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3736 "Attempted to execute control transfer"
3737 " when USB is disconnected");
3738 }
3739 return -ENOTTY;
3740 }
3741
3742 /* Ensure that we have sane parameters */
3743 if (!write_data) write_len = 0;
3744 if (!read_data) read_len = 0;
3745 if (write_len > PVR2_CTL_BUFFSIZE) {
3746 pvr2_trace(
3747 PVR2_TRACE_ERROR_LEGS,
3748 "Attempted to execute %d byte"
3749 " control-write transfer (limit=%d)",
3750 write_len,PVR2_CTL_BUFFSIZE);
3751 return -EINVAL;
3752 }
3753 if (read_len > PVR2_CTL_BUFFSIZE) {
3754 pvr2_trace(
3755 PVR2_TRACE_ERROR_LEGS,
3756 "Attempted to execute %d byte"
3757 " control-read transfer (limit=%d)",
3758 write_len,PVR2_CTL_BUFFSIZE);
3759 return -EINVAL;
3760 }
3761 if ((!write_len) && (!read_len)) {
3762 pvr2_trace(
3763 PVR2_TRACE_ERROR_LEGS,
3764 "Attempted to execute null control transfer?");
3765 return -EINVAL;
3766 }
3767
3768
3769 hdw->cmd_debug_state = 1;
3770 if (write_len) {
3771 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3772 } else {
3773 hdw->cmd_debug_code = 0;
3774 }
3775 hdw->cmd_debug_write_len = write_len;
3776 hdw->cmd_debug_read_len = read_len;
3777
3778 /* Initialize common stuff */
3779 init_completion(&hdw->ctl_done);
3780 hdw->ctl_timeout_flag = 0;
3781 hdw->ctl_write_pend_flag = 0;
3782 hdw->ctl_read_pend_flag = 0;
3783 init_timer(&timer);
3784 timer.expires = jiffies + timeout;
3785 timer.data = (unsigned long)hdw;
3786 timer.function = pvr2_ctl_timeout;
3787
3788 if (write_len) {
3789 hdw->cmd_debug_state = 2;
3790 /* Transfer write data to internal buffer */
3791 for (idx = 0; idx < write_len; idx++) {
3792 hdw->ctl_write_buffer[idx] =
3793 ((unsigned char *)write_data)[idx];
3794 }
3795 /* Initiate a write request */
3796 usb_fill_bulk_urb(hdw->ctl_write_urb,
3797 hdw->usb_dev,
3798 usb_sndbulkpipe(hdw->usb_dev,
3799 PVR2_CTL_WRITE_ENDPOINT),
3800 hdw->ctl_write_buffer,
3801 write_len,
3802 pvr2_ctl_write_complete,
3803 hdw);
3804 hdw->ctl_write_urb->actual_length = 0;
3805 hdw->ctl_write_pend_flag = !0;
3806 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3807 if (status < 0) {
3808 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3809 "Failed to submit write-control"
3810 " URB status=%d",status);
3811 hdw->ctl_write_pend_flag = 0;
3812 goto done;
3813 }
3814 }
3815
3816 if (read_len) {
3817 hdw->cmd_debug_state = 3;
3818 memset(hdw->ctl_read_buffer,0x43,read_len);
3819 /* Initiate a read request */
3820 usb_fill_bulk_urb(hdw->ctl_read_urb,
3821 hdw->usb_dev,
3822 usb_rcvbulkpipe(hdw->usb_dev,
3823 PVR2_CTL_READ_ENDPOINT),
3824 hdw->ctl_read_buffer,
3825 read_len,
3826 pvr2_ctl_read_complete,
3827 hdw);
3828 hdw->ctl_read_urb->actual_length = 0;
3829 hdw->ctl_read_pend_flag = !0;
3830 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3831 if (status < 0) {
3832 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3833 "Failed to submit read-control"
3834 " URB status=%d",status);
3835 hdw->ctl_read_pend_flag = 0;
3836 goto done;
3837 }
3838 }
3839
3840 /* Start timer */
3841 add_timer(&timer);
3842
3843 /* Now wait for all I/O to complete */
3844 hdw->cmd_debug_state = 4;
3845 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3846 wait_for_completion(&hdw->ctl_done);
3847 }
3848 hdw->cmd_debug_state = 5;
3849
3850 /* Stop timer */
3851 del_timer_sync(&timer);
3852
3853 hdw->cmd_debug_state = 6;
3854 status = 0;
3855
3856 if (hdw->ctl_timeout_flag) {
3857 status = -ETIMEDOUT;
3858 if (!probe_fl) {
3859 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3860 "Timed out control-write");
3861 }
3862 goto done;
3863 }
3864
3865 if (write_len) {
3866 /* Validate results of write request */
3867 if ((hdw->ctl_write_urb->status != 0) &&
3868 (hdw->ctl_write_urb->status != -ENOENT) &&
3869 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3870 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3871 /* USB subsystem is reporting some kind of failure
3872 on the write */
3873 status = hdw->ctl_write_urb->status;
3874 if (!probe_fl) {
3875 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3876 "control-write URB failure,"
3877 " status=%d",
3878 status);
3879 }
3880 goto done;
3881 }
3882 if (hdw->ctl_write_urb->actual_length < write_len) {
3883 /* Failed to write enough data */
3884 status = -EIO;
3885 if (!probe_fl) {
3886 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3887 "control-write URB short,"
3888 " expected=%d got=%d",
3889 write_len,
3890 hdw->ctl_write_urb->actual_length);
3891 }
3892 goto done;
3893 }
3894 }
3895 if (read_len) {
3896 /* Validate results of read request */
3897 if ((hdw->ctl_read_urb->status != 0) &&
3898 (hdw->ctl_read_urb->status != -ENOENT) &&
3899 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3900 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3901 /* USB subsystem is reporting some kind of failure
3902 on the read */
3903 status = hdw->ctl_read_urb->status;
3904 if (!probe_fl) {
3905 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3906 "control-read URB failure,"
3907 " status=%d",
3908 status);
3909 }
3910 goto done;
3911 }
3912 if (hdw->ctl_read_urb->actual_length < read_len) {
3913 /* Failed to read enough data */
3914 status = -EIO;
3915 if (!probe_fl) {
3916 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3917 "control-read URB short,"
3918 " expected=%d got=%d",
3919 read_len,
3920 hdw->ctl_read_urb->actual_length);
3921 }
3922 goto done;
3923 }
3924 /* Transfer retrieved data out from internal buffer */
3925 for (idx = 0; idx < read_len; idx++) {
3926 ((unsigned char *)read_data)[idx] =
3927 hdw->ctl_read_buffer[idx];
3928 }
3929 }
3930
3931 done:
3932
3933 hdw->cmd_debug_state = 0;
3934 if ((status < 0) && (!probe_fl)) {
681c7399 3935 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3936 }
3937 return status;
3938}
3939
3940
3941int pvr2_send_request(struct pvr2_hdw *hdw,
3942 void *write_data,unsigned int write_len,
3943 void *read_data,unsigned int read_len)
3944{
3945 return pvr2_send_request_ex(hdw,HZ*4,0,
3946 write_data,write_len,
3947 read_data,read_len);
3948}
3949
1c9d10d4
MI		 3950
3951static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3952{
3953 int ret;
3954 unsigned int cnt = 1;
3955 unsigned int args = 0;
3956 LOCK_TAKE(hdw->ctl_lock);
3957 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3958 args = (cmdcode >> 8) & 0xffu;
3959 args = (args > 2) ? 2 : args;
3960 if (args) {
3961 cnt += args;
3962 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3963 if (args > 1) {
3964 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3965 }
3966 }
3967 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3968 unsigned int idx;
3969 unsigned int ccnt,bcnt;
3970 char tbuf[50];
3971 cmdcode &= 0xffu;
3972 bcnt = 0;
3973 ccnt = scnprintf(tbuf+bcnt,
3974 sizeof(tbuf)-bcnt,
3975 "Sending FX2 command 0x%x",cmdcode);
3976 bcnt += ccnt;
3977 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3978 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3979 ccnt = scnprintf(tbuf+bcnt,
3980 sizeof(tbuf)-bcnt,
3981 " \"%s\"",
3982 pvr2_fx2cmd_desc[idx].desc);
3983 bcnt += ccnt;
3984 break;
3985 }
3986 }
3987 if (args) {
3988 ccnt = scnprintf(tbuf+bcnt,
3989 sizeof(tbuf)-bcnt,
3990 " (%u",hdw->cmd_buffer[1]);
3991 bcnt += ccnt;
3992 if (args > 1) {
3993 ccnt = scnprintf(tbuf+bcnt,
3994 sizeof(tbuf)-bcnt,
3995 ",%u",hdw->cmd_buffer[2]);
3996 bcnt += ccnt;
3997 }
3998 ccnt = scnprintf(tbuf+bcnt,
3999 sizeof(tbuf)-bcnt,
4000 ")");
4001 bcnt += ccnt;
4002 }
4003 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
4004 }
4005 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
4006 LOCK_GIVE(hdw->ctl_lock);
4007 return ret;
4008}
4009
4010
d855497e
MI		 4011int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
4012{
4013 int ret;
4014
4015 LOCK_TAKE(hdw->ctl_lock);
4016
8d364363 4017 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 4018 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
4019 hdw->cmd_buffer[5] = 0;
4020 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4021 hdw->cmd_buffer[7] = reg & 0xff;
4022
4023
4024 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
4025
4026 LOCK_GIVE(hdw->ctl_lock);
4027
4028 return ret;
4029}
4030
4031
07e337ee 4032static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 4033{
4034 int ret = 0;
4035
4036 LOCK_TAKE(hdw->ctl_lock);
4037
8d364363 4038 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 4039 hdw->cmd_buffer[1] = 0;
4040 hdw->cmd_buffer[2] = 0;
4041 hdw->cmd_buffer[3] = 0;
4042 hdw->cmd_buffer[4] = 0;
4043 hdw->cmd_buffer[5] = 0;
4044 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4045 hdw->cmd_buffer[7] = reg & 0xff;
4046
4047 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
4048 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
4049
4050 LOCK_GIVE(hdw->ctl_lock);
4051
4052 return ret;
4053}
4054
4055
681c7399 4056void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 4057{
4058 if (!hdw->flag_ok) return;
681c7399
MI		 4059 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4060 "Device being rendered inoperable");
d855497e 4061 if (hdw->vid_stream) {
a0fd1cb1 4062 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 4063 }
681c7399
MI		 4064 hdw->flag_ok = 0;
4065 trace_stbit("flag_ok",hdw->flag_ok);
4066 pvr2_hdw_state_sched(hdw);
d855497e
MI		 4067}
4068
4069
4070void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4071{
4072 int ret;
4073 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 4074 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
011b15df 4075 if (ret == 0) {
d855497e
MI		 4076 ret = usb_reset_device(hdw->usb_dev);
4077 usb_unlock_device(hdw->usb_dev);
4078 } else {
4079 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4080 "Failed to lock USB device ret=%d",ret);
4081 }
4082 if (init_pause_msec) {
4083 pvr2_trace(PVR2_TRACE_INFO,
4084 "Waiting %u msec for hardware to settle",
4085 init_pause_msec);
4086 msleep(init_pause_msec);
4087 }
4088
4089}
4090
4091
4092void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4093{
6861800c 4094 char *da;
d855497e
MI		 4095 unsigned int pipe;
4096 int ret;
4097
4098 if (!hdw->usb_dev) return;
4099
6861800c
MI		 4100 da = kmalloc(16, GFP_KERNEL);
4101
4102 if (da == NULL) {
4103 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4104 "Unable to allocate memory to control CPU reset");
4105 return;
4106 }
4107
d855497e
MI		 4108 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4109
4110 da[0] = val ? 0x01 : 0x00;
4111
4112 /* Write the CPUCS register on the 8051. The lsb of the register
4113 is the reset bit; a 1 asserts reset while a 0 clears it. */
4114 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4115 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4116 if (ret < 0) {
4117 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4118 "cpureset_assert(%d) error=%d",val,ret);
4119 pvr2_hdw_render_useless(hdw);
4120 }
6861800c
MI		 4121
4122 kfree(da);
d855497e
MI		 4123}
4124
4125
4126int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4127{
1c9d10d4 4128 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
d855497e
MI		 4129}
4130
4131
e1edb19a
MK		 4132int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4133{
1c9d10d4 4134 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
e1edb19a
MK		 4135}
4136
1c9d10d4 4137
e1edb19a
MK		 4138int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4139{
1c9d10d4 4140 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
e1edb19a
MK		 4141}
4142
d855497e
MI		 4143
4144int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4145{
af78e16b
MI		 4146 pvr2_trace(PVR2_TRACE_INIT,
4147 "Requesting decoder reset");
af78e16b
MI		 4148 if (hdw->decoder_client_id) {
4149 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4150 core, reset, 0);
e17d787c 4151 pvr2_hdw_cx25840_vbi_hack(hdw);
af78e16b 4152 return 0;
d855497e 4153 }
d855497e 4154 pvr2_trace(PVR2_TRACE_INIT,
af78e16b
MI		 4155 "Unable to reset decoder: nothing attached");
4156 return -ENOTTY;
d855497e
MI		 4157}
4158
4159
62433e31 4160static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
84147f3d 4161{
1c9d10d4
MI		 4162 hdw->flag_ok = !0;
4163 return pvr2_issue_simple_cmd(hdw,
4164 FX2CMD_HCW_DEMOD_RESETIN |
4165 (1 << 8) |
4166 ((onoff ? 1 : 0) << 16));
84147f3d
MI		 4167}
4168
84147f3d 4169
62433e31 4170static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
84147f3d 4171{
1c9d10d4
MI		 4172 hdw->flag_ok = !0;
4173 return pvr2_issue_simple_cmd(hdw,(onoff ?
4174 FX2CMD_ONAIR_DTV_POWER_ON :
4175 FX2CMD_ONAIR_DTV_POWER_OFF));
84147f3d
MI		 4176}
4177
62433e31
MI		 4178
4179static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4180 int onoff)
84147f3d 4181{
1c9d10d4
MI		 4182 return pvr2_issue_simple_cmd(hdw,(onoff ?
4183 FX2CMD_ONAIR_DTV_STREAMING_ON :
4184 FX2CMD_ONAIR_DTV_STREAMING_OFF));
84147f3d
MI		 4185}
4186
62433e31
MI		 4187
4188static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4189{
4190 int cmode;
4191 /* Compare digital/analog desired setting with current setting. If
4192 they don't match, fix it... */
4193 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4194 if (cmode == hdw->pathway_state) {
4195 /* They match; nothing to do */
4196 return;
4197 }
4198
4199 switch (hdw->hdw_desc->digital_control_scheme) {
4200 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4201 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4202 if (cmode == PVR2_PATHWAY_ANALOG) {
4203 /* If moving to analog mode, also force the decoder
4204 to reset. If no decoder is attached, then it's
4205 ok to ignore this because if/when the decoder
4206 attaches, it will reset itself at that time. */
4207 pvr2_hdw_cmd_decoder_reset(hdw);
4208 }
4209 break;
4210 case PVR2_DIGITAL_SCHEME_ONAIR:
4211 /* Supposedly we should always have the power on whether in
4212 digital or analog mode. But for now do what appears to
4213 work... */
bb0c2fe0 4214 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
62433e31
MI		 4215 break;
4216 default: break;
4217 }
4218
1b9c18c5 4219 pvr2_hdw_untrip_unlocked(hdw);
62433e31
MI		 4220 hdw->pathway_state = cmode;
4221}
4222
4223
e9b59f6e 4224static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
c55a97d7
MI		 4225{
4226 /* change some GPIO data
4227 *
4228 * note: bit d7 of dir appears to control the LED,
4229 * so we shut it off here.
4230 *
c55a97d7 4231 */
40381cb0 4232 if (onoff) {
c55a97d7 4233 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
40381cb0 4234 } else {
c55a97d7 4235 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
40381cb0 4236 }
c55a97d7 4237 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
40381cb0 4238}
c55a97d7 4239
40381cb0
MI		 4240
4241typedef void (*led_method_func)(struct pvr2_hdw *,int);
4242
4243static led_method_func led_methods[] = {
4244 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4245};
4246
4247
4248/* Toggle LED */
4249static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4250{
4251 unsigned int scheme_id;
4252 led_method_func fp;
4253
4254 if ((!onoff) == (!hdw->led_on)) return;
4255
4256 hdw->led_on = onoff != 0;
4257
4258 scheme_id = hdw->hdw_desc->led_scheme;
4259 if (scheme_id < ARRAY_SIZE(led_methods)) {
4260 fp = led_methods[scheme_id];
4261 } else {
4262 fp = NULL;
4263 }
4264
4265 if (fp) (*fp)(hdw,onoff);
c55a97d7
MI		 4266}
4267
4268
e61b6fc5 4269/* Stop / start video stream transport */
07e337ee 4270static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e 4271{
bb0c2fe0
MI		 4272 int ret;
4273
4274 /* If we're in analog mode, then just issue the usual analog
4275 command. */
4276 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4277 return pvr2_issue_simple_cmd(hdw,
4278 (runFl ?
4279 FX2CMD_STREAMING_ON :
4280 FX2CMD_STREAMING_OFF));
4281 /*Note: Not reached */
4282 }
4283
4284 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4285 /* Whoops, we don't know what mode we're in... */
4286 return -EINVAL;
4287 }
4288
4289 /* To get here we have to be in digital mode. The mechanism here
4290 is unfortunately different for different vendors. So we switch
4291 on the device's digital scheme attribute in order to figure out
4292 what to do. */
4293 switch (hdw->hdw_desc->digital_control_scheme) {
4294 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4295 return pvr2_issue_simple_cmd(hdw,
4296 (runFl ?
4297 FX2CMD_HCW_DTV_STREAMING_ON :
4298 FX2CMD_HCW_DTV_STREAMING_OFF));
4299 case PVR2_DIGITAL_SCHEME_ONAIR:
4300 ret = pvr2_issue_simple_cmd(hdw,
4301 (runFl ?
4302 FX2CMD_STREAMING_ON :
4303 FX2CMD_STREAMING_OFF));
4304 if (ret) return ret;
4305 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4306 default:
4307 return -EINVAL;
62433e31 4308 }
d855497e
MI		 4309}
4310
4311
62433e31
MI		 4312/* Evaluate whether or not state_pathway_ok can change */
4313static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4314{
4315 if (hdw->state_pathway_ok) {
4316 /* Nothing to do if pathway is already ok */
4317 return 0;
4318 }
4319 if (!hdw->state_pipeline_idle) {
4320 /* Not allowed to change anything if pipeline is not idle */
4321 return 0;
4322 }
4323 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4324 hdw->state_pathway_ok = !0;
e9db1ff2 4325 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 4326 return !0;
4327}
4328
4329
681c7399
MI		 4330/* Evaluate whether or not state_encoder_ok can change */
4331static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4332{
4333 if (hdw->state_encoder_ok) return 0;
4334 if (hdw->flag_tripped) return 0;
4335 if (hdw->state_encoder_run) return 0;
4336 if (hdw->state_encoder_config) return 0;
4337 if (hdw->state_decoder_run) return 0;
4338 if (hdw->state_usbstream_run) return 0;
72998b71
MI		 4339 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4340 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4341 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4342 return 0;
4343 }
4344
681c7399
MI		 4345 if (pvr2_upload_firmware2(hdw) < 0) {
4346 hdw->flag_tripped = !0;
4347 trace_stbit("flag_tripped",hdw->flag_tripped);
4348 return !0;
4349 }
4350 hdw->state_encoder_ok = !0;
4351 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4352 return !0;
4353}
4354
4355
4356/* Evaluate whether or not state_encoder_config can change */
4357static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4358{
4359 if (hdw->state_encoder_config) {
4360 if (hdw->state_encoder_ok) {
4361 if (hdw->state_pipeline_req &&
4362 !hdw->state_pipeline_pause) return 0;
4363 }
4364 hdw->state_encoder_config = 0;
4365 hdw->state_encoder_waitok = 0;
4366 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4367 /* paranoia - solve race if timer just completed */
4368 del_timer_sync(&hdw->encoder_wait_timer);
4369 } else {
62433e31
MI		 4370 if (!hdw->state_pathway_ok ||
4371 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4372 !hdw->state_encoder_ok ||
681c7399
MI		 4373 !hdw->state_pipeline_idle ||
4374 hdw->state_pipeline_pause ||
4375 !hdw->state_pipeline_req ||
4376 !hdw->state_pipeline_config) {
4377 /* We must reset the enforced wait interval if
4378 anything has happened that might have disturbed
4379 the encoder. This should be a rare case. */
4380 if (timer_pending(&hdw->encoder_wait_timer)) {
4381 del_timer_sync(&hdw->encoder_wait_timer);
4382 }
4383 if (hdw->state_encoder_waitok) {
4384 /* Must clear the state - therefore we did
4385 something to a state bit and must also
4386 return true. */
4387 hdw->state_encoder_waitok = 0;
4388 trace_stbit("state_encoder_waitok",
4389 hdw->state_encoder_waitok);
4390 return !0;
4391 }
4392 return 0;
4393 }
4394 if (!hdw->state_encoder_waitok) {
4395 if (!timer_pending(&hdw->encoder_wait_timer)) {
4396 /* waitok flag wasn't set and timer isn't
4397 running. Check flag once more to avoid
4398 a race then start the timer. This is
4399 the point when we measure out a minimal
4400 quiet interval before doing something to
4401 the encoder. */
4402 if (!hdw->state_encoder_waitok) {
4403 hdw->encoder_wait_timer.expires =
83ce57aa
MI		 4404 jiffies +
4405 (HZ * TIME_MSEC_ENCODER_WAIT
4406 / 1000);
681c7399
MI		 4407 add_timer(&hdw->encoder_wait_timer);
4408 }
4409 }
4410 /* We can't continue until we know we have been
4411 quiet for the interval measured by this
4412 timer. */
4413 return 0;
4414 }
4415 pvr2_encoder_configure(hdw);
4416 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4417 }
4418 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4419 return !0;
4420}
4421
4422
d913d630
MI		 4423/* Return true if the encoder should not be running. */
4424static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4425{
4426 if (!hdw->state_encoder_ok) {
4427 /* Encoder isn't healthy at the moment, so stop it. */
4428 return !0;
4429 }
4430 if (!hdw->state_pathway_ok) {
4431 /* Mode is not understood at the moment (i.e. it wants to
4432 change), so encoder must be stopped. */
4433 return !0;
4434 }
4435
4436 switch (hdw->pathway_state) {
4437 case PVR2_PATHWAY_ANALOG:
4438 if (!hdw->state_decoder_run) {
4439 /* We're in analog mode and the decoder is not
4440 running; thus the encoder should be stopped as
4441 well. */
4442 return !0;
4443 }
4444 break;
4445 case PVR2_PATHWAY_DIGITAL:
4446 if (hdw->state_encoder_runok) {
4447 /* This is a funny case. We're in digital mode so
4448 really the encoder should be stopped. However
4449 if it really is running, only kill it after
4450 runok has been set. This gives a chance for the
4451 onair quirk to function (encoder must run
4452 briefly first, at least once, before onair
4453 digital streaming can work). */
4454 return !0;
4455 }
4456 break;
4457 default:
4458 /* Unknown mode; so encoder should be stopped. */
4459 return !0;
4460 }
4461
4462 /* If we get here, we haven't found a reason to stop the
4463 encoder. */
4464 return 0;
4465}
4466
4467
4468/* Return true if the encoder should be running. */
4469static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4470{
4471 if (!hdw->state_encoder_ok) {
4472 /* Don't run the encoder if it isn't healthy... */
4473 return 0;
4474 }
4475 if (!hdw->state_pathway_ok) {
4476 /* Don't run the encoder if we don't (yet) know what mode
4477 we need to be in... */
4478 return 0;
4479 }
4480
4481 switch (hdw->pathway_state) {
4482 case PVR2_PATHWAY_ANALOG:
6e931375 4483 if (hdw->state_decoder_run && hdw->state_decoder_ready) {
d913d630
MI		 4484 /* In analog mode, if the decoder is running, then
4485 run the encoder. */
4486 return !0;
4487 }
4488 break;
4489 case PVR2_PATHWAY_DIGITAL:
4490 if ((hdw->hdw_desc->digital_control_scheme ==
4491 PVR2_DIGITAL_SCHEME_ONAIR) &&
4492 !hdw->state_encoder_runok) {
4493 /* This is a quirk. OnAir hardware won't stream
4494 digital until the encoder has been run at least
4495 once, for a minimal period of time (empiricially
4496 measured to be 1/4 second). So if we're on
4497 OnAir hardware and the encoder has never been
4498 run at all, then start the encoder. Normal
4499 state machine logic in the driver will
4500 automatically handle the remaining bits. */
4501 return !0;
4502 }
4503 break;
4504 default:
4505 /* For completeness (unknown mode; encoder won't run ever) */
4506 break;
4507 }
4508 /* If we get here, then we haven't found any reason to run the
4509 encoder, so don't run it. */
4510 return 0;
4511}
4512
4513
681c7399
MI		 4514/* Evaluate whether or not state_encoder_run can change */
4515static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4516{
4517 if (hdw->state_encoder_run) {
d913d630 4518 if (!state_check_disable_encoder_run(hdw)) return 0;
681c7399 4519 if (hdw->state_encoder_ok) {
d913d630 4520 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 4521 if (pvr2_encoder_stop(hdw) < 0) return !0;
4522 }
4523 hdw->state_encoder_run = 0;
4524 } else {
d913d630 4525 if (!state_check_enable_encoder_run(hdw)) return 0;
681c7399
MI		 4526 if (pvr2_encoder_start(hdw) < 0) return !0;
4527 hdw->state_encoder_run = !0;
d913d630
MI		 4528 if (!hdw->state_encoder_runok) {
4529 hdw->encoder_run_timer.expires =
83ce57aa 4530 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
d913d630
MI		 4531 add_timer(&hdw->encoder_run_timer);
4532 }
681c7399
MI		 4533 }
4534 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4535 return !0;
4536}
4537
4538
4539/* Timeout function for quiescent timer. */
4540static void pvr2_hdw_quiescent_timeout(unsigned long data)
4541{
4542 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4543 hdw->state_decoder_quiescent = !0;
4544 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4545 hdw->state_stale = !0;
4546 queue_work(hdw->workqueue,&hdw->workpoll);
4547}
4548
4549
6e931375
MI		 4550/* Timeout function for decoder stabilization timer. */
4551static void pvr2_hdw_decoder_stabilization_timeout(unsigned long data)
4552{
4553 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4554 hdw->state_decoder_ready = !0;
4555 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4556 hdw->state_stale = !0;
4557 queue_work(hdw->workqueue, &hdw->workpoll);
4558}
4559
4560
681c7399
MI		 4561/* Timeout function for encoder wait timer. */
4562static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4563{
4564 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4565 hdw->state_encoder_waitok = !0;
4566 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4567 hdw->state_stale = !0;
4568 queue_work(hdw->workqueue,&hdw->workpoll);
4569}
4570
4571
d913d630
MI		 4572/* Timeout function for encoder run timer. */
4573static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4574{
4575 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4576 if (!hdw->state_encoder_runok) {
4577 hdw->state_encoder_runok = !0;
4578 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4579 hdw->state_stale = !0;
4580 queue_work(hdw->workqueue,&hdw->workpoll);
4581 }
4582}
4583
4584
681c7399
MI		 4585/* Evaluate whether or not state_decoder_run can change */
4586static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4587{
4588 if (hdw->state_decoder_run) {
4589 if (hdw->state_encoder_ok) {
4590 if (hdw->state_pipeline_req &&
62433e31
MI		 4591 !hdw->state_pipeline_pause &&
4592 hdw->state_pathway_ok) return 0;
681c7399
MI		 4593 }
4594 if (!hdw->flag_decoder_missed) {
4595 pvr2_decoder_enable(hdw,0);
4596 }
4597 hdw->state_decoder_quiescent = 0;
4598 hdw->state_decoder_run = 0;
6e931375 4599 /* paranoia - solve race if timer(s) just completed */
681c7399 4600 del_timer_sync(&hdw->quiescent_timer);
6e931375
MI		 4601 /* Kill the stabilization timer, in case we're killing the
4602 encoder before the previous stabilization interval has
4603 been properly timed. */
4604 del_timer_sync(&hdw->decoder_stabilization_timer);
4605 hdw->state_decoder_ready = 0;
681c7399
MI		 4606 } else {
4607 if (!hdw->state_decoder_quiescent) {
4608 if (!timer_pending(&hdw->quiescent_timer)) {
4609 /* We don't do something about the
4610 quiescent timer until right here because
4611 we also want to catch cases where the
4612 decoder was already not running (like
4613 after initialization) as opposed to
4614 knowing that we had just stopped it.
4615 The second flag check is here to cover a
4616 race - the timer could have run and set
4617 this flag just after the previous check
4618 but before we did the pending check. */
4619 if (!hdw->state_decoder_quiescent) {
4620 hdw->quiescent_timer.expires =
83ce57aa
MI		 4621 jiffies +
4622 (HZ * TIME_MSEC_DECODER_WAIT
4623 / 1000);
681c7399
MI		 4624 add_timer(&hdw->quiescent_timer);
4625 }
4626 }
4627 /* Don't allow decoder to start again until it has
4628 been quiesced first. This little detail should
4629 hopefully further stabilize the encoder. */
4630 return 0;
4631 }
62433e31
MI		 4632 if (!hdw->state_pathway_ok ||
4633 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4634 !hdw->state_pipeline_req ||
681c7399
MI		 4635 hdw->state_pipeline_pause ||
4636 !hdw->state_pipeline_config ||
4637 !hdw->state_encoder_config ||
4638 !hdw->state_encoder_ok) return 0;
4639 del_timer_sync(&hdw->quiescent_timer);
4640 if (hdw->flag_decoder_missed) return 0;
4641 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4642 hdw->state_decoder_quiescent = 0;
6e931375 4643 hdw->state_decoder_ready = 0;
681c7399 4644 hdw->state_decoder_run = !0;
fb640224
MI		 4645 if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4646 hdw->decoder_stabilization_timer.expires =
4647 jiffies +
4648 (HZ * TIME_MSEC_DECODER_STABILIZATION_WAIT /
4649 1000);
4650 add_timer(&hdw->decoder_stabilization_timer);
4651 } else {
4652 hdw->state_decoder_ready = !0;
4653 }
681c7399
MI		 4654 }
4655 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4656 trace_stbit("state_decoder_run",hdw->state_decoder_run);
6e931375 4657 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
681c7399
MI		 4658 return !0;
4659}
4660
4661
4662/* Evaluate whether or not state_usbstream_run can change */
4663static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4664{
4665 if (hdw->state_usbstream_run) {
72998b71 4666 int fl = !0;
62433e31 4667 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
72998b71
MI		 4668 fl = (hdw->state_encoder_ok &&
4669 hdw->state_encoder_run);
4670 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4671 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4672 fl = hdw->state_encoder_ok;
4673 }
4674 if (fl &&
4675 hdw->state_pipeline_req &&
4676 !hdw->state_pipeline_pause &&
4677 hdw->state_pathway_ok) {
4678 return 0;
681c7399
MI		 4679 }
4680 pvr2_hdw_cmd_usbstream(hdw,0);
4681 hdw->state_usbstream_run = 0;
4682 } else {
62433e31
MI		 4683 if (!hdw->state_pipeline_req ||
4684 hdw->state_pipeline_pause ||
4685 !hdw->state_pathway_ok) return 0;
4686 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4687 if (!hdw->state_encoder_ok ||
4688 !hdw->state_encoder_run) return 0;
72998b71
MI		 4689 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4690 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4691 if (!hdw->state_encoder_ok) return 0;
d913d630
MI		 4692 if (hdw->state_encoder_run) return 0;
4693 if (hdw->hdw_desc->digital_control_scheme ==
4694 PVR2_DIGITAL_SCHEME_ONAIR) {
4695 /* OnAir digital receivers won't stream
4696 unless the analog encoder has run first.
4697 Why? I have no idea. But don't even
4698 try until we know the analog side is
4699 known to have run. */
4700 if (!hdw->state_encoder_runok) return 0;
4701 }
62433e31 4702 }
681c7399
MI		 4703 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4704 hdw->state_usbstream_run = !0;
4705 }
4706 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4707 return !0;
4708}
4709
4710
4711/* Attempt to configure pipeline, if needed */
4712static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4713{
4714 if (hdw->state_pipeline_config ||
4715 hdw->state_pipeline_pause) return 0;
4716 pvr2_hdw_commit_execute(hdw);
4717 return !0;
4718}
4719
4720
4721/* Update pipeline idle and pipeline pause tracking states based on other
4722 inputs. This must be called whenever the other relevant inputs have
4723 changed. */
4724static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4725{
4726 unsigned int st;
4727 int updatedFl = 0;
4728 /* Update pipeline state */
4729 st = !(hdw->state_encoder_run ||
4730 hdw->state_decoder_run ||
4731 hdw->state_usbstream_run ||
4732 (!hdw->state_decoder_quiescent));
4733 if (!st != !hdw->state_pipeline_idle) {
4734 hdw->state_pipeline_idle = st;
4735 updatedFl = !0;
4736 }
4737 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4738 hdw->state_pipeline_pause = 0;
4739 updatedFl = !0;
4740 }
4741 return updatedFl;
4742}
4743
4744
4745typedef int (*state_eval_func)(struct pvr2_hdw *);
4746
4747/* Set of functions to be run to evaluate various states in the driver. */
ebff0330 4748static const state_eval_func eval_funcs[] = {
62433e31 4749 state_eval_pathway_ok,
681c7399
MI		 4750 state_eval_pipeline_config,
4751 state_eval_encoder_ok,
4752 state_eval_encoder_config,
4753 state_eval_decoder_run,
4754 state_eval_encoder_run,
4755 state_eval_usbstream_run,
4756};
4757
4758
4759/* Process various states and return true if we did anything interesting. */
4760static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4761{
4762 unsigned int i;
4763 int state_updated = 0;
4764 int check_flag;
4765
4766 if (!hdw->state_stale) return 0;
4767 if ((hdw->fw1_state != FW1_STATE_OK) ||
4768 !hdw->flag_ok) {
4769 hdw->state_stale = 0;
4770 return !0;
4771 }
4772 /* This loop is the heart of the entire driver. It keeps trying to
4773 evaluate various bits of driver state until nothing changes for
4774 one full iteration. Each "bit of state" tracks some global
4775 aspect of the driver, e.g. whether decoder should run, if
4776 pipeline is configured, usb streaming is on, etc. We separately
4777 evaluate each of those questions based on other driver state to
4778 arrive at the correct running configuration. */
4779 do {
4780 check_flag = 0;
4781 state_update_pipeline_state(hdw);
4782 /* Iterate over each bit of state */
4783 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4784 if ((*eval_funcs[i])(hdw)) {
4785 check_flag = !0;
4786 state_updated = !0;
4787 state_update_pipeline_state(hdw);
4788 }
4789 }
4790 } while (check_flag && hdw->flag_ok);
4791 hdw->state_stale = 0;
4792 trace_stbit("state_stale",hdw->state_stale);
4793 return state_updated;
4794}
4795
4796
1cb03b76
MI		 4797static unsigned int print_input_mask(unsigned int msk,
4798 char *buf,unsigned int acnt)
4799{
4800 unsigned int idx,ccnt;
4801 unsigned int tcnt = 0;
4802 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4803 if (!((1 << idx) & msk)) continue;
4804 ccnt = scnprintf(buf+tcnt,
4805 acnt-tcnt,
4806 "%s%s",
4807 (tcnt ? ", " : ""),
4808 control_values_input[idx]);
4809 tcnt += ccnt;
4810 }
4811 return tcnt;
4812}
4813
4814
62433e31
MI		 4815static const char *pvr2_pathway_state_name(int id)
4816{
4817 switch (id) {
4818 case PVR2_PATHWAY_ANALOG: return "analog";
4819 case PVR2_PATHWAY_DIGITAL: return "digital";
4820 default: return "unknown";
4821 }
4822}
4823
4824
681c7399
MI		 4825static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4826 char *buf,unsigned int acnt)
4827{
4828 switch (which) {
4829 case 0:
4830 return scnprintf(
4831 buf,acnt,
e9db1ff2 4832 "driver:%s%s%s%s%s <mode=%s>",
681c7399
MI		 4833 (hdw->flag_ok ? " <ok>" : " <fail>"),
4834 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4835 (hdw->flag_disconnected ? " <disconnected>" :
4836 " <connected>"),
4837 (hdw->flag_tripped ? " <tripped>" : ""),
62433e31
MI		 4838 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4839 pvr2_pathway_state_name(hdw->pathway_state));
4840
681c7399
MI		 4841 case 1:
4842 return scnprintf(
4843 buf,acnt,
4844 "pipeline:%s%s%s%s",
4845 (hdw->state_pipeline_idle ? " <idle>" : ""),
4846 (hdw->state_pipeline_config ?
4847 " <configok>" : " <stale>"),
4848 (hdw->state_pipeline_req ? " <req>" : ""),
4849 (hdw->state_pipeline_pause ? " <pause>" : ""));
4850 case 2:
4851 return scnprintf(
4852 buf,acnt,
62433e31 4853 "worker:%s%s%s%s%s%s%s",
681c7399 4854 (hdw->state_decoder_run ?
6e931375
MI		 4855 (hdw->state_decoder_ready ?
4856 "<decode:run>" : " <decode:start>") :
681c7399
MI		 4857 (hdw->state_decoder_quiescent ?
4858 "" : " <decode:stop>")),
4859 (hdw->state_decoder_quiescent ?
4860 " <decode:quiescent>" : ""),
4861 (hdw->state_encoder_ok ?
4862 "" : " <encode:init>"),
4863 (hdw->state_encoder_run ?
d913d630
MI		 4864 (hdw->state_encoder_runok ?
4865 " <encode:run>" :
4866 " <encode:firstrun>") :
4867 (hdw->state_encoder_runok ?
4868 " <encode:stop>" :
4869 " <encode:virgin>")),
681c7399
MI		 4870 (hdw->state_encoder_config ?
4871 " <encode:configok>" :
4872 (hdw->state_encoder_waitok ?
b9a37d91 4873 "" : " <encode:waitok>")),
681c7399 4874 (hdw->state_usbstream_run ?
62433e31
MI		 4875 " <usb:run>" : " <usb:stop>"),
4876 (hdw->state_pathway_ok ?
e9db1ff2 4877 " <pathway:ok>" : ""));
681c7399
MI		 4878 case 3:
4879 return scnprintf(
4880 buf,acnt,
4881 "state: %s",
4882 pvr2_get_state_name(hdw->master_state));
ad0992e9 4883 case 4: {
1cb03b76
MI		 4884 unsigned int tcnt = 0;
4885 unsigned int ccnt;
4886
4887 ccnt = scnprintf(buf,
4888 acnt,
4889 "Hardware supported inputs: ");
4890 tcnt += ccnt;
4891 tcnt += print_input_mask(hdw->input_avail_mask,
4892 buf+tcnt,
4893 acnt-tcnt);
4894 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4895 ccnt = scnprintf(buf+tcnt,
4896 acnt-tcnt,
4897 "; allowed inputs: ");
4898 tcnt += ccnt;
4899 tcnt += print_input_mask(hdw->input_allowed_mask,
4900 buf+tcnt,
4901 acnt-tcnt);
4902 }
4903 return tcnt;
4904 }
4905 case 5: {
ad0992e9
MI		 4906 struct pvr2_stream_stats stats;
4907 if (!hdw->vid_stream) break;
4908 pvr2_stream_get_stats(hdw->vid_stream,
4909 &stats,
4910 0);
4911 return scnprintf(
4912 buf,acnt,
4913 "Bytes streamed=%u"
4914 " URBs: queued=%u idle=%u ready=%u"
4915 " processed=%u failed=%u",
4916 stats.bytes_processed,
4917 stats.buffers_in_queue,
4918 stats.buffers_in_idle,
4919 stats.buffers_in_ready,
4920 stats.buffers_processed,
4921 stats.buffers_failed);
4922 }
27eab384
MI		 4923 case 6: {
4924 unsigned int id = hdw->ir_scheme_active;
4925 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4926 (id >= ARRAY_SIZE(ir_scheme_names) ?
4927 "?" : ir_scheme_names[id]));
4928 }
2eb563b7
MI		 4929 default: break;
4930 }
4931 return 0;
4932}
4933
4934
4935/* Generate report containing info about attached sub-devices and attached
4936 i2c clients, including an indication of which attached i2c clients are
4937 actually sub-devices. */
4938static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4939 char *buf, unsigned int acnt)
4940{
4941 struct v4l2_subdev *sd;
4942 unsigned int tcnt = 0;
4943 unsigned int ccnt;
4944 struct i2c_client *client;
2eb563b7
MI		 4945 const char *p;
4946 unsigned int id;
4947
fa7ce764 4948 ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
2eb563b7
MI		 4949 tcnt += ccnt;
4950 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4951 id = sd->grp_id;
4952 p = NULL;
4953 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4954 if (p) {
fa7ce764 4955 ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s:", p);
2eb563b7
MI		 4956 tcnt += ccnt;
4957 } else {
4958 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
fa7ce764 4959 " (unknown id=%u):", id);
2eb563b7
MI		 4960 tcnt += ccnt;
4961 }
fa7ce764
JD		 4962 client = v4l2_get_subdevdata(sd);
4963 if (client) {
4964 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4965 " %s @ %02x\n", client->name,
4966 client->addr);
4967 tcnt += ccnt;
4968 } else {
4969 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4970 " no i2c client\n");
4971 tcnt += ccnt;
858f910e 4972 }
681c7399 4973 }
2eb563b7 4974 return tcnt;
681c7399
MI		 4975}
4976
4977
4978unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4979 char *buf,unsigned int acnt)
4980{
4981 unsigned int bcnt,ccnt,idx;
4982 bcnt = 0;
4983 LOCK_TAKE(hdw->big_lock);
4984 for (idx = 0; ; idx++) {
4985 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4986 if (!ccnt) break;
4987 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4988 if (!acnt) break;
4989 buf[0] = '\n'; ccnt = 1;
4990 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4991 }
2eb563b7
MI		 4992 ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4993 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
681c7399
MI		 4994 LOCK_GIVE(hdw->big_lock);
4995 return bcnt;
4996}
4997
4998
4999static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
5000{
2eb563b7
MI		 5001 char buf[256];
5002 unsigned int idx, ccnt;
5003 unsigned int lcnt, ucnt;
681c7399
MI		 5004
5005 for (idx = 0; ; idx++) {
5006 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
5007 if (!ccnt) break;
5008 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
5009 }
2eb563b7
MI		 5010 ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
5011 ucnt = 0;
5012 while (ucnt < ccnt) {
5013 lcnt = 0;
5014 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
5015 lcnt++;
5016 }
5017 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
5018 ucnt += lcnt + 1;
5019 }
681c7399
MI		 5020}
5021
5022
5023/* Evaluate and update the driver's current state, taking various actions
5024 as appropriate for the update. */
5025static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
5026{
5027 unsigned int st;
5028 int state_updated = 0;
5029 int callback_flag = 0;
1b9c18c5 5030 int analog_mode;
681c7399
MI		 5031
5032 pvr2_trace(PVR2_TRACE_STBITS,
5033 "Drive state check START");
5034 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5035 pvr2_hdw_state_log_state(hdw);
5036 }
5037
5038 /* Process all state and get back over disposition */
5039 state_updated = pvr2_hdw_state_update(hdw);
5040
1b9c18c5
MI		 5041 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
5042
681c7399
MI		 5043 /* Update master state based upon all other states. */
5044 if (!hdw->flag_ok) {
5045 st = PVR2_STATE_DEAD;
5046 } else if (hdw->fw1_state != FW1_STATE_OK) {
5047 st = PVR2_STATE_COLD;
72998b71
MI		 5048 } else if ((analog_mode ||
5049 hdw->hdw_desc->flag_digital_requires_cx23416) &&
5050 !hdw->state_encoder_ok) {
681c7399 5051 st = PVR2_STATE_WARM;
1b9c18c5
MI		 5052 } else if (hdw->flag_tripped ||
5053 (analog_mode && hdw->flag_decoder_missed)) {
681c7399 5054 st = PVR2_STATE_ERROR;
62433e31 5055 } else if (hdw->state_usbstream_run &&
1b9c18c5 5056 (!analog_mode ||
62433e31 5057 (hdw->state_encoder_run && hdw->state_decoder_run))) {
681c7399
MI		 5058 st = PVR2_STATE_RUN;
5059 } else {
5060 st = PVR2_STATE_READY;
5061 }
5062 if (hdw->master_state != st) {
5063 pvr2_trace(PVR2_TRACE_STATE,
5064 "Device state change from %s to %s",
5065 pvr2_get_state_name(hdw->master_state),
5066 pvr2_get_state_name(st));
40381cb0 5067 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
681c7399
MI		 5068 hdw->master_state = st;
5069 state_updated = !0;
5070 callback_flag = !0;
5071 }
5072 if (state_updated) {
5073 /* Trigger anyone waiting on any state changes here. */
5074 wake_up(&hdw->state_wait_data);
5075 }
5076
5077 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5078 pvr2_hdw_state_log_state(hdw);
5079 }
5080 pvr2_trace(PVR2_TRACE_STBITS,
5081 "Drive state check DONE callback=%d",callback_flag);
5082
5083 return callback_flag;
5084}
5085
5086
5087/* Cause kernel thread to check / update driver state */
5088static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
5089{
5090 if (hdw->state_stale) return;
5091 hdw->state_stale = !0;
5092 trace_stbit("state_stale",hdw->state_stale);
5093 queue_work(hdw->workqueue,&hdw->workpoll);
5094}
5095
5096
d855497e
MI		 5097int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
5098{
5099 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5100}
5101
5102
5103int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5104{
5105 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5106}
5107
5108
5109int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5110{
5111 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5112}
5113
5114
5115int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5116{
5117 u32 cval,nval;
5118 int ret;
5119 if (~msk) {
5120 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5121 if (ret) return ret;
5122 nval = (cval & ~msk) | (val & msk);
5123 pvr2_trace(PVR2_TRACE_GPIO,
5124 "GPIO direction changing 0x%x:0x%x"
5125 " from 0x%x to 0x%x",
5126 msk,val,cval,nval);
5127 } else {
5128 nval = val;
5129 pvr2_trace(PVR2_TRACE_GPIO,
5130 "GPIO direction changing to 0x%x",nval);
5131 }
5132 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5133}
5134
5135
5136int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5137{
5138 u32 cval,nval;
5139 int ret;
5140 if (~msk) {
5141 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5142 if (ret) return ret;
5143 nval = (cval & ~msk) | (val & msk);
5144 pvr2_trace(PVR2_TRACE_GPIO,
5145 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5146 msk,val,cval,nval);
5147 } else {
5148 nval = val;
5149 pvr2_trace(PVR2_TRACE_GPIO,
5150 "GPIO output changing to 0x%x",nval);
5151 }
5152 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5153}
5154
5155
a51f5000
MI		 5156void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5157{
40f07111
MI		 5158 struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5159 memset(vtp, 0, sizeof(*vtp));
2641df36 5160 hdw->tuner_signal_stale = 0;
40f07111
MI		 5161 /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5162 using v4l2-subdev - therefore we can't support that AT ALL right
5163 now. (Of course, no sub-drivers seem to implement it either.
5164 But now it's a a chicken and egg problem...) */
4cfe3319 5165 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp);
2641df36 5166 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
40f07111
MI		 5167 " type=%u strength=%u audio=0x%x cap=0x%x"
5168 " low=%u hi=%u",
5169 vtp->type,
5170 vtp->signal, vtp->rxsubchans, vtp->capability,
5171 vtp->rangelow, vtp->rangehigh);
2641df36
MI		 5172
5173 /* We have to do this to avoid getting into constant polling if
5174 there's nobody to answer a poll of cropcap info. */
5175 hdw->cropcap_stale = 0;
a51f5000
MI		 5176}
5177
5178
7fb20fa3
MI		 5179unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5180{
5181 return hdw->input_avail_mask;
5182}
5183
5184
1cb03b76
MI		 5185unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5186{
5187 return hdw->input_allowed_mask;
5188}
5189
5190
5191static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5192{
5193 if (hdw->input_val != v) {
5194 hdw->input_val = v;
5195 hdw->input_dirty = !0;
5196 }
5197
5198 /* Handle side effects - if we switch to a mode that needs the RF
5199 tuner, then select the right frequency choice as well and mark
5200 it dirty. */
5201 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5202 hdw->freqSelector = 0;
5203 hdw->freqDirty = !0;
5204 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5205 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5206 hdw->freqSelector = 1;
5207 hdw->freqDirty = !0;
5208 }
5209 return 0;
5210}
5211
5212
5213int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5214 unsigned int change_mask,
5215 unsigned int change_val)
5216{
5217 int ret = 0;
5218 unsigned int nv,m,idx;
5219 LOCK_TAKE(hdw->big_lock);
5220 do {
5221 nv = hdw->input_allowed_mask & ~change_mask;
5222 nv |= (change_val & change_mask);
5223 nv &= hdw->input_avail_mask;
5224 if (!nv) {
5225 /* No legal modes left; return error instead. */
5226 ret = -EPERM;
5227 break;
5228 }
5229 hdw->input_allowed_mask = nv;
5230 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5231 /* Current mode is still in the allowed mask, so
5232 we're done. */
5233 break;
5234 }
5235 /* Select and switch to a mode that is still in the allowed
5236 mask */
5237 if (!hdw->input_allowed_mask) {
5238 /* Nothing legal; give up */
5239 break;
5240 }
5241 m = hdw->input_allowed_mask;
5242 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5243 if (!((1 << idx) & m)) continue;
5244 pvr2_hdw_set_input(hdw,idx);
5245 break;
5246 }
5247 } while (0);
5248 LOCK_GIVE(hdw->big_lock);
5249 return ret;
5250}
5251
5252
e61b6fc5 5253/* Find I2C address of eeprom */
07e337ee 5254static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 5255{
5256 int result;
5257 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 5258 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 5259 result = pvr2_send_request(hdw,
5260 hdw->cmd_buffer,1,
5261 hdw->cmd_buffer,1);
5262 if (result < 0) break;
5263 result = hdw->cmd_buffer[0];
5264 } while(0); LOCK_GIVE(hdw->ctl_lock);
5265 return result;
5266}
5267
5268
32ffa9ae 5269int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
aecde8b5
HV		 5270 struct v4l2_dbg_match *match, u64 reg_id,
5271 int setFl, u64 *val_ptr)
32ffa9ae
MI		 5272{
5273#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 5274 struct v4l2_dbg_register req;
6d98816f
MI		 5275 int stat = 0;
5276 int okFl = 0;
32ffa9ae 5277
201f5c9c
MI		 5278 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5279
aecde8b5 5280 req.match = *match;
32ffa9ae
MI		 5281 req.reg = reg_id;
5282 if (setFl) req.val = *val_ptr;
d8f5b9ba
MI		 5283 /* It would be nice to know if a sub-device answered the request */
5284 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5285 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 5286 if (okFl) {
5287 return stat;
5288 }
32ffa9ae
MI		 5289 return -EINVAL;
5290#else
5291 return -ENOSYS;
5292#endif
5293}
5294
5295
d855497e
MI		 5296/*
5297 Stuff for Emacs to see, in order to encourage consistent editing style:
5298 *** Local Variables: ***
5299 *** mode: c ***
5300 *** fill-column: 75 ***
5301 *** tab-width: 8 ***
5302 *** c-basic-offset: 8 ***
5303 *** End: ***
5304 */
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