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V4L/DVB (6696): pvrusb2: Miscellaneous tweaks for controlling tuner type and video...
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
3 * $Id$
4 *
5 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#include <linux/errno.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/firmware.h>
d855497e 26#include <linux/videodev2.h>
32ffa9ae 27#include <media/v4l2-common.h>
b2bbaa93 28#include <asm/semaphore.h>
d855497e
MI		 29#include "pvrusb2.h"
30#include "pvrusb2-std.h"
31#include "pvrusb2-util.h"
32#include "pvrusb2-hdw.h"
33#include "pvrusb2-i2c-core.h"
34#include "pvrusb2-tuner.h"
35#include "pvrusb2-eeprom.h"
36#include "pvrusb2-hdw-internal.h"
37#include "pvrusb2-encoder.h"
38#include "pvrusb2-debug.h"
8d364363 39#include "pvrusb2-fx2-cmd.h"
d855497e 40
1bde0289
MI		 41#define TV_MIN_FREQ 55250000L
42#define TV_MAX_FREQ 850000000L
25d8527a 43
a0fd1cb1 44static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 45static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e
MI		 46
47static int ctlchg = 0;
48static int initusbreset = 1;
49static int procreload = 0;
50static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
51static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
52static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
53static int init_pause_msec = 0;
54
55module_param(ctlchg, int, S_IRUGO|S_IWUSR);
56MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
57module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
58MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
59module_param(initusbreset, int, S_IRUGO|S_IWUSR);
60MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
61module_param(procreload, int, S_IRUGO|S_IWUSR);
62MODULE_PARM_DESC(procreload,
63 "Attempt init failure recovery with firmware reload");
64module_param_array(tuner, int, NULL, 0444);
65MODULE_PARM_DESC(tuner,"specify installed tuner type");
66module_param_array(video_std, int, NULL, 0444);
67MODULE_PARM_DESC(video_std,"specify initial video standard");
68module_param_array(tolerance, int, NULL, 0444);
69MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
70
71#define PVR2_CTL_WRITE_ENDPOINT 0x01
72#define PVR2_CTL_READ_ENDPOINT 0x81
73
74#define PVR2_GPIO_IN 0x9008
75#define PVR2_GPIO_OUT 0x900c
76#define PVR2_GPIO_DIR 0x9020
77
78#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
79
80#define PVR2_FIRMWARE_ENDPOINT 0x02
81
82/* size of a firmware chunk */
83#define FIRMWARE_CHUNK_SIZE 0x2000
84
b30d2441
MI		 85/* Define the list of additional controls we'll dynamically construct based
86 on query of the cx2341x module. */
87struct pvr2_mpeg_ids {
88 const char *strid;
89 int id;
90};
91static const struct pvr2_mpeg_ids mpeg_ids[] = {
92 {
93 .strid = "audio_layer",
94 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
95 },{
96 .strid = "audio_bitrate",
97 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
98 },{
99 /* Already using audio_mode elsewhere :-( */
100 .strid = "mpeg_audio_mode",
101 .id = V4L2_CID_MPEG_AUDIO_MODE,
102 },{
103 .strid = "mpeg_audio_mode_extension",
104 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
105 },{
106 .strid = "audio_emphasis",
107 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
108 },{
109 .strid = "audio_crc",
110 .id = V4L2_CID_MPEG_AUDIO_CRC,
111 },{
112 .strid = "video_aspect",
113 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
114 },{
115 .strid = "video_b_frames",
116 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
117 },{
118 .strid = "video_gop_size",
119 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
120 },{
121 .strid = "video_gop_closure",
122 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 123 },{
124 .strid = "video_bitrate_mode",
125 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
126 },{
127 .strid = "video_bitrate",
128 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
129 },{
130 .strid = "video_bitrate_peak",
131 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
132 },{
133 .strid = "video_temporal_decimation",
134 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
135 },{
136 .strid = "stream_type",
137 .id = V4L2_CID_MPEG_STREAM_TYPE,
138 },{
139 .strid = "video_spatial_filter_mode",
140 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
141 },{
142 .strid = "video_spatial_filter",
143 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
144 },{
145 .strid = "video_luma_spatial_filter_type",
146 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
147 },{
148 .strid = "video_chroma_spatial_filter_type",
149 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
150 },{
151 .strid = "video_temporal_filter_mode",
152 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
153 },{
154 .strid = "video_temporal_filter",
155 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
156 },{
157 .strid = "video_median_filter_type",
158 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
159 },{
160 .strid = "video_luma_median_filter_top",
161 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
162 },{
163 .strid = "video_luma_median_filter_bottom",
164 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
165 },{
166 .strid = "video_chroma_median_filter_top",
167 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
168 },{
169 .strid = "video_chroma_median_filter_bottom",
170 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
171 }
172};
eca8ebfc 173#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 174
434449f4 175
d855497e 176static const char *control_values_srate[] = {
434449f4
MI		 177 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
178 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
179 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 180};
181
182
d855497e 183
d855497e
MI		 184static const char *control_values_input[] = {
185 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
186 [PVR2_CVAL_INPUT_RADIO] = "radio",
187 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
188 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
189};
190
191
192static const char *control_values_audiomode[] = {
193 [V4L2_TUNER_MODE_MONO] = "Mono",
194 [V4L2_TUNER_MODE_STEREO] = "Stereo",
195 [V4L2_TUNER_MODE_LANG1] = "Lang1",
196 [V4L2_TUNER_MODE_LANG2] = "Lang2",
197 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
198};
199
200
201static const char *control_values_hsm[] = {
202 [PVR2_CVAL_HSM_FAIL] = "Fail",
203 [PVR2_CVAL_HSM_HIGH] = "High",
204 [PVR2_CVAL_HSM_FULL] = "Full",
205};
206
207
681c7399
MI		 208static const char *pvr2_state_names[] = {
209 [PVR2_STATE_NONE] = "none",
210 [PVR2_STATE_DEAD] = "dead",
211 [PVR2_STATE_COLD] = "cold",
212 [PVR2_STATE_WARM] = "warm",
213 [PVR2_STATE_ERROR] = "error",
214 [PVR2_STATE_READY] = "ready",
215 [PVR2_STATE_RUN] = "run",
d855497e
MI		 216};
217
681c7399
MI		 218
219static void pvr2_hdw_state_sched(struct pvr2_hdw *);
220static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 221static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399
MI		 222static void pvr2_hdw_worker_i2c(struct work_struct *work);
223static void pvr2_hdw_worker_poll(struct work_struct *work);
224static void pvr2_hdw_worker_init(struct work_struct *work);
225static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
226static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
227static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 228static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 229static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 230static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 231static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
232static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
681c7399
MI		 233static void pvr2_hdw_quiescent_timeout(unsigned long);
234static void pvr2_hdw_encoder_wait_timeout(unsigned long);
07e337ee
AB		 235static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
236 unsigned int timeout,int probe_fl,
237 void *write_data,unsigned int write_len,
238 void *read_data,unsigned int read_len);
d855497e 239
681c7399
MI		 240
241static void trace_stbit(const char *name,int val)
242{
243 pvr2_trace(PVR2_TRACE_STBITS,
244 "State bit %s <-- %s",
245 name,(val ? "true" : "false"));
246}
247
d855497e
MI		 248static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
249{
250 struct pvr2_hdw *hdw = cptr->hdw;
251 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
252 *vp = hdw->freqTable[hdw->freqProgSlot-1];
253 } else {
254 *vp = 0;
255 }
256 return 0;
257}
258
259static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
260{
261 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 262 unsigned int slotId = hdw->freqProgSlot;
263 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
264 hdw->freqTable[slotId-1] = v;
265 /* Handle side effects correctly - if we're tuned to this
266 slot, then forgot the slot id relation since the stored
267 frequency has been changed. */
268 if (hdw->freqSelector) {
269 if (hdw->freqSlotRadio == slotId) {
270 hdw->freqSlotRadio = 0;
271 }
272 } else {
273 if (hdw->freqSlotTelevision == slotId) {
274 hdw->freqSlotTelevision = 0;
275 }
276 }
d855497e
MI		 277 }
278 return 0;
279}
280
281static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
282{
283 *vp = cptr->hdw->freqProgSlot;
284 return 0;
285}
286
287static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
288{
289 struct pvr2_hdw *hdw = cptr->hdw;
290 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
291 hdw->freqProgSlot = v;
292 }
293 return 0;
294}
295
296static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
297{
1bde0289
MI		 298 struct pvr2_hdw *hdw = cptr->hdw;
299 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 300 return 0;
301}
302
1bde0289 303static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 304{
305 unsigned freq = 0;
306 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 307 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
308 if (slotId > 0) {
309 freq = hdw->freqTable[slotId-1];
310 if (!freq) return 0;
311 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 312 }
1bde0289
MI		 313 if (hdw->freqSelector) {
314 hdw->freqSlotRadio = slotId;
315 } else {
316 hdw->freqSlotTelevision = slotId;
d855497e
MI		 317 }
318 return 0;
319}
320
321static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
322{
1bde0289 323 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 324 return 0;
325}
326
327static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
328{
329 return cptr->hdw->freqDirty != 0;
330}
331
332static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
333{
334 cptr->hdw->freqDirty = 0;
335}
336
337static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
338{
1bde0289 339 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 340 return 0;
341}
342
3ad9fc37
MI		 343static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
344{
345 /* Actual maximum depends on the video standard in effect. */
346 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
347 *vp = 480;
348 } else {
349 *vp = 576;
350 }
351 return 0;
352}
353
354static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
355{
989eb154
MI		 356 /* Actual minimum depends on device digitizer type. */
357 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 358 *vp = 75;
359 } else {
360 *vp = 17;
361 }
362 return 0;
363}
364
1bde0289 365static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 366{
1bde0289
MI		 367 *vp = cptr->hdw->input_val;
368 return 0;
369}
370
371static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
372{
373 struct pvr2_hdw *hdw = cptr->hdw;
374
375 if (hdw->input_val != v) {
376 hdw->input_val = v;
377 hdw->input_dirty = !0;
378 }
379
380 /* Handle side effects - if we switch to a mode that needs the RF
381 tuner, then select the right frequency choice as well and mark
382 it dirty. */
383 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
384 hdw->freqSelector = 0;
385 hdw->freqDirty = !0;
386 } else if (hdw->input_val == PVR2_CVAL_INPUT_TV) {
387 hdw->freqSelector = 1;
388 hdw->freqDirty = !0;
5549f54f 389 }
1bde0289
MI		 390 return 0;
391}
392
393static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
394{
395 return cptr->hdw->input_dirty != 0;
396}
397
398static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
399{
400 cptr->hdw->input_dirty = 0;
401}
402
5549f54f 403
25d8527a
PK		 404static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
405{
644afdb9
MI		 406 unsigned long fv;
407 struct pvr2_hdw *hdw = cptr->hdw;
408 if (hdw->tuner_signal_stale) {
409 pvr2_i2c_core_status_poll(hdw);
410 }
411 fv = hdw->tuner_signal_info.rangehigh;
412 if (!fv) {
413 /* Safety fallback */
25d8527a 414 *vp = TV_MAX_FREQ;
644afdb9 415 return 0;
25d8527a 416 }
644afdb9
MI		 417 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
418 fv = (fv * 125) / 2;
419 } else {
420 fv = fv * 62500;
421 }
422 *vp = fv;
25d8527a
PK		 423 return 0;
424}
425
426static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
427{
644afdb9
MI		 428 unsigned long fv;
429 struct pvr2_hdw *hdw = cptr->hdw;
430 if (hdw->tuner_signal_stale) {
431 pvr2_i2c_core_status_poll(hdw);
432 }
433 fv = hdw->tuner_signal_info.rangelow;
434 if (!fv) {
435 /* Safety fallback */
25d8527a 436 *vp = TV_MIN_FREQ;
644afdb9
MI		 437 return 0;
438 }
439 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
440 fv = (fv * 125) / 2;
441 } else {
442 fv = fv * 62500;
25d8527a 443 }
644afdb9 444 *vp = fv;
25d8527a
PK		 445 return 0;
446}
447
b30d2441
MI		 448static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
449{
450 return cptr->hdw->enc_stale != 0;
451}
452
453static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
454{
455 cptr->hdw->enc_stale = 0;
681c7399 456 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 457}
458
459static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
460{
461 int ret;
462 struct v4l2_ext_controls cs;
463 struct v4l2_ext_control c1;
464 memset(&cs,0,sizeof(cs));
465 memset(&c1,0,sizeof(c1));
466 cs.controls = &c1;
467 cs.count = 1;
468 c1.id = cptr->info->v4l_id;
01f1e44f 469 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 470 VIDIOC_G_EXT_CTRLS);
471 if (ret) return ret;
472 *vp = c1.value;
473 return 0;
474}
475
476static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
477{
478 int ret;
681c7399 479 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 480 struct v4l2_ext_controls cs;
481 struct v4l2_ext_control c1;
482 memset(&cs,0,sizeof(cs));
483 memset(&c1,0,sizeof(c1));
484 cs.controls = &c1;
485 cs.count = 1;
486 c1.id = cptr->info->v4l_id;
487 c1.value = v;
681c7399
MI		 488 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
489 hdw->state_encoder_run, &cs,
b30d2441 490 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 491 if (ret == -EBUSY) {
492 /* Oops. cx2341x is telling us it's not safe to change
493 this control while we're capturing. Make a note of this
494 fact so that the pipeline will be stopped the next time
495 controls are committed. Then go on ahead and store this
496 change anyway. */
497 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
498 0, &cs,
499 VIDIOC_S_EXT_CTRLS);
500 if (!ret) hdw->enc_unsafe_stale = !0;
501 }
b30d2441 502 if (ret) return ret;
681c7399 503 hdw->enc_stale = !0;
b30d2441
MI		 504 return 0;
505}
506
507static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
508{
509 struct v4l2_queryctrl qctrl;
510 struct pvr2_ctl_info *info;
511 qctrl.id = cptr->info->v4l_id;
512 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
513 /* Strip out the const so we can adjust a function pointer. It's
514 OK to do this here because we know this is a dynamically created
515 control, so the underlying storage for the info pointer is (a)
516 private to us, and (b) not in read-only storage. Either we do
517 this or we significantly complicate the underlying control
518 implementation. */
519 info = (struct pvr2_ctl_info *)(cptr->info);
520 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
521 if (info->set_value) {
a0fd1cb1 522 info->set_value = NULL;
b30d2441
MI		 523 }
524 } else {
525 if (!(info->set_value)) {
526 info->set_value = ctrl_cx2341x_set;
527 }
528 }
529 return qctrl.flags;
530}
531
d855497e
MI		 532static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
533{
681c7399
MI		 534 *vp = cptr->hdw->state_pipeline_req;
535 return 0;
536}
537
538static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
539{
540 *vp = cptr->hdw->master_state;
d855497e
MI		 541 return 0;
542}
543
544static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
545{
546 int result = pvr2_hdw_is_hsm(cptr->hdw);
547 *vp = PVR2_CVAL_HSM_FULL;
548 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
549 if (result) *vp = PVR2_CVAL_HSM_HIGH;
550 return 0;
551}
552
553static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
554{
555 *vp = cptr->hdw->std_mask_avail;
556 return 0;
557}
558
559static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
560{
561 struct pvr2_hdw *hdw = cptr->hdw;
562 v4l2_std_id ns;
563 ns = hdw->std_mask_avail;
564 ns = (ns & ~m) | (v & m);
565 if (ns == hdw->std_mask_avail) return 0;
566 hdw->std_mask_avail = ns;
567 pvr2_hdw_internal_set_std_avail(hdw);
568 pvr2_hdw_internal_find_stdenum(hdw);
569 return 0;
570}
571
572static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
573 char *bufPtr,unsigned int bufSize,
574 unsigned int *len)
575{
576 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
577 return 0;
578}
579
580static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
581 const char *bufPtr,unsigned int bufSize,
582 int *mskp,int *valp)
583{
584 int ret;
585 v4l2_std_id id;
586 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
587 if (ret < 0) return ret;
588 if (mskp) *mskp = id;
589 if (valp) *valp = id;
590 return 0;
591}
592
593static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
594{
595 *vp = cptr->hdw->std_mask_cur;
596 return 0;
597}
598
599static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
600{
601 struct pvr2_hdw *hdw = cptr->hdw;
602 v4l2_std_id ns;
603 ns = hdw->std_mask_cur;
604 ns = (ns & ~m) | (v & m);
605 if (ns == hdw->std_mask_cur) return 0;
606 hdw->std_mask_cur = ns;
607 hdw->std_dirty = !0;
608 pvr2_hdw_internal_find_stdenum(hdw);
609 return 0;
610}
611
612static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
613{
614 return cptr->hdw->std_dirty != 0;
615}
616
617static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
618{
619 cptr->hdw->std_dirty = 0;
620}
621
622static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
623{
18103c57
MI		 624 struct pvr2_hdw *hdw = cptr->hdw;
625 pvr2_i2c_core_status_poll(hdw);
626 *vp = hdw->tuner_signal_info.signal;
627 return 0;
628}
629
630static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
631{
632 int val = 0;
633 unsigned int subchan;
634 struct pvr2_hdw *hdw = cptr->hdw;
644afdb9 635 pvr2_i2c_core_status_poll(hdw);
18103c57
MI		 636 subchan = hdw->tuner_signal_info.rxsubchans;
637 if (subchan & V4L2_TUNER_SUB_MONO) {
638 val |= (1 << V4L2_TUNER_MODE_MONO);
639 }
640 if (subchan & V4L2_TUNER_SUB_STEREO) {
641 val |= (1 << V4L2_TUNER_MODE_STEREO);
642 }
643 if (subchan & V4L2_TUNER_SUB_LANG1) {
644 val |= (1 << V4L2_TUNER_MODE_LANG1);
645 }
646 if (subchan & V4L2_TUNER_SUB_LANG2) {
647 val |= (1 << V4L2_TUNER_MODE_LANG2);
648 }
649 *vp = val;
d855497e
MI		 650 return 0;
651}
652
d855497e
MI		 653
654static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
655{
656 struct pvr2_hdw *hdw = cptr->hdw;
657 if (v < 0) return -EINVAL;
658 if (v > hdw->std_enum_cnt) return -EINVAL;
659 hdw->std_enum_cur = v;
660 if (!v) return 0;
661 v--;
662 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
663 hdw->std_mask_cur = hdw->std_defs[v].id;
664 hdw->std_dirty = !0;
665 return 0;
666}
667
668
669static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
670{
671 *vp = cptr->hdw->std_enum_cur;
672 return 0;
673}
674
675
676static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
677{
678 return cptr->hdw->std_dirty != 0;
679}
680
681
682static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
683{
684 cptr->hdw->std_dirty = 0;
685}
686
687
688#define DEFINT(vmin,vmax) \
689 .type = pvr2_ctl_int, \
690 .def.type_int.min_value = vmin, \
691 .def.type_int.max_value = vmax
692
693#define DEFENUM(tab) \
694 .type = pvr2_ctl_enum, \
27c7b710 695 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 696 .def.type_enum.value_names = tab
697
33213963
MI		 698#define DEFBOOL \
699 .type = pvr2_ctl_bool
700
d855497e
MI		 701#define DEFMASK(msk,tab) \
702 .type = pvr2_ctl_bitmask, \
703 .def.type_bitmask.valid_bits = msk, \
704 .def.type_bitmask.bit_names = tab
705
706#define DEFREF(vname) \
707 .set_value = ctrl_set_##vname, \
708 .get_value = ctrl_get_##vname, \
709 .is_dirty = ctrl_isdirty_##vname, \
710 .clear_dirty = ctrl_cleardirty_##vname
711
712
713#define VCREATE_FUNCS(vname) \
714static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
715{*vp = cptr->hdw->vname##_val; return 0;} \
716static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
717{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
718static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
719{return cptr->hdw->vname##_dirty != 0;} \
720static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
721{cptr->hdw->vname##_dirty = 0;}
722
723VCREATE_FUNCS(brightness)
724VCREATE_FUNCS(contrast)
725VCREATE_FUNCS(saturation)
726VCREATE_FUNCS(hue)
727VCREATE_FUNCS(volume)
728VCREATE_FUNCS(balance)
729VCREATE_FUNCS(bass)
730VCREATE_FUNCS(treble)
731VCREATE_FUNCS(mute)
c05c0462
MI		 732VCREATE_FUNCS(audiomode)
733VCREATE_FUNCS(res_hor)
734VCREATE_FUNCS(res_ver)
d855497e 735VCREATE_FUNCS(srate)
d855497e 736
d855497e
MI		 737/* Table definition of all controls which can be manipulated */
738static const struct pvr2_ctl_info control_defs[] = {
739 {
740 .v4l_id = V4L2_CID_BRIGHTNESS,
741 .desc = "Brightness",
742 .name = "brightness",
743 .default_value = 128,
744 DEFREF(brightness),
745 DEFINT(0,255),
746 },{
747 .v4l_id = V4L2_CID_CONTRAST,
748 .desc = "Contrast",
749 .name = "contrast",
750 .default_value = 68,
751 DEFREF(contrast),
752 DEFINT(0,127),
753 },{
754 .v4l_id = V4L2_CID_SATURATION,
755 .desc = "Saturation",
756 .name = "saturation",
757 .default_value = 64,
758 DEFREF(saturation),
759 DEFINT(0,127),
760 },{
761 .v4l_id = V4L2_CID_HUE,
762 .desc = "Hue",
763 .name = "hue",
764 .default_value = 0,
765 DEFREF(hue),
766 DEFINT(-128,127),
767 },{
768 .v4l_id = V4L2_CID_AUDIO_VOLUME,
769 .desc = "Volume",
770 .name = "volume",
139eecf9 771 .default_value = 62000,
d855497e
MI		 772 DEFREF(volume),
773 DEFINT(0,65535),
774 },{
775 .v4l_id = V4L2_CID_AUDIO_BALANCE,
776 .desc = "Balance",
777 .name = "balance",
778 .default_value = 0,
779 DEFREF(balance),
780 DEFINT(-32768,32767),
781 },{
782 .v4l_id = V4L2_CID_AUDIO_BASS,
783 .desc = "Bass",
784 .name = "bass",
785 .default_value = 0,
786 DEFREF(bass),
787 DEFINT(-32768,32767),
788 },{
789 .v4l_id = V4L2_CID_AUDIO_TREBLE,
790 .desc = "Treble",
791 .name = "treble",
792 .default_value = 0,
793 DEFREF(treble),
794 DEFINT(-32768,32767),
795 },{
796 .v4l_id = V4L2_CID_AUDIO_MUTE,
797 .desc = "Mute",
798 .name = "mute",
799 .default_value = 0,
800 DEFREF(mute),
33213963 801 DEFBOOL,
c05c0462
MI		 802 },{
803 .desc = "Video Source",
804 .name = "input",
805 .internal_id = PVR2_CID_INPUT,
806 .default_value = PVR2_CVAL_INPUT_TV,
807 DEFREF(input),
808 DEFENUM(control_values_input),
809 },{
810 .desc = "Audio Mode",
811 .name = "audio_mode",
812 .internal_id = PVR2_CID_AUDIOMODE,
813 .default_value = V4L2_TUNER_MODE_STEREO,
814 DEFREF(audiomode),
815 DEFENUM(control_values_audiomode),
816 },{
817 .desc = "Horizontal capture resolution",
818 .name = "resolution_hor",
819 .internal_id = PVR2_CID_HRES,
820 .default_value = 720,
821 DEFREF(res_hor),
3ad9fc37 822 DEFINT(19,720),
c05c0462
MI		 823 },{
824 .desc = "Vertical capture resolution",
825 .name = "resolution_ver",
826 .internal_id = PVR2_CID_VRES,
827 .default_value = 480,
828 DEFREF(res_ver),
3ad9fc37
MI		 829 DEFINT(17,576),
830 /* Hook in check for video standard and adjust maximum
831 depending on the standard. */
832 .get_max_value = ctrl_vres_max_get,
833 .get_min_value = ctrl_vres_min_get,
d855497e 834 },{
b30d2441 835 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 836 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
837 .desc = "Audio Sampling Frequency",
d855497e 838 .name = "srate",
d855497e
MI		 839 DEFREF(srate),
840 DEFENUM(control_values_srate),
d855497e
MI		 841 },{
842 .desc = "Tuner Frequency (Hz)",
843 .name = "frequency",
844 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 845 .default_value = 0,
d855497e
MI		 846 .set_value = ctrl_freq_set,
847 .get_value = ctrl_freq_get,
848 .is_dirty = ctrl_freq_is_dirty,
849 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 850 DEFINT(0,0),
25d8527a
PK		 851 /* Hook in check for input value (tv/radio) and adjust
852 max/min values accordingly */
853 .get_max_value = ctrl_freq_max_get,
854 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 855 },{
856 .desc = "Channel",
857 .name = "channel",
858 .set_value = ctrl_channel_set,
859 .get_value = ctrl_channel_get,
860 DEFINT(0,FREQTABLE_SIZE),
861 },{
862 .desc = "Channel Program Frequency",
863 .name = "freq_table_value",
864 .set_value = ctrl_channelfreq_set,
865 .get_value = ctrl_channelfreq_get,
644afdb9 866 DEFINT(0,0),
1bde0289
MI		 867 /* Hook in check for input value (tv/radio) and adjust
868 max/min values accordingly */
1bde0289
MI		 869 .get_max_value = ctrl_freq_max_get,
870 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 871 },{
872 .desc = "Channel Program ID",
873 .name = "freq_table_channel",
874 .set_value = ctrl_channelprog_set,
875 .get_value = ctrl_channelprog_get,
876 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 877 },{
878 .desc = "Streaming Enabled",
879 .name = "streaming_enabled",
880 .get_value = ctrl_streamingenabled_get,
33213963 881 DEFBOOL,
d855497e
MI		 882 },{
883 .desc = "USB Speed",
884 .name = "usb_speed",
885 .get_value = ctrl_hsm_get,
886 DEFENUM(control_values_hsm),
681c7399
MI		 887 },{
888 .desc = "Master State",
889 .name = "master_state",
890 .get_value = ctrl_masterstate_get,
891 DEFENUM(pvr2_state_names),
d855497e
MI		 892 },{
893 .desc = "Signal Present",
894 .name = "signal_present",
895 .get_value = ctrl_signal_get,
18103c57
MI		 896 DEFINT(0,65535),
897 },{
898 .desc = "Audio Modes Present",
899 .name = "audio_modes_present",
900 .get_value = ctrl_audio_modes_present_get,
901 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
902 v4l. Nothing outside of this module cares about this,
903 but I reuse it in order to also reuse the
904 control_values_audiomode string table. */
905 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
906 (1 << V4L2_TUNER_MODE_STEREO)|
907 (1 << V4L2_TUNER_MODE_LANG1)|
908 (1 << V4L2_TUNER_MODE_LANG2)),
909 control_values_audiomode),
d855497e
MI		 910 },{
911 .desc = "Video Standards Available Mask",
912 .name = "video_standard_mask_available",
913 .internal_id = PVR2_CID_STDAVAIL,
914 .skip_init = !0,
915 .get_value = ctrl_stdavail_get,
916 .set_value = ctrl_stdavail_set,
917 .val_to_sym = ctrl_std_val_to_sym,
918 .sym_to_val = ctrl_std_sym_to_val,
919 .type = pvr2_ctl_bitmask,
920 },{
921 .desc = "Video Standards In Use Mask",
922 .name = "video_standard_mask_active",
923 .internal_id = PVR2_CID_STDCUR,
924 .skip_init = !0,
925 .get_value = ctrl_stdcur_get,
926 .set_value = ctrl_stdcur_set,
927 .is_dirty = ctrl_stdcur_is_dirty,
928 .clear_dirty = ctrl_stdcur_clear_dirty,
929 .val_to_sym = ctrl_std_val_to_sym,
930 .sym_to_val = ctrl_std_sym_to_val,
931 .type = pvr2_ctl_bitmask,
d855497e
MI		 932 },{
933 .desc = "Video Standard Name",
934 .name = "video_standard",
935 .internal_id = PVR2_CID_STDENUM,
936 .skip_init = !0,
937 .get_value = ctrl_stdenumcur_get,
938 .set_value = ctrl_stdenumcur_set,
939 .is_dirty = ctrl_stdenumcur_is_dirty,
940 .clear_dirty = ctrl_stdenumcur_clear_dirty,
941 .type = pvr2_ctl_enum,
942 }
943};
944
eca8ebfc 945#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 946
947
948const char *pvr2_config_get_name(enum pvr2_config cfg)
949{
950 switch (cfg) {
951 case pvr2_config_empty: return "empty";
952 case pvr2_config_mpeg: return "mpeg";
953 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 954 case pvr2_config_pcm: return "pcm";
955 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 956 }
957 return "<unknown>";
958}
959
960
961struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
962{
963 return hdw->usb_dev;
964}
965
966
967unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
968{
969 return hdw->serial_number;
970}
971
31a18547
MI		 972
973const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
974{
975 return hdw->bus_info;
976}
977
978
1bde0289
MI		 979unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
980{
981 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
982}
983
984/* Set the currently tuned frequency and account for all possible
985 driver-core side effects of this action. */
986void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
987{
7c74e57e 988 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 989 if (hdw->freqSelector) {
990 /* Swing over to radio frequency selection */
991 hdw->freqSelector = 0;
992 hdw->freqDirty = !0;
993 }
1bde0289
MI		 994 if (hdw->freqValRadio != val) {
995 hdw->freqValRadio = val;
996 hdw->freqSlotRadio = 0;
7c74e57e 997 hdw->freqDirty = !0;
1bde0289 998 }
7c74e57e 999 } else {
1bde0289
MI		 1000 if (!(hdw->freqSelector)) {
1001 /* Swing over to television frequency selection */
1002 hdw->freqSelector = 1;
1003 hdw->freqDirty = !0;
1004 }
1bde0289
MI		 1005 if (hdw->freqValTelevision != val) {
1006 hdw->freqValTelevision = val;
1007 hdw->freqSlotTelevision = 0;
7c74e57e 1008 hdw->freqDirty = !0;
1bde0289 1009 }
1bde0289
MI		 1010 }
1011}
1012
d855497e
MI		 1013int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1014{
1015 return hdw->unit_number;
1016}
1017
1018
1019/* Attempt to locate one of the given set of files. Messages are logged
1020 appropriate to what has been found. The return value will be 0 or
1021 greater on success (it will be the index of the file name found) and
1022 fw_entry will be filled in. Otherwise a negative error is returned on
1023 failure. If the return value is -ENOENT then no viable firmware file
1024 could be located. */
1025static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1026 const struct firmware **fw_entry,
1027 const char *fwtypename,
1028 unsigned int fwcount,
1029 const char *fwnames[])
1030{
1031 unsigned int idx;
1032 int ret = -EINVAL;
1033 for (idx = 0; idx < fwcount; idx++) {
1034 ret = request_firmware(fw_entry,
1035 fwnames[idx],
1036 &hdw->usb_dev->dev);
1037 if (!ret) {
1038 trace_firmware("Located %s firmware: %s;"
1039 " uploading...",
1040 fwtypename,
1041 fwnames[idx]);
1042 return idx;
1043 }
1044 if (ret == -ENOENT) continue;
1045 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1046 "request_firmware fatal error with code=%d",ret);
1047 return ret;
1048 }
1049 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1050 "***WARNING***"
1051 " Device %s firmware"
1052 " seems to be missing.",
1053 fwtypename);
1054 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1055 "Did you install the pvrusb2 firmware files"
1056 " in their proper location?");
1057 if (fwcount == 1) {
1058 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1059 "request_firmware unable to locate %s file %s",
1060 fwtypename,fwnames[0]);
1061 } else {
1062 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1063 "request_firmware unable to locate"
1064 " one of the following %s files:",
1065 fwtypename);
1066 for (idx = 0; idx < fwcount; idx++) {
1067 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1068 "request_firmware: Failed to find %s",
1069 fwnames[idx]);
1070 }
1071 }
1072 return ret;
1073}
1074
1075
1076/*
1077 * pvr2_upload_firmware1().
1078 *
1079 * Send the 8051 firmware to the device. After the upload, arrange for
1080 * device to re-enumerate.
1081 *
1082 * NOTE : the pointer to the firmware data given by request_firmware()
1083 * is not suitable for an usb transaction.
1084 *
1085 */
07e337ee 1086static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1087{
a0fd1cb1 1088 const struct firmware *fw_entry = NULL;
d855497e
MI		 1089 void *fw_ptr;
1090 unsigned int pipe;
1091 int ret;
1092 u16 address;
1d643a37 1093
989eb154 1094 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1095 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1096 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1097 "Connected device type defines"
1098 " no firmware to upload; ignoring firmware");
1099 return -ENOTTY;
1d643a37
MI		 1100 }
1101
d855497e
MI		 1102 hdw->fw1_state = FW1_STATE_FAILED; // default result
1103
1104 trace_firmware("pvr2_upload_firmware1");
1105
1106 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1107 hdw->hdw_desc->fx2_firmware.cnt,
1108 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1109 if (ret < 0) {
1110 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1111 return ret;
1112 }
1113
1114 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1115 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1116
1117 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1118
1119 if (fw_entry->size != 0x2000){
1120 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1121 release_firmware(fw_entry);
1122 return -ENOMEM;
1123 }
1124
1125 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1126 if (fw_ptr == NULL){
1127 release_firmware(fw_entry);
1128 return -ENOMEM;
1129 }
1130
1131 /* We have to hold the CPU during firmware upload. */
1132 pvr2_hdw_cpureset_assert(hdw,1);
1133
1134 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1135 chunk. */
1136
1137 ret = 0;
1138 for(address = 0; address < fw_entry->size; address += 0x800) {
1139 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1140 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1141 0, fw_ptr, 0x800, HZ);
1142 }
1143
1144 trace_firmware("Upload done, releasing device's CPU");
1145
1146 /* Now release the CPU. It will disconnect and reconnect later. */
1147 pvr2_hdw_cpureset_assert(hdw,0);
1148
1149 kfree(fw_ptr);
1150 release_firmware(fw_entry);
1151
1152 trace_firmware("Upload done (%d bytes sent)",ret);
1153
1154 /* We should have written 8192 bytes */
1155 if (ret == 8192) {
1156 hdw->fw1_state = FW1_STATE_RELOAD;
1157 return 0;
1158 }
1159
1160 return -EIO;
1161}
1162
1163
1164/*
1165 * pvr2_upload_firmware2()
1166 *
1167 * This uploads encoder firmware on endpoint 2.
1168 *
1169 */
1170
1171int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1172{
a0fd1cb1 1173 const struct firmware *fw_entry = NULL;
d855497e 1174 void *fw_ptr;
90060d32 1175 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1176 int actual_length;
1177 int ret = 0;
1178 int fwidx;
1179 static const char *fw_files[] = {
1180 CX2341X_FIRM_ENC_FILENAME,
1181 };
1182
989eb154 1183 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1184 return 0;
1185 }
1186
d855497e
MI		 1187 trace_firmware("pvr2_upload_firmware2");
1188
1189 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1190 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1191 if (ret < 0) return ret;
1192 fwidx = ret;
1193 ret = 0;
b30d2441
MI		 1194 /* Since we're about to completely reinitialize the encoder,
1195 invalidate our cached copy of its configuration state. Next
1196 time we configure the encoder, then we'll fully configure it. */
1197 hdw->enc_cur_valid = 0;
d855497e
MI		 1198
1199 /* First prepare firmware loading */
1200 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1201 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1202 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1203 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1204 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1205 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1206 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1207 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1208 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1209 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1210 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1211 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1212 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1213 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1214 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1215 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
567d7115
MI		 1216 LOCK_TAKE(hdw->ctl_lock); do {
1217 hdw->cmd_buffer[0] = FX2CMD_FWPOST1;
89952d13 1218 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
567d7115
MI		 1219 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1220 hdw->cmd_buffer[1] = 0;
89952d13 1221 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
567d7115 1222 } while (0); LOCK_GIVE(hdw->ctl_lock);
d855497e
MI		 1223
1224 if (ret) {
1225 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1226 "firmware2 upload prep failed, ret=%d",ret);
1227 release_firmware(fw_entry);
1228 return ret;
1229 }
1230
1231 /* Now send firmware */
1232
1233 fw_len = fw_entry->size;
1234
90060d32 1235 if (fw_len % sizeof(u32)) {
d855497e
MI		 1236 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1237 "size of %s firmware"
48dc30a1 1238 " must be a multiple of %zu bytes",
90060d32 1239 fw_files[fwidx],sizeof(u32));
d855497e
MI		 1240 release_firmware(fw_entry);
1241 return -1;
1242 }
1243
1244 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1245 if (fw_ptr == NULL){
1246 release_firmware(fw_entry);
1247 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1248 "failed to allocate memory for firmware2 upload");
1249 return -ENOMEM;
1250 }
1251
1252 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1253
90060d32
MI		 1254 fw_done = 0;
1255 for (fw_done = 0; fw_done < fw_len;) {
1256 bcnt = fw_len - fw_done;
1257 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1258 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1259 /* Usbsnoop log shows that we must swap bytes... */
1260 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1261 ((u32 *)fw_ptr)[icnt] =
1262 ___swab32(((u32 *)fw_ptr)[icnt]);
1263
1264 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1265 &actual_length, HZ);
90060d32
MI		 1266 ret |= (actual_length != bcnt);
1267 if (ret) break;
1268 fw_done += bcnt;
d855497e
MI		 1269 }
1270
1271 trace_firmware("upload of %s : %i / %i ",
1272 fw_files[fwidx],fw_done,fw_len);
1273
1274 kfree(fw_ptr);
1275 release_firmware(fw_entry);
1276
1277 if (ret) {
1278 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1279 "firmware2 upload transfer failure");
1280 return ret;
1281 }
1282
1283 /* Finish upload */
1284
1285 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1286 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
567d7115
MI		 1287 LOCK_TAKE(hdw->ctl_lock); do {
1288 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1289 hdw->cmd_buffer[1] = 0;
89952d13 1290 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
567d7115 1291 } while (0); LOCK_GIVE(hdw->ctl_lock);
d855497e
MI		 1292
1293 if (ret) {
1294 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1295 "firmware2 upload post-proc failure");
d855497e
MI		 1296 }
1297 return ret;
1298}
1299
1300
681c7399
MI		 1301static const char *pvr2_get_state_name(unsigned int st)
1302{
1303 if (st < ARRAY_SIZE(pvr2_state_names)) {
1304 return pvr2_state_names[st];
d855497e 1305 }
681c7399 1306 return "???";
d855497e
MI		 1307}
1308
681c7399 1309static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1310{
681c7399
MI		 1311 if (!hdw->decoder_ctrl) {
1312 if (!hdw->flag_decoder_missed) {
1313 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1314 "WARNING: No decoder present");
1315 hdw->flag_decoder_missed = !0;
1316 trace_stbit("flag_decoder_missed",
1317 hdw->flag_decoder_missed);
1318 }
1319 return -EIO;
1320 }
1321 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1322 return 0;
d855497e
MI		 1323}
1324
1325
681c7399 1326void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
d855497e 1327{
681c7399
MI		 1328 if (hdw->decoder_ctrl == ptr) return;
1329 hdw->decoder_ctrl = ptr;
1330 if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1331 hdw->flag_decoder_missed = 0;
1332 trace_stbit("flag_decoder_missed",
1333 hdw->flag_decoder_missed);
1334 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1335 "Decoder has appeared");
1336 pvr2_hdw_state_sched(hdw);
1337 }
d855497e
MI		 1338}
1339
1340
681c7399 1341int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1342{
681c7399 1343 return hdw->master_state;
d855497e
MI		 1344}
1345
1346
681c7399 1347static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1348{
681c7399
MI		 1349 if (!hdw->flag_tripped) return 0;
1350 hdw->flag_tripped = 0;
1351 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1352 "Clearing driver error statuss");
1353 return !0;
d855497e
MI		 1354}
1355
1356
681c7399 1357int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1358{
681c7399 1359 int fl;
d855497e 1360 LOCK_TAKE(hdw->big_lock); do {
681c7399 1361 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1362 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1363 if (fl) pvr2_hdw_state_sched(hdw);
1364 return 0;
d855497e
MI		 1365}
1366
1367
681c7399 1368const char *pvr2_hdw_get_state_name(unsigned int id)
d855497e 1369{
681c7399
MI		 1370 if (id >= ARRAY_SIZE(pvr2_state_names)) return NULL;
1371 return pvr2_state_names[id];
d855497e
MI		 1372}
1373
1374
1375int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1376{
681c7399 1377 return hdw->state_pipeline_req != 0;
d855497e
MI		 1378}
1379
1380
1381int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1382{
681c7399 1383 int ret,st;
d855497e 1384 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1385 pvr2_hdw_untrip_unlocked(hdw);
1386 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1387 hdw->state_pipeline_req = enable_flag != 0;
1388 pvr2_trace(PVR2_TRACE_START_STOP,
1389 "/*--TRACE_STREAM--*/ %s",
1390 enable_flag ? "enable" : "disable");
1391 }
1392 pvr2_hdw_state_sched(hdw);
d855497e 1393 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1394 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1395 if (enable_flag) {
1396 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1397 if (st != PVR2_STATE_READY) return -EIO;
1398 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1399 }
1400 }
d855497e
MI		 1401 return 0;
1402}
1403
1404
1405int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1406{
681c7399 1407 int fl;
d855497e 1408 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1409 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1410 hdw->desired_stream_type = config;
1411 hdw->state_pipeline_config = 0;
1412 trace_stbit("state_pipeline_config",
1413 hdw->state_pipeline_config);
1414 pvr2_hdw_state_sched(hdw);
1415 }
d855497e 1416 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1417 if (fl) return 0;
1418 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1419}
1420
1421
1422static int get_default_tuner_type(struct pvr2_hdw *hdw)
1423{
1424 int unit_number = hdw->unit_number;
1425 int tp = -1;
1426 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1427 tp = tuner[unit_number];
1428 }
1429 if (tp < 0) return -EINVAL;
1430 hdw->tuner_type = tp;
1431 return 0;
1432}
1433
1434
1435static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1436{
1437 int unit_number = hdw->unit_number;
1438 int tp = 0;
1439 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1440 tp = video_std[unit_number];
1441 }
1442 return tp;
1443}
1444
1445
1446static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1447{
1448 int unit_number = hdw->unit_number;
1449 int tp = 0;
1450 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1451 tp = tolerance[unit_number];
1452 }
1453 return tp;
1454}
1455
1456
1457static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1458{
1459 /* Try a harmless request to fetch the eeprom's address over
1460 endpoint 1. See what happens. Only the full FX2 image can
1461 respond to this. If this probe fails then likely the FX2
1462 firmware needs be loaded. */
1463 int result;
1464 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1465 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1466 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1467 hdw->cmd_buffer,1,
1468 hdw->cmd_buffer,1);
1469 if (result < 0) break;
1470 } while(0); LOCK_GIVE(hdw->ctl_lock);
1471 if (result) {
1472 pvr2_trace(PVR2_TRACE_INIT,
1473 "Probe of device endpoint 1 result status %d",
1474 result);
1475 } else {
1476 pvr2_trace(PVR2_TRACE_INIT,
1477 "Probe of device endpoint 1 succeeded");
1478 }
1479 return result == 0;
1480}
1481
9f66d4ea
MI		 1482struct pvr2_std_hack {
1483 v4l2_std_id pat; /* Pattern to match */
1484 v4l2_std_id msk; /* Which bits we care about */
1485 v4l2_std_id std; /* What additional standards or default to set */
1486};
1487
1488/* This data structure labels specific combinations of standards from
1489 tveeprom that we'll try to recognize. If we recognize one, then assume
1490 a specified default standard to use. This is here because tveeprom only
1491 tells us about available standards not the intended default standard (if
1492 any) for the device in question. We guess the default based on what has
1493 been reported as available. Note that this is only for guessing a
1494 default - which can always be overridden explicitly - and if the user
1495 has otherwise named a default then that default will always be used in
1496 place of this table. */
1497const static struct pvr2_std_hack std_eeprom_maps[] = {
1498 { /* PAL(B/G) */
1499 .pat = V4L2_STD_B|V4L2_STD_GH,
1500 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1501 },
1502 { /* NTSC(M) */
1503 .pat = V4L2_STD_MN,
1504 .std = V4L2_STD_NTSC_M,
1505 },
1506 { /* PAL(I) */
1507 .pat = V4L2_STD_PAL_I,
1508 .std = V4L2_STD_PAL_I,
1509 },
1510 { /* SECAM(L/L') */
1511 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1512 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1513 },
1514 { /* PAL(D/D1/K) */
1515 .pat = V4L2_STD_DK,
1516 .std = V4L2_STD_PAL_D/V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1517 },
1518};
1519
d855497e
MI		 1520static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1521{
1522 char buf[40];
1523 unsigned int bcnt;
1524 v4l2_std_id std1,std2;
1525
1526 std1 = get_default_standard(hdw);
1527
1528 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1529 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1530 "Supported video standard(s) reported available"
1531 " in hardware: %.*s",
d855497e
MI		 1532 bcnt,buf);
1533
1534 hdw->std_mask_avail = hdw->std_mask_eeprom;
1535
1536 std2 = std1 & ~hdw->std_mask_avail;
1537 if (std2) {
1538 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1539 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1540 "Expanding supported video standards"
1541 " to include: %.*s",
1542 bcnt,buf);
1543 hdw->std_mask_avail |= std2;
1544 }
1545
1546 pvr2_hdw_internal_set_std_avail(hdw);
1547
1548 if (std1) {
1549 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1550 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1551 "Initial video standard forced to %.*s",
1552 bcnt,buf);
1553 hdw->std_mask_cur = std1;
1554 hdw->std_dirty = !0;
1555 pvr2_hdw_internal_find_stdenum(hdw);
1556 return;
1557 }
1558
9f66d4ea
MI		 1559 {
1560 unsigned int idx;
1561 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1562 if (std_eeprom_maps[idx].msk ?
1563 ((std_eeprom_maps[idx].pat ^
1564 hdw->std_mask_eeprom) &
1565 std_eeprom_maps[idx].msk) :
1566 (std_eeprom_maps[idx].pat !=
1567 hdw->std_mask_eeprom)) continue;
1568 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1569 std_eeprom_maps[idx].std);
56585386 1570 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1571 "Initial video standard guessed as %.*s",
1572 bcnt,buf);
1573 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1574 hdw->std_dirty = !0;
1575 pvr2_hdw_internal_find_stdenum(hdw);
1576 return;
1577 }
1578 }
1579
d855497e
MI		 1580 if (hdw->std_enum_cnt > 1) {
1581 // Autoselect the first listed standard
1582 hdw->std_enum_cur = 1;
1583 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1584 hdw->std_dirty = !0;
56585386 1585 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1586 "Initial video standard auto-selected to %s",
1587 hdw->std_defs[hdw->std_enum_cur-1].name);
1588 return;
1589 }
1590
0885ba1d 1591 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1592 "Unable to select a viable initial video standard");
1593}
1594
1595
1596static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1597{
1598 int ret;
1599 unsigned int idx;
1600 struct pvr2_ctrl *cptr;
1601 int reloadFl = 0;
989eb154 1602 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 1603 if (!reloadFl) {
1604 reloadFl =
1605 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1606 == 0);
1607 if (reloadFl) {
1608 pvr2_trace(PVR2_TRACE_INIT,
1609 "USB endpoint config looks strange"
1610 "; possibly firmware needs to be"
1611 " loaded");
1612 }
d855497e 1613 }
1d643a37
MI		 1614 if (!reloadFl) {
1615 reloadFl = !pvr2_hdw_check_firmware(hdw);
1616 if (reloadFl) {
1617 pvr2_trace(PVR2_TRACE_INIT,
1618 "Check for FX2 firmware failed"
1619 "; possibly firmware needs to be"
1620 " loaded");
1621 }
d855497e 1622 }
1d643a37
MI		 1623 if (reloadFl) {
1624 if (pvr2_upload_firmware1(hdw) != 0) {
1625 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1626 "Failure uploading firmware1");
1627 }
1628 return;
d855497e 1629 }
d855497e
MI		 1630 }
1631 hdw->fw1_state = FW1_STATE_OK;
1632
1633 if (initusbreset) {
1634 pvr2_hdw_device_reset(hdw);
1635 }
1636 if (!pvr2_hdw_dev_ok(hdw)) return;
1637
989eb154
MI		 1638 for (idx = 0; idx < hdw->hdw_desc->client_modules.cnt; idx++) {
1639 request_module(hdw->hdw_desc->client_modules.lst[idx]);
d855497e
MI		 1640 }
1641
989eb154 1642 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 1643 pvr2_hdw_cmd_powerup(hdw);
1644 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 1645 }
1646
1647 // This step MUST happen after the earlier powerup step.
1648 pvr2_i2c_core_init(hdw);
1649 if (!pvr2_hdw_dev_ok(hdw)) return;
1650
c05c0462 1651 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 1652 cptr = hdw->controls + idx;
1653 if (cptr->info->skip_init) continue;
1654 if (!cptr->info->set_value) continue;
1655 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1656 }
1657
1bde0289
MI		 1658 /* Set up special default values for the television and radio
1659 frequencies here. It's not really important what these defaults
1660 are, but I set them to something usable in the Chicago area just
1661 to make driver testing a little easier. */
1662
1663 /* US Broadcast channel 7 (175.25 MHz) */
1664 hdw->freqValTelevision = 175250000L;
1665 /* 104.3 MHz, a usable FM station for my area */
1666 hdw->freqValRadio = 104300000L;
1667
d855497e
MI		 1668 // Do not use pvr2_reset_ctl_endpoints() here. It is not
1669 // thread-safe against the normal pvr2_send_request() mechanism.
1670 // (We should make it thread safe).
1671
1672 ret = pvr2_hdw_get_eeprom_addr(hdw);
1673 if (!pvr2_hdw_dev_ok(hdw)) return;
1674 if (ret < 0) {
1675 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1676 "Unable to determine location of eeprom, skipping");
1677 } else {
1678 hdw->eeprom_addr = ret;
1679 pvr2_eeprom_analyze(hdw);
1680 if (!pvr2_hdw_dev_ok(hdw)) return;
1681 }
1682
1683 pvr2_hdw_setup_std(hdw);
1684
1685 if (!get_default_tuner_type(hdw)) {
1686 pvr2_trace(PVR2_TRACE_INIT,
1687 "pvr2_hdw_setup: Tuner type overridden to %d",
1688 hdw->tuner_type);
56dcbfa0 1689 hdw->tuner_updated = !0;
d855497e
MI		 1690 }
1691
d855497e
MI		 1692 pvr2_i2c_core_check_stale(hdw);
1693 hdw->tuner_updated = 0;
1694
1695 if (!pvr2_hdw_dev_ok(hdw)) return;
1696
681c7399 1697 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 1698
1699 hdw->vid_stream = pvr2_stream_create();
1700 if (!pvr2_hdw_dev_ok(hdw)) return;
1701 pvr2_trace(PVR2_TRACE_INIT,
1702 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1703 if (hdw->vid_stream) {
1704 idx = get_default_error_tolerance(hdw);
1705 if (idx) {
1706 pvr2_trace(PVR2_TRACE_INIT,
1707 "pvr2_hdw_setup: video stream %p"
1708 " setting tolerance %u",
1709 hdw->vid_stream,idx);
1710 }
1711 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1712 PVR2_VID_ENDPOINT,idx);
1713 }
1714
1715 if (!pvr2_hdw_dev_ok(hdw)) return;
1716
d855497e 1717 hdw->flag_init_ok = !0;
681c7399
MI		 1718
1719 pvr2_hdw_state_sched(hdw);
d855497e
MI		 1720}
1721
1722
681c7399
MI		 1723/* Set up the structure and attempt to put the device into a usable state.
1724 This can be a time-consuming operation, which is why it is not done
1725 internally as part of the create() step. */
1726static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 1727{
1728 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 1729 do {
d855497e
MI		 1730 pvr2_hdw_setup_low(hdw);
1731 pvr2_trace(PVR2_TRACE_INIT,
1732 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 1733 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 1734 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 1735 if (hdw->flag_init_ok) {
d855497e
MI		 1736 pvr2_trace(
1737 PVR2_TRACE_INFO,
1738 "Device initialization"
1739 " completed successfully.");
1740 break;
1741 }
1742 if (hdw->fw1_state == FW1_STATE_RELOAD) {
1743 pvr2_trace(
1744 PVR2_TRACE_INFO,
1745 "Device microcontroller firmware"
1746 " (re)loaded; it should now reset"
1747 " and reconnect.");
1748 break;
1749 }
1750 pvr2_trace(
1751 PVR2_TRACE_ERROR_LEGS,
1752 "Device initialization was not successful.");
1753 if (hdw->fw1_state == FW1_STATE_MISSING) {
1754 pvr2_trace(
1755 PVR2_TRACE_ERROR_LEGS,
1756 "Giving up since device"
1757 " microcontroller firmware"
1758 " appears to be missing.");
1759 break;
1760 }
1761 }
1762 if (procreload) {
1763 pvr2_trace(
1764 PVR2_TRACE_ERROR_LEGS,
1765 "Attempting pvrusb2 recovery by reloading"
1766 " primary firmware.");
1767 pvr2_trace(
1768 PVR2_TRACE_ERROR_LEGS,
1769 "If this works, device should disconnect"
1770 " and reconnect in a sane state.");
1771 hdw->fw1_state = FW1_STATE_UNKNOWN;
1772 pvr2_upload_firmware1(hdw);
1773 } else {
1774 pvr2_trace(
1775 PVR2_TRACE_ERROR_LEGS,
1776 "***WARNING*** pvrusb2 device hardware"
1777 " appears to be jammed"
1778 " and I can't clear it.");
1779 pvr2_trace(
1780 PVR2_TRACE_ERROR_LEGS,
1781 "You might need to power cycle"
1782 " the pvrusb2 device"
1783 " in order to recover.");
1784 }
681c7399 1785 } while (0);
d855497e 1786 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 1787}
1788
1789
1790/* Create and return a structure for interacting with the underlying
1791 hardware */
1792struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1793 const struct usb_device_id *devid)
1794{
1795 unsigned int idx,cnt1,cnt2;
1796 struct pvr2_hdw *hdw;
1797 unsigned int hdw_type;
1798 int valid_std_mask;
1799 struct pvr2_ctrl *cptr;
989eb154 1800 const struct pvr2_device_desc *hdw_desc;
d855497e 1801 __u8 ifnum;
b30d2441
MI		 1802 struct v4l2_queryctrl qctrl;
1803 struct pvr2_ctl_info *ciptr;
d855497e
MI		 1804
1805 hdw_type = devid - pvr2_device_table;
989eb154 1806 if (hdw_type >= pvr2_device_count) {
d855497e
MI		 1807 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1808 "Bogus device type of %u reported",hdw_type);
a0fd1cb1 1809 return NULL;
d855497e 1810 }
989eb154 1811 hdw_desc = pvr2_device_descriptions + hdw_type;
d855497e 1812
ca545f7c 1813 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 1814 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 1815 hdw,hdw_desc->description);
d855497e 1816 if (!hdw) goto fail;
681c7399
MI		 1817
1818 init_timer(&hdw->quiescent_timer);
1819 hdw->quiescent_timer.data = (unsigned long)hdw;
1820 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
1821
1822 init_timer(&hdw->encoder_wait_timer);
1823 hdw->encoder_wait_timer.data = (unsigned long)hdw;
1824 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
1825
1826 hdw->master_state = PVR2_STATE_DEAD;
1827
1828 init_waitqueue_head(&hdw->state_wait_data);
1829
18103c57 1830 hdw->tuner_signal_stale = !0;
b30d2441 1831 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 1832
c05c0462 1833 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 1834 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 1835 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 1836 GFP_KERNEL);
1837 if (!hdw->controls) goto fail;
989eb154 1838 hdw->hdw_desc = hdw_desc;
c05c0462
MI		 1839 for (idx = 0; idx < hdw->control_cnt; idx++) {
1840 cptr = hdw->controls + idx;
1841 cptr->hdw = hdw;
1842 }
d855497e
MI		 1843 for (idx = 0; idx < 32; idx++) {
1844 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1845 }
c05c0462 1846 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 1847 cptr = hdw->controls + idx;
d855497e
MI		 1848 cptr->info = control_defs+idx;
1849 }
b30d2441 1850 /* Define and configure additional controls from cx2341x module. */
ca545f7c 1851 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 1852 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1853 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 1854 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1855 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1856 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1857 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1858 ciptr->name = mpeg_ids[idx].strid;
1859 ciptr->v4l_id = mpeg_ids[idx].id;
1860 ciptr->skip_init = !0;
1861 ciptr->get_value = ctrl_cx2341x_get;
1862 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1863 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1864 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1865 qctrl.id = ciptr->v4l_id;
1866 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1867 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1868 ciptr->set_value = ctrl_cx2341x_set;
1869 }
1870 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1871 PVR2_CTLD_INFO_DESC_SIZE);
1872 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
1873 ciptr->default_value = qctrl.default_value;
1874 switch (qctrl.type) {
1875 default:
1876 case V4L2_CTRL_TYPE_INTEGER:
1877 ciptr->type = pvr2_ctl_int;
1878 ciptr->def.type_int.min_value = qctrl.minimum;
1879 ciptr->def.type_int.max_value = qctrl.maximum;
1880 break;
1881 case V4L2_CTRL_TYPE_BOOLEAN:
1882 ciptr->type = pvr2_ctl_bool;
1883 break;
1884 case V4L2_CTRL_TYPE_MENU:
1885 ciptr->type = pvr2_ctl_enum;
1886 ciptr->def.type_enum.value_names =
1887 cx2341x_ctrl_get_menu(ciptr->v4l_id);
1888 for (cnt1 = 0;
1889 ciptr->def.type_enum.value_names[cnt1] != NULL;
1890 cnt1++) { }
1891 ciptr->def.type_enum.count = cnt1;
1892 break;
1893 }
1894 cptr->info = ciptr;
1895 }
d855497e
MI		 1896
1897 // Initialize video standard enum dynamic control
1898 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1899 if (cptr) {
1900 memcpy(&hdw->std_info_enum,cptr->info,
1901 sizeof(hdw->std_info_enum));
1902 cptr->info = &hdw->std_info_enum;
1903
1904 }
1905 // Initialize control data regarding video standard masks
1906 valid_std_mask = pvr2_std_get_usable();
1907 for (idx = 0; idx < 32; idx++) {
1908 if (!(valid_std_mask & (1 << idx))) continue;
1909 cnt1 = pvr2_std_id_to_str(
1910 hdw->std_mask_names[idx],
1911 sizeof(hdw->std_mask_names[idx])-1,
1912 1 << idx);
1913 hdw->std_mask_names[idx][cnt1] = 0;
1914 }
1915 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1916 if (cptr) {
1917 memcpy(&hdw->std_info_avail,cptr->info,
1918 sizeof(hdw->std_info_avail));
1919 cptr->info = &hdw->std_info_avail;
1920 hdw->std_info_avail.def.type_bitmask.bit_names =
1921 hdw->std_mask_ptrs;
1922 hdw->std_info_avail.def.type_bitmask.valid_bits =
1923 valid_std_mask;
1924 }
1925 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1926 if (cptr) {
1927 memcpy(&hdw->std_info_cur,cptr->info,
1928 sizeof(hdw->std_info_cur));
1929 cptr->info = &hdw->std_info_cur;
1930 hdw->std_info_cur.def.type_bitmask.bit_names =
1931 hdw->std_mask_ptrs;
1932 hdw->std_info_avail.def.type_bitmask.valid_bits =
1933 valid_std_mask;
1934 }
1935
1936 hdw->eeprom_addr = -1;
1937 hdw->unit_number = -1;
8079384e
MI		 1938 hdw->v4l_minor_number_video = -1;
1939 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 1940 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 1941 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1942 if (!hdw->ctl_write_buffer) goto fail;
1943 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1944 if (!hdw->ctl_read_buffer) goto fail;
1945 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
1946 if (!hdw->ctl_write_urb) goto fail;
1947 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
1948 if (!hdw->ctl_read_urb) goto fail;
1949
8df0c87c 1950 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 1951 for (idx = 0; idx < PVR_NUM; idx++) {
1952 if (unit_pointers[idx]) continue;
1953 hdw->unit_number = idx;
1954 unit_pointers[idx] = hdw;
1955 break;
1956 }
8df0c87c 1957 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 1958
1959 cnt1 = 0;
1960 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
1961 cnt1 += cnt2;
1962 if (hdw->unit_number >= 0) {
1963 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
1964 ('a' + hdw->unit_number));
1965 cnt1 += cnt2;
1966 }
1967 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
1968 hdw->name[cnt1] = 0;
1969
681c7399
MI		 1970 hdw->workqueue = create_singlethread_workqueue(hdw->name);
1971 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
1972 INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
1973 INIT_WORK(&hdw->workinit,pvr2_hdw_worker_init);
1974
d855497e
MI		 1975 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
1976 hdw->unit_number,hdw->name);
1977
1978 hdw->tuner_type = -1;
1979 hdw->flag_ok = !0;
d855497e
MI		 1980
1981 hdw->usb_intf = intf;
1982 hdw->usb_dev = interface_to_usbdev(intf);
1983
31a18547
MI		 1984 scnprintf(hdw->bus_info,sizeof(hdw->bus_info),
1985 "usb %s address %d",
1986 hdw->usb_dev->dev.bus_id,
1987 hdw->usb_dev->devnum);
1988
d855497e
MI		 1989 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
1990 usb_set_interface(hdw->usb_dev,ifnum,0);
1991
1992 mutex_init(&hdw->ctl_lock_mutex);
1993 mutex_init(&hdw->big_lock_mutex);
1994
681c7399 1995 queue_work(hdw->workqueue,&hdw->workinit);
d855497e
MI		 1996 return hdw;
1997 fail:
1998 if (hdw) {
681c7399
MI		 1999 del_timer_sync(&hdw->quiescent_timer);
2000 del_timer_sync(&hdw->encoder_wait_timer);
2001 if (hdw->workqueue) {
2002 flush_workqueue(hdw->workqueue);
2003 destroy_workqueue(hdw->workqueue);
2004 hdw->workqueue = NULL;
2005 }
5e55d2ce
MK		 2006 usb_free_urb(hdw->ctl_read_urb);
2007 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2008 kfree(hdw->ctl_read_buffer);
2009 kfree(hdw->ctl_write_buffer);
2010 kfree(hdw->controls);
2011 kfree(hdw->mpeg_ctrl_info);
681c7399
MI		 2012 kfree(hdw->std_defs);
2013 kfree(hdw->std_enum_names);
d855497e
MI		 2014 kfree(hdw);
2015 }
a0fd1cb1 2016 return NULL;
d855497e
MI		 2017}
2018
2019
2020/* Remove _all_ associations between this driver and the underlying USB
2021 layer. */
07e337ee 2022static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2023{
2024 if (hdw->flag_disconnected) return;
2025 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2026 if (hdw->ctl_read_urb) {
2027 usb_kill_urb(hdw->ctl_read_urb);
2028 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2029 hdw->ctl_read_urb = NULL;
d855497e
MI		 2030 }
2031 if (hdw->ctl_write_urb) {
2032 usb_kill_urb(hdw->ctl_write_urb);
2033 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2034 hdw->ctl_write_urb = NULL;
d855497e
MI		 2035 }
2036 if (hdw->ctl_read_buffer) {
2037 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2038 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2039 }
2040 if (hdw->ctl_write_buffer) {
2041 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2042 hdw->ctl_write_buffer = NULL;
d855497e 2043 }
d855497e 2044 hdw->flag_disconnected = !0;
a0fd1cb1
MI		 2045 hdw->usb_dev = NULL;
2046 hdw->usb_intf = NULL;
681c7399 2047 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2048}
2049
2050
2051/* Destroy hardware interaction structure */
2052void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2053{
401c27ce 2054 if (!hdw) return;
d855497e 2055 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2056 del_timer_sync(&hdw->quiescent_timer);
2057 del_timer_sync(&hdw->encoder_wait_timer);
2058 if (hdw->workqueue) {
2059 flush_workqueue(hdw->workqueue);
2060 destroy_workqueue(hdw->workqueue);
2061 hdw->workqueue = NULL;
2062 }
d855497e
MI		 2063 if (hdw->fw_buffer) {
2064 kfree(hdw->fw_buffer);
a0fd1cb1 2065 hdw->fw_buffer = NULL;
d855497e
MI		 2066 }
2067 if (hdw->vid_stream) {
2068 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2069 hdw->vid_stream = NULL;
d855497e 2070 }
d855497e
MI		 2071 if (hdw->decoder_ctrl) {
2072 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2073 }
2074 pvr2_i2c_core_done(hdw);
2075 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2076 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2077 if ((hdw->unit_number >= 0) &&
2078 (hdw->unit_number < PVR_NUM) &&
2079 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2080 unit_pointers[hdw->unit_number] = NULL;
d855497e 2081 }
8df0c87c 2082 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2083 kfree(hdw->controls);
2084 kfree(hdw->mpeg_ctrl_info);
2085 kfree(hdw->std_defs);
2086 kfree(hdw->std_enum_names);
d855497e
MI		 2087 kfree(hdw);
2088}
2089
2090
d855497e
MI		 2091int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2092{
2093 return (hdw && hdw->flag_ok);
2094}
2095
2096
2097/* Called when hardware has been unplugged */
2098void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2099{
2100 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2101 LOCK_TAKE(hdw->big_lock);
2102 LOCK_TAKE(hdw->ctl_lock);
2103 pvr2_hdw_remove_usb_stuff(hdw);
2104 LOCK_GIVE(hdw->ctl_lock);
2105 LOCK_GIVE(hdw->big_lock);
2106}
2107
2108
2109// Attempt to autoselect an appropriate value for std_enum_cur given
2110// whatever is currently in std_mask_cur
07e337ee 2111static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2112{
2113 unsigned int idx;
2114 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2115 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2116 hdw->std_enum_cur = idx;
2117 return;
2118 }
2119 }
2120 hdw->std_enum_cur = 0;
2121}
2122
2123
2124// Calculate correct set of enumerated standards based on currently known
2125// set of available standards bits.
07e337ee 2126static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2127{
2128 struct v4l2_standard *newstd;
2129 unsigned int std_cnt;
2130 unsigned int idx;
2131
2132 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2133
2134 if (hdw->std_defs) {
2135 kfree(hdw->std_defs);
a0fd1cb1 2136 hdw->std_defs = NULL;
d855497e
MI		 2137 }
2138 hdw->std_enum_cnt = 0;
2139 if (hdw->std_enum_names) {
2140 kfree(hdw->std_enum_names);
a0fd1cb1 2141 hdw->std_enum_names = NULL;
d855497e
MI		 2142 }
2143
2144 if (!std_cnt) {
2145 pvr2_trace(
2146 PVR2_TRACE_ERROR_LEGS,
2147 "WARNING: Failed to identify any viable standards");
2148 }
2149 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2150 hdw->std_enum_names[0] = "none";
2151 for (idx = 0; idx < std_cnt; idx++) {
2152 hdw->std_enum_names[idx+1] =
2153 newstd[idx].name;
2154 }
2155 // Set up the dynamic control for this standard
2156 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2157 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2158 hdw->std_defs = newstd;
2159 hdw->std_enum_cnt = std_cnt+1;
2160 hdw->std_enum_cur = 0;
2161 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2162}
2163
2164
2165int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2166 struct v4l2_standard *std,
2167 unsigned int idx)
2168{
2169 int ret = -EINVAL;
2170 if (!idx) return ret;
2171 LOCK_TAKE(hdw->big_lock); do {
2172 if (idx >= hdw->std_enum_cnt) break;
2173 idx--;
2174 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2175 ret = 0;
2176 } while (0); LOCK_GIVE(hdw->big_lock);
2177 return ret;
2178}
2179
2180
2181/* Get the number of defined controls */
2182unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2183{
c05c0462 2184 return hdw->control_cnt;
d855497e
MI		 2185}
2186
2187
2188/* Retrieve a control handle given its index (0..count-1) */
2189struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2190 unsigned int idx)
2191{
a0fd1cb1 2192 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2193 return hdw->controls + idx;
2194}
2195
2196
2197/* Retrieve a control handle given its index (0..count-1) */
2198struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2199 unsigned int ctl_id)
2200{
2201 struct pvr2_ctrl *cptr;
2202 unsigned int idx;
2203 int i;
2204
2205 /* This could be made a lot more efficient, but for now... */
c05c0462 2206 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2207 cptr = hdw->controls + idx;
2208 i = cptr->info->internal_id;
2209 if (i && (i == ctl_id)) return cptr;
2210 }
a0fd1cb1 2211 return NULL;
d855497e
MI		 2212}
2213
2214
a761f431 2215/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2216struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2217{
2218 struct pvr2_ctrl *cptr;
2219 unsigned int idx;
2220 int i;
2221
2222 /* This could be made a lot more efficient, but for now... */
c05c0462 2223 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2224 cptr = hdw->controls + idx;
2225 i = cptr->info->v4l_id;
2226 if (i && (i == ctl_id)) return cptr;
2227 }
a0fd1cb1 2228 return NULL;
d855497e
MI		 2229}
2230
2231
a761f431
MI		 2232/* Given a V4L ID for its immediate predecessor, retrieve the control
2233 structure associated with it. */
2234struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2235 unsigned int ctl_id)
2236{
2237 struct pvr2_ctrl *cptr,*cp2;
2238 unsigned int idx;
2239 int i;
2240
2241 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2242 cp2 = NULL;
a761f431
MI		 2243 for (idx = 0; idx < hdw->control_cnt; idx++) {
2244 cptr = hdw->controls + idx;
2245 i = cptr->info->v4l_id;
2246 if (!i) continue;
2247 if (i <= ctl_id) continue;
2248 if (cp2 && (cp2->info->v4l_id < i)) continue;
2249 cp2 = cptr;
2250 }
2251 return cp2;
a0fd1cb1 2252 return NULL;
a761f431
MI		 2253}
2254
2255
d855497e
MI		 2256static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2257{
2258 switch (tp) {
2259 case pvr2_ctl_int: return "integer";
2260 case pvr2_ctl_enum: return "enum";
33213963 2261 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2262 case pvr2_ctl_bitmask: return "bitmask";
2263 }
2264 return "";
2265}
2266
2267
681c7399
MI		 2268/* Figure out if we need to commit control changes. If so, mark internal
2269 state flags to indicate this fact and return true. Otherwise do nothing
2270 else and return false. */
2271static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 2272{
d855497e
MI		 2273 unsigned int idx;
2274 struct pvr2_ctrl *cptr;
2275 int value;
2276 int commit_flag = 0;
2277 char buf[100];
2278 unsigned int bcnt,ccnt;
2279
c05c0462 2280 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2281 cptr = hdw->controls + idx;
2282 if (cptr->info->is_dirty == 0) continue;
2283 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 2284 commit_flag = !0;
d855497e 2285
fe23a280 2286 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 2287 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2288 cptr->info->name);
2289 value = 0;
2290 cptr->info->get_value(cptr,&value);
2291 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2292 buf+bcnt,
2293 sizeof(buf)-bcnt,&ccnt);
2294 bcnt += ccnt;
2295 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2296 get_ctrl_typename(cptr->info->type));
2297 pvr2_trace(PVR2_TRACE_CTL,
2298 "/*--TRACE_COMMIT--*/ %.*s",
2299 bcnt,buf);
2300 }
2301
2302 if (!commit_flag) {
2303 /* Nothing has changed */
2304 return 0;
2305 }
2306
681c7399
MI		 2307 hdw->state_pipeline_config = 0;
2308 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2309 pvr2_hdw_state_sched(hdw);
2310
2311 return !0;
2312}
2313
2314
2315/* Perform all operations needed to commit all control changes. This must
2316 be performed in synchronization with the pipeline state and is thus
2317 expected to be called as part of the driver's worker thread. Return
2318 true if commit successful, otherwise return false to indicate that
2319 commit isn't possible at this time. */
2320static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
2321{
2322 unsigned int idx;
2323 struct pvr2_ctrl *cptr;
2324 int disruptive_change;
2325
d855497e
MI		 2326 /* When video standard changes, reset the hres and vres values -
2327 but if the user has pending changes there, then let the changes
2328 take priority. */
2329 if (hdw->std_dirty) {
2330 /* Rewrite the vertical resolution to be appropriate to the
2331 video standard that has been selected. */
2332 int nvres;
2333 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2334 nvres = 480;
2335 } else {
2336 nvres = 576;
2337 }
2338 if (nvres != hdw->res_ver_val) {
2339 hdw->res_ver_val = nvres;
2340 hdw->res_ver_dirty = !0;
2341 }
d855497e
MI		 2342 }
2343
681c7399
MI		 2344 /* If any of the below has changed, then we can't do the update
2345 while the pipeline is running. Pipeline must be paused first
2346 and decoder -> encoder connection be made quiescent before we
2347 can proceed. */
2348 disruptive_change =
2349 (hdw->std_dirty ||
2350 hdw->enc_unsafe_stale ||
2351 hdw->srate_dirty ||
2352 hdw->res_ver_dirty ||
2353 hdw->res_hor_dirty ||
2354 hdw->input_dirty ||
2355 (hdw->active_stream_type != hdw->desired_stream_type));
2356 if (disruptive_change && !hdw->state_pipeline_idle) {
2357 /* Pipeline is not idle; we can't proceed. Arrange to
2358 cause pipeline to stop so that we can try this again
2359 later.... */
2360 hdw->state_pipeline_pause = !0;
2361 return 0;
275b2e28
PK		 2362 }
2363
b30d2441
MI		 2364 if (hdw->srate_dirty) {
2365 /* Write new sample rate into control structure since
2366 * the master copy is stale. We must track srate
2367 * separate from the mpeg control structure because
2368 * other logic also uses this value. */
2369 struct v4l2_ext_controls cs;
2370 struct v4l2_ext_control c1;
2371 memset(&cs,0,sizeof(cs));
2372 memset(&c1,0,sizeof(c1));
2373 cs.controls = &c1;
2374 cs.count = 1;
2375 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2376 c1.value = hdw->srate_val;
01f1e44f 2377 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 2378 }
c05c0462 2379
d855497e
MI		 2380 /* Scan i2c core at this point - before we clear all the dirty
2381 bits. Various parts of the i2c core will notice dirty bits as
2382 appropriate and arrange to broadcast or directly send updates to
2383 the client drivers in order to keep everything in sync */
2384 pvr2_i2c_core_check_stale(hdw);
2385
c05c0462 2386 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2387 cptr = hdw->controls + idx;
2388 if (!cptr->info->clear_dirty) continue;
2389 cptr->info->clear_dirty(cptr);
2390 }
2391
681c7399
MI		 2392 if (hdw->active_stream_type != hdw->desired_stream_type) {
2393 /* Handle any side effects of stream config here */
2394 hdw->active_stream_type = hdw->desired_stream_type;
2395 }
2396
d855497e
MI		 2397 /* Now execute i2c core update */
2398 pvr2_i2c_core_sync(hdw);
2399
681c7399
MI		 2400 if (hdw->state_encoder_run) {
2401 /* If encoder isn't running, then this will get worked out
2402 later when we start the encoder. */
2403 if (pvr2_encoder_adjust(hdw) < 0) return !0;
2404 }
d855497e 2405
681c7399
MI		 2406 hdw->state_pipeline_config = !0;
2407 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2408 return !0;
d855497e
MI		 2409}
2410
2411
2412int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2413{
681c7399
MI		 2414 int fl;
2415 LOCK_TAKE(hdw->big_lock);
2416 fl = pvr2_hdw_commit_setup(hdw);
2417 LOCK_GIVE(hdw->big_lock);
2418 if (!fl) return 0;
2419 return pvr2_hdw_wait(hdw,0);
2420}
2421
2422
2423static void pvr2_hdw_worker_i2c(struct work_struct *work)
2424{
2425 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
d855497e 2426 LOCK_TAKE(hdw->big_lock); do {
681c7399 2427 pvr2_i2c_core_sync(hdw);
d855497e 2428 } while (0); LOCK_GIVE(hdw->big_lock);
d855497e
MI		 2429}
2430
2431
681c7399 2432static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 2433{
681c7399
MI		 2434 int fl = 0;
2435 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 2436 LOCK_TAKE(hdw->big_lock); do {
681c7399 2437 fl = pvr2_hdw_state_eval(hdw);
d855497e 2438 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 2439 if (fl && hdw->state_func) {
2440 hdw->state_func(hdw->state_data);
2441 }
d855497e
MI		 2442}
2443
2444
681c7399 2445static void pvr2_hdw_worker_init(struct work_struct *work)
d855497e 2446{
681c7399 2447 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workinit);
d855497e 2448 LOCK_TAKE(hdw->big_lock); do {
681c7399 2449 pvr2_hdw_setup(hdw);
d855497e
MI		 2450 } while (0); LOCK_GIVE(hdw->big_lock);
2451}
2452
2453
681c7399 2454static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 2455{
681c7399
MI		 2456 return wait_event_interruptible(
2457 hdw->state_wait_data,
2458 (hdw->state_stale == 0) &&
2459 (!state || (hdw->master_state != state)));
2460}
2461
2462
2463void pvr2_hdw_set_state_callback(struct pvr2_hdw *hdw,
2464 void (*callback_func)(void *),
2465 void *callback_data)
2466{
2467 LOCK_TAKE(hdw->big_lock); do {
2468 hdw->state_data = callback_data;
2469 hdw->state_func = callback_func;
2470 } while (0); LOCK_GIVE(hdw->big_lock);
d855497e
MI		 2471}
2472
681c7399 2473
d855497e
MI		 2474/* Return name for this driver instance */
2475const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2476{
2477 return hdw->name;
2478}
2479
2480
78a47101
MI		 2481const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
2482{
2483 return hdw->hdw_desc->description;
2484}
2485
2486
2487const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
2488{
2489 return hdw->hdw_desc->shortname;
2490}
2491
2492
d855497e
MI		 2493int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2494{
2495 int result;
2496 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 2497 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 2498 result = pvr2_send_request(hdw,
2499 hdw->cmd_buffer,1,
2500 hdw->cmd_buffer,1);
2501 if (result < 0) break;
2502 result = (hdw->cmd_buffer[0] != 0);
2503 } while(0); LOCK_GIVE(hdw->ctl_lock);
2504 return result;
2505}
2506
2507
18103c57
MI		 2508/* Execute poll of tuner status */
2509void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 2510{
d855497e 2511 LOCK_TAKE(hdw->big_lock); do {
18103c57 2512 pvr2_i2c_core_status_poll(hdw);
d855497e 2513 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 2514}
2515
2516
2517/* Return information about the tuner */
2518int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
2519{
2520 LOCK_TAKE(hdw->big_lock); do {
2521 if (hdw->tuner_signal_stale) {
2522 pvr2_i2c_core_status_poll(hdw);
2523 }
2524 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
2525 } while (0); LOCK_GIVE(hdw->big_lock);
2526 return 0;
d855497e
MI		 2527}
2528
2529
2530/* Get handle to video output stream */
2531struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2532{
2533 return hp->vid_stream;
2534}
2535
2536
2537void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2538{
4f1a3e5b 2539 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e
MI		 2540 LOCK_TAKE(hdw->big_lock); do {
2541 hdw->log_requested = !0;
4f1a3e5b 2542 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
d855497e
MI		 2543 pvr2_i2c_core_check_stale(hdw);
2544 hdw->log_requested = 0;
2545 pvr2_i2c_core_sync(hdw);
b30d2441 2546 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 2547 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 2548 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 2549 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 2550 } while (0); LOCK_GIVE(hdw->big_lock);
2551}
2552
4db666cc
MI		 2553
2554/* Grab EEPROM contents, needed for direct method. */
2555#define EEPROM_SIZE 8192
2556#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
2557static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
2558{
2559 struct i2c_msg msg[2];
2560 u8 *eeprom;
2561 u8 iadd[2];
2562 u8 addr;
2563 u16 eepromSize;
2564 unsigned int offs;
2565 int ret;
2566 int mode16 = 0;
2567 unsigned pcnt,tcnt;
2568 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
2569 if (!eeprom) {
2570 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2571 "Failed to allocate memory"
2572 " required to read eeprom");
2573 return NULL;
2574 }
2575
2576 trace_eeprom("Value for eeprom addr from controller was 0x%x",
2577 hdw->eeprom_addr);
2578 addr = hdw->eeprom_addr;
2579 /* Seems that if the high bit is set, then the *real* eeprom
2580 address is shifted right now bit position (noticed this in
2581 newer PVR USB2 hardware) */
2582 if (addr & 0x80) addr >>= 1;
2583
2584 /* FX2 documentation states that a 16bit-addressed eeprom is
2585 expected if the I2C address is an odd number (yeah, this is
2586 strange but it's what they do) */
2587 mode16 = (addr & 1);
2588 eepromSize = (mode16 ? EEPROM_SIZE : 256);
2589 trace_eeprom("Examining %d byte eeprom at location 0x%x"
2590 " using %d bit addressing",eepromSize,addr,
2591 mode16 ? 16 : 8);
2592
2593 msg[0].addr = addr;
2594 msg[0].flags = 0;
2595 msg[0].len = mode16 ? 2 : 1;
2596 msg[0].buf = iadd;
2597 msg[1].addr = addr;
2598 msg[1].flags = I2C_M_RD;
2599
2600 /* We have to do the actual eeprom data fetch ourselves, because
2601 (1) we're only fetching part of the eeprom, and (2) if we were
2602 getting the whole thing our I2C driver can't grab it in one
2603 pass - which is what tveeprom is otherwise going to attempt */
2604 memset(eeprom,0,EEPROM_SIZE);
2605 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
2606 pcnt = 16;
2607 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
2608 offs = tcnt + (eepromSize - EEPROM_SIZE);
2609 if (mode16) {
2610 iadd[0] = offs >> 8;
2611 iadd[1] = offs;
2612 } else {
2613 iadd[0] = offs;
2614 }
2615 msg[1].len = pcnt;
2616 msg[1].buf = eeprom+tcnt;
2617 if ((ret = i2c_transfer(&hdw->i2c_adap,
2618 msg,ARRAY_SIZE(msg))) != 2) {
2619 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2620 "eeprom fetch set offs err=%d",ret);
2621 kfree(eeprom);
2622 return NULL;
2623 }
2624 }
2625 return eeprom;
2626}
2627
2628
2629void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
2630 int prom_flag,
2631 int enable_flag)
d855497e
MI		 2632{
2633 int ret;
2634 u16 address;
2635 unsigned int pipe;
2636 LOCK_TAKE(hdw->big_lock); do {
2637 if ((hdw->fw_buffer == 0) == !enable_flag) break;
2638
2639 if (!enable_flag) {
2640 pvr2_trace(PVR2_TRACE_FIRMWARE,
2641 "Cleaning up after CPU firmware fetch");
2642 kfree(hdw->fw_buffer);
a0fd1cb1 2643 hdw->fw_buffer = NULL;
d855497e 2644 hdw->fw_size = 0;
4db666cc
MI		 2645 if (hdw->fw_cpu_flag) {
2646 /* Now release the CPU. It will disconnect
2647 and reconnect later. */
2648 pvr2_hdw_cpureset_assert(hdw,0);
2649 }
d855497e
MI		 2650 break;
2651 }
2652
4db666cc
MI		 2653 hdw->fw_cpu_flag = (prom_flag == 0);
2654 if (hdw->fw_cpu_flag) {
2655 pvr2_trace(PVR2_TRACE_FIRMWARE,
2656 "Preparing to suck out CPU firmware");
2657 hdw->fw_size = 0x2000;
2658 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
2659 if (!hdw->fw_buffer) {
2660 hdw->fw_size = 0;
2661 break;
2662 }
d855497e 2663
4db666cc
MI		 2664 /* We have to hold the CPU during firmware upload. */
2665 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 2666
4db666cc
MI		 2667 /* download the firmware from address 0000-1fff in 2048
2668 (=0x800) bytes chunk. */
d855497e 2669
4db666cc
MI		 2670 pvr2_trace(PVR2_TRACE_FIRMWARE,
2671 "Grabbing CPU firmware");
2672 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2673 for(address = 0; address < hdw->fw_size;
2674 address += 0x800) {
2675 ret = usb_control_msg(hdw->usb_dev,pipe,
2676 0xa0,0xc0,
2677 address,0,
2678 hdw->fw_buffer+address,
2679 0x800,HZ);
2680 if (ret < 0) break;
2681 }
d855497e 2682
4db666cc
MI		 2683 pvr2_trace(PVR2_TRACE_FIRMWARE,
2684 "Done grabbing CPU firmware");
2685 } else {
2686 pvr2_trace(PVR2_TRACE_FIRMWARE,
2687 "Sucking down EEPROM contents");
2688 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
2689 if (!hdw->fw_buffer) {
2690 pvr2_trace(PVR2_TRACE_FIRMWARE,
2691 "EEPROM content suck failed.");
2692 break;
2693 }
2694 hdw->fw_size = EEPROM_SIZE;
2695 pvr2_trace(PVR2_TRACE_FIRMWARE,
2696 "Done sucking down EEPROM contents");
2697 }
d855497e
MI		 2698
2699 } while (0); LOCK_GIVE(hdw->big_lock);
2700}
2701
2702
2703/* Return true if we're in a mode for retrieval CPU firmware */
2704int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2705{
2706 return hdw->fw_buffer != 0;
2707}
2708
2709
2710int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2711 char *buf,unsigned int cnt)
2712{
2713 int ret = -EINVAL;
2714 LOCK_TAKE(hdw->big_lock); do {
2715 if (!buf) break;
2716 if (!cnt) break;
2717
2718 if (!hdw->fw_buffer) {
2719 ret = -EIO;
2720 break;
2721 }
2722
2723 if (offs >= hdw->fw_size) {
2724 pvr2_trace(PVR2_TRACE_FIRMWARE,
2725 "Read firmware data offs=%d EOF",
2726 offs);
2727 ret = 0;
2728 break;
2729 }
2730
2731 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2732
2733 memcpy(buf,hdw->fw_buffer+offs,cnt);
2734
2735 pvr2_trace(PVR2_TRACE_FIRMWARE,
2736 "Read firmware data offs=%d cnt=%d",
2737 offs,cnt);
2738 ret = cnt;
2739 } while (0); LOCK_GIVE(hdw->big_lock);
2740
2741 return ret;
2742}
2743
2744
fd5a75fe 2745int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 2746 enum pvr2_v4l_type index)
d855497e 2747{
fd5a75fe 2748 switch (index) {
8079384e
MI		 2749 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
2750 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
2751 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 2752 default: return -1;
2753 }
d855497e
MI		 2754}
2755
2756
2fdf3d9c 2757/* Store a v4l minor device number */
fd5a75fe 2758void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 2759 enum pvr2_v4l_type index,int v)
d855497e 2760{
fd5a75fe 2761 switch (index) {
8079384e
MI		 2762 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
2763 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
2764 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 2765 default: break;
2766 }
d855497e
MI		 2767}
2768
2769
7d12e780 2770static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 2771{
2772 struct pvr2_hdw *hdw = urb->context;
2773 hdw->ctl_write_pend_flag = 0;
2774 if (hdw->ctl_read_pend_flag) return;
2775 complete(&hdw->ctl_done);
2776}
2777
2778
7d12e780 2779static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 2780{
2781 struct pvr2_hdw *hdw = urb->context;
2782 hdw->ctl_read_pend_flag = 0;
2783 if (hdw->ctl_write_pend_flag) return;
2784 complete(&hdw->ctl_done);
2785}
2786
2787
2788static void pvr2_ctl_timeout(unsigned long data)
2789{
2790 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2791 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2792 hdw->ctl_timeout_flag = !0;
5e55d2ce 2793 if (hdw->ctl_write_pend_flag)
d855497e 2794 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 2795 if (hdw->ctl_read_pend_flag)
d855497e 2796 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 2797 }
2798}
2799
2800
e61b6fc5
MI		 2801/* Issue a command and get a response from the device. This extended
2802 version includes a probe flag (which if set means that device errors
2803 should not be logged or treated as fatal) and a timeout in jiffies.
2804 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 2805static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2806 unsigned int timeout,int probe_fl,
2807 void *write_data,unsigned int write_len,
2808 void *read_data,unsigned int read_len)
d855497e
MI		 2809{
2810 unsigned int idx;
2811 int status = 0;
2812 struct timer_list timer;
2813 if (!hdw->ctl_lock_held) {
2814 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2815 "Attempted to execute control transfer"
2816 " without lock!!");
2817 return -EDEADLK;
2818 }
681c7399 2819 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 2820 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2821 "Attempted to execute control transfer"
2822 " when device not ok");
2823 return -EIO;
2824 }
2825 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2826 if (!probe_fl) {
2827 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2828 "Attempted to execute control transfer"
2829 " when USB is disconnected");
2830 }
2831 return -ENOTTY;
2832 }
2833
2834 /* Ensure that we have sane parameters */
2835 if (!write_data) write_len = 0;
2836 if (!read_data) read_len = 0;
2837 if (write_len > PVR2_CTL_BUFFSIZE) {
2838 pvr2_trace(
2839 PVR2_TRACE_ERROR_LEGS,
2840 "Attempted to execute %d byte"
2841 " control-write transfer (limit=%d)",
2842 write_len,PVR2_CTL_BUFFSIZE);
2843 return -EINVAL;
2844 }
2845 if (read_len > PVR2_CTL_BUFFSIZE) {
2846 pvr2_trace(
2847 PVR2_TRACE_ERROR_LEGS,
2848 "Attempted to execute %d byte"
2849 " control-read transfer (limit=%d)",
2850 write_len,PVR2_CTL_BUFFSIZE);
2851 return -EINVAL;
2852 }
2853 if ((!write_len) && (!read_len)) {
2854 pvr2_trace(
2855 PVR2_TRACE_ERROR_LEGS,
2856 "Attempted to execute null control transfer?");
2857 return -EINVAL;
2858 }
2859
2860
2861 hdw->cmd_debug_state = 1;
2862 if (write_len) {
2863 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2864 } else {
2865 hdw->cmd_debug_code = 0;
2866 }
2867 hdw->cmd_debug_write_len = write_len;
2868 hdw->cmd_debug_read_len = read_len;
2869
2870 /* Initialize common stuff */
2871 init_completion(&hdw->ctl_done);
2872 hdw->ctl_timeout_flag = 0;
2873 hdw->ctl_write_pend_flag = 0;
2874 hdw->ctl_read_pend_flag = 0;
2875 init_timer(&timer);
2876 timer.expires = jiffies + timeout;
2877 timer.data = (unsigned long)hdw;
2878 timer.function = pvr2_ctl_timeout;
2879
2880 if (write_len) {
2881 hdw->cmd_debug_state = 2;
2882 /* Transfer write data to internal buffer */
2883 for (idx = 0; idx < write_len; idx++) {
2884 hdw->ctl_write_buffer[idx] =
2885 ((unsigned char *)write_data)[idx];
2886 }
2887 /* Initiate a write request */
2888 usb_fill_bulk_urb(hdw->ctl_write_urb,
2889 hdw->usb_dev,
2890 usb_sndbulkpipe(hdw->usb_dev,
2891 PVR2_CTL_WRITE_ENDPOINT),
2892 hdw->ctl_write_buffer,
2893 write_len,
2894 pvr2_ctl_write_complete,
2895 hdw);
2896 hdw->ctl_write_urb->actual_length = 0;
2897 hdw->ctl_write_pend_flag = !0;
2898 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2899 if (status < 0) {
2900 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2901 "Failed to submit write-control"
2902 " URB status=%d",status);
2903 hdw->ctl_write_pend_flag = 0;
2904 goto done;
2905 }
2906 }
2907
2908 if (read_len) {
2909 hdw->cmd_debug_state = 3;
2910 memset(hdw->ctl_read_buffer,0x43,read_len);
2911 /* Initiate a read request */
2912 usb_fill_bulk_urb(hdw->ctl_read_urb,
2913 hdw->usb_dev,
2914 usb_rcvbulkpipe(hdw->usb_dev,
2915 PVR2_CTL_READ_ENDPOINT),
2916 hdw->ctl_read_buffer,
2917 read_len,
2918 pvr2_ctl_read_complete,
2919 hdw);
2920 hdw->ctl_read_urb->actual_length = 0;
2921 hdw->ctl_read_pend_flag = !0;
2922 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2923 if (status < 0) {
2924 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2925 "Failed to submit read-control"
2926 " URB status=%d",status);
2927 hdw->ctl_read_pend_flag = 0;
2928 goto done;
2929 }
2930 }
2931
2932 /* Start timer */
2933 add_timer(&timer);
2934
2935 /* Now wait for all I/O to complete */
2936 hdw->cmd_debug_state = 4;
2937 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2938 wait_for_completion(&hdw->ctl_done);
2939 }
2940 hdw->cmd_debug_state = 5;
2941
2942 /* Stop timer */
2943 del_timer_sync(&timer);
2944
2945 hdw->cmd_debug_state = 6;
2946 status = 0;
2947
2948 if (hdw->ctl_timeout_flag) {
2949 status = -ETIMEDOUT;
2950 if (!probe_fl) {
2951 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2952 "Timed out control-write");
2953 }
2954 goto done;
2955 }
2956
2957 if (write_len) {
2958 /* Validate results of write request */
2959 if ((hdw->ctl_write_urb->status != 0) &&
2960 (hdw->ctl_write_urb->status != -ENOENT) &&
2961 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2962 (hdw->ctl_write_urb->status != -ECONNRESET)) {
2963 /* USB subsystem is reporting some kind of failure
2964 on the write */
2965 status = hdw->ctl_write_urb->status;
2966 if (!probe_fl) {
2967 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2968 "control-write URB failure,"
2969 " status=%d",
2970 status);
2971 }
2972 goto done;
2973 }
2974 if (hdw->ctl_write_urb->actual_length < write_len) {
2975 /* Failed to write enough data */
2976 status = -EIO;
2977 if (!probe_fl) {
2978 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2979 "control-write URB short,"
2980 " expected=%d got=%d",
2981 write_len,
2982 hdw->ctl_write_urb->actual_length);
2983 }
2984 goto done;
2985 }
2986 }
2987 if (read_len) {
2988 /* Validate results of read request */
2989 if ((hdw->ctl_read_urb->status != 0) &&
2990 (hdw->ctl_read_urb->status != -ENOENT) &&
2991 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
2992 (hdw->ctl_read_urb->status != -ECONNRESET)) {
2993 /* USB subsystem is reporting some kind of failure
2994 on the read */
2995 status = hdw->ctl_read_urb->status;
2996 if (!probe_fl) {
2997 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2998 "control-read URB failure,"
2999 " status=%d",
3000 status);
3001 }
3002 goto done;
3003 }
3004 if (hdw->ctl_read_urb->actual_length < read_len) {
3005 /* Failed to read enough data */
3006 status = -EIO;
3007 if (!probe_fl) {
3008 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3009 "control-read URB short,"
3010 " expected=%d got=%d",
3011 read_len,
3012 hdw->ctl_read_urb->actual_length);
3013 }
3014 goto done;
3015 }
3016 /* Transfer retrieved data out from internal buffer */
3017 for (idx = 0; idx < read_len; idx++) {
3018 ((unsigned char *)read_data)[idx] =
3019 hdw->ctl_read_buffer[idx];
3020 }
3021 }
3022
3023 done:
3024
3025 hdw->cmd_debug_state = 0;
3026 if ((status < 0) && (!probe_fl)) {
681c7399 3027 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3028 }
3029 return status;
3030}
3031
3032
3033int pvr2_send_request(struct pvr2_hdw *hdw,
3034 void *write_data,unsigned int write_len,
3035 void *read_data,unsigned int read_len)
3036{
3037 return pvr2_send_request_ex(hdw,HZ*4,0,
3038 write_data,write_len,
3039 read_data,read_len);
3040}
3041
3042int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3043{
3044 int ret;
3045
3046 LOCK_TAKE(hdw->ctl_lock);
3047
8d364363 3048 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 3049 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3050 hdw->cmd_buffer[5] = 0;
3051 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3052 hdw->cmd_buffer[7] = reg & 0xff;
3053
3054
3055 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3056
3057 LOCK_GIVE(hdw->ctl_lock);
3058
3059 return ret;
3060}
3061
3062
07e337ee 3063static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 3064{
3065 int ret = 0;
3066
3067 LOCK_TAKE(hdw->ctl_lock);
3068
8d364363 3069 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 3070 hdw->cmd_buffer[1] = 0;
3071 hdw->cmd_buffer[2] = 0;
3072 hdw->cmd_buffer[3] = 0;
3073 hdw->cmd_buffer[4] = 0;
3074 hdw->cmd_buffer[5] = 0;
3075 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3076 hdw->cmd_buffer[7] = reg & 0xff;
3077
3078 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3079 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3080
3081 LOCK_GIVE(hdw->ctl_lock);
3082
3083 return ret;
3084}
3085
3086
681c7399 3087void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 3088{
3089 if (!hdw->flag_ok) return;
681c7399
MI		 3090 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3091 "Device being rendered inoperable");
d855497e 3092 if (hdw->vid_stream) {
a0fd1cb1 3093 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 3094 }
681c7399
MI		 3095 hdw->flag_ok = 0;
3096 trace_stbit("flag_ok",hdw->flag_ok);
3097 pvr2_hdw_state_sched(hdw);
d855497e
MI		 3098}
3099
3100
3101void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3102{
3103 int ret;
3104 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 3105 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
d855497e
MI		 3106 if (ret == 1) {
3107 ret = usb_reset_device(hdw->usb_dev);
3108 usb_unlock_device(hdw->usb_dev);
3109 } else {
3110 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3111 "Failed to lock USB device ret=%d",ret);
3112 }
3113 if (init_pause_msec) {
3114 pvr2_trace(PVR2_TRACE_INFO,
3115 "Waiting %u msec for hardware to settle",
3116 init_pause_msec);
3117 msleep(init_pause_msec);
3118 }
3119
3120}
3121
3122
3123void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3124{
3125 char da[1];
3126 unsigned int pipe;
3127 int ret;
3128
3129 if (!hdw->usb_dev) return;
3130
3131 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3132
3133 da[0] = val ? 0x01 : 0x00;
3134
3135 /* Write the CPUCS register on the 8051. The lsb of the register
3136 is the reset bit; a 1 asserts reset while a 0 clears it. */
3137 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3138 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3139 if (ret < 0) {
3140 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3141 "cpureset_assert(%d) error=%d",val,ret);
3142 pvr2_hdw_render_useless(hdw);
3143 }
3144}
3145
3146
3147int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3148{
3149 int status;
3150 LOCK_TAKE(hdw->ctl_lock); do {
3151 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
8d364363 3152 hdw->cmd_buffer[0] = FX2CMD_DEEP_RESET;
a0fd1cb1 3153 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
d855497e
MI		 3154 } while (0); LOCK_GIVE(hdw->ctl_lock);
3155 return status;
3156}
3157
3158
3159int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3160{
3161 int status;
3162 LOCK_TAKE(hdw->ctl_lock); do {
3163 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
8d364363 3164 hdw->cmd_buffer[0] = FX2CMD_POWER_ON;
a0fd1cb1 3165 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
d855497e
MI		 3166 } while (0); LOCK_GIVE(hdw->ctl_lock);
3167 return status;
3168}
3169
3170
3171int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3172{
3173 if (!hdw->decoder_ctrl) {
3174 pvr2_trace(PVR2_TRACE_INIT,
3175 "Unable to reset decoder: nothing attached");
3176 return -ENOTTY;
3177 }
3178
3179 if (!hdw->decoder_ctrl->force_reset) {
3180 pvr2_trace(PVR2_TRACE_INIT,
3181 "Unable to reset decoder: not implemented");
3182 return -ENOTTY;
3183 }
3184
3185 pvr2_trace(PVR2_TRACE_INIT,
3186 "Requesting decoder reset");
3187 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3188 return 0;
3189}
3190
3191
e61b6fc5 3192/* Stop / start video stream transport */
07e337ee 3193static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e
MI		 3194{
3195 int status;
3196 LOCK_TAKE(hdw->ctl_lock); do {
8d364363
MK		 3197 hdw->cmd_buffer[0] =
3198 (runFl ? FX2CMD_STREAMING_ON : FX2CMD_STREAMING_OFF);
a0fd1cb1 3199 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
d855497e 3200 } while (0); LOCK_GIVE(hdw->ctl_lock);
d855497e
MI		 3201 return status;
3202}
3203
3204
681c7399
MI		 3205/* Evaluate whether or not state_encoder_ok can change */
3206static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
3207{
3208 if (hdw->state_encoder_ok) return 0;
3209 if (hdw->flag_tripped) return 0;
3210 if (hdw->state_encoder_run) return 0;
3211 if (hdw->state_encoder_config) return 0;
3212 if (hdw->state_decoder_run) return 0;
3213 if (hdw->state_usbstream_run) return 0;
3214 if (pvr2_upload_firmware2(hdw) < 0) {
3215 hdw->flag_tripped = !0;
3216 trace_stbit("flag_tripped",hdw->flag_tripped);
3217 return !0;
3218 }
3219 hdw->state_encoder_ok = !0;
3220 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
3221 return !0;
3222}
3223
3224
3225/* Evaluate whether or not state_encoder_config can change */
3226static int state_eval_encoder_config(struct pvr2_hdw *hdw)
3227{
3228 if (hdw->state_encoder_config) {
3229 if (hdw->state_encoder_ok) {
3230 if (hdw->state_pipeline_req &&
3231 !hdw->state_pipeline_pause) return 0;
3232 }
3233 hdw->state_encoder_config = 0;
3234 hdw->state_encoder_waitok = 0;
3235 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3236 /* paranoia - solve race if timer just completed */
3237 del_timer_sync(&hdw->encoder_wait_timer);
3238 } else {
3239 if (!hdw->state_encoder_ok ||
3240 !hdw->state_pipeline_idle ||
3241 hdw->state_pipeline_pause ||
3242 !hdw->state_pipeline_req ||
3243 !hdw->state_pipeline_config) {
3244 /* We must reset the enforced wait interval if
3245 anything has happened that might have disturbed
3246 the encoder. This should be a rare case. */
3247 if (timer_pending(&hdw->encoder_wait_timer)) {
3248 del_timer_sync(&hdw->encoder_wait_timer);
3249 }
3250 if (hdw->state_encoder_waitok) {
3251 /* Must clear the state - therefore we did
3252 something to a state bit and must also
3253 return true. */
3254 hdw->state_encoder_waitok = 0;
3255 trace_stbit("state_encoder_waitok",
3256 hdw->state_encoder_waitok);
3257 return !0;
3258 }
3259 return 0;
3260 }
3261 if (!hdw->state_encoder_waitok) {
3262 if (!timer_pending(&hdw->encoder_wait_timer)) {
3263 /* waitok flag wasn't set and timer isn't
3264 running. Check flag once more to avoid
3265 a race then start the timer. This is
3266 the point when we measure out a minimal
3267 quiet interval before doing something to
3268 the encoder. */
3269 if (!hdw->state_encoder_waitok) {
3270 hdw->encoder_wait_timer.expires =
3271 jiffies + (HZ*50/1000);
3272 add_timer(&hdw->encoder_wait_timer);
3273 }
3274 }
3275 /* We can't continue until we know we have been
3276 quiet for the interval measured by this
3277 timer. */
3278 return 0;
3279 }
3280 pvr2_encoder_configure(hdw);
3281 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
3282 }
3283 trace_stbit("state_encoder_config",hdw->state_encoder_config);
3284 return !0;
3285}
3286
3287
3288/* Evaluate whether or not state_encoder_run can change */
3289static int state_eval_encoder_run(struct pvr2_hdw *hdw)
3290{
3291 if (hdw->state_encoder_run) {
3292 if (hdw->state_encoder_ok) {
3293 if (hdw->state_decoder_run) return 0;
3294 if (pvr2_encoder_stop(hdw) < 0) return !0;
3295 }
3296 hdw->state_encoder_run = 0;
3297 } else {
3298 if (!hdw->state_encoder_ok) return 0;
3299 if (!hdw->state_decoder_run) return 0;
3300 if (pvr2_encoder_start(hdw) < 0) return !0;
3301 hdw->state_encoder_run = !0;
3302 }
3303 trace_stbit("state_encoder_run",hdw->state_encoder_run);
3304 return !0;
3305}
3306
3307
3308/* Timeout function for quiescent timer. */
3309static void pvr2_hdw_quiescent_timeout(unsigned long data)
3310{
3311 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3312 hdw->state_decoder_quiescent = !0;
3313 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3314 hdw->state_stale = !0;
3315 queue_work(hdw->workqueue,&hdw->workpoll);
3316}
3317
3318
3319/* Timeout function for encoder wait timer. */
3320static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
3321{
3322 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3323 hdw->state_encoder_waitok = !0;
3324 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3325 hdw->state_stale = !0;
3326 queue_work(hdw->workqueue,&hdw->workpoll);
3327}
3328
3329
3330/* Evaluate whether or not state_decoder_run can change */
3331static int state_eval_decoder_run(struct pvr2_hdw *hdw)
3332{
3333 if (hdw->state_decoder_run) {
3334 if (hdw->state_encoder_ok) {
3335 if (hdw->state_pipeline_req &&
3336 !hdw->state_pipeline_pause) return 0;
3337 }
3338 if (!hdw->flag_decoder_missed) {
3339 pvr2_decoder_enable(hdw,0);
3340 }
3341 hdw->state_decoder_quiescent = 0;
3342 hdw->state_decoder_run = 0;
3343 /* paranoia - solve race if timer just completed */
3344 del_timer_sync(&hdw->quiescent_timer);
3345 } else {
3346 if (!hdw->state_decoder_quiescent) {
3347 if (!timer_pending(&hdw->quiescent_timer)) {
3348 /* We don't do something about the
3349 quiescent timer until right here because
3350 we also want to catch cases where the
3351 decoder was already not running (like
3352 after initialization) as opposed to
3353 knowing that we had just stopped it.
3354 The second flag check is here to cover a
3355 race - the timer could have run and set
3356 this flag just after the previous check
3357 but before we did the pending check. */
3358 if (!hdw->state_decoder_quiescent) {
3359 hdw->quiescent_timer.expires =
3360 jiffies + (HZ*50/1000);
3361 add_timer(&hdw->quiescent_timer);
3362 }
3363 }
3364 /* Don't allow decoder to start again until it has
3365 been quiesced first. This little detail should
3366 hopefully further stabilize the encoder. */
3367 return 0;
3368 }
3369 if (!hdw->state_pipeline_req ||
3370 hdw->state_pipeline_pause ||
3371 !hdw->state_pipeline_config ||
3372 !hdw->state_encoder_config ||
3373 !hdw->state_encoder_ok) return 0;
3374 del_timer_sync(&hdw->quiescent_timer);
3375 if (hdw->flag_decoder_missed) return 0;
3376 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
3377 hdw->state_decoder_quiescent = 0;
3378 hdw->state_decoder_run = !0;
3379 }
3380 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3381 trace_stbit("state_decoder_run",hdw->state_decoder_run);
3382 return !0;
3383}
3384
3385
3386/* Evaluate whether or not state_usbstream_run can change */
3387static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
3388{
3389 if (hdw->state_usbstream_run) {
3390 if (hdw->state_encoder_ok) {
3391 if (hdw->state_encoder_run) return 0;
3392 }
3393 pvr2_hdw_cmd_usbstream(hdw,0);
3394 hdw->state_usbstream_run = 0;
3395 } else {
3396 if (!hdw->state_encoder_ok ||
3397 !hdw->state_encoder_run ||
3398 !hdw->state_pipeline_req ||
3399 hdw->state_pipeline_pause) return 0;
3400 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
3401 hdw->state_usbstream_run = !0;
3402 }
3403 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
3404 return !0;
3405}
3406
3407
3408/* Attempt to configure pipeline, if needed */
3409static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
3410{
3411 if (hdw->state_pipeline_config ||
3412 hdw->state_pipeline_pause) return 0;
3413 pvr2_hdw_commit_execute(hdw);
3414 return !0;
3415}
3416
3417
3418/* Update pipeline idle and pipeline pause tracking states based on other
3419 inputs. This must be called whenever the other relevant inputs have
3420 changed. */
3421static int state_update_pipeline_state(struct pvr2_hdw *hdw)
3422{
3423 unsigned int st;
3424 int updatedFl = 0;
3425 /* Update pipeline state */
3426 st = !(hdw->state_encoder_run ||
3427 hdw->state_decoder_run ||
3428 hdw->state_usbstream_run ||
3429 (!hdw->state_decoder_quiescent));
3430 if (!st != !hdw->state_pipeline_idle) {
3431 hdw->state_pipeline_idle = st;
3432 updatedFl = !0;
3433 }
3434 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
3435 hdw->state_pipeline_pause = 0;
3436 updatedFl = !0;
3437 }
3438 return updatedFl;
3439}
3440
3441
3442typedef int (*state_eval_func)(struct pvr2_hdw *);
3443
3444/* Set of functions to be run to evaluate various states in the driver. */
3445const static state_eval_func eval_funcs[] = {
3446 state_eval_pipeline_config,
3447 state_eval_encoder_ok,
3448 state_eval_encoder_config,
3449 state_eval_decoder_run,
3450 state_eval_encoder_run,
3451 state_eval_usbstream_run,
3452};
3453
3454
3455/* Process various states and return true if we did anything interesting. */
3456static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
3457{
3458 unsigned int i;
3459 int state_updated = 0;
3460 int check_flag;
3461
3462 if (!hdw->state_stale) return 0;
3463 if ((hdw->fw1_state != FW1_STATE_OK) ||
3464 !hdw->flag_ok) {
3465 hdw->state_stale = 0;
3466 return !0;
3467 }
3468 /* This loop is the heart of the entire driver. It keeps trying to
3469 evaluate various bits of driver state until nothing changes for
3470 one full iteration. Each "bit of state" tracks some global
3471 aspect of the driver, e.g. whether decoder should run, if
3472 pipeline is configured, usb streaming is on, etc. We separately
3473 evaluate each of those questions based on other driver state to
3474 arrive at the correct running configuration. */
3475 do {
3476 check_flag = 0;
3477 state_update_pipeline_state(hdw);
3478 /* Iterate over each bit of state */
3479 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
3480 if ((*eval_funcs[i])(hdw)) {
3481 check_flag = !0;
3482 state_updated = !0;
3483 state_update_pipeline_state(hdw);
3484 }
3485 }
3486 } while (check_flag && hdw->flag_ok);
3487 hdw->state_stale = 0;
3488 trace_stbit("state_stale",hdw->state_stale);
3489 return state_updated;
3490}
3491
3492
3493static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
3494 char *buf,unsigned int acnt)
3495{
3496 switch (which) {
3497 case 0:
3498 return scnprintf(
3499 buf,acnt,
3500 "driver:%s%s%s%s%s",
3501 (hdw->flag_ok ? " <ok>" : " <fail>"),
3502 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
3503 (hdw->flag_disconnected ? " <disconnected>" :
3504 " <connected>"),
3505 (hdw->flag_tripped ? " <tripped>" : ""),
3506 (hdw->flag_decoder_missed ? " <no decoder>" : ""));
3507 case 1:
3508 return scnprintf(
3509 buf,acnt,
3510 "pipeline:%s%s%s%s",
3511 (hdw->state_pipeline_idle ? " <idle>" : ""),
3512 (hdw->state_pipeline_config ?
3513 " <configok>" : " <stale>"),
3514 (hdw->state_pipeline_req ? " <req>" : ""),
3515 (hdw->state_pipeline_pause ? " <pause>" : ""));
3516 case 2:
3517 return scnprintf(
3518 buf,acnt,
3519 "worker:%s%s%s%s%s%s",
3520 (hdw->state_decoder_run ?
3521 " <decode:run>" :
3522 (hdw->state_decoder_quiescent ?
3523 "" : " <decode:stop>")),
3524 (hdw->state_decoder_quiescent ?
3525 " <decode:quiescent>" : ""),
3526 (hdw->state_encoder_ok ?
3527 "" : " <encode:init>"),
3528 (hdw->state_encoder_run ?
3529 " <encode:run>" : " <encode:stop>"),
3530 (hdw->state_encoder_config ?
3531 " <encode:configok>" :
3532 (hdw->state_encoder_waitok ?
3533 "" : " <encode:wait>")),
3534 (hdw->state_usbstream_run ?
3535 " <usb:run>" : " <usb:stop>"));
3536 break;
3537 case 3:
3538 return scnprintf(
3539 buf,acnt,
3540 "state: %s",
3541 pvr2_get_state_name(hdw->master_state));
3542 break;
3543 default: break;
3544 }
3545 return 0;
3546}
3547
3548
3549unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
3550 char *buf,unsigned int acnt)
3551{
3552 unsigned int bcnt,ccnt,idx;
3553 bcnt = 0;
3554 LOCK_TAKE(hdw->big_lock);
3555 for (idx = 0; ; idx++) {
3556 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
3557 if (!ccnt) break;
3558 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
3559 if (!acnt) break;
3560 buf[0] = '\n'; ccnt = 1;
3561 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
3562 }
3563 LOCK_GIVE(hdw->big_lock);
3564 return bcnt;
3565}
3566
3567
3568static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
3569{
3570 char buf[128];
3571 unsigned int idx,ccnt;
3572
3573 for (idx = 0; ; idx++) {
3574 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
3575 if (!ccnt) break;
3576 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
3577 }
3578}
3579
3580
3581/* Evaluate and update the driver's current state, taking various actions
3582 as appropriate for the update. */
3583static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
3584{
3585 unsigned int st;
3586 int state_updated = 0;
3587 int callback_flag = 0;
3588
3589 pvr2_trace(PVR2_TRACE_STBITS,
3590 "Drive state check START");
3591 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
3592 pvr2_hdw_state_log_state(hdw);
3593 }
3594
3595 /* Process all state and get back over disposition */
3596 state_updated = pvr2_hdw_state_update(hdw);
3597
3598 /* Update master state based upon all other states. */
3599 if (!hdw->flag_ok) {
3600 st = PVR2_STATE_DEAD;
3601 } else if (hdw->fw1_state != FW1_STATE_OK) {
3602 st = PVR2_STATE_COLD;
3603 } else if (!hdw->state_encoder_ok) {
3604 st = PVR2_STATE_WARM;
3605 } else if (hdw->flag_tripped || hdw->flag_decoder_missed) {
3606 st = PVR2_STATE_ERROR;
3607 } else if (hdw->state_encoder_run &&
3608 hdw->state_decoder_run &&
3609 hdw->state_usbstream_run) {
3610 st = PVR2_STATE_RUN;
3611 } else {
3612 st = PVR2_STATE_READY;
3613 }
3614 if (hdw->master_state != st) {
3615 pvr2_trace(PVR2_TRACE_STATE,
3616 "Device state change from %s to %s",
3617 pvr2_get_state_name(hdw->master_state),
3618 pvr2_get_state_name(st));
3619 hdw->master_state = st;
3620 state_updated = !0;
3621 callback_flag = !0;
3622 }
3623 if (state_updated) {
3624 /* Trigger anyone waiting on any state changes here. */
3625 wake_up(&hdw->state_wait_data);
3626 }
3627
3628 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
3629 pvr2_hdw_state_log_state(hdw);
3630 }
3631 pvr2_trace(PVR2_TRACE_STBITS,
3632 "Drive state check DONE callback=%d",callback_flag);
3633
3634 return callback_flag;
3635}
3636
3637
3638/* Cause kernel thread to check / update driver state */
3639static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
3640{
3641 if (hdw->state_stale) return;
3642 hdw->state_stale = !0;
3643 trace_stbit("state_stale",hdw->state_stale);
3644 queue_work(hdw->workqueue,&hdw->workpoll);
3645}
3646
3647
3648void pvr2_hdw_get_debug_info_unlocked(const struct pvr2_hdw *hdw,
3649 struct pvr2_hdw_debug_info *ptr)
d855497e
MI		 3650{
3651 ptr->big_lock_held = hdw->big_lock_held;
3652 ptr->ctl_lock_held = hdw->ctl_lock_held;
d855497e
MI		 3653 ptr->flag_disconnected = hdw->flag_disconnected;
3654 ptr->flag_init_ok = hdw->flag_init_ok;
681c7399
MI		 3655 ptr->flag_ok = hdw->flag_ok;
3656 ptr->fw1_state = hdw->fw1_state;
3657 ptr->flag_decoder_missed = hdw->flag_decoder_missed;
3658 ptr->flag_tripped = hdw->flag_tripped;
3659 ptr->state_encoder_ok = hdw->state_encoder_ok;
3660 ptr->state_encoder_run = hdw->state_encoder_run;
3661 ptr->state_decoder_run = hdw->state_decoder_run;
3662 ptr->state_usbstream_run = hdw->state_usbstream_run;
3663 ptr->state_decoder_quiescent = hdw->state_decoder_quiescent;
3664 ptr->state_pipeline_config = hdw->state_pipeline_config;
3665 ptr->state_pipeline_req = hdw->state_pipeline_req;
3666 ptr->state_pipeline_pause = hdw->state_pipeline_pause;
3667 ptr->state_pipeline_idle = hdw->state_pipeline_idle;
d855497e
MI		 3668 ptr->cmd_debug_state = hdw->cmd_debug_state;
3669 ptr->cmd_code = hdw->cmd_debug_code;
3670 ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
3671 ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
3672 ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
3673 ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
3674 ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
3675 ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
3676 ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
3677}
3678
3679
681c7399
MI		 3680void pvr2_hdw_get_debug_info_locked(struct pvr2_hdw *hdw,
3681 struct pvr2_hdw_debug_info *ptr)
3682{
3683 LOCK_TAKE(hdw->ctl_lock); do {
3684 pvr2_hdw_get_debug_info_unlocked(hdw,ptr);
3685 } while(0); LOCK_GIVE(hdw->ctl_lock);
3686}
3687
3688
d855497e
MI		 3689int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
3690{
3691 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
3692}
3693
3694
3695int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
3696{
3697 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
3698}
3699
3700
3701int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
3702{
3703 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
3704}
3705
3706
3707int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
3708{
3709 u32 cval,nval;
3710 int ret;
3711 if (~msk) {
3712 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
3713 if (ret) return ret;
3714 nval = (cval & ~msk) | (val & msk);
3715 pvr2_trace(PVR2_TRACE_GPIO,
3716 "GPIO direction changing 0x%x:0x%x"
3717 " from 0x%x to 0x%x",
3718 msk,val,cval,nval);
3719 } else {
3720 nval = val;
3721 pvr2_trace(PVR2_TRACE_GPIO,
3722 "GPIO direction changing to 0x%x",nval);
3723 }
3724 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
3725}
3726
3727
3728int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
3729{
3730 u32 cval,nval;
3731 int ret;
3732 if (~msk) {
3733 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
3734 if (ret) return ret;
3735 nval = (cval & ~msk) | (val & msk);
3736 pvr2_trace(PVR2_TRACE_GPIO,
3737 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
3738 msk,val,cval,nval);
3739 } else {
3740 nval = val;
3741 pvr2_trace(PVR2_TRACE_GPIO,
3742 "GPIO output changing to 0x%x",nval);
3743 }
3744 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
3745}
3746
3747
e61b6fc5 3748/* Find I2C address of eeprom */
07e337ee 3749static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 3750{
3751 int result;
3752 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3753 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 3754 result = pvr2_send_request(hdw,
3755 hdw->cmd_buffer,1,
3756 hdw->cmd_buffer,1);
3757 if (result < 0) break;
3758 result = hdw->cmd_buffer[0];
3759 } while(0); LOCK_GIVE(hdw->ctl_lock);
3760 return result;
3761}
3762
3763
32ffa9ae 3764int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
f3d092b8
HV		 3765 u32 match_type, u32 match_chip, u64 reg_id,
3766 int setFl,u64 *val_ptr)
32ffa9ae
MI		 3767{
3768#ifdef CONFIG_VIDEO_ADV_DEBUG
32ffa9ae
MI		 3769 struct pvr2_i2c_client *cp;
3770 struct v4l2_register req;
6d98816f
MI		 3771 int stat = 0;
3772 int okFl = 0;
32ffa9ae 3773
201f5c9c
MI		 3774 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
3775
f3d092b8
HV		 3776 req.match_type = match_type;
3777 req.match_chip = match_chip;
32ffa9ae
MI		 3778 req.reg = reg_id;
3779 if (setFl) req.val = *val_ptr;
3780 mutex_lock(&hdw->i2c_list_lock); do {
e77e2c2f 3781 list_for_each_entry(cp, &hdw->i2c_clients, list) {
8481a750
MI		 3782 if (!v4l2_chip_match_i2c_client(
3783 cp->client,
3784 req.match_type, req.match_chip)) {
f3d092b8
HV		 3785 continue;
3786 }
32ffa9ae 3787 stat = pvr2_i2c_client_cmd(
52ebc763
TP		 3788 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
3789 VIDIOC_DBG_G_REGISTER),&req);
32ffa9ae 3790 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 3791 okFl = !0;
3792 break;
32ffa9ae
MI		 3793 }
3794 } while (0); mutex_unlock(&hdw->i2c_list_lock);
6d98816f
MI		 3795 if (okFl) {
3796 return stat;
3797 }
32ffa9ae
MI		 3798 return -EINVAL;
3799#else
3800 return -ENOSYS;
3801#endif
3802}
3803
3804
d855497e
MI		 3805/*
3806 Stuff for Emacs to see, in order to encourage consistent editing style:
3807 *** Local Variables: ***
3808 *** mode: c ***
3809 *** fill-column: 75 ***
3810 *** tab-width: 8 ***
3811 *** c-basic-offset: 8 ***
3812 *** End: ***
3813 */
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