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Merge branch 'for-linus' of git://git.kernel.dk/linux-2.6-block
[mirror_ubuntu-kernels.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
d855497e
MI		 3 *
4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21#include <linux/errno.h>
22#include <linux/string.h>
23#include <linux/slab.h>
24#include <linux/firmware.h>
d855497e 25#include <linux/videodev2.h>
32ffa9ae 26#include <media/v4l2-common.h>
75212a02 27#include <media/tuner.h>
d855497e
MI		 28#include "pvrusb2.h"
29#include "pvrusb2-std.h"
30#include "pvrusb2-util.h"
31#include "pvrusb2-hdw.h"
32#include "pvrusb2-i2c-core.h"
d855497e
MI		 33#include "pvrusb2-eeprom.h"
34#include "pvrusb2-hdw-internal.h"
35#include "pvrusb2-encoder.h"
36#include "pvrusb2-debug.h"
8d364363 37#include "pvrusb2-fx2-cmd.h"
5f6dae80 38#include "pvrusb2-wm8775.h"
6f956512 39#include "pvrusb2-video-v4l.h"
634ba268 40#include "pvrusb2-cx2584x-v4l.h"
2a6b627f 41#include "pvrusb2-cs53l32a.h"
76891d65 42#include "pvrusb2-audio.h"
d855497e 43
1bde0289
MI		 44#define TV_MIN_FREQ 55250000L
45#define TV_MAX_FREQ 850000000L
25d8527a 46
83ce57aa
MI		 47/* This defines a minimum interval that the decoder must remain quiet
48 before we are allowed to start it running. */
49#define TIME_MSEC_DECODER_WAIT 50
50
51/* This defines a minimum interval that the encoder must remain quiet
fa98e594
MI		 52 before we are allowed to configure it. I had this originally set to
53 50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
54 things work better when it's set to 100msec. */
55#define TIME_MSEC_ENCODER_WAIT 100
83ce57aa
MI		 56
57/* This defines the minimum interval that the encoder must successfully run
58 before we consider that the encoder has run at least once since its
59 firmware has been loaded. This measurement is in important for cases
60 where we can't do something until we know that the encoder has been run
61 at least once. */
62#define TIME_MSEC_ENCODER_OK 250
63
a0fd1cb1 64static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 65static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e 66
ff699e6b 67static int ctlchg;
ff699e6b 68static int procreload;
d855497e
MI		 69static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
70static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
71static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
ff699e6b 72static int init_pause_msec;
d855497e
MI		 73
74module_param(ctlchg, int, S_IRUGO|S_IWUSR);
75MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
76module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
77MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
d855497e
MI		 78module_param(procreload, int, S_IRUGO|S_IWUSR);
79MODULE_PARM_DESC(procreload,
80 "Attempt init failure recovery with firmware reload");
81module_param_array(tuner, int, NULL, 0444);
82MODULE_PARM_DESC(tuner,"specify installed tuner type");
83module_param_array(video_std, int, NULL, 0444);
84MODULE_PARM_DESC(video_std,"specify initial video standard");
85module_param_array(tolerance, int, NULL, 0444);
86MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
87
5a4f5da6
MK		 88/* US Broadcast channel 7 (175.25 MHz) */
89static int default_tv_freq = 175250000L;
90/* 104.3 MHz, a usable FM station for my area */
91static int default_radio_freq = 104300000L;
92
93module_param_named(tv_freq, default_tv_freq, int, 0444);
94MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
95module_param_named(radio_freq, default_radio_freq, int, 0444);
96MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
97
d855497e
MI		 98#define PVR2_CTL_WRITE_ENDPOINT 0x01
99#define PVR2_CTL_READ_ENDPOINT 0x81
100
101#define PVR2_GPIO_IN 0x9008
102#define PVR2_GPIO_OUT 0x900c
103#define PVR2_GPIO_DIR 0x9020
104
105#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
106
107#define PVR2_FIRMWARE_ENDPOINT 0x02
108
109/* size of a firmware chunk */
110#define FIRMWARE_CHUNK_SIZE 0x2000
111
edb9dcb8
MI		 112typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
113 struct v4l2_subdev *);
114
115static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
4ecbc28d 116 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
6f956512 117 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
76891d65 118 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
634ba268 119 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
2a6b627f 120 [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
edb9dcb8
MI		 121};
122
e9c64a78
MI		 123static const char *module_names[] = {
124 [PVR2_CLIENT_ID_MSP3400] = "msp3400",
125 [PVR2_CLIENT_ID_CX25840] = "cx25840",
126 [PVR2_CLIENT_ID_SAA7115] = "saa7115",
127 [PVR2_CLIENT_ID_TUNER] = "tuner",
bb65242a 128 [PVR2_CLIENT_ID_DEMOD] = "tuner",
851981a1 129 [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
5f6dae80 130 [PVR2_CLIENT_ID_WM8775] = "wm8775",
e9c64a78
MI		 131};
132
133
134static const unsigned char *module_i2c_addresses[] = {
135 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
bb65242a 136 [PVR2_CLIENT_ID_DEMOD] = "\x43",
1dfe6c77
MI		 137 [PVR2_CLIENT_ID_MSP3400] = "\x40",
138 [PVR2_CLIENT_ID_SAA7115] = "\x21",
ae111f76 139 [PVR2_CLIENT_ID_WM8775] = "\x1b",
0b467014 140 [PVR2_CLIENT_ID_CX25840] = "\x44",
23334a22 141 [PVR2_CLIENT_ID_CS53L32A] = "\x11",
e9c64a78
MI		 142};
143
144
b30d2441
MI		 145/* Define the list of additional controls we'll dynamically construct based
146 on query of the cx2341x module. */
147struct pvr2_mpeg_ids {
148 const char *strid;
149 int id;
150};
151static const struct pvr2_mpeg_ids mpeg_ids[] = {
152 {
153 .strid = "audio_layer",
154 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
155 },{
156 .strid = "audio_bitrate",
157 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
158 },{
159 /* Already using audio_mode elsewhere :-( */
160 .strid = "mpeg_audio_mode",
161 .id = V4L2_CID_MPEG_AUDIO_MODE,
162 },{
163 .strid = "mpeg_audio_mode_extension",
164 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
165 },{
166 .strid = "audio_emphasis",
167 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
168 },{
169 .strid = "audio_crc",
170 .id = V4L2_CID_MPEG_AUDIO_CRC,
171 },{
172 .strid = "video_aspect",
173 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
174 },{
175 .strid = "video_b_frames",
176 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
177 },{
178 .strid = "video_gop_size",
179 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
180 },{
181 .strid = "video_gop_closure",
182 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 183 },{
184 .strid = "video_bitrate_mode",
185 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
186 },{
187 .strid = "video_bitrate",
188 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
189 },{
190 .strid = "video_bitrate_peak",
191 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
192 },{
193 .strid = "video_temporal_decimation",
194 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
195 },{
196 .strid = "stream_type",
197 .id = V4L2_CID_MPEG_STREAM_TYPE,
198 },{
199 .strid = "video_spatial_filter_mode",
200 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
201 },{
202 .strid = "video_spatial_filter",
203 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
204 },{
205 .strid = "video_luma_spatial_filter_type",
206 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
207 },{
208 .strid = "video_chroma_spatial_filter_type",
209 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
210 },{
211 .strid = "video_temporal_filter_mode",
212 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
213 },{
214 .strid = "video_temporal_filter",
215 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
216 },{
217 .strid = "video_median_filter_type",
218 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
219 },{
220 .strid = "video_luma_median_filter_top",
221 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
222 },{
223 .strid = "video_luma_median_filter_bottom",
224 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
225 },{
226 .strid = "video_chroma_median_filter_top",
227 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
228 },{
229 .strid = "video_chroma_median_filter_bottom",
230 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
231 }
232};
eca8ebfc 233#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 234
434449f4 235
d855497e 236static const char *control_values_srate[] = {
434449f4
MI		 237 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
238 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
239 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 240};
241
242
d855497e 243
d855497e
MI		 244static const char *control_values_input[] = {
245 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
29bf5b1d 246 [PVR2_CVAL_INPUT_DTV] = "dtv",
d855497e
MI		 247 [PVR2_CVAL_INPUT_RADIO] = "radio",
248 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
249 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
250};
251
252
253static const char *control_values_audiomode[] = {
254 [V4L2_TUNER_MODE_MONO] = "Mono",
255 [V4L2_TUNER_MODE_STEREO] = "Stereo",
256 [V4L2_TUNER_MODE_LANG1] = "Lang1",
257 [V4L2_TUNER_MODE_LANG2] = "Lang2",
258 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
259};
260
261
262static const char *control_values_hsm[] = {
263 [PVR2_CVAL_HSM_FAIL] = "Fail",
264 [PVR2_CVAL_HSM_HIGH] = "High",
265 [PVR2_CVAL_HSM_FULL] = "Full",
266};
267
268
681c7399
MI		 269static const char *pvr2_state_names[] = {
270 [PVR2_STATE_NONE] = "none",
271 [PVR2_STATE_DEAD] = "dead",
272 [PVR2_STATE_COLD] = "cold",
273 [PVR2_STATE_WARM] = "warm",
274 [PVR2_STATE_ERROR] = "error",
275 [PVR2_STATE_READY] = "ready",
276 [PVR2_STATE_RUN] = "run",
d855497e
MI		 277};
278
681c7399 279
694dca2b 280struct pvr2_fx2cmd_descdef {
1c9d10d4
MI		 281 unsigned char id;
282 unsigned char *desc;
283};
284
694dca2b 285static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
1c9d10d4
MI		 286 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
287 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
31335b13 288 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
1c9d10d4
MI		 289 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
290 {FX2CMD_REG_WRITE, "write encoder register"},
291 {FX2CMD_REG_READ, "read encoder register"},
292 {FX2CMD_MEMSEL, "encoder memsel"},
293 {FX2CMD_I2C_WRITE, "i2c write"},
294 {FX2CMD_I2C_READ, "i2c read"},
295 {FX2CMD_GET_USB_SPEED, "get USB speed"},
296 {FX2CMD_STREAMING_ON, "stream on"},
297 {FX2CMD_STREAMING_OFF, "stream off"},
298 {FX2CMD_FWPOST1, "fwpost1"},
299 {FX2CMD_POWER_OFF, "power off"},
300 {FX2CMD_POWER_ON, "power on"},
301 {FX2CMD_DEEP_RESET, "deep reset"},
302 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
303 {FX2CMD_GET_IR_CODE, "get IR code"},
304 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
305 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
306 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
307 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
308 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
309 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
310 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
311};
312
313
1cb03b76 314static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
681c7399
MI		 315static void pvr2_hdw_state_sched(struct pvr2_hdw *);
316static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 317static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399 318static void pvr2_hdw_worker_poll(struct work_struct *work);
681c7399
MI		 319static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
320static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
321static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 322static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 323static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 324static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 325static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
326static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
681c7399
MI		 327static void pvr2_hdw_quiescent_timeout(unsigned long);
328static void pvr2_hdw_encoder_wait_timeout(unsigned long);
d913d630 329static void pvr2_hdw_encoder_run_timeout(unsigned long);
1c9d10d4 330static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
07e337ee
AB		 331static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
332 unsigned int timeout,int probe_fl,
333 void *write_data,unsigned int write_len,
334 void *read_data,unsigned int read_len);
432907f7 335static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
d855497e 336
681c7399
MI		 337
338static void trace_stbit(const char *name,int val)
339{
340 pvr2_trace(PVR2_TRACE_STBITS,
341 "State bit %s <-- %s",
342 name,(val ? "true" : "false"));
343}
344
d855497e
MI		 345static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
346{
347 struct pvr2_hdw *hdw = cptr->hdw;
348 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
349 *vp = hdw->freqTable[hdw->freqProgSlot-1];
350 } else {
351 *vp = 0;
352 }
353 return 0;
354}
355
356static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
357{
358 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 359 unsigned int slotId = hdw->freqProgSlot;
360 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
361 hdw->freqTable[slotId-1] = v;
362 /* Handle side effects correctly - if we're tuned to this
363 slot, then forgot the slot id relation since the stored
364 frequency has been changed. */
365 if (hdw->freqSelector) {
366 if (hdw->freqSlotRadio == slotId) {
367 hdw->freqSlotRadio = 0;
368 }
369 } else {
370 if (hdw->freqSlotTelevision == slotId) {
371 hdw->freqSlotTelevision = 0;
372 }
373 }
d855497e
MI		 374 }
375 return 0;
376}
377
378static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
379{
380 *vp = cptr->hdw->freqProgSlot;
381 return 0;
382}
383
384static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
385{
386 struct pvr2_hdw *hdw = cptr->hdw;
387 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
388 hdw->freqProgSlot = v;
389 }
390 return 0;
391}
392
393static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
394{
1bde0289
MI		 395 struct pvr2_hdw *hdw = cptr->hdw;
396 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 397 return 0;
398}
399
1bde0289 400static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 401{
402 unsigned freq = 0;
403 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 404 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
405 if (slotId > 0) {
406 freq = hdw->freqTable[slotId-1];
407 if (!freq) return 0;
408 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 409 }
1bde0289
MI		 410 if (hdw->freqSelector) {
411 hdw->freqSlotRadio = slotId;
412 } else {
413 hdw->freqSlotTelevision = slotId;
d855497e
MI		 414 }
415 return 0;
416}
417
418static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
419{
1bde0289 420 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 421 return 0;
422}
423
424static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
425{
426 return cptr->hdw->freqDirty != 0;
427}
428
429static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
430{
431 cptr->hdw->freqDirty = 0;
432}
433
434static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
435{
1bde0289 436 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 437 return 0;
438}
439
e784bfb9 440static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
441{
432907f7
MI		 442 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
443 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
444 if (stat != 0) {
432907f7 445 return stat;
e784bfb9 446 }
432907f7 447 *left = cap->bounds.left;
e784bfb9 448 return 0;
449}
450
451static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
452{
432907f7
MI		 453 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
454 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
455 if (stat != 0) {
432907f7
MI		 456 return stat;
457 }
458 *left = cap->bounds.left;
459 if (cap->bounds.width > cptr->hdw->cropw_val) {
432907f7 460 *left += cap->bounds.width - cptr->hdw->cropw_val;
e784bfb9 461 }
462 return 0;
463}
464
465static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
466{
432907f7
MI		 467 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
468 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
469 if (stat != 0) {
432907f7 470 return stat;
e784bfb9 471 }
432907f7 472 *top = cap->bounds.top;
e784bfb9 473 return 0;
474}
475
432907f7 476static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
3ad9fc37 477{
432907f7
MI		 478 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
479 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
480 if (stat != 0) {
432907f7
MI		 481 return stat;
482 }
483 *top = cap->bounds.top;
484 if (cap->bounds.height > cptr->hdw->croph_val) {
432907f7 485 *top += cap->bounds.height - cptr->hdw->croph_val;
3ad9fc37
MI		 486 }
487 return 0;
488}
489
432907f7
MI		 490static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
491{
492 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
493 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
494 if (stat != 0) {
432907f7
MI		 495 return stat;
496 }
497 *val = 0;
498 if (cap->bounds.width > cptr->hdw->cropl_val) {
432907f7
MI		 499 *val = cap->bounds.width - cptr->hdw->cropl_val;
500 }
501 return 0;
502}
503
504static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
505{
506 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
507 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
508 if (stat != 0) {
432907f7
MI		 509 return stat;
510 }
511 *val = 0;
512 if (cap->bounds.height > cptr->hdw->cropt_val) {
432907f7
MI		 513 *val = cap->bounds.height - cptr->hdw->cropt_val;
514 }
515 return 0;
516}
517
518static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
519{
520 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
521 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
522 if (stat != 0) {
432907f7
MI		 523 return stat;
524 }
525 *val = cap->bounds.left;
526 return 0;
527}
528
529static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
530{
531 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
532 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
533 if (stat != 0) {
432907f7
MI		 534 return stat;
535 }
536 *val = cap->bounds.top;
537 return 0;
538}
539
540static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
541{
542 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
543 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
544 if (stat != 0) {
432907f7
MI		 545 return stat;
546 }
547 *val = cap->bounds.width;
548 return 0;
549}
550
551static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
552{
553 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
554 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
555 if (stat != 0) {
432907f7
MI		 556 return stat;
557 }
558 *val = cap->bounds.height;
559 return 0;
560}
561
562static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
563{
564 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
565 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
566 if (stat != 0) {
432907f7
MI		 567 return stat;
568 }
569 *val = cap->defrect.left;
570 return 0;
571}
572
573static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
574{
575 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
576 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
577 if (stat != 0) {
432907f7
MI		 578 return stat;
579 }
580 *val = cap->defrect.top;
581 return 0;
582}
583
584static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
585{
586 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
587 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
588 if (stat != 0) {
432907f7
MI		 589 return stat;
590 }
591 *val = cap->defrect.width;
592 return 0;
593}
594
595static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
596{
597 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
598 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
599 if (stat != 0) {
432907f7
MI		 600 return stat;
601 }
602 *val = cap->defrect.height;
603 return 0;
604}
605
606static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
607{
608 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
609 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
610 if (stat != 0) {
432907f7
MI		 611 return stat;
612 }
613 *val = cap->pixelaspect.numerator;
614 return 0;
615}
616
617static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
618{
619 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
620 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
621 if (stat != 0) {
432907f7
MI		 622 return stat;
623 }
624 *val = cap->pixelaspect.denominator;
625 return 0;
626}
627
628static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
e784bfb9 629{
432907f7
MI		 630 /* Actual maximum depends on the video standard in effect. */
631 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
632 *vp = 480;
e784bfb9 633 } else {
432907f7 634 *vp = 576;
e784bfb9 635 }
636 return 0;
637}
638
3ad9fc37
MI		 639static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
640{
989eb154
MI		 641 /* Actual minimum depends on device digitizer type. */
642 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 643 *vp = 75;
644 } else {
645 *vp = 17;
646 }
647 return 0;
648}
649
1bde0289 650static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 651{
1bde0289
MI		 652 *vp = cptr->hdw->input_val;
653 return 0;
654}
655
29bf5b1d
MI		 656static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
657{
1cb03b76 658 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
29bf5b1d
MI		 659}
660
1bde0289
MI		 661static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
662{
1cb03b76 663 return pvr2_hdw_set_input(cptr->hdw,v);
1bde0289
MI		 664}
665
666static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
667{
668 return cptr->hdw->input_dirty != 0;
669}
670
671static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
672{
673 cptr->hdw->input_dirty = 0;
674}
675
5549f54f 676
25d8527a
PK		 677static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
678{
644afdb9
MI		 679 unsigned long fv;
680 struct pvr2_hdw *hdw = cptr->hdw;
681 if (hdw->tuner_signal_stale) {
a51f5000 682 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 683 }
684 fv = hdw->tuner_signal_info.rangehigh;
685 if (!fv) {
686 /* Safety fallback */
25d8527a 687 *vp = TV_MAX_FREQ;
644afdb9 688 return 0;
25d8527a 689 }
644afdb9
MI		 690 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
691 fv = (fv * 125) / 2;
692 } else {
693 fv = fv * 62500;
694 }
695 *vp = fv;
25d8527a
PK		 696 return 0;
697}
698
699static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
700{
644afdb9
MI		 701 unsigned long fv;
702 struct pvr2_hdw *hdw = cptr->hdw;
703 if (hdw->tuner_signal_stale) {
a51f5000 704 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 705 }
706 fv = hdw->tuner_signal_info.rangelow;
707 if (!fv) {
708 /* Safety fallback */
25d8527a 709 *vp = TV_MIN_FREQ;
644afdb9
MI		 710 return 0;
711 }
712 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
713 fv = (fv * 125) / 2;
714 } else {
715 fv = fv * 62500;
25d8527a 716 }
644afdb9 717 *vp = fv;
25d8527a
PK		 718 return 0;
719}
720
b30d2441
MI		 721static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
722{
723 return cptr->hdw->enc_stale != 0;
724}
725
726static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
727{
728 cptr->hdw->enc_stale = 0;
681c7399 729 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 730}
731
732static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
733{
734 int ret;
735 struct v4l2_ext_controls cs;
736 struct v4l2_ext_control c1;
737 memset(&cs,0,sizeof(cs));
738 memset(&c1,0,sizeof(c1));
739 cs.controls = &c1;
740 cs.count = 1;
741 c1.id = cptr->info->v4l_id;
01f1e44f 742 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 743 VIDIOC_G_EXT_CTRLS);
744 if (ret) return ret;
745 *vp = c1.value;
746 return 0;
747}
748
749static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
750{
751 int ret;
681c7399 752 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 753 struct v4l2_ext_controls cs;
754 struct v4l2_ext_control c1;
755 memset(&cs,0,sizeof(cs));
756 memset(&c1,0,sizeof(c1));
757 cs.controls = &c1;
758 cs.count = 1;
759 c1.id = cptr->info->v4l_id;
760 c1.value = v;
681c7399
MI		 761 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
762 hdw->state_encoder_run, &cs,
b30d2441 763 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 764 if (ret == -EBUSY) {
765 /* Oops. cx2341x is telling us it's not safe to change
766 this control while we're capturing. Make a note of this
767 fact so that the pipeline will be stopped the next time
768 controls are committed. Then go on ahead and store this
769 change anyway. */
770 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
771 0, &cs,
772 VIDIOC_S_EXT_CTRLS);
773 if (!ret) hdw->enc_unsafe_stale = !0;
774 }
b30d2441 775 if (ret) return ret;
681c7399 776 hdw->enc_stale = !0;
b30d2441
MI		 777 return 0;
778}
779
780static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
781{
782 struct v4l2_queryctrl qctrl;
783 struct pvr2_ctl_info *info;
784 qctrl.id = cptr->info->v4l_id;
785 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
786 /* Strip out the const so we can adjust a function pointer. It's
787 OK to do this here because we know this is a dynamically created
788 control, so the underlying storage for the info pointer is (a)
789 private to us, and (b) not in read-only storage. Either we do
790 this or we significantly complicate the underlying control
791 implementation. */
792 info = (struct pvr2_ctl_info *)(cptr->info);
793 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
794 if (info->set_value) {
a0fd1cb1 795 info->set_value = NULL;
b30d2441
MI		 796 }
797 } else {
798 if (!(info->set_value)) {
799 info->set_value = ctrl_cx2341x_set;
800 }
801 }
802 return qctrl.flags;
803}
804
d855497e
MI		 805static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
806{
681c7399
MI		 807 *vp = cptr->hdw->state_pipeline_req;
808 return 0;
809}
810
811static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
812{
813 *vp = cptr->hdw->master_state;
d855497e
MI		 814 return 0;
815}
816
817static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
818{
819 int result = pvr2_hdw_is_hsm(cptr->hdw);
820 *vp = PVR2_CVAL_HSM_FULL;
821 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
822 if (result) *vp = PVR2_CVAL_HSM_HIGH;
823 return 0;
824}
825
826static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
827{
828 *vp = cptr->hdw->std_mask_avail;
829 return 0;
830}
831
832static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
833{
834 struct pvr2_hdw *hdw = cptr->hdw;
835 v4l2_std_id ns;
836 ns = hdw->std_mask_avail;
837 ns = (ns & ~m) | (v & m);
838 if (ns == hdw->std_mask_avail) return 0;
839 hdw->std_mask_avail = ns;
840 pvr2_hdw_internal_set_std_avail(hdw);
841 pvr2_hdw_internal_find_stdenum(hdw);
842 return 0;
843}
844
845static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
846 char *bufPtr,unsigned int bufSize,
847 unsigned int *len)
848{
849 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
850 return 0;
851}
852
853static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
854 const char *bufPtr,unsigned int bufSize,
855 int *mskp,int *valp)
856{
857 int ret;
858 v4l2_std_id id;
859 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
860 if (ret < 0) return ret;
861 if (mskp) *mskp = id;
862 if (valp) *valp = id;
863 return 0;
864}
865
866static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
867{
868 *vp = cptr->hdw->std_mask_cur;
869 return 0;
870}
871
872static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
873{
874 struct pvr2_hdw *hdw = cptr->hdw;
875 v4l2_std_id ns;
876 ns = hdw->std_mask_cur;
877 ns = (ns & ~m) | (v & m);
878 if (ns == hdw->std_mask_cur) return 0;
879 hdw->std_mask_cur = ns;
880 hdw->std_dirty = !0;
881 pvr2_hdw_internal_find_stdenum(hdw);
882 return 0;
883}
884
885static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
886{
887 return cptr->hdw->std_dirty != 0;
888}
889
890static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
891{
892 cptr->hdw->std_dirty = 0;
893}
894
895static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
896{
18103c57 897 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 898 pvr2_hdw_status_poll(hdw);
18103c57
MI		 899 *vp = hdw->tuner_signal_info.signal;
900 return 0;
901}
902
903static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
904{
905 int val = 0;
906 unsigned int subchan;
907 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 908 pvr2_hdw_status_poll(hdw);
18103c57
MI		 909 subchan = hdw->tuner_signal_info.rxsubchans;
910 if (subchan & V4L2_TUNER_SUB_MONO) {
911 val |= (1 << V4L2_TUNER_MODE_MONO);
912 }
913 if (subchan & V4L2_TUNER_SUB_STEREO) {
914 val |= (1 << V4L2_TUNER_MODE_STEREO);
915 }
916 if (subchan & V4L2_TUNER_SUB_LANG1) {
917 val |= (1 << V4L2_TUNER_MODE_LANG1);
918 }
919 if (subchan & V4L2_TUNER_SUB_LANG2) {
920 val |= (1 << V4L2_TUNER_MODE_LANG2);
921 }
922 *vp = val;
d855497e
MI		 923 return 0;
924}
925
d855497e
MI		 926
927static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
928{
929 struct pvr2_hdw *hdw = cptr->hdw;
930 if (v < 0) return -EINVAL;
931 if (v > hdw->std_enum_cnt) return -EINVAL;
932 hdw->std_enum_cur = v;
933 if (!v) return 0;
934 v--;
935 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
936 hdw->std_mask_cur = hdw->std_defs[v].id;
937 hdw->std_dirty = !0;
938 return 0;
939}
940
941
942static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
943{
944 *vp = cptr->hdw->std_enum_cur;
945 return 0;
946}
947
948
949static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
950{
951 return cptr->hdw->std_dirty != 0;
952}
953
954
955static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
956{
957 cptr->hdw->std_dirty = 0;
958}
959
960
961#define DEFINT(vmin,vmax) \
962 .type = pvr2_ctl_int, \
963 .def.type_int.min_value = vmin, \
964 .def.type_int.max_value = vmax
965
966#define DEFENUM(tab) \
967 .type = pvr2_ctl_enum, \
27c7b710 968 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 969 .def.type_enum.value_names = tab
970
33213963
MI		 971#define DEFBOOL \
972 .type = pvr2_ctl_bool
973
d855497e
MI		 974#define DEFMASK(msk,tab) \
975 .type = pvr2_ctl_bitmask, \
976 .def.type_bitmask.valid_bits = msk, \
977 .def.type_bitmask.bit_names = tab
978
979#define DEFREF(vname) \
980 .set_value = ctrl_set_##vname, \
981 .get_value = ctrl_get_##vname, \
982 .is_dirty = ctrl_isdirty_##vname, \
983 .clear_dirty = ctrl_cleardirty_##vname
984
985
986#define VCREATE_FUNCS(vname) \
987static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
988{*vp = cptr->hdw->vname##_val; return 0;} \
989static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
990{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
991static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
992{return cptr->hdw->vname##_dirty != 0;} \
993static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
994{cptr->hdw->vname##_dirty = 0;}
995
996VCREATE_FUNCS(brightness)
997VCREATE_FUNCS(contrast)
998VCREATE_FUNCS(saturation)
999VCREATE_FUNCS(hue)
1000VCREATE_FUNCS(volume)
1001VCREATE_FUNCS(balance)
1002VCREATE_FUNCS(bass)
1003VCREATE_FUNCS(treble)
1004VCREATE_FUNCS(mute)
e784bfb9 1005VCREATE_FUNCS(cropl)
1006VCREATE_FUNCS(cropt)
1007VCREATE_FUNCS(cropw)
1008VCREATE_FUNCS(croph)
c05c0462
MI		 1009VCREATE_FUNCS(audiomode)
1010VCREATE_FUNCS(res_hor)
1011VCREATE_FUNCS(res_ver)
d855497e 1012VCREATE_FUNCS(srate)
d855497e 1013
d855497e
MI		 1014/* Table definition of all controls which can be manipulated */
1015static const struct pvr2_ctl_info control_defs[] = {
1016 {
1017 .v4l_id = V4L2_CID_BRIGHTNESS,
1018 .desc = "Brightness",
1019 .name = "brightness",
1020 .default_value = 128,
1021 DEFREF(brightness),
1022 DEFINT(0,255),
1023 },{
1024 .v4l_id = V4L2_CID_CONTRAST,
1025 .desc = "Contrast",
1026 .name = "contrast",
1027 .default_value = 68,
1028 DEFREF(contrast),
1029 DEFINT(0,127),
1030 },{
1031 .v4l_id = V4L2_CID_SATURATION,
1032 .desc = "Saturation",
1033 .name = "saturation",
1034 .default_value = 64,
1035 DEFREF(saturation),
1036 DEFINT(0,127),
1037 },{
1038 .v4l_id = V4L2_CID_HUE,
1039 .desc = "Hue",
1040 .name = "hue",
1041 .default_value = 0,
1042 DEFREF(hue),
1043 DEFINT(-128,127),
1044 },{
1045 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1046 .desc = "Volume",
1047 .name = "volume",
139eecf9 1048 .default_value = 62000,
d855497e
MI		 1049 DEFREF(volume),
1050 DEFINT(0,65535),
1051 },{
1052 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1053 .desc = "Balance",
1054 .name = "balance",
1055 .default_value = 0,
1056 DEFREF(balance),
1057 DEFINT(-32768,32767),
1058 },{
1059 .v4l_id = V4L2_CID_AUDIO_BASS,
1060 .desc = "Bass",
1061 .name = "bass",
1062 .default_value = 0,
1063 DEFREF(bass),
1064 DEFINT(-32768,32767),
1065 },{
1066 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1067 .desc = "Treble",
1068 .name = "treble",
1069 .default_value = 0,
1070 DEFREF(treble),
1071 DEFINT(-32768,32767),
1072 },{
1073 .v4l_id = V4L2_CID_AUDIO_MUTE,
1074 .desc = "Mute",
1075 .name = "mute",
1076 .default_value = 0,
1077 DEFREF(mute),
33213963 1078 DEFBOOL,
e784bfb9 1079 }, {
432907f7 1080 .desc = "Capture crop left margin",
e784bfb9 1081 .name = "crop_left",
1082 .internal_id = PVR2_CID_CROPL,
1083 .default_value = 0,
1084 DEFREF(cropl),
1085 DEFINT(-129, 340),
1086 .get_min_value = ctrl_cropl_min_get,
1087 .get_max_value = ctrl_cropl_max_get,
432907f7 1088 .get_def_value = ctrl_get_cropcapdl,
e784bfb9 1089 }, {
432907f7 1090 .desc = "Capture crop top margin",
e784bfb9 1091 .name = "crop_top",
1092 .internal_id = PVR2_CID_CROPT,
1093 .default_value = 0,
1094 DEFREF(cropt),
1095 DEFINT(-35, 544),
1096 .get_min_value = ctrl_cropt_min_get,
1097 .get_max_value = ctrl_cropt_max_get,
432907f7 1098 .get_def_value = ctrl_get_cropcapdt,
e784bfb9 1099 }, {
432907f7 1100 .desc = "Capture crop width",
e784bfb9 1101 .name = "crop_width",
1102 .internal_id = PVR2_CID_CROPW,
1103 .default_value = 720,
1104 DEFREF(cropw),
432907f7
MI		 1105 .get_max_value = ctrl_cropw_max_get,
1106 .get_def_value = ctrl_get_cropcapdw,
e784bfb9 1107 }, {
432907f7 1108 .desc = "Capture crop height",
e784bfb9 1109 .name = "crop_height",
1110 .internal_id = PVR2_CID_CROPH,
1111 .default_value = 480,
1112 DEFREF(croph),
432907f7
MI		 1113 .get_max_value = ctrl_croph_max_get,
1114 .get_def_value = ctrl_get_cropcapdh,
1115 }, {
1116 .desc = "Capture capability pixel aspect numerator",
1117 .name = "cropcap_pixel_numerator",
1118 .internal_id = PVR2_CID_CROPCAPPAN,
1119 .get_value = ctrl_get_cropcappan,
1120 }, {
1121 .desc = "Capture capability pixel aspect denominator",
1122 .name = "cropcap_pixel_denominator",
1123 .internal_id = PVR2_CID_CROPCAPPAD,
1124 .get_value = ctrl_get_cropcappad,
1125 }, {
1126 .desc = "Capture capability bounds top",
1127 .name = "cropcap_bounds_top",
1128 .internal_id = PVR2_CID_CROPCAPBT,
1129 .get_value = ctrl_get_cropcapbt,
1130 }, {
1131 .desc = "Capture capability bounds left",
1132 .name = "cropcap_bounds_left",
1133 .internal_id = PVR2_CID_CROPCAPBL,
1134 .get_value = ctrl_get_cropcapbl,
1135 }, {
1136 .desc = "Capture capability bounds width",
1137 .name = "cropcap_bounds_width",
1138 .internal_id = PVR2_CID_CROPCAPBW,
1139 .get_value = ctrl_get_cropcapbw,
1140 }, {
1141 .desc = "Capture capability bounds height",
1142 .name = "cropcap_bounds_height",
1143 .internal_id = PVR2_CID_CROPCAPBH,
1144 .get_value = ctrl_get_cropcapbh,
c05c0462
MI		 1145 },{
1146 .desc = "Video Source",
1147 .name = "input",
1148 .internal_id = PVR2_CID_INPUT,
1149 .default_value = PVR2_CVAL_INPUT_TV,
29bf5b1d 1150 .check_value = ctrl_check_input,
c05c0462
MI		 1151 DEFREF(input),
1152 DEFENUM(control_values_input),
1153 },{
1154 .desc = "Audio Mode",
1155 .name = "audio_mode",
1156 .internal_id = PVR2_CID_AUDIOMODE,
1157 .default_value = V4L2_TUNER_MODE_STEREO,
1158 DEFREF(audiomode),
1159 DEFENUM(control_values_audiomode),
1160 },{
1161 .desc = "Horizontal capture resolution",
1162 .name = "resolution_hor",
1163 .internal_id = PVR2_CID_HRES,
1164 .default_value = 720,
1165 DEFREF(res_hor),
3ad9fc37 1166 DEFINT(19,720),
c05c0462
MI		 1167 },{
1168 .desc = "Vertical capture resolution",
1169 .name = "resolution_ver",
1170 .internal_id = PVR2_CID_VRES,
1171 .default_value = 480,
1172 DEFREF(res_ver),
3ad9fc37
MI		 1173 DEFINT(17,576),
1174 /* Hook in check for video standard and adjust maximum
1175 depending on the standard. */
1176 .get_max_value = ctrl_vres_max_get,
1177 .get_min_value = ctrl_vres_min_get,
d855497e 1178 },{
b30d2441 1179 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 1180 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1181 .desc = "Audio Sampling Frequency",
d855497e 1182 .name = "srate",
d855497e
MI		 1183 DEFREF(srate),
1184 DEFENUM(control_values_srate),
d855497e
MI		 1185 },{
1186 .desc = "Tuner Frequency (Hz)",
1187 .name = "frequency",
1188 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 1189 .default_value = 0,
d855497e
MI		 1190 .set_value = ctrl_freq_set,
1191 .get_value = ctrl_freq_get,
1192 .is_dirty = ctrl_freq_is_dirty,
1193 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 1194 DEFINT(0,0),
25d8527a
PK		 1195 /* Hook in check for input value (tv/radio) and adjust
1196 max/min values accordingly */
1197 .get_max_value = ctrl_freq_max_get,
1198 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1199 },{
1200 .desc = "Channel",
1201 .name = "channel",
1202 .set_value = ctrl_channel_set,
1203 .get_value = ctrl_channel_get,
1204 DEFINT(0,FREQTABLE_SIZE),
1205 },{
1206 .desc = "Channel Program Frequency",
1207 .name = "freq_table_value",
1208 .set_value = ctrl_channelfreq_set,
1209 .get_value = ctrl_channelfreq_get,
644afdb9 1210 DEFINT(0,0),
1bde0289
MI		 1211 /* Hook in check for input value (tv/radio) and adjust
1212 max/min values accordingly */
1bde0289
MI		 1213 .get_max_value = ctrl_freq_max_get,
1214 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1215 },{
1216 .desc = "Channel Program ID",
1217 .name = "freq_table_channel",
1218 .set_value = ctrl_channelprog_set,
1219 .get_value = ctrl_channelprog_get,
1220 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 1221 },{
1222 .desc = "Streaming Enabled",
1223 .name = "streaming_enabled",
1224 .get_value = ctrl_streamingenabled_get,
33213963 1225 DEFBOOL,
d855497e
MI		 1226 },{
1227 .desc = "USB Speed",
1228 .name = "usb_speed",
1229 .get_value = ctrl_hsm_get,
1230 DEFENUM(control_values_hsm),
681c7399
MI		 1231 },{
1232 .desc = "Master State",
1233 .name = "master_state",
1234 .get_value = ctrl_masterstate_get,
1235 DEFENUM(pvr2_state_names),
d855497e
MI		 1236 },{
1237 .desc = "Signal Present",
1238 .name = "signal_present",
1239 .get_value = ctrl_signal_get,
18103c57
MI		 1240 DEFINT(0,65535),
1241 },{
1242 .desc = "Audio Modes Present",
1243 .name = "audio_modes_present",
1244 .get_value = ctrl_audio_modes_present_get,
1245 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1246 v4l. Nothing outside of this module cares about this,
1247 but I reuse it in order to also reuse the
1248 control_values_audiomode string table. */
1249 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1250 (1 << V4L2_TUNER_MODE_STEREO)|
1251 (1 << V4L2_TUNER_MODE_LANG1)|
1252 (1 << V4L2_TUNER_MODE_LANG2)),
1253 control_values_audiomode),
d855497e
MI		 1254 },{
1255 .desc = "Video Standards Available Mask",
1256 .name = "video_standard_mask_available",
1257 .internal_id = PVR2_CID_STDAVAIL,
1258 .skip_init = !0,
1259 .get_value = ctrl_stdavail_get,
1260 .set_value = ctrl_stdavail_set,
1261 .val_to_sym = ctrl_std_val_to_sym,
1262 .sym_to_val = ctrl_std_sym_to_val,
1263 .type = pvr2_ctl_bitmask,
1264 },{
1265 .desc = "Video Standards In Use Mask",
1266 .name = "video_standard_mask_active",
1267 .internal_id = PVR2_CID_STDCUR,
1268 .skip_init = !0,
1269 .get_value = ctrl_stdcur_get,
1270 .set_value = ctrl_stdcur_set,
1271 .is_dirty = ctrl_stdcur_is_dirty,
1272 .clear_dirty = ctrl_stdcur_clear_dirty,
1273 .val_to_sym = ctrl_std_val_to_sym,
1274 .sym_to_val = ctrl_std_sym_to_val,
1275 .type = pvr2_ctl_bitmask,
d855497e
MI		 1276 },{
1277 .desc = "Video Standard Name",
1278 .name = "video_standard",
1279 .internal_id = PVR2_CID_STDENUM,
1280 .skip_init = !0,
1281 .get_value = ctrl_stdenumcur_get,
1282 .set_value = ctrl_stdenumcur_set,
1283 .is_dirty = ctrl_stdenumcur_is_dirty,
1284 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1285 .type = pvr2_ctl_enum,
1286 }
1287};
1288
eca8ebfc 1289#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 1290
1291
1292const char *pvr2_config_get_name(enum pvr2_config cfg)
1293{
1294 switch (cfg) {
1295 case pvr2_config_empty: return "empty";
1296 case pvr2_config_mpeg: return "mpeg";
1297 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 1298 case pvr2_config_pcm: return "pcm";
1299 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 1300 }
1301 return "<unknown>";
1302}
1303
1304
1305struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1306{
1307 return hdw->usb_dev;
1308}
1309
1310
1311unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1312{
1313 return hdw->serial_number;
1314}
1315
31a18547
MI		 1316
1317const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1318{
1319 return hdw->bus_info;
1320}
1321
1322
13a88797
MI		 1323const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1324{
1325 return hdw->identifier;
1326}
1327
1328
1bde0289
MI		 1329unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1330{
1331 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1332}
1333
1334/* Set the currently tuned frequency and account for all possible
1335 driver-core side effects of this action. */
f55a8712 1336static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1bde0289 1337{
7c74e57e 1338 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 1339 if (hdw->freqSelector) {
1340 /* Swing over to radio frequency selection */
1341 hdw->freqSelector = 0;
1342 hdw->freqDirty = !0;
1343 }
1bde0289
MI		 1344 if (hdw->freqValRadio != val) {
1345 hdw->freqValRadio = val;
1346 hdw->freqSlotRadio = 0;
7c74e57e 1347 hdw->freqDirty = !0;
1bde0289 1348 }
7c74e57e 1349 } else {
1bde0289
MI		 1350 if (!(hdw->freqSelector)) {
1351 /* Swing over to television frequency selection */
1352 hdw->freqSelector = 1;
1353 hdw->freqDirty = !0;
1354 }
1bde0289
MI		 1355 if (hdw->freqValTelevision != val) {
1356 hdw->freqValTelevision = val;
1357 hdw->freqSlotTelevision = 0;
7c74e57e 1358 hdw->freqDirty = !0;
1bde0289 1359 }
1bde0289
MI		 1360 }
1361}
1362
d855497e
MI		 1363int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1364{
1365 return hdw->unit_number;
1366}
1367
1368
1369/* Attempt to locate one of the given set of files. Messages are logged
1370 appropriate to what has been found. The return value will be 0 or
1371 greater on success (it will be the index of the file name found) and
1372 fw_entry will be filled in. Otherwise a negative error is returned on
1373 failure. If the return value is -ENOENT then no viable firmware file
1374 could be located. */
1375static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1376 const struct firmware **fw_entry,
1377 const char *fwtypename,
1378 unsigned int fwcount,
1379 const char *fwnames[])
1380{
1381 unsigned int idx;
1382 int ret = -EINVAL;
1383 for (idx = 0; idx < fwcount; idx++) {
1384 ret = request_firmware(fw_entry,
1385 fwnames[idx],
1386 &hdw->usb_dev->dev);
1387 if (!ret) {
1388 trace_firmware("Located %s firmware: %s;"
1389 " uploading...",
1390 fwtypename,
1391 fwnames[idx]);
1392 return idx;
1393 }
1394 if (ret == -ENOENT) continue;
1395 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1396 "request_firmware fatal error with code=%d",ret);
1397 return ret;
1398 }
1399 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1400 "***WARNING***"
1401 " Device %s firmware"
1402 " seems to be missing.",
1403 fwtypename);
1404 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1405 "Did you install the pvrusb2 firmware files"
1406 " in their proper location?");
1407 if (fwcount == 1) {
1408 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1409 "request_firmware unable to locate %s file %s",
1410 fwtypename,fwnames[0]);
1411 } else {
1412 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1413 "request_firmware unable to locate"
1414 " one of the following %s files:",
1415 fwtypename);
1416 for (idx = 0; idx < fwcount; idx++) {
1417 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1418 "request_firmware: Failed to find %s",
1419 fwnames[idx]);
1420 }
1421 }
1422 return ret;
1423}
1424
1425
1426/*
1427 * pvr2_upload_firmware1().
1428 *
1429 * Send the 8051 firmware to the device. After the upload, arrange for
1430 * device to re-enumerate.
1431 *
1432 * NOTE : the pointer to the firmware data given by request_firmware()
1433 * is not suitable for an usb transaction.
1434 *
1435 */
07e337ee 1436static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1437{
a0fd1cb1 1438 const struct firmware *fw_entry = NULL;
d855497e
MI		 1439 void *fw_ptr;
1440 unsigned int pipe;
1441 int ret;
1442 u16 address;
1d643a37 1443
989eb154 1444 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1445 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1446 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1447 "Connected device type defines"
1448 " no firmware to upload; ignoring firmware");
1449 return -ENOTTY;
1d643a37
MI		 1450 }
1451
d855497e
MI		 1452 hdw->fw1_state = FW1_STATE_FAILED; // default result
1453
1454 trace_firmware("pvr2_upload_firmware1");
1455
1456 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1457 hdw->hdw_desc->fx2_firmware.cnt,
1458 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1459 if (ret < 0) {
1460 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1461 return ret;
1462 }
1463
1464 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1465 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1466
1467 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1468
1469 if (fw_entry->size != 0x2000){
1470 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1471 release_firmware(fw_entry);
1472 return -ENOMEM;
1473 }
1474
1475 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1476 if (fw_ptr == NULL){
1477 release_firmware(fw_entry);
1478 return -ENOMEM;
1479 }
1480
1481 /* We have to hold the CPU during firmware upload. */
1482 pvr2_hdw_cpureset_assert(hdw,1);
1483
1484 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1485 chunk. */
1486
1487 ret = 0;
1488 for(address = 0; address < fw_entry->size; address += 0x800) {
1489 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1490 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1491 0, fw_ptr, 0x800, HZ);
1492 }
1493
1494 trace_firmware("Upload done, releasing device's CPU");
1495
1496 /* Now release the CPU. It will disconnect and reconnect later. */
1497 pvr2_hdw_cpureset_assert(hdw,0);
1498
1499 kfree(fw_ptr);
1500 release_firmware(fw_entry);
1501
1502 trace_firmware("Upload done (%d bytes sent)",ret);
1503
1504 /* We should have written 8192 bytes */
1505 if (ret == 8192) {
1506 hdw->fw1_state = FW1_STATE_RELOAD;
1507 return 0;
1508 }
1509
1510 return -EIO;
1511}
1512
1513
1514/*
1515 * pvr2_upload_firmware2()
1516 *
1517 * This uploads encoder firmware on endpoint 2.
1518 *
1519 */
1520
1521int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1522{
a0fd1cb1 1523 const struct firmware *fw_entry = NULL;
d855497e 1524 void *fw_ptr;
90060d32 1525 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1526 int actual_length;
1527 int ret = 0;
1528 int fwidx;
1529 static const char *fw_files[] = {
1530 CX2341X_FIRM_ENC_FILENAME,
1531 };
1532
989eb154 1533 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1534 return 0;
1535 }
1536
d855497e
MI		 1537 trace_firmware("pvr2_upload_firmware2");
1538
1539 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1540 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1541 if (ret < 0) return ret;
1542 fwidx = ret;
1543 ret = 0;
b30d2441
MI		 1544 /* Since we're about to completely reinitialize the encoder,
1545 invalidate our cached copy of its configuration state. Next
1546 time we configure the encoder, then we'll fully configure it. */
1547 hdw->enc_cur_valid = 0;
d855497e 1548
d913d630
MI		 1549 /* Encoder is about to be reset so note that as far as we're
1550 concerned now, the encoder has never been run. */
1551 del_timer_sync(&hdw->encoder_run_timer);
1552 if (hdw->state_encoder_runok) {
1553 hdw->state_encoder_runok = 0;
1554 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1555 }
1556
d855497e
MI		 1557 /* First prepare firmware loading */
1558 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1559 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1560 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1561 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1562 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1563 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1564 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1565 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1566 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1567 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1568 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1569 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1570 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1571 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1572 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1573 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1c9d10d4
MI		 1574 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1575 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1576
1577 if (ret) {
1578 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1579 "firmware2 upload prep failed, ret=%d",ret);
1580 release_firmware(fw_entry);
21684ba9 1581 goto done;
d855497e
MI		 1582 }
1583
1584 /* Now send firmware */
1585
1586 fw_len = fw_entry->size;
1587
90060d32 1588 if (fw_len % sizeof(u32)) {
d855497e
MI		 1589 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1590 "size of %s firmware"
48dc30a1 1591 " must be a multiple of %zu bytes",
90060d32 1592 fw_files[fwidx],sizeof(u32));
d855497e 1593 release_firmware(fw_entry);
21684ba9
MI		 1594 ret = -EINVAL;
1595 goto done;
d855497e
MI		 1596 }
1597
1598 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1599 if (fw_ptr == NULL){
1600 release_firmware(fw_entry);
1601 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1602 "failed to allocate memory for firmware2 upload");
21684ba9
MI		 1603 ret = -ENOMEM;
1604 goto done;
d855497e
MI		 1605 }
1606
1607 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1608
90060d32
MI		 1609 fw_done = 0;
1610 for (fw_done = 0; fw_done < fw_len;) {
1611 bcnt = fw_len - fw_done;
1612 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1613 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1614 /* Usbsnoop log shows that we must swap bytes... */
5f33df14
MI		 1615 /* Some background info: The data being swapped here is a
1616 firmware image destined for the mpeg encoder chip that
1617 lives at the other end of a USB endpoint. The encoder
1618 chip always talks in 32 bit chunks and its storage is
1619 organized into 32 bit words. However from the file
1620 system to the encoder chip everything is purely a byte
1621 stream. The firmware file's contents are always 32 bit
1622 swapped from what the encoder expects. Thus the need
1623 always exists to swap the bytes regardless of the endian
1624 type of the host processor and therefore swab32() makes
1625 the most sense. */
90060d32 1626 for (icnt = 0; icnt < bcnt/4 ; icnt++)
513edce6 1627 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
90060d32
MI		 1628
1629 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1630 &actual_length, HZ);
90060d32
MI		 1631 ret |= (actual_length != bcnt);
1632 if (ret) break;
1633 fw_done += bcnt;
d855497e
MI		 1634 }
1635
1636 trace_firmware("upload of %s : %i / %i ",
1637 fw_files[fwidx],fw_done,fw_len);
1638
1639 kfree(fw_ptr);
1640 release_firmware(fw_entry);
1641
1642 if (ret) {
1643 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1644 "firmware2 upload transfer failure");
21684ba9 1645 goto done;
d855497e
MI		 1646 }
1647
1648 /* Finish upload */
1649
1650 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1651 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1c9d10d4 1652 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1653
1654 if (ret) {
1655 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1656 "firmware2 upload post-proc failure");
d855497e 1657 }
21684ba9
MI		 1658
1659 done:
1df59f0b
MI		 1660 if (hdw->hdw_desc->signal_routing_scheme ==
1661 PVR2_ROUTING_SCHEME_GOTVIEW) {
1662 /* Ensure that GPIO 11 is set to output for GOTVIEW
1663 hardware. */
1664 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1665 }
d855497e
MI		 1666 return ret;
1667}
1668
1669
681c7399
MI		 1670static const char *pvr2_get_state_name(unsigned int st)
1671{
1672 if (st < ARRAY_SIZE(pvr2_state_names)) {
1673 return pvr2_state_names[st];
d855497e 1674 }
681c7399 1675 return "???";
d855497e
MI		 1676}
1677
681c7399 1678static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1679{
af78e16b
MI		 1680 /* Even though we really only care about the video decoder chip at
1681 this point, we'll broadcast stream on/off to all sub-devices
1682 anyway, just in case somebody else wants to hear the
1683 command... */
e260508d
MI		 1684 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1685 (enablefl ? "on" : "off"));
af78e16b
MI		 1686 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1687 if (hdw->decoder_client_id) {
1688 /* We get here if the encoder has been noticed. Otherwise
1689 we'll issue a warning to the user (which should
1690 normally never happen). */
1691 return 0;
1692 }
1693 if (!hdw->flag_decoder_missed) {
1694 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1695 "WARNING: No decoder present");
1696 hdw->flag_decoder_missed = !0;
1697 trace_stbit("flag_decoder_missed",
1698 hdw->flag_decoder_missed);
1699 }
1700 return -EIO;
d855497e
MI		 1701}
1702
1703
681c7399 1704int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1705{
681c7399 1706 return hdw->master_state;
d855497e
MI		 1707}
1708
1709
681c7399 1710static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1711{
681c7399
MI		 1712 if (!hdw->flag_tripped) return 0;
1713 hdw->flag_tripped = 0;
1714 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1715 "Clearing driver error statuss");
1716 return !0;
d855497e
MI		 1717}
1718
1719
681c7399 1720int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1721{
681c7399 1722 int fl;
d855497e 1723 LOCK_TAKE(hdw->big_lock); do {
681c7399 1724 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1725 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1726 if (fl) pvr2_hdw_state_sched(hdw);
1727 return 0;
d855497e
MI		 1728}
1729
1730
d855497e
MI		 1731
1732
1733int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1734{
681c7399 1735 return hdw->state_pipeline_req != 0;
d855497e
MI		 1736}
1737
1738
1739int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1740{
681c7399 1741 int ret,st;
d855497e 1742 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1743 pvr2_hdw_untrip_unlocked(hdw);
1744 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1745 hdw->state_pipeline_req = enable_flag != 0;
1746 pvr2_trace(PVR2_TRACE_START_STOP,
1747 "/*--TRACE_STREAM--*/ %s",
1748 enable_flag ? "enable" : "disable");
1749 }
1750 pvr2_hdw_state_sched(hdw);
d855497e 1751 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1752 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1753 if (enable_flag) {
1754 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1755 if (st != PVR2_STATE_READY) return -EIO;
1756 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1757 }
1758 }
d855497e
MI		 1759 return 0;
1760}
1761
1762
1763int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1764{
681c7399 1765 int fl;
d855497e 1766 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1767 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1768 hdw->desired_stream_type = config;
1769 hdw->state_pipeline_config = 0;
1770 trace_stbit("state_pipeline_config",
1771 hdw->state_pipeline_config);
1772 pvr2_hdw_state_sched(hdw);
1773 }
d855497e 1774 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1775 if (fl) return 0;
1776 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1777}
1778
1779
1780static int get_default_tuner_type(struct pvr2_hdw *hdw)
1781{
1782 int unit_number = hdw->unit_number;
1783 int tp = -1;
1784 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1785 tp = tuner[unit_number];
1786 }
1787 if (tp < 0) return -EINVAL;
1788 hdw->tuner_type = tp;
aaf7884d 1789 hdw->tuner_updated = !0;
d855497e
MI		 1790 return 0;
1791}
1792
1793
1794static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1795{
1796 int unit_number = hdw->unit_number;
1797 int tp = 0;
1798 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1799 tp = video_std[unit_number];
6a540254 1800 if (tp) return tp;
d855497e 1801 }
6a540254 1802 return 0;
d855497e
MI		 1803}
1804
1805
1806static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1807{
1808 int unit_number = hdw->unit_number;
1809 int tp = 0;
1810 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1811 tp = tolerance[unit_number];
1812 }
1813 return tp;
1814}
1815
1816
1817static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1818{
1819 /* Try a harmless request to fetch the eeprom's address over
1820 endpoint 1. See what happens. Only the full FX2 image can
1821 respond to this. If this probe fails then likely the FX2
1822 firmware needs be loaded. */
1823 int result;
1824 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1825 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1826 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1827 hdw->cmd_buffer,1,
1828 hdw->cmd_buffer,1);
1829 if (result < 0) break;
1830 } while(0); LOCK_GIVE(hdw->ctl_lock);
1831 if (result) {
1832 pvr2_trace(PVR2_TRACE_INIT,
1833 "Probe of device endpoint 1 result status %d",
1834 result);
1835 } else {
1836 pvr2_trace(PVR2_TRACE_INIT,
1837 "Probe of device endpoint 1 succeeded");
1838 }
1839 return result == 0;
1840}
1841
9f66d4ea
MI		 1842struct pvr2_std_hack {
1843 v4l2_std_id pat; /* Pattern to match */
1844 v4l2_std_id msk; /* Which bits we care about */
1845 v4l2_std_id std; /* What additional standards or default to set */
1846};
1847
1848/* This data structure labels specific combinations of standards from
1849 tveeprom that we'll try to recognize. If we recognize one, then assume
1850 a specified default standard to use. This is here because tveeprom only
1851 tells us about available standards not the intended default standard (if
1852 any) for the device in question. We guess the default based on what has
1853 been reported as available. Note that this is only for guessing a
1854 default - which can always be overridden explicitly - and if the user
1855 has otherwise named a default then that default will always be used in
1856 place of this table. */
ebff0330 1857static const struct pvr2_std_hack std_eeprom_maps[] = {
9f66d4ea
MI		 1858 { /* PAL(B/G) */
1859 .pat = V4L2_STD_B|V4L2_STD_GH,
1860 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1861 },
1862 { /* NTSC(M) */
1863 .pat = V4L2_STD_MN,
1864 .std = V4L2_STD_NTSC_M,
1865 },
1866 { /* PAL(I) */
1867 .pat = V4L2_STD_PAL_I,
1868 .std = V4L2_STD_PAL_I,
1869 },
1870 { /* SECAM(L/L') */
1871 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1872 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1873 },
1874 { /* PAL(D/D1/K) */
1875 .pat = V4L2_STD_DK,
ea2562d9 1876 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
9f66d4ea
MI		 1877 },
1878};
1879
d855497e
MI		 1880static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1881{
1882 char buf[40];
1883 unsigned int bcnt;
3d290bdb 1884 v4l2_std_id std1,std2,std3;
d855497e
MI		 1885
1886 std1 = get_default_standard(hdw);
3d290bdb 1887 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
d855497e
MI		 1888
1889 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1890 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1891 "Supported video standard(s) reported available"
1892 " in hardware: %.*s",
d855497e
MI		 1893 bcnt,buf);
1894
1895 hdw->std_mask_avail = hdw->std_mask_eeprom;
1896
3d290bdb 1897 std2 = (std1|std3) & ~hdw->std_mask_avail;
d855497e
MI		 1898 if (std2) {
1899 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1900 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1901 "Expanding supported video standards"
1902 " to include: %.*s",
1903 bcnt,buf);
1904 hdw->std_mask_avail |= std2;
1905 }
1906
1907 pvr2_hdw_internal_set_std_avail(hdw);
1908
1909 if (std1) {
1910 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1911 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1912 "Initial video standard forced to %.*s",
1913 bcnt,buf);
1914 hdw->std_mask_cur = std1;
1915 hdw->std_dirty = !0;
1916 pvr2_hdw_internal_find_stdenum(hdw);
1917 return;
1918 }
3d290bdb
MI		 1919 if (std3) {
1920 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1921 pvr2_trace(PVR2_TRACE_STD,
1922 "Initial video standard"
1923 " (determined by device type): %.*s",bcnt,buf);
1924 hdw->std_mask_cur = std3;
1925 hdw->std_dirty = !0;
1926 pvr2_hdw_internal_find_stdenum(hdw);
1927 return;
1928 }
d855497e 1929
9f66d4ea
MI		 1930 {
1931 unsigned int idx;
1932 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1933 if (std_eeprom_maps[idx].msk ?
1934 ((std_eeprom_maps[idx].pat ^
1935 hdw->std_mask_eeprom) &
1936 std_eeprom_maps[idx].msk) :
1937 (std_eeprom_maps[idx].pat !=
1938 hdw->std_mask_eeprom)) continue;
1939 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1940 std_eeprom_maps[idx].std);
56585386 1941 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1942 "Initial video standard guessed as %.*s",
1943 bcnt,buf);
1944 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1945 hdw->std_dirty = !0;
1946 pvr2_hdw_internal_find_stdenum(hdw);
1947 return;
1948 }
1949 }
1950
d855497e
MI		 1951 if (hdw->std_enum_cnt > 1) {
1952 // Autoselect the first listed standard
1953 hdw->std_enum_cur = 1;
1954 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1955 hdw->std_dirty = !0;
56585386 1956 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1957 "Initial video standard auto-selected to %s",
1958 hdw->std_defs[hdw->std_enum_cur-1].name);
1959 return;
1960 }
1961
0885ba1d 1962 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1963 "Unable to select a viable initial video standard");
1964}
1965
1966
e9c64a78
MI		 1967static unsigned int pvr2_copy_i2c_addr_list(
1968 unsigned short *dst, const unsigned char *src,
1969 unsigned int dst_max)
1970{
3ab8d295 1971 unsigned int cnt = 0;
e9c64a78
MI		 1972 if (!src) return 0;
1973 while (src[cnt] && (cnt + 1) < dst_max) {
1974 dst[cnt] = src[cnt];
1975 cnt++;
1976 }
1977 dst[cnt] = I2C_CLIENT_END;
1978 return cnt;
1979}
1980
1981
1ab5e74f
MI		 1982static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1983 const struct pvr2_device_client_desc *cd)
e9c64a78
MI		 1984{
1985 const char *fname;
1986 unsigned char mid;
1987 struct v4l2_subdev *sd;
1988 unsigned int i2ccnt;
1989 const unsigned char *p;
1990 /* Arbitrary count - max # i2c addresses we will probe */
1991 unsigned short i2caddr[25];
1992
1993 mid = cd->module_id;
1994 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
1995 if (!fname) {
1996 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f 1997 "Module ID %u for device %s has no name",
e9c64a78
MI		 1998 mid,
1999 hdw->hdw_desc->description);
1ab5e74f 2000 return -EINVAL;
e9c64a78 2001 }
bd14d4f8
MI		 2002 pvr2_trace(PVR2_TRACE_INIT,
2003 "Module ID %u (%s) for device %s being loaded...",
2004 mid, fname,
2005 hdw->hdw_desc->description);
e9c64a78
MI		 2006
2007 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2008 ARRAY_SIZE(i2caddr));
2009 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2010 module_i2c_addresses[mid] : NULL) != NULL)) {
2011 /* Second chance: Try default i2c address list */
2012 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2013 ARRAY_SIZE(i2caddr));
bd14d4f8
MI		 2014 if (i2ccnt) {
2015 pvr2_trace(PVR2_TRACE_INIT,
2016 "Module ID %u:"
2017 " Using default i2c address list",
2018 mid);
2019 }
e9c64a78
MI		 2020 }
2021
2022 if (!i2ccnt) {
2023 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f
MI		 2024 "Module ID %u (%s) for device %s:"
2025 " No i2c addresses",
2026 mid, fname, hdw->hdw_desc->description);
2027 return -EINVAL;
e9c64a78
MI		 2028 }
2029
2030 /* Note how the 2nd and 3rd arguments are the same for both
2031 * v4l2_i2c_new_subdev() and v4l2_i2c_new_probed_subdev(). Why?
2032 * Well the 2nd argument is the module name to load, while the 3rd
2033 * argument is documented in the framework as being the "chipid" -
2034 * and every other place where I can find examples of this, the
2035 * "chipid" appears to just be the module name again. So here we
2036 * just do the same thing. */
2037 if (i2ccnt == 1) {
bd14d4f8
MI		 2038 pvr2_trace(PVR2_TRACE_INIT,
2039 "Module ID %u:"
2040 " Setting up with specified i2c address 0x%x",
2041 mid, i2caddr[0]);
e6574f2f 2042 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
e9c64a78
MI		 2043 fname, fname,
2044 i2caddr[0]);
2045 } else {
bd14d4f8
MI		 2046 pvr2_trace(PVR2_TRACE_INIT,
2047 "Module ID %u:"
2048 " Setting up with address probe list",
2049 mid);
e6574f2f 2050 sd = v4l2_i2c_new_probed_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
e9c64a78
MI		 2051 fname, fname,
2052 i2caddr);
2053 }
2054
446dfdc6
MI		 2055 if (!sd) {
2056 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f
MI		 2057 "Module ID %u (%s) for device %s failed to load",
2058 mid, fname, hdw->hdw_desc->description);
2059 return -EIO;
446dfdc6
MI		 2060 }
2061
2062 /* Tag this sub-device instance with the module ID we know about.
2063 In other places we'll use that tag to determine if the instance
2064 requires special handling. */
2065 sd->grp_id = mid;
2066
bd14d4f8 2067 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
a932f507 2068
e9c64a78 2069
00e5f736
MI		 2070 /* client-specific setup... */
2071 switch (mid) {
2072 case PVR2_CLIENT_ID_CX25840:
2073 hdw->decoder_client_id = mid;
2074 {
2075 /*
2076 Mike Isely <isely@pobox.com> 19-Nov-2006 - This
2077 bit of nuttiness for cx25840 causes that module
2078 to correctly set up its video scaling. This is
2079 really a problem in the cx25840 module itself,
2080 but we work around it here. The problem has not
2081 been seen in ivtv because there VBI is supported
2082 and set up. We don't do VBI here (at least not
2083 yet) and thus we never attempted to even set it
2084 up.
2085 */
2086 struct v4l2_format fmt;
bd14d4f8
MI		 2087 pvr2_trace(PVR2_TRACE_INIT,
2088 "Module ID %u:"
2089 " Executing cx25840 VBI hack",
2090 mid);
00e5f736
MI		 2091 memset(&fmt, 0, sizeof(fmt));
2092 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2093 v4l2_device_call_all(&hdw->v4l2_dev, mid,
2094 video, s_fmt, &fmt);
2095 }
2096 break;
2097 case PVR2_CLIENT_ID_SAA7115:
2098 hdw->decoder_client_id = mid;
2099 break;
2100 default: break;
2101 }
1ab5e74f
MI		 2102
2103 return 0;
e9c64a78
MI		 2104}
2105
2106
2107static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2108{
2109 unsigned int idx;
2110 const struct pvr2_string_table *cm;
2111 const struct pvr2_device_client_table *ct;
1ab5e74f 2112 int okFl = !0;
e9c64a78
MI		 2113
2114 cm = &hdw->hdw_desc->client_modules;
2115 for (idx = 0; idx < cm->cnt; idx++) {
2116 request_module(cm->lst[idx]);
2117 }
2118
2119 ct = &hdw->hdw_desc->client_table;
2120 for (idx = 0; idx < ct->cnt; idx++) {
bd14d4f8 2121 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
e9c64a78 2122 }
1ab5e74f 2123 if (!okFl) pvr2_hdw_render_useless(hdw);
e9c64a78
MI		 2124}
2125
2126
d855497e
MI		 2127static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2128{
2129 int ret;
2130 unsigned int idx;
2131 struct pvr2_ctrl *cptr;
2132 int reloadFl = 0;
989eb154 2133 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 2134 if (!reloadFl) {
2135 reloadFl =
2136 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2137 == 0);
2138 if (reloadFl) {
2139 pvr2_trace(PVR2_TRACE_INIT,
2140 "USB endpoint config looks strange"
2141 "; possibly firmware needs to be"
2142 " loaded");
2143 }
d855497e 2144 }
1d643a37
MI		 2145 if (!reloadFl) {
2146 reloadFl = !pvr2_hdw_check_firmware(hdw);
2147 if (reloadFl) {
2148 pvr2_trace(PVR2_TRACE_INIT,
2149 "Check for FX2 firmware failed"
2150 "; possibly firmware needs to be"
2151 " loaded");
2152 }
d855497e 2153 }
1d643a37
MI		 2154 if (reloadFl) {
2155 if (pvr2_upload_firmware1(hdw) != 0) {
2156 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2157 "Failure uploading firmware1");
2158 }
2159 return;
d855497e 2160 }
d855497e
MI		 2161 }
2162 hdw->fw1_state = FW1_STATE_OK;
2163
d855497e
MI		 2164 if (!pvr2_hdw_dev_ok(hdw)) return;
2165
27764726
MI		 2166 hdw->force_dirty = !0;
2167
989eb154 2168 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 2169 pvr2_hdw_cmd_powerup(hdw);
2170 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 2171 }
2172
31335b13
MI		 2173 /* Take the IR chip out of reset, if appropriate */
2174 if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
2175 pvr2_issue_simple_cmd(hdw,
2176 FX2CMD_HCW_ZILOG_RESET |
2177 (1 << 8) |
2178 ((0) << 16));
2179 }
2180
d855497e
MI		 2181 // This step MUST happen after the earlier powerup step.
2182 pvr2_i2c_core_init(hdw);
2183 if (!pvr2_hdw_dev_ok(hdw)) return;
2184
e9c64a78 2185 pvr2_hdw_load_modules(hdw);
1ab5e74f 2186 if (!pvr2_hdw_dev_ok(hdw)) return;
e9c64a78 2187
cc26b076 2188 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
5c6cb4e2 2189
c05c0462 2190 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 2191 cptr = hdw->controls + idx;
2192 if (cptr->info->skip_init) continue;
2193 if (!cptr->info->set_value) continue;
2194 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2195 }
2196
1bde0289
MI		 2197 /* Set up special default values for the television and radio
2198 frequencies here. It's not really important what these defaults
2199 are, but I set them to something usable in the Chicago area just
2200 to make driver testing a little easier. */
2201
5a4f5da6
MK		 2202 hdw->freqValTelevision = default_tv_freq;
2203 hdw->freqValRadio = default_radio_freq;
1bde0289 2204
d855497e
MI		 2205 // Do not use pvr2_reset_ctl_endpoints() here. It is not
2206 // thread-safe against the normal pvr2_send_request() mechanism.
2207 // (We should make it thread safe).
2208
aaf7884d
MI		 2209 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2210 ret = pvr2_hdw_get_eeprom_addr(hdw);
d855497e 2211 if (!pvr2_hdw_dev_ok(hdw)) return;
aaf7884d
MI		 2212 if (ret < 0) {
2213 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2214 "Unable to determine location of eeprom,"
2215 " skipping");
2216 } else {
2217 hdw->eeprom_addr = ret;
2218 pvr2_eeprom_analyze(hdw);
2219 if (!pvr2_hdw_dev_ok(hdw)) return;
2220 }
2221 } else {
2222 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2223 hdw->tuner_updated = !0;
2224 hdw->std_mask_eeprom = V4L2_STD_ALL;
d855497e
MI		 2225 }
2226
13a88797
MI		 2227 if (hdw->serial_number) {
2228 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2229 "sn-%lu", hdw->serial_number);
2230 } else if (hdw->unit_number >= 0) {
2231 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2232 "unit-%c",
2233 hdw->unit_number + 'a');
2234 } else {
2235 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2236 "unit-??");
2237 }
2238 hdw->identifier[idx] = 0;
2239
d855497e
MI		 2240 pvr2_hdw_setup_std(hdw);
2241
2242 if (!get_default_tuner_type(hdw)) {
2243 pvr2_trace(PVR2_TRACE_INIT,
2244 "pvr2_hdw_setup: Tuner type overridden to %d",
2245 hdw->tuner_type);
2246 }
2247
d855497e
MI		 2248
2249 if (!pvr2_hdw_dev_ok(hdw)) return;
2250
1df59f0b
MI		 2251 if (hdw->hdw_desc->signal_routing_scheme ==
2252 PVR2_ROUTING_SCHEME_GOTVIEW) {
2253 /* Ensure that GPIO 11 is set to output for GOTVIEW
2254 hardware. */
2255 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2256 }
2257
681c7399 2258 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 2259
2260 hdw->vid_stream = pvr2_stream_create();
2261 if (!pvr2_hdw_dev_ok(hdw)) return;
2262 pvr2_trace(PVR2_TRACE_INIT,
2263 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2264 if (hdw->vid_stream) {
2265 idx = get_default_error_tolerance(hdw);
2266 if (idx) {
2267 pvr2_trace(PVR2_TRACE_INIT,
2268 "pvr2_hdw_setup: video stream %p"
2269 " setting tolerance %u",
2270 hdw->vid_stream,idx);
2271 }
2272 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2273 PVR2_VID_ENDPOINT,idx);
2274 }
2275
2276 if (!pvr2_hdw_dev_ok(hdw)) return;
2277
d855497e 2278 hdw->flag_init_ok = !0;
681c7399
MI		 2279
2280 pvr2_hdw_state_sched(hdw);
d855497e
MI		 2281}
2282
2283
681c7399
MI		 2284/* Set up the structure and attempt to put the device into a usable state.
2285 This can be a time-consuming operation, which is why it is not done
2286 internally as part of the create() step. */
2287static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 2288{
2289 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 2290 do {
d855497e
MI		 2291 pvr2_hdw_setup_low(hdw);
2292 pvr2_trace(PVR2_TRACE_INIT,
2293 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 2294 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 2295 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 2296 if (hdw->flag_init_ok) {
d855497e
MI		 2297 pvr2_trace(
2298 PVR2_TRACE_INFO,
2299 "Device initialization"
2300 " completed successfully.");
2301 break;
2302 }
2303 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2304 pvr2_trace(
2305 PVR2_TRACE_INFO,
2306 "Device microcontroller firmware"
2307 " (re)loaded; it should now reset"
2308 " and reconnect.");
2309 break;
2310 }
2311 pvr2_trace(
2312 PVR2_TRACE_ERROR_LEGS,
2313 "Device initialization was not successful.");
2314 if (hdw->fw1_state == FW1_STATE_MISSING) {
2315 pvr2_trace(
2316 PVR2_TRACE_ERROR_LEGS,
2317 "Giving up since device"
2318 " microcontroller firmware"
2319 " appears to be missing.");
2320 break;
2321 }
2322 }
2323 if (procreload) {
2324 pvr2_trace(
2325 PVR2_TRACE_ERROR_LEGS,
2326 "Attempting pvrusb2 recovery by reloading"
2327 " primary firmware.");
2328 pvr2_trace(
2329 PVR2_TRACE_ERROR_LEGS,
2330 "If this works, device should disconnect"
2331 " and reconnect in a sane state.");
2332 hdw->fw1_state = FW1_STATE_UNKNOWN;
2333 pvr2_upload_firmware1(hdw);
2334 } else {
2335 pvr2_trace(
2336 PVR2_TRACE_ERROR_LEGS,
2337 "***WARNING*** pvrusb2 device hardware"
2338 " appears to be jammed"
2339 " and I can't clear it.");
2340 pvr2_trace(
2341 PVR2_TRACE_ERROR_LEGS,
2342 "You might need to power cycle"
2343 " the pvrusb2 device"
2344 " in order to recover.");
2345 }
681c7399 2346 } while (0);
d855497e 2347 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 2348}
2349
2350
c4a8828d
MI		 2351/* Perform second stage initialization. Set callback pointer first so that
2352 we can avoid a possible initialization race (if the kernel thread runs
2353 before the callback has been set). */
794b1607
MI		 2354int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2355 void (*callback_func)(void *),
2356 void *callback_data)
c4a8828d
MI		 2357{
2358 LOCK_TAKE(hdw->big_lock); do {
97f26ff6
MI		 2359 if (hdw->flag_disconnected) {
2360 /* Handle a race here: If we're already
2361 disconnected by this point, then give up. If we
2362 get past this then we'll remain connected for
2363 the duration of initialization since the entire
2364 initialization sequence is now protected by the
2365 big_lock. */
2366 break;
2367 }
c4a8828d
MI		 2368 hdw->state_data = callback_data;
2369 hdw->state_func = callback_func;
97f26ff6 2370 pvr2_hdw_setup(hdw);
c4a8828d 2371 } while (0); LOCK_GIVE(hdw->big_lock);
794b1607 2372 return hdw->flag_init_ok;
c4a8828d
MI		 2373}
2374
2375
2376/* Create, set up, and return a structure for interacting with the
2377 underlying hardware. */
d855497e
MI		 2378struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2379 const struct usb_device_id *devid)
2380{
7fb20fa3 2381 unsigned int idx,cnt1,cnt2,m;
fe15f136 2382 struct pvr2_hdw *hdw = NULL;
d855497e
MI		 2383 int valid_std_mask;
2384 struct pvr2_ctrl *cptr;
b72b7bf5 2385 struct usb_device *usb_dev;
989eb154 2386 const struct pvr2_device_desc *hdw_desc;
d855497e 2387 __u8 ifnum;
b30d2441
MI		 2388 struct v4l2_queryctrl qctrl;
2389 struct pvr2_ctl_info *ciptr;
d855497e 2390
b72b7bf5
MI		 2391 usb_dev = interface_to_usbdev(intf);
2392
d130fa8a 2393 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
d855497e 2394
fe15f136
MI		 2395 if (hdw_desc == NULL) {
2396 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2397 " No device description pointer,"
2398 " unable to continue.");
2399 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2400 " please contact Mike Isely <isely@pobox.com>"
2401 " to get it included in the driver\n");
2402 goto fail;
2403 }
2404
ca545f7c 2405 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 2406 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 2407 hdw,hdw_desc->description);
d855497e 2408 if (!hdw) goto fail;
681c7399
MI		 2409
2410 init_timer(&hdw->quiescent_timer);
2411 hdw->quiescent_timer.data = (unsigned long)hdw;
2412 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2413
2414 init_timer(&hdw->encoder_wait_timer);
2415 hdw->encoder_wait_timer.data = (unsigned long)hdw;
2416 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2417
d913d630
MI		 2418 init_timer(&hdw->encoder_run_timer);
2419 hdw->encoder_run_timer.data = (unsigned long)hdw;
2420 hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2421
681c7399
MI		 2422 hdw->master_state = PVR2_STATE_DEAD;
2423
2424 init_waitqueue_head(&hdw->state_wait_data);
2425
18103c57 2426 hdw->tuner_signal_stale = !0;
b30d2441 2427 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 2428
7fb20fa3
MI		 2429 /* Calculate which inputs are OK */
2430 m = 0;
2431 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
e8f5bacf
MI		 2432 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2433 m |= 1 << PVR2_CVAL_INPUT_DTV;
2434 }
7fb20fa3
MI		 2435 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2436 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2437 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2438 hdw->input_avail_mask = m;
1cb03b76 2439 hdw->input_allowed_mask = hdw->input_avail_mask;
7fb20fa3 2440
62433e31
MI		 2441 /* If not a hybrid device, pathway_state never changes. So
2442 initialize it here to what it should forever be. */
2443 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2444 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2445 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2446 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2447 }
2448
c05c0462 2449 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 2450 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 2451 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 2452 GFP_KERNEL);
2453 if (!hdw->controls) goto fail;
989eb154 2454 hdw->hdw_desc = hdw_desc;
c05c0462
MI		 2455 for (idx = 0; idx < hdw->control_cnt; idx++) {
2456 cptr = hdw->controls + idx;
2457 cptr->hdw = hdw;
2458 }
d855497e
MI		 2459 for (idx = 0; idx < 32; idx++) {
2460 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2461 }
c05c0462 2462 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 2463 cptr = hdw->controls + idx;
d855497e
MI		 2464 cptr->info = control_defs+idx;
2465 }
dbc40a0e
MI		 2466
2467 /* Ensure that default input choice is a valid one. */
2468 m = hdw->input_avail_mask;
2469 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2470 if (!((1 << idx) & m)) continue;
2471 hdw->input_val = idx;
2472 break;
2473 }
2474
b30d2441 2475 /* Define and configure additional controls from cx2341x module. */
ca545f7c 2476 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 2477 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2478 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 2479 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2480 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2481 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2482 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2483 ciptr->name = mpeg_ids[idx].strid;
2484 ciptr->v4l_id = mpeg_ids[idx].id;
2485 ciptr->skip_init = !0;
2486 ciptr->get_value = ctrl_cx2341x_get;
2487 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2488 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2489 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2490 qctrl.id = ciptr->v4l_id;
2491 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2492 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2493 ciptr->set_value = ctrl_cx2341x_set;
2494 }
2495 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2496 PVR2_CTLD_INFO_DESC_SIZE);
2497 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2498 ciptr->default_value = qctrl.default_value;
2499 switch (qctrl.type) {
2500 default:
2501 case V4L2_CTRL_TYPE_INTEGER:
2502 ciptr->type = pvr2_ctl_int;
2503 ciptr->def.type_int.min_value = qctrl.minimum;
2504 ciptr->def.type_int.max_value = qctrl.maximum;
2505 break;
2506 case V4L2_CTRL_TYPE_BOOLEAN:
2507 ciptr->type = pvr2_ctl_bool;
2508 break;
2509 case V4L2_CTRL_TYPE_MENU:
2510 ciptr->type = pvr2_ctl_enum;
2511 ciptr->def.type_enum.value_names =
e0e31cdb
HV		 2512 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2513 ciptr->v4l_id);
b30d2441
MI		 2514 for (cnt1 = 0;
2515 ciptr->def.type_enum.value_names[cnt1] != NULL;
2516 cnt1++) { }
2517 ciptr->def.type_enum.count = cnt1;
2518 break;
2519 }
2520 cptr->info = ciptr;
2521 }
d855497e
MI		 2522
2523 // Initialize video standard enum dynamic control
2524 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2525 if (cptr) {
2526 memcpy(&hdw->std_info_enum,cptr->info,
2527 sizeof(hdw->std_info_enum));
2528 cptr->info = &hdw->std_info_enum;
2529
2530 }
2531 // Initialize control data regarding video standard masks
2532 valid_std_mask = pvr2_std_get_usable();
2533 for (idx = 0; idx < 32; idx++) {
2534 if (!(valid_std_mask & (1 << idx))) continue;
2535 cnt1 = pvr2_std_id_to_str(
2536 hdw->std_mask_names[idx],
2537 sizeof(hdw->std_mask_names[idx])-1,
2538 1 << idx);
2539 hdw->std_mask_names[idx][cnt1] = 0;
2540 }
2541 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2542 if (cptr) {
2543 memcpy(&hdw->std_info_avail,cptr->info,
2544 sizeof(hdw->std_info_avail));
2545 cptr->info = &hdw->std_info_avail;
2546 hdw->std_info_avail.def.type_bitmask.bit_names =
2547 hdw->std_mask_ptrs;
2548 hdw->std_info_avail.def.type_bitmask.valid_bits =
2549 valid_std_mask;
2550 }
2551 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2552 if (cptr) {
2553 memcpy(&hdw->std_info_cur,cptr->info,
2554 sizeof(hdw->std_info_cur));
2555 cptr->info = &hdw->std_info_cur;
2556 hdw->std_info_cur.def.type_bitmask.bit_names =
2557 hdw->std_mask_ptrs;
2558 hdw->std_info_avail.def.type_bitmask.valid_bits =
2559 valid_std_mask;
2560 }
2561
432907f7 2562 hdw->cropcap_stale = !0;
d855497e
MI		 2563 hdw->eeprom_addr = -1;
2564 hdw->unit_number = -1;
8079384e
MI		 2565 hdw->v4l_minor_number_video = -1;
2566 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 2567 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 2568 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2569 if (!hdw->ctl_write_buffer) goto fail;
2570 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2571 if (!hdw->ctl_read_buffer) goto fail;
2572 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2573 if (!hdw->ctl_write_urb) goto fail;
2574 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2575 if (!hdw->ctl_read_urb) goto fail;
2576
70ad6383 2577 if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
b72b7bf5
MI		 2578 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2579 "Error registering with v4l core, giving up");
2580 goto fail;
2581 }
8df0c87c 2582 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2583 for (idx = 0; idx < PVR_NUM; idx++) {
2584 if (unit_pointers[idx]) continue;
2585 hdw->unit_number = idx;
2586 unit_pointers[idx] = hdw;
2587 break;
2588 }
8df0c87c 2589 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 2590
2591 cnt1 = 0;
2592 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2593 cnt1 += cnt2;
2594 if (hdw->unit_number >= 0) {
2595 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2596 ('a' + hdw->unit_number));
2597 cnt1 += cnt2;
2598 }
2599 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2600 hdw->name[cnt1] = 0;
2601
681c7399
MI		 2602 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2603 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
681c7399 2604
d855497e
MI		 2605 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2606 hdw->unit_number,hdw->name);
2607
2608 hdw->tuner_type = -1;
2609 hdw->flag_ok = !0;
d855497e
MI		 2610
2611 hdw->usb_intf = intf;
b72b7bf5 2612 hdw->usb_dev = usb_dev;
d855497e 2613
87e3495c 2614 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
31a18547 2615
d855497e
MI		 2616 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2617 usb_set_interface(hdw->usb_dev,ifnum,0);
2618
2619 mutex_init(&hdw->ctl_lock_mutex);
2620 mutex_init(&hdw->big_lock_mutex);
2621
2622 return hdw;
2623 fail:
2624 if (hdw) {
681c7399 2625 del_timer_sync(&hdw->quiescent_timer);
d913d630 2626 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 2627 del_timer_sync(&hdw->encoder_wait_timer);
2628 if (hdw->workqueue) {
2629 flush_workqueue(hdw->workqueue);
2630 destroy_workqueue(hdw->workqueue);
2631 hdw->workqueue = NULL;
2632 }
5e55d2ce
MK		 2633 usb_free_urb(hdw->ctl_read_urb);
2634 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2635 kfree(hdw->ctl_read_buffer);
2636 kfree(hdw->ctl_write_buffer);
2637 kfree(hdw->controls);
2638 kfree(hdw->mpeg_ctrl_info);
681c7399
MI		 2639 kfree(hdw->std_defs);
2640 kfree(hdw->std_enum_names);
d855497e
MI		 2641 kfree(hdw);
2642 }
a0fd1cb1 2643 return NULL;
d855497e
MI		 2644}
2645
2646
2647/* Remove _all_ associations between this driver and the underlying USB
2648 layer. */
07e337ee 2649static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2650{
2651 if (hdw->flag_disconnected) return;
2652 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2653 if (hdw->ctl_read_urb) {
2654 usb_kill_urb(hdw->ctl_read_urb);
2655 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2656 hdw->ctl_read_urb = NULL;
d855497e
MI		 2657 }
2658 if (hdw->ctl_write_urb) {
2659 usb_kill_urb(hdw->ctl_write_urb);
2660 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2661 hdw->ctl_write_urb = NULL;
d855497e
MI		 2662 }
2663 if (hdw->ctl_read_buffer) {
2664 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2665 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2666 }
2667 if (hdw->ctl_write_buffer) {
2668 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2669 hdw->ctl_write_buffer = NULL;
d855497e 2670 }
d855497e 2671 hdw->flag_disconnected = !0;
b72b7bf5
MI		 2672 /* If we don't do this, then there will be a dangling struct device
2673 reference to our disappearing device persisting inside the V4L
2674 core... */
dc070bcc 2675 v4l2_device_disconnect(&hdw->v4l2_dev);
a0fd1cb1
MI		 2676 hdw->usb_dev = NULL;
2677 hdw->usb_intf = NULL;
681c7399 2678 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2679}
2680
2681
2682/* Destroy hardware interaction structure */
2683void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2684{
401c27ce 2685 if (!hdw) return;
d855497e 2686 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2687 if (hdw->workqueue) {
2688 flush_workqueue(hdw->workqueue);
2689 destroy_workqueue(hdw->workqueue);
2690 hdw->workqueue = NULL;
2691 }
8f59100a 2692 del_timer_sync(&hdw->quiescent_timer);
d913d630 2693 del_timer_sync(&hdw->encoder_run_timer);
8f59100a 2694 del_timer_sync(&hdw->encoder_wait_timer);
d855497e
MI		 2695 if (hdw->fw_buffer) {
2696 kfree(hdw->fw_buffer);
a0fd1cb1 2697 hdw->fw_buffer = NULL;
d855497e
MI		 2698 }
2699 if (hdw->vid_stream) {
2700 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2701 hdw->vid_stream = NULL;
d855497e 2702 }
d855497e 2703 pvr2_i2c_core_done(hdw);
b72b7bf5 2704 v4l2_device_unregister(&hdw->v4l2_dev);
d855497e 2705 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2706 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2707 if ((hdw->unit_number >= 0) &&
2708 (hdw->unit_number < PVR_NUM) &&
2709 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2710 unit_pointers[hdw->unit_number] = NULL;
d855497e 2711 }
8df0c87c 2712 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2713 kfree(hdw->controls);
2714 kfree(hdw->mpeg_ctrl_info);
2715 kfree(hdw->std_defs);
2716 kfree(hdw->std_enum_names);
d855497e
MI		 2717 kfree(hdw);
2718}
2719
2720
d855497e
MI		 2721int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2722{
2723 return (hdw && hdw->flag_ok);
2724}
2725
2726
2727/* Called when hardware has been unplugged */
2728void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2729{
2730 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2731 LOCK_TAKE(hdw->big_lock);
2732 LOCK_TAKE(hdw->ctl_lock);
2733 pvr2_hdw_remove_usb_stuff(hdw);
2734 LOCK_GIVE(hdw->ctl_lock);
2735 LOCK_GIVE(hdw->big_lock);
2736}
2737
2738
2739// Attempt to autoselect an appropriate value for std_enum_cur given
2740// whatever is currently in std_mask_cur
07e337ee 2741static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2742{
2743 unsigned int idx;
2744 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2745 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2746 hdw->std_enum_cur = idx;
2747 return;
2748 }
2749 }
2750 hdw->std_enum_cur = 0;
2751}
2752
2753
2754// Calculate correct set of enumerated standards based on currently known
2755// set of available standards bits.
07e337ee 2756static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2757{
2758 struct v4l2_standard *newstd;
2759 unsigned int std_cnt;
2760 unsigned int idx;
2761
2762 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2763
2764 if (hdw->std_defs) {
2765 kfree(hdw->std_defs);
a0fd1cb1 2766 hdw->std_defs = NULL;
d855497e
MI		 2767 }
2768 hdw->std_enum_cnt = 0;
2769 if (hdw->std_enum_names) {
2770 kfree(hdw->std_enum_names);
a0fd1cb1 2771 hdw->std_enum_names = NULL;
d855497e
MI		 2772 }
2773
2774 if (!std_cnt) {
2775 pvr2_trace(
2776 PVR2_TRACE_ERROR_LEGS,
2777 "WARNING: Failed to identify any viable standards");
2778 }
2779 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2780 hdw->std_enum_names[0] = "none";
2781 for (idx = 0; idx < std_cnt; idx++) {
2782 hdw->std_enum_names[idx+1] =
2783 newstd[idx].name;
2784 }
2785 // Set up the dynamic control for this standard
2786 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2787 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2788 hdw->std_defs = newstd;
2789 hdw->std_enum_cnt = std_cnt+1;
2790 hdw->std_enum_cur = 0;
2791 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2792}
2793
2794
2795int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2796 struct v4l2_standard *std,
2797 unsigned int idx)
2798{
2799 int ret = -EINVAL;
2800 if (!idx) return ret;
2801 LOCK_TAKE(hdw->big_lock); do {
2802 if (idx >= hdw->std_enum_cnt) break;
2803 idx--;
2804 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2805 ret = 0;
2806 } while (0); LOCK_GIVE(hdw->big_lock);
2807 return ret;
2808}
2809
2810
2811/* Get the number of defined controls */
2812unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2813{
c05c0462 2814 return hdw->control_cnt;
d855497e
MI		 2815}
2816
2817
2818/* Retrieve a control handle given its index (0..count-1) */
2819struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2820 unsigned int idx)
2821{
a0fd1cb1 2822 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2823 return hdw->controls + idx;
2824}
2825
2826
2827/* Retrieve a control handle given its index (0..count-1) */
2828struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2829 unsigned int ctl_id)
2830{
2831 struct pvr2_ctrl *cptr;
2832 unsigned int idx;
2833 int i;
2834
2835 /* This could be made a lot more efficient, but for now... */
c05c0462 2836 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2837 cptr = hdw->controls + idx;
2838 i = cptr->info->internal_id;
2839 if (i && (i == ctl_id)) return cptr;
2840 }
a0fd1cb1 2841 return NULL;
d855497e
MI		 2842}
2843
2844
a761f431 2845/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2846struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2847{
2848 struct pvr2_ctrl *cptr;
2849 unsigned int idx;
2850 int i;
2851
2852 /* This could be made a lot more efficient, but for now... */
c05c0462 2853 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2854 cptr = hdw->controls + idx;
2855 i = cptr->info->v4l_id;
2856 if (i && (i == ctl_id)) return cptr;
2857 }
a0fd1cb1 2858 return NULL;
d855497e
MI		 2859}
2860
2861
a761f431
MI		 2862/* Given a V4L ID for its immediate predecessor, retrieve the control
2863 structure associated with it. */
2864struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2865 unsigned int ctl_id)
2866{
2867 struct pvr2_ctrl *cptr,*cp2;
2868 unsigned int idx;
2869 int i;
2870
2871 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2872 cp2 = NULL;
a761f431
MI		 2873 for (idx = 0; idx < hdw->control_cnt; idx++) {
2874 cptr = hdw->controls + idx;
2875 i = cptr->info->v4l_id;
2876 if (!i) continue;
2877 if (i <= ctl_id) continue;
2878 if (cp2 && (cp2->info->v4l_id < i)) continue;
2879 cp2 = cptr;
2880 }
2881 return cp2;
a0fd1cb1 2882 return NULL;
a761f431
MI		 2883}
2884
2885
d855497e
MI		 2886static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2887{
2888 switch (tp) {
2889 case pvr2_ctl_int: return "integer";
2890 case pvr2_ctl_enum: return "enum";
33213963 2891 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2892 case pvr2_ctl_bitmask: return "bitmask";
2893 }
2894 return "";
2895}
2896
2897
2641df36
MI		 2898static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2899 const char *name, int val)
2900{
2901 struct v4l2_control ctrl;
2902 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2903 memset(&ctrl, 0, sizeof(ctrl));
2904 ctrl.id = id;
2905 ctrl.value = val;
2906 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2907}
2908
2909#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
27764726 2910 if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \
2641df36
MI		 2911 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2912 }
2913
5ceaad14 2914/* Execute whatever commands are required to update the state of all the
2641df36 2915 sub-devices so that they match our current control values. */
5ceaad14
MI		 2916static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2917{
edb9dcb8
MI		 2918 struct v4l2_subdev *sd;
2919 unsigned int id;
2920 pvr2_subdev_update_func fp;
2921
75212a02
MI		 2922 pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2923
27764726 2924 if (hdw->tuner_updated || hdw->force_dirty) {
75212a02
MI		 2925 struct tuner_setup setup;
2926 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2927 hdw->tuner_type);
2928 if (((int)(hdw->tuner_type)) >= 0) {
fcd62cf7 2929 memset(&setup, 0, sizeof(setup));
75212a02
MI		 2930 setup.addr = ADDR_UNSET;
2931 setup.type = hdw->tuner_type;
2932 setup.mode_mask = T_RADIO | T_ANALOG_TV;
2933 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2934 tuner, s_type_addr, &setup);
2935 }
2936 }
2937
27764726 2938 if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
b481880b 2939 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2641df36
MI		 2940 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2941 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2942 tuner, s_radio);
2943 } else {
2944 v4l2_std_id vs;
2945 vs = hdw->std_mask_cur;
2946 v4l2_device_call_all(&hdw->v4l2_dev, 0,
f41737ec 2947 core, s_std, vs);
2641df36
MI		 2948 }
2949 hdw->tuner_signal_stale = !0;
2950 hdw->cropcap_stale = !0;
2951 }
2952
2953 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2954 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2955 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2956 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2957 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2958 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2959 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2960 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2961 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2962
27764726 2963 if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2641df36
MI		 2964 struct v4l2_tuner vt;
2965 memset(&vt, 0, sizeof(vt));
2966 vt.audmode = hdw->audiomode_val;
2967 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2968 }
2969
27764726 2970 if (hdw->freqDirty || hdw->force_dirty) {
2641df36
MI		 2971 unsigned long fv;
2972 struct v4l2_frequency freq;
2973 fv = pvr2_hdw_get_cur_freq(hdw);
2974 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2975 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2976 memset(&freq, 0, sizeof(freq));
2977 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2978 /* ((fv * 1000) / 62500) */
2979 freq.frequency = (fv * 2) / 125;
2980 } else {
2981 freq.frequency = fv / 62500;
2982 }
2983 /* tuner-core currently doesn't seem to care about this, but
2984 let's set it anyway for completeness. */
2985 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2986 freq.type = V4L2_TUNER_RADIO;
2987 } else {
2988 freq.type = V4L2_TUNER_ANALOG_TV;
2989 }
2990 freq.tuner = 0;
2991 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2992 s_frequency, &freq);
2993 }
2994
27764726 2995 if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
2641df36
MI		 2996 struct v4l2_format fmt;
2997 memset(&fmt, 0, sizeof(fmt));
2998 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2999 fmt.fmt.pix.width = hdw->res_hor_val;
3000 fmt.fmt.pix.height = hdw->res_ver_val;
7dfdf1ee 3001 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
2641df36
MI		 3002 fmt.fmt.pix.width, fmt.fmt.pix.height);
3003 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
3004 }
3005
27764726 3006 if (hdw->srate_dirty || hdw->force_dirty) {
01c59df8
MI		 3007 u32 val;
3008 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3009 hdw->srate_val);
3010 switch (hdw->srate_val) {
3011 default:
3012 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3013 val = 48000;
3014 break;
3015 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3016 val = 44100;
3017 break;
3018 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3019 val = 32000;
3020 break;
3021 }
3022 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3023 audio, s_clock_freq, val);
3024 }
3025
2641df36
MI		 3026 /* Unable to set crop parameters; there is apparently no equivalent
3027 for VIDIOC_S_CROP */
3028
edb9dcb8
MI		 3029 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3030 id = sd->grp_id;
3031 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3032 fp = pvr2_module_update_functions[id];
3033 if (!fp) continue;
3034 (*fp)(hdw, sd);
3035 }
2641df36 3036
27764726 3037 if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
2641df36
MI		 3038 pvr2_hdw_status_poll(hdw);
3039 }
5ceaad14
MI		 3040}
3041
3042
681c7399
MI		 3043/* Figure out if we need to commit control changes. If so, mark internal
3044 state flags to indicate this fact and return true. Otherwise do nothing
3045 else and return false. */
3046static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 3047{
d855497e
MI		 3048 unsigned int idx;
3049 struct pvr2_ctrl *cptr;
3050 int value;
27764726 3051 int commit_flag = hdw->force_dirty;
d855497e
MI		 3052 char buf[100];
3053 unsigned int bcnt,ccnt;
3054
c05c0462 3055 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e 3056 cptr = hdw->controls + idx;
5fa1247a 3057 if (!cptr->info->is_dirty) continue;
d855497e 3058 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 3059 commit_flag = !0;
d855497e 3060
fe23a280 3061 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 3062 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3063 cptr->info->name);
3064 value = 0;
3065 cptr->info->get_value(cptr,&value);
3066 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3067 buf+bcnt,
3068 sizeof(buf)-bcnt,&ccnt);
3069 bcnt += ccnt;
3070 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3071 get_ctrl_typename(cptr->info->type));
3072 pvr2_trace(PVR2_TRACE_CTL,
3073 "/*--TRACE_COMMIT--*/ %.*s",
3074 bcnt,buf);
3075 }
3076
3077 if (!commit_flag) {
3078 /* Nothing has changed */
3079 return 0;
3080 }
3081
681c7399
MI		 3082 hdw->state_pipeline_config = 0;
3083 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3084 pvr2_hdw_state_sched(hdw);
3085
3086 return !0;
3087}
3088
3089
3090/* Perform all operations needed to commit all control changes. This must
3091 be performed in synchronization with the pipeline state and is thus
3092 expected to be called as part of the driver's worker thread. Return
3093 true if commit successful, otherwise return false to indicate that
3094 commit isn't possible at this time. */
3095static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3096{
3097 unsigned int idx;
3098 struct pvr2_ctrl *cptr;
3099 int disruptive_change;
3100
ab062fe3
MI		 3101 /* Handle some required side effects when the video standard is
3102 changed.... */
d855497e 3103 if (hdw->std_dirty) {
d855497e 3104 int nvres;
00528d9c 3105 int gop_size;
d855497e
MI		 3106 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3107 nvres = 480;
00528d9c 3108 gop_size = 15;
d855497e
MI		 3109 } else {
3110 nvres = 576;
00528d9c 3111 gop_size = 12;
d855497e 3112 }
00528d9c
MI		 3113 /* Rewrite the vertical resolution to be appropriate to the
3114 video standard that has been selected. */
d855497e
MI		 3115 if (nvres != hdw->res_ver_val) {
3116 hdw->res_ver_val = nvres;
3117 hdw->res_ver_dirty = !0;
3118 }
00528d9c
MI		 3119 /* Rewrite the GOP size to be appropriate to the video
3120 standard that has been selected. */
3121 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3122 struct v4l2_ext_controls cs;
3123 struct v4l2_ext_control c1;
3124 memset(&cs, 0, sizeof(cs));
3125 memset(&c1, 0, sizeof(c1));
3126 cs.controls = &c1;
3127 cs.count = 1;
3128 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3129 c1.value = gop_size;
3130 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3131 VIDIOC_S_EXT_CTRLS);
3132 }
d855497e
MI		 3133 }
3134
38d9a2cf 3135 if (hdw->input_dirty && hdw->state_pathway_ok &&
62433e31
MI		 3136 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3137 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3138 hdw->pathway_state)) {
3139 /* Change of mode being asked for... */
3140 hdw->state_pathway_ok = 0;
e9db1ff2 3141 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 3142 }
3143 if (!hdw->state_pathway_ok) {
3144 /* Can't commit anything until pathway is ok. */
3145 return 0;
3146 }
e784bfb9 3147 /* The broadcast decoder can only scale down, so if
3148 * res_*_dirty && crop window < output format ==> enlarge crop.
3149 *
3150 * The mpeg encoder receives fields of res_hor_val dots and
3151 * res_ver_val halflines. Limits: hor<=720, ver<=576.
3152 */
3153 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3154 hdw->cropw_val = hdw->res_hor_val;
3155 hdw->cropw_dirty = !0;
3156 } else if (hdw->cropw_dirty) {
3157 hdw->res_hor_dirty = !0; /* must rescale */
3158 hdw->res_hor_val = min(720, hdw->cropw_val);
3159 }
3160 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3161 hdw->croph_val = hdw->res_ver_val;
3162 hdw->croph_dirty = !0;
3163 } else if (hdw->croph_dirty) {
3164 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3165 hdw->res_ver_dirty = !0;
3166 hdw->res_ver_val = min(nvres, hdw->croph_val);
3167 }
3168
681c7399
MI		 3169 /* If any of the below has changed, then we can't do the update
3170 while the pipeline is running. Pipeline must be paused first
3171 and decoder -> encoder connection be made quiescent before we
3172 can proceed. */
3173 disruptive_change =
3174 (hdw->std_dirty ||
3175 hdw->enc_unsafe_stale ||
3176 hdw->srate_dirty ||
3177 hdw->res_ver_dirty ||
3178 hdw->res_hor_dirty ||
755879c6
MI		 3179 hdw->cropw_dirty ||
3180 hdw->croph_dirty ||
681c7399
MI		 3181 hdw->input_dirty ||
3182 (hdw->active_stream_type != hdw->desired_stream_type));
3183 if (disruptive_change && !hdw->state_pipeline_idle) {
3184 /* Pipeline is not idle; we can't proceed. Arrange to
3185 cause pipeline to stop so that we can try this again
3186 later.... */
3187 hdw->state_pipeline_pause = !0;
3188 return 0;
275b2e28
PK		 3189 }
3190
b30d2441
MI		 3191 if (hdw->srate_dirty) {
3192 /* Write new sample rate into control structure since
3193 * the master copy is stale. We must track srate
3194 * separate from the mpeg control structure because
3195 * other logic also uses this value. */
3196 struct v4l2_ext_controls cs;
3197 struct v4l2_ext_control c1;
3198 memset(&cs,0,sizeof(cs));
3199 memset(&c1,0,sizeof(c1));
3200 cs.controls = &c1;
3201 cs.count = 1;
3202 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3203 c1.value = hdw->srate_val;
01f1e44f 3204 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 3205 }
c05c0462 3206
681c7399
MI		 3207 if (hdw->active_stream_type != hdw->desired_stream_type) {
3208 /* Handle any side effects of stream config here */
3209 hdw->active_stream_type = hdw->desired_stream_type;
3210 }
3211
1df59f0b
MI		 3212 if (hdw->hdw_desc->signal_routing_scheme ==
3213 PVR2_ROUTING_SCHEME_GOTVIEW) {
3214 u32 b;
3215 /* Handle GOTVIEW audio switching */
3216 pvr2_hdw_gpio_get_out(hdw,&b);
3217 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3218 /* Set GPIO 11 */
3219 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3220 } else {
3221 /* Clear GPIO 11 */
3222 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3223 }
3224 }
3225
e68a619a
MI		 3226 /* Check and update state for all sub-devices. */
3227 pvr2_subdev_update(hdw);
3228
75212a02 3229 hdw->tuner_updated = 0;
27764726 3230 hdw->force_dirty = 0;
5ceaad14
MI		 3231 for (idx = 0; idx < hdw->control_cnt; idx++) {
3232 cptr = hdw->controls + idx;
3233 if (!cptr->info->clear_dirty) continue;
3234 cptr->info->clear_dirty(cptr);
3235 }
3236
62433e31
MI		 3237 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3238 hdw->state_encoder_run) {
3239 /* If encoder isn't running or it can't be touched, then
3240 this will get worked out later when we start the
3241 encoder. */
681c7399
MI		 3242 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3243 }
d855497e 3244
681c7399 3245 hdw->state_pipeline_config = !0;
432907f7
MI		 3246 /* Hardware state may have changed in a way to cause the cropping
3247 capabilities to have changed. So mark it stale, which will
3248 cause a later re-fetch. */
681c7399
MI		 3249 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3250 return !0;
d855497e
MI		 3251}
3252
3253
3254int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3255{
681c7399
MI		 3256 int fl;
3257 LOCK_TAKE(hdw->big_lock);
3258 fl = pvr2_hdw_commit_setup(hdw);
3259 LOCK_GIVE(hdw->big_lock);
3260 if (!fl) return 0;
3261 return pvr2_hdw_wait(hdw,0);
3262}
3263
3264
681c7399 3265static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 3266{
681c7399
MI		 3267 int fl = 0;
3268 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 3269 LOCK_TAKE(hdw->big_lock); do {
681c7399 3270 fl = pvr2_hdw_state_eval(hdw);
d855497e 3271 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 3272 if (fl && hdw->state_func) {
3273 hdw->state_func(hdw->state_data);
3274 }
d855497e
MI		 3275}
3276
3277
681c7399 3278static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 3279{
681c7399
MI		 3280 return wait_event_interruptible(
3281 hdw->state_wait_data,
3282 (hdw->state_stale == 0) &&
3283 (!state || (hdw->master_state != state)));
3284}
3285
3286
d855497e
MI		 3287/* Return name for this driver instance */
3288const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3289{
3290 return hdw->name;
3291}
3292
3293
78a47101
MI		 3294const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3295{
3296 return hdw->hdw_desc->description;
3297}
3298
3299
3300const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3301{
3302 return hdw->hdw_desc->shortname;
3303}
3304
3305
d855497e
MI		 3306int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3307{
3308 int result;
3309 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3310 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 3311 result = pvr2_send_request(hdw,
3312 hdw->cmd_buffer,1,
3313 hdw->cmd_buffer,1);
3314 if (result < 0) break;
3315 result = (hdw->cmd_buffer[0] != 0);
3316 } while(0); LOCK_GIVE(hdw->ctl_lock);
3317 return result;
3318}
3319
3320
18103c57
MI		 3321/* Execute poll of tuner status */
3322void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 3323{
d855497e 3324 LOCK_TAKE(hdw->big_lock); do {
a51f5000 3325 pvr2_hdw_status_poll(hdw);
d855497e 3326 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 3327}
3328
3329
432907f7
MI		 3330static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3331{
3332 if (!hdw->cropcap_stale) {
432907f7
MI		 3333 return 0;
3334 }
a51f5000 3335 pvr2_hdw_status_poll(hdw);
432907f7 3336 if (hdw->cropcap_stale) {
432907f7
MI		 3337 return -EIO;
3338 }
3339 return 0;
3340}
3341
3342
3343/* Return information about cropping capabilities */
3344int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3345{
3346 int stat = 0;
3347 LOCK_TAKE(hdw->big_lock);
3348 stat = pvr2_hdw_check_cropcap(hdw);
3349 if (!stat) {
432907f7
MI		 3350 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3351 }
3352 LOCK_GIVE(hdw->big_lock);
3353 return stat;
3354}
3355
3356
18103c57
MI		 3357/* Return information about the tuner */
3358int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3359{
3360 LOCK_TAKE(hdw->big_lock); do {
3361 if (hdw->tuner_signal_stale) {
a51f5000 3362 pvr2_hdw_status_poll(hdw);
18103c57
MI		 3363 }
3364 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3365 } while (0); LOCK_GIVE(hdw->big_lock);
3366 return 0;
d855497e
MI		 3367}
3368
3369
3370/* Get handle to video output stream */
3371struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3372{
3373 return hp->vid_stream;
3374}
3375
3376
3377void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3378{
4f1a3e5b 3379 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e 3380 LOCK_TAKE(hdw->big_lock); do {
4f1a3e5b 3381 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
ed3261a8 3382 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
b30d2441 3383 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 3384 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 3385 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 3386 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 3387 } while (0); LOCK_GIVE(hdw->big_lock);
3388}
3389
4db666cc
MI		 3390
3391/* Grab EEPROM contents, needed for direct method. */
3392#define EEPROM_SIZE 8192
3393#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3394static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3395{
3396 struct i2c_msg msg[2];
3397 u8 *eeprom;
3398 u8 iadd[2];
3399 u8 addr;
3400 u16 eepromSize;
3401 unsigned int offs;
3402 int ret;
3403 int mode16 = 0;
3404 unsigned pcnt,tcnt;
3405 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3406 if (!eeprom) {
3407 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3408 "Failed to allocate memory"
3409 " required to read eeprom");
3410 return NULL;
3411 }
3412
3413 trace_eeprom("Value for eeprom addr from controller was 0x%x",
3414 hdw->eeprom_addr);
3415 addr = hdw->eeprom_addr;
3416 /* Seems that if the high bit is set, then the *real* eeprom
3417 address is shifted right now bit position (noticed this in
3418 newer PVR USB2 hardware) */
3419 if (addr & 0x80) addr >>= 1;
3420
3421 /* FX2 documentation states that a 16bit-addressed eeprom is
3422 expected if the I2C address is an odd number (yeah, this is
3423 strange but it's what they do) */
3424 mode16 = (addr & 1);
3425 eepromSize = (mode16 ? EEPROM_SIZE : 256);
3426 trace_eeprom("Examining %d byte eeprom at location 0x%x"
3427 " using %d bit addressing",eepromSize,addr,
3428 mode16 ? 16 : 8);
3429
3430 msg[0].addr = addr;
3431 msg[0].flags = 0;
3432 msg[0].len = mode16 ? 2 : 1;
3433 msg[0].buf = iadd;
3434 msg[1].addr = addr;
3435 msg[1].flags = I2C_M_RD;
3436
3437 /* We have to do the actual eeprom data fetch ourselves, because
3438 (1) we're only fetching part of the eeprom, and (2) if we were
3439 getting the whole thing our I2C driver can't grab it in one
3440 pass - which is what tveeprom is otherwise going to attempt */
3441 memset(eeprom,0,EEPROM_SIZE);
3442 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3443 pcnt = 16;
3444 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3445 offs = tcnt + (eepromSize - EEPROM_SIZE);
3446 if (mode16) {
3447 iadd[0] = offs >> 8;
3448 iadd[1] = offs;
3449 } else {
3450 iadd[0] = offs;
3451 }
3452 msg[1].len = pcnt;
3453 msg[1].buf = eeprom+tcnt;
3454 if ((ret = i2c_transfer(&hdw->i2c_adap,
3455 msg,ARRAY_SIZE(msg))) != 2) {
3456 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3457 "eeprom fetch set offs err=%d",ret);
3458 kfree(eeprom);
3459 return NULL;
3460 }
3461 }
3462 return eeprom;
3463}
3464
3465
3466void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3467 int prom_flag,
3468 int enable_flag)
d855497e
MI		 3469{
3470 int ret;
3471 u16 address;
3472 unsigned int pipe;
3473 LOCK_TAKE(hdw->big_lock); do {
5fa1247a 3474 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
d855497e
MI		 3475
3476 if (!enable_flag) {
3477 pvr2_trace(PVR2_TRACE_FIRMWARE,
3478 "Cleaning up after CPU firmware fetch");
3479 kfree(hdw->fw_buffer);
a0fd1cb1 3480 hdw->fw_buffer = NULL;
d855497e 3481 hdw->fw_size = 0;
4db666cc
MI		 3482 if (hdw->fw_cpu_flag) {
3483 /* Now release the CPU. It will disconnect
3484 and reconnect later. */
3485 pvr2_hdw_cpureset_assert(hdw,0);
3486 }
d855497e
MI		 3487 break;
3488 }
3489
4db666cc
MI		 3490 hdw->fw_cpu_flag = (prom_flag == 0);
3491 if (hdw->fw_cpu_flag) {
3492 pvr2_trace(PVR2_TRACE_FIRMWARE,
3493 "Preparing to suck out CPU firmware");
3494 hdw->fw_size = 0x2000;
3495 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3496 if (!hdw->fw_buffer) {
3497 hdw->fw_size = 0;
3498 break;
3499 }
d855497e 3500
4db666cc
MI		 3501 /* We have to hold the CPU during firmware upload. */
3502 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 3503
4db666cc
MI		 3504 /* download the firmware from address 0000-1fff in 2048
3505 (=0x800) bytes chunk. */
d855497e 3506
4db666cc
MI		 3507 pvr2_trace(PVR2_TRACE_FIRMWARE,
3508 "Grabbing CPU firmware");
3509 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3510 for(address = 0; address < hdw->fw_size;
3511 address += 0x800) {
3512 ret = usb_control_msg(hdw->usb_dev,pipe,
3513 0xa0,0xc0,
3514 address,0,
3515 hdw->fw_buffer+address,
3516 0x800,HZ);
3517 if (ret < 0) break;
3518 }
d855497e 3519
4db666cc
MI		 3520 pvr2_trace(PVR2_TRACE_FIRMWARE,
3521 "Done grabbing CPU firmware");
3522 } else {
3523 pvr2_trace(PVR2_TRACE_FIRMWARE,
3524 "Sucking down EEPROM contents");
3525 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3526 if (!hdw->fw_buffer) {
3527 pvr2_trace(PVR2_TRACE_FIRMWARE,
3528 "EEPROM content suck failed.");
3529 break;
3530 }
3531 hdw->fw_size = EEPROM_SIZE;
3532 pvr2_trace(PVR2_TRACE_FIRMWARE,
3533 "Done sucking down EEPROM contents");
3534 }
d855497e
MI		 3535
3536 } while (0); LOCK_GIVE(hdw->big_lock);
3537}
3538
3539
3540/* Return true if we're in a mode for retrieval CPU firmware */
3541int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3542{
5fa1247a 3543 return hdw->fw_buffer != NULL;
d855497e
MI		 3544}
3545
3546
3547int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3548 char *buf,unsigned int cnt)
3549{
3550 int ret = -EINVAL;
3551 LOCK_TAKE(hdw->big_lock); do {
3552 if (!buf) break;
3553 if (!cnt) break;
3554
3555 if (!hdw->fw_buffer) {
3556 ret = -EIO;
3557 break;
3558 }
3559
3560 if (offs >= hdw->fw_size) {
3561 pvr2_trace(PVR2_TRACE_FIRMWARE,
3562 "Read firmware data offs=%d EOF",
3563 offs);
3564 ret = 0;
3565 break;
3566 }
3567
3568 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3569
3570 memcpy(buf,hdw->fw_buffer+offs,cnt);
3571
3572 pvr2_trace(PVR2_TRACE_FIRMWARE,
3573 "Read firmware data offs=%d cnt=%d",
3574 offs,cnt);
3575 ret = cnt;
3576 } while (0); LOCK_GIVE(hdw->big_lock);
3577
3578 return ret;
3579}
3580
3581
fd5a75fe 3582int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 3583 enum pvr2_v4l_type index)
d855497e 3584{
fd5a75fe 3585 switch (index) {
8079384e
MI		 3586 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3587 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3588 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 3589 default: return -1;
3590 }
d855497e
MI		 3591}
3592
3593
2fdf3d9c 3594/* Store a v4l minor device number */
fd5a75fe 3595void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 3596 enum pvr2_v4l_type index,int v)
d855497e 3597{
fd5a75fe 3598 switch (index) {
8079384e
MI		 3599 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3600 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3601 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 3602 default: break;
3603 }
d855497e
MI		 3604}
3605
3606
7d12e780 3607static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 3608{
3609 struct pvr2_hdw *hdw = urb->context;
3610 hdw->ctl_write_pend_flag = 0;
3611 if (hdw->ctl_read_pend_flag) return;
3612 complete(&hdw->ctl_done);
3613}
3614
3615
7d12e780 3616static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 3617{
3618 struct pvr2_hdw *hdw = urb->context;
3619 hdw->ctl_read_pend_flag = 0;
3620 if (hdw->ctl_write_pend_flag) return;
3621 complete(&hdw->ctl_done);
3622}
3623
3624
3625static void pvr2_ctl_timeout(unsigned long data)
3626{
3627 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3628 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3629 hdw->ctl_timeout_flag = !0;
5e55d2ce 3630 if (hdw->ctl_write_pend_flag)
d855497e 3631 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 3632 if (hdw->ctl_read_pend_flag)
d855497e 3633 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 3634 }
3635}
3636
3637
e61b6fc5
MI		 3638/* Issue a command and get a response from the device. This extended
3639 version includes a probe flag (which if set means that device errors
3640 should not be logged or treated as fatal) and a timeout in jiffies.
3641 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 3642static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3643 unsigned int timeout,int probe_fl,
3644 void *write_data,unsigned int write_len,
3645 void *read_data,unsigned int read_len)
d855497e
MI		 3646{
3647 unsigned int idx;
3648 int status = 0;
3649 struct timer_list timer;
3650 if (!hdw->ctl_lock_held) {
3651 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3652 "Attempted to execute control transfer"
3653 " without lock!!");
3654 return -EDEADLK;
3655 }
681c7399 3656 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 3657 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3658 "Attempted to execute control transfer"
3659 " when device not ok");
3660 return -EIO;
3661 }
3662 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3663 if (!probe_fl) {
3664 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3665 "Attempted to execute control transfer"
3666 " when USB is disconnected");
3667 }
3668 return -ENOTTY;
3669 }
3670
3671 /* Ensure that we have sane parameters */
3672 if (!write_data) write_len = 0;
3673 if (!read_data) read_len = 0;
3674 if (write_len > PVR2_CTL_BUFFSIZE) {
3675 pvr2_trace(
3676 PVR2_TRACE_ERROR_LEGS,
3677 "Attempted to execute %d byte"
3678 " control-write transfer (limit=%d)",
3679 write_len,PVR2_CTL_BUFFSIZE);
3680 return -EINVAL;
3681 }
3682 if (read_len > PVR2_CTL_BUFFSIZE) {
3683 pvr2_trace(
3684 PVR2_TRACE_ERROR_LEGS,
3685 "Attempted to execute %d byte"
3686 " control-read transfer (limit=%d)",
3687 write_len,PVR2_CTL_BUFFSIZE);
3688 return -EINVAL;
3689 }
3690 if ((!write_len) && (!read_len)) {
3691 pvr2_trace(
3692 PVR2_TRACE_ERROR_LEGS,
3693 "Attempted to execute null control transfer?");
3694 return -EINVAL;
3695 }
3696
3697
3698 hdw->cmd_debug_state = 1;
3699 if (write_len) {
3700 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3701 } else {
3702 hdw->cmd_debug_code = 0;
3703 }
3704 hdw->cmd_debug_write_len = write_len;
3705 hdw->cmd_debug_read_len = read_len;
3706
3707 /* Initialize common stuff */
3708 init_completion(&hdw->ctl_done);
3709 hdw->ctl_timeout_flag = 0;
3710 hdw->ctl_write_pend_flag = 0;
3711 hdw->ctl_read_pend_flag = 0;
3712 init_timer(&timer);
3713 timer.expires = jiffies + timeout;
3714 timer.data = (unsigned long)hdw;
3715 timer.function = pvr2_ctl_timeout;
3716
3717 if (write_len) {
3718 hdw->cmd_debug_state = 2;
3719 /* Transfer write data to internal buffer */
3720 for (idx = 0; idx < write_len; idx++) {
3721 hdw->ctl_write_buffer[idx] =
3722 ((unsigned char *)write_data)[idx];
3723 }
3724 /* Initiate a write request */
3725 usb_fill_bulk_urb(hdw->ctl_write_urb,
3726 hdw->usb_dev,
3727 usb_sndbulkpipe(hdw->usb_dev,
3728 PVR2_CTL_WRITE_ENDPOINT),
3729 hdw->ctl_write_buffer,
3730 write_len,
3731 pvr2_ctl_write_complete,
3732 hdw);
3733 hdw->ctl_write_urb->actual_length = 0;
3734 hdw->ctl_write_pend_flag = !0;
3735 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3736 if (status < 0) {
3737 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3738 "Failed to submit write-control"
3739 " URB status=%d",status);
3740 hdw->ctl_write_pend_flag = 0;
3741 goto done;
3742 }
3743 }
3744
3745 if (read_len) {
3746 hdw->cmd_debug_state = 3;
3747 memset(hdw->ctl_read_buffer,0x43,read_len);
3748 /* Initiate a read request */
3749 usb_fill_bulk_urb(hdw->ctl_read_urb,
3750 hdw->usb_dev,
3751 usb_rcvbulkpipe(hdw->usb_dev,
3752 PVR2_CTL_READ_ENDPOINT),
3753 hdw->ctl_read_buffer,
3754 read_len,
3755 pvr2_ctl_read_complete,
3756 hdw);
3757 hdw->ctl_read_urb->actual_length = 0;
3758 hdw->ctl_read_pend_flag = !0;
3759 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3760 if (status < 0) {
3761 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3762 "Failed to submit read-control"
3763 " URB status=%d",status);
3764 hdw->ctl_read_pend_flag = 0;
3765 goto done;
3766 }
3767 }
3768
3769 /* Start timer */
3770 add_timer(&timer);
3771
3772 /* Now wait for all I/O to complete */
3773 hdw->cmd_debug_state = 4;
3774 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3775 wait_for_completion(&hdw->ctl_done);
3776 }
3777 hdw->cmd_debug_state = 5;
3778
3779 /* Stop timer */
3780 del_timer_sync(&timer);
3781
3782 hdw->cmd_debug_state = 6;
3783 status = 0;
3784
3785 if (hdw->ctl_timeout_flag) {
3786 status = -ETIMEDOUT;
3787 if (!probe_fl) {
3788 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3789 "Timed out control-write");
3790 }
3791 goto done;
3792 }
3793
3794 if (write_len) {
3795 /* Validate results of write request */
3796 if ((hdw->ctl_write_urb->status != 0) &&
3797 (hdw->ctl_write_urb->status != -ENOENT) &&
3798 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3799 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3800 /* USB subsystem is reporting some kind of failure
3801 on the write */
3802 status = hdw->ctl_write_urb->status;
3803 if (!probe_fl) {
3804 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3805 "control-write URB failure,"
3806 " status=%d",
3807 status);
3808 }
3809 goto done;
3810 }
3811 if (hdw->ctl_write_urb->actual_length < write_len) {
3812 /* Failed to write enough data */
3813 status = -EIO;
3814 if (!probe_fl) {
3815 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3816 "control-write URB short,"
3817 " expected=%d got=%d",
3818 write_len,
3819 hdw->ctl_write_urb->actual_length);
3820 }
3821 goto done;
3822 }
3823 }
3824 if (read_len) {
3825 /* Validate results of read request */
3826 if ((hdw->ctl_read_urb->status != 0) &&
3827 (hdw->ctl_read_urb->status != -ENOENT) &&
3828 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3829 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3830 /* USB subsystem is reporting some kind of failure
3831 on the read */
3832 status = hdw->ctl_read_urb->status;
3833 if (!probe_fl) {
3834 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3835 "control-read URB failure,"
3836 " status=%d",
3837 status);
3838 }
3839 goto done;
3840 }
3841 if (hdw->ctl_read_urb->actual_length < read_len) {
3842 /* Failed to read enough data */
3843 status = -EIO;
3844 if (!probe_fl) {
3845 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3846 "control-read URB short,"
3847 " expected=%d got=%d",
3848 read_len,
3849 hdw->ctl_read_urb->actual_length);
3850 }
3851 goto done;
3852 }
3853 /* Transfer retrieved data out from internal buffer */
3854 for (idx = 0; idx < read_len; idx++) {
3855 ((unsigned char *)read_data)[idx] =
3856 hdw->ctl_read_buffer[idx];
3857 }
3858 }
3859
3860 done:
3861
3862 hdw->cmd_debug_state = 0;
3863 if ((status < 0) && (!probe_fl)) {
681c7399 3864 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3865 }
3866 return status;
3867}
3868
3869
3870int pvr2_send_request(struct pvr2_hdw *hdw,
3871 void *write_data,unsigned int write_len,
3872 void *read_data,unsigned int read_len)
3873{
3874 return pvr2_send_request_ex(hdw,HZ*4,0,
3875 write_data,write_len,
3876 read_data,read_len);
3877}
3878
1c9d10d4
MI		 3879
3880static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3881{
3882 int ret;
3883 unsigned int cnt = 1;
3884 unsigned int args = 0;
3885 LOCK_TAKE(hdw->ctl_lock);
3886 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3887 args = (cmdcode >> 8) & 0xffu;
3888 args = (args > 2) ? 2 : args;
3889 if (args) {
3890 cnt += args;
3891 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3892 if (args > 1) {
3893 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3894 }
3895 }
3896 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3897 unsigned int idx;
3898 unsigned int ccnt,bcnt;
3899 char tbuf[50];
3900 cmdcode &= 0xffu;
3901 bcnt = 0;
3902 ccnt = scnprintf(tbuf+bcnt,
3903 sizeof(tbuf)-bcnt,
3904 "Sending FX2 command 0x%x",cmdcode);
3905 bcnt += ccnt;
3906 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3907 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3908 ccnt = scnprintf(tbuf+bcnt,
3909 sizeof(tbuf)-bcnt,
3910 " \"%s\"",
3911 pvr2_fx2cmd_desc[idx].desc);
3912 bcnt += ccnt;
3913 break;
3914 }
3915 }
3916 if (args) {
3917 ccnt = scnprintf(tbuf+bcnt,
3918 sizeof(tbuf)-bcnt,
3919 " (%u",hdw->cmd_buffer[1]);
3920 bcnt += ccnt;
3921 if (args > 1) {
3922 ccnt = scnprintf(tbuf+bcnt,
3923 sizeof(tbuf)-bcnt,
3924 ",%u",hdw->cmd_buffer[2]);
3925 bcnt += ccnt;
3926 }
3927 ccnt = scnprintf(tbuf+bcnt,
3928 sizeof(tbuf)-bcnt,
3929 ")");
3930 bcnt += ccnt;
3931 }
3932 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3933 }
3934 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3935 LOCK_GIVE(hdw->ctl_lock);
3936 return ret;
3937}
3938
3939
d855497e
MI		 3940int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3941{
3942 int ret;
3943
3944 LOCK_TAKE(hdw->ctl_lock);
3945
8d364363 3946 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 3947 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3948 hdw->cmd_buffer[5] = 0;
3949 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3950 hdw->cmd_buffer[7] = reg & 0xff;
3951
3952
3953 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3954
3955 LOCK_GIVE(hdw->ctl_lock);
3956
3957 return ret;
3958}
3959
3960
07e337ee 3961static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 3962{
3963 int ret = 0;
3964
3965 LOCK_TAKE(hdw->ctl_lock);
3966
8d364363 3967 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 3968 hdw->cmd_buffer[1] = 0;
3969 hdw->cmd_buffer[2] = 0;
3970 hdw->cmd_buffer[3] = 0;
3971 hdw->cmd_buffer[4] = 0;
3972 hdw->cmd_buffer[5] = 0;
3973 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3974 hdw->cmd_buffer[7] = reg & 0xff;
3975
3976 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3977 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3978
3979 LOCK_GIVE(hdw->ctl_lock);
3980
3981 return ret;
3982}
3983
3984
681c7399 3985void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 3986{
3987 if (!hdw->flag_ok) return;
681c7399
MI		 3988 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3989 "Device being rendered inoperable");
d855497e 3990 if (hdw->vid_stream) {
a0fd1cb1 3991 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 3992 }
681c7399
MI		 3993 hdw->flag_ok = 0;
3994 trace_stbit("flag_ok",hdw->flag_ok);
3995 pvr2_hdw_state_sched(hdw);
d855497e
MI		 3996}
3997
3998
3999void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4000{
4001 int ret;
4002 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 4003 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
011b15df 4004 if (ret == 0) {
d855497e
MI		 4005 ret = usb_reset_device(hdw->usb_dev);
4006 usb_unlock_device(hdw->usb_dev);
4007 } else {
4008 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4009 "Failed to lock USB device ret=%d",ret);
4010 }
4011 if (init_pause_msec) {
4012 pvr2_trace(PVR2_TRACE_INFO,
4013 "Waiting %u msec for hardware to settle",
4014 init_pause_msec);
4015 msleep(init_pause_msec);
4016 }
4017
4018}
4019
4020
4021void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4022{
4023 char da[1];
4024 unsigned int pipe;
4025 int ret;
4026
4027 if (!hdw->usb_dev) return;
4028
4029 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4030
4031 da[0] = val ? 0x01 : 0x00;
4032
4033 /* Write the CPUCS register on the 8051. The lsb of the register
4034 is the reset bit; a 1 asserts reset while a 0 clears it. */
4035 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4036 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4037 if (ret < 0) {
4038 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4039 "cpureset_assert(%d) error=%d",val,ret);
4040 pvr2_hdw_render_useless(hdw);
4041 }
4042}
4043
4044
4045int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4046{
1c9d10d4 4047 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
d855497e
MI		 4048}
4049
4050
e1edb19a
MK		 4051int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4052{
1c9d10d4 4053 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
e1edb19a
MK		 4054}
4055
1c9d10d4 4056
e1edb19a
MK		 4057int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4058{
1c9d10d4 4059 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
e1edb19a
MK		 4060}
4061
d855497e
MI		 4062
4063int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4064{
af78e16b
MI		 4065 pvr2_trace(PVR2_TRACE_INIT,
4066 "Requesting decoder reset");
af78e16b
MI		 4067 if (hdw->decoder_client_id) {
4068 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4069 core, reset, 0);
4070 return 0;
d855497e 4071 }
d855497e 4072 pvr2_trace(PVR2_TRACE_INIT,
af78e16b
MI		 4073 "Unable to reset decoder: nothing attached");
4074 return -ENOTTY;
d855497e
MI		 4075}
4076
4077
62433e31 4078static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
84147f3d 4079{
1c9d10d4
MI		 4080 hdw->flag_ok = !0;
4081 return pvr2_issue_simple_cmd(hdw,
4082 FX2CMD_HCW_DEMOD_RESETIN |
4083 (1 << 8) |
4084 ((onoff ? 1 : 0) << 16));
84147f3d
MI		 4085}
4086
84147f3d 4087
62433e31 4088static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
84147f3d 4089{
1c9d10d4
MI		 4090 hdw->flag_ok = !0;
4091 return pvr2_issue_simple_cmd(hdw,(onoff ?
4092 FX2CMD_ONAIR_DTV_POWER_ON :
4093 FX2CMD_ONAIR_DTV_POWER_OFF));
84147f3d
MI		 4094}
4095
62433e31
MI		 4096
4097static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4098 int onoff)
84147f3d 4099{
1c9d10d4
MI		 4100 return pvr2_issue_simple_cmd(hdw,(onoff ?
4101 FX2CMD_ONAIR_DTV_STREAMING_ON :
4102 FX2CMD_ONAIR_DTV_STREAMING_OFF));
84147f3d
MI		 4103}
4104
62433e31
MI		 4105
4106static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4107{
4108 int cmode;
4109 /* Compare digital/analog desired setting with current setting. If
4110 they don't match, fix it... */
4111 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4112 if (cmode == hdw->pathway_state) {
4113 /* They match; nothing to do */
4114 return;
4115 }
4116
4117 switch (hdw->hdw_desc->digital_control_scheme) {
4118 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4119 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4120 if (cmode == PVR2_PATHWAY_ANALOG) {
4121 /* If moving to analog mode, also force the decoder
4122 to reset. If no decoder is attached, then it's
4123 ok to ignore this because if/when the decoder
4124 attaches, it will reset itself at that time. */
4125 pvr2_hdw_cmd_decoder_reset(hdw);
4126 }
4127 break;
4128 case PVR2_DIGITAL_SCHEME_ONAIR:
4129 /* Supposedly we should always have the power on whether in
4130 digital or analog mode. But for now do what appears to
4131 work... */
bb0c2fe0 4132 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
62433e31
MI		 4133 break;
4134 default: break;
4135 }
4136
1b9c18c5 4137 pvr2_hdw_untrip_unlocked(hdw);
62433e31
MI		 4138 hdw->pathway_state = cmode;
4139}
4140
4141
e9b59f6e 4142static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
c55a97d7
MI		 4143{
4144 /* change some GPIO data
4145 *
4146 * note: bit d7 of dir appears to control the LED,
4147 * so we shut it off here.
4148 *
c55a97d7 4149 */
40381cb0 4150 if (onoff) {
c55a97d7 4151 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
40381cb0 4152 } else {
c55a97d7 4153 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
40381cb0 4154 }
c55a97d7 4155 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
40381cb0 4156}
c55a97d7 4157
40381cb0
MI		 4158
4159typedef void (*led_method_func)(struct pvr2_hdw *,int);
4160
4161static led_method_func led_methods[] = {
4162 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4163};
4164
4165
4166/* Toggle LED */
4167static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4168{
4169 unsigned int scheme_id;
4170 led_method_func fp;
4171
4172 if ((!onoff) == (!hdw->led_on)) return;
4173
4174 hdw->led_on = onoff != 0;
4175
4176 scheme_id = hdw->hdw_desc->led_scheme;
4177 if (scheme_id < ARRAY_SIZE(led_methods)) {
4178 fp = led_methods[scheme_id];
4179 } else {
4180 fp = NULL;
4181 }
4182
4183 if (fp) (*fp)(hdw,onoff);
c55a97d7
MI		 4184}
4185
4186
e61b6fc5 4187/* Stop / start video stream transport */
07e337ee 4188static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e 4189{
bb0c2fe0
MI		 4190 int ret;
4191
4192 /* If we're in analog mode, then just issue the usual analog
4193 command. */
4194 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4195 return pvr2_issue_simple_cmd(hdw,
4196 (runFl ?
4197 FX2CMD_STREAMING_ON :
4198 FX2CMD_STREAMING_OFF));
4199 /*Note: Not reached */
4200 }
4201
4202 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4203 /* Whoops, we don't know what mode we're in... */
4204 return -EINVAL;
4205 }
4206
4207 /* To get here we have to be in digital mode. The mechanism here
4208 is unfortunately different for different vendors. So we switch
4209 on the device's digital scheme attribute in order to figure out
4210 what to do. */
4211 switch (hdw->hdw_desc->digital_control_scheme) {
4212 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4213 return pvr2_issue_simple_cmd(hdw,
4214 (runFl ?
4215 FX2CMD_HCW_DTV_STREAMING_ON :
4216 FX2CMD_HCW_DTV_STREAMING_OFF));
4217 case PVR2_DIGITAL_SCHEME_ONAIR:
4218 ret = pvr2_issue_simple_cmd(hdw,
4219 (runFl ?
4220 FX2CMD_STREAMING_ON :
4221 FX2CMD_STREAMING_OFF));
4222 if (ret) return ret;
4223 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4224 default:
4225 return -EINVAL;
62433e31 4226 }
d855497e
MI		 4227}
4228
4229
62433e31
MI		 4230/* Evaluate whether or not state_pathway_ok can change */
4231static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4232{
4233 if (hdw->state_pathway_ok) {
4234 /* Nothing to do if pathway is already ok */
4235 return 0;
4236 }
4237 if (!hdw->state_pipeline_idle) {
4238 /* Not allowed to change anything if pipeline is not idle */
4239 return 0;
4240 }
4241 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4242 hdw->state_pathway_ok = !0;
e9db1ff2 4243 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 4244 return !0;
4245}
4246
4247
681c7399
MI		 4248/* Evaluate whether or not state_encoder_ok can change */
4249static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4250{
4251 if (hdw->state_encoder_ok) return 0;
4252 if (hdw->flag_tripped) return 0;
4253 if (hdw->state_encoder_run) return 0;
4254 if (hdw->state_encoder_config) return 0;
4255 if (hdw->state_decoder_run) return 0;
4256 if (hdw->state_usbstream_run) return 0;
72998b71
MI		 4257 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4258 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4259 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4260 return 0;
4261 }
4262
681c7399
MI		 4263 if (pvr2_upload_firmware2(hdw) < 0) {
4264 hdw->flag_tripped = !0;
4265 trace_stbit("flag_tripped",hdw->flag_tripped);
4266 return !0;
4267 }
4268 hdw->state_encoder_ok = !0;
4269 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4270 return !0;
4271}
4272
4273
4274/* Evaluate whether or not state_encoder_config can change */
4275static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4276{
4277 if (hdw->state_encoder_config) {
4278 if (hdw->state_encoder_ok) {
4279 if (hdw->state_pipeline_req &&
4280 !hdw->state_pipeline_pause) return 0;
4281 }
4282 hdw->state_encoder_config = 0;
4283 hdw->state_encoder_waitok = 0;
4284 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4285 /* paranoia - solve race if timer just completed */
4286 del_timer_sync(&hdw->encoder_wait_timer);
4287 } else {
62433e31
MI		 4288 if (!hdw->state_pathway_ok ||
4289 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4290 !hdw->state_encoder_ok ||
681c7399
MI		 4291 !hdw->state_pipeline_idle ||
4292 hdw->state_pipeline_pause ||
4293 !hdw->state_pipeline_req ||
4294 !hdw->state_pipeline_config) {
4295 /* We must reset the enforced wait interval if
4296 anything has happened that might have disturbed
4297 the encoder. This should be a rare case. */
4298 if (timer_pending(&hdw->encoder_wait_timer)) {
4299 del_timer_sync(&hdw->encoder_wait_timer);
4300 }
4301 if (hdw->state_encoder_waitok) {
4302 /* Must clear the state - therefore we did
4303 something to a state bit and must also
4304 return true. */
4305 hdw->state_encoder_waitok = 0;
4306 trace_stbit("state_encoder_waitok",
4307 hdw->state_encoder_waitok);
4308 return !0;
4309 }
4310 return 0;
4311 }
4312 if (!hdw->state_encoder_waitok) {
4313 if (!timer_pending(&hdw->encoder_wait_timer)) {
4314 /* waitok flag wasn't set and timer isn't
4315 running. Check flag once more to avoid
4316 a race then start the timer. This is
4317 the point when we measure out a minimal
4318 quiet interval before doing something to
4319 the encoder. */
4320 if (!hdw->state_encoder_waitok) {
4321 hdw->encoder_wait_timer.expires =
83ce57aa
MI		 4322 jiffies +
4323 (HZ * TIME_MSEC_ENCODER_WAIT
4324 / 1000);
681c7399
MI		 4325 add_timer(&hdw->encoder_wait_timer);
4326 }
4327 }
4328 /* We can't continue until we know we have been
4329 quiet for the interval measured by this
4330 timer. */
4331 return 0;
4332 }
4333 pvr2_encoder_configure(hdw);
4334 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4335 }
4336 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4337 return !0;
4338}
4339
4340
d913d630
MI		 4341/* Return true if the encoder should not be running. */
4342static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4343{
4344 if (!hdw->state_encoder_ok) {
4345 /* Encoder isn't healthy at the moment, so stop it. */
4346 return !0;
4347 }
4348 if (!hdw->state_pathway_ok) {
4349 /* Mode is not understood at the moment (i.e. it wants to
4350 change), so encoder must be stopped. */
4351 return !0;
4352 }
4353
4354 switch (hdw->pathway_state) {
4355 case PVR2_PATHWAY_ANALOG:
4356 if (!hdw->state_decoder_run) {
4357 /* We're in analog mode and the decoder is not
4358 running; thus the encoder should be stopped as
4359 well. */
4360 return !0;
4361 }
4362 break;
4363 case PVR2_PATHWAY_DIGITAL:
4364 if (hdw->state_encoder_runok) {
4365 /* This is a funny case. We're in digital mode so
4366 really the encoder should be stopped. However
4367 if it really is running, only kill it after
4368 runok has been set. This gives a chance for the
4369 onair quirk to function (encoder must run
4370 briefly first, at least once, before onair
4371 digital streaming can work). */
4372 return !0;
4373 }
4374 break;
4375 default:
4376 /* Unknown mode; so encoder should be stopped. */
4377 return !0;
4378 }
4379
4380 /* If we get here, we haven't found a reason to stop the
4381 encoder. */
4382 return 0;
4383}
4384
4385
4386/* Return true if the encoder should be running. */
4387static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4388{
4389 if (!hdw->state_encoder_ok) {
4390 /* Don't run the encoder if it isn't healthy... */
4391 return 0;
4392 }
4393 if (!hdw->state_pathway_ok) {
4394 /* Don't run the encoder if we don't (yet) know what mode
4395 we need to be in... */
4396 return 0;
4397 }
4398
4399 switch (hdw->pathway_state) {
4400 case PVR2_PATHWAY_ANALOG:
4401 if (hdw->state_decoder_run) {
4402 /* In analog mode, if the decoder is running, then
4403 run the encoder. */
4404 return !0;
4405 }
4406 break;
4407 case PVR2_PATHWAY_DIGITAL:
4408 if ((hdw->hdw_desc->digital_control_scheme ==
4409 PVR2_DIGITAL_SCHEME_ONAIR) &&
4410 !hdw->state_encoder_runok) {
4411 /* This is a quirk. OnAir hardware won't stream
4412 digital until the encoder has been run at least
4413 once, for a minimal period of time (empiricially
4414 measured to be 1/4 second). So if we're on
4415 OnAir hardware and the encoder has never been
4416 run at all, then start the encoder. Normal
4417 state machine logic in the driver will
4418 automatically handle the remaining bits. */
4419 return !0;
4420 }
4421 break;
4422 default:
4423 /* For completeness (unknown mode; encoder won't run ever) */
4424 break;
4425 }
4426 /* If we get here, then we haven't found any reason to run the
4427 encoder, so don't run it. */
4428 return 0;
4429}
4430
4431
681c7399
MI		 4432/* Evaluate whether or not state_encoder_run can change */
4433static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4434{
4435 if (hdw->state_encoder_run) {
d913d630 4436 if (!state_check_disable_encoder_run(hdw)) return 0;
681c7399 4437 if (hdw->state_encoder_ok) {
d913d630 4438 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 4439 if (pvr2_encoder_stop(hdw) < 0) return !0;
4440 }
4441 hdw->state_encoder_run = 0;
4442 } else {
d913d630 4443 if (!state_check_enable_encoder_run(hdw)) return 0;
681c7399
MI		 4444 if (pvr2_encoder_start(hdw) < 0) return !0;
4445 hdw->state_encoder_run = !0;
d913d630
MI		 4446 if (!hdw->state_encoder_runok) {
4447 hdw->encoder_run_timer.expires =
83ce57aa 4448 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
d913d630
MI		 4449 add_timer(&hdw->encoder_run_timer);
4450 }
681c7399
MI		 4451 }
4452 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4453 return !0;
4454}
4455
4456
4457/* Timeout function for quiescent timer. */
4458static void pvr2_hdw_quiescent_timeout(unsigned long data)
4459{
4460 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4461 hdw->state_decoder_quiescent = !0;
4462 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4463 hdw->state_stale = !0;
4464 queue_work(hdw->workqueue,&hdw->workpoll);
4465}
4466
4467
4468/* Timeout function for encoder wait timer. */
4469static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4470{
4471 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4472 hdw->state_encoder_waitok = !0;
4473 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4474 hdw->state_stale = !0;
4475 queue_work(hdw->workqueue,&hdw->workpoll);
4476}
4477
4478
d913d630
MI		 4479/* Timeout function for encoder run timer. */
4480static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4481{
4482 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4483 if (!hdw->state_encoder_runok) {
4484 hdw->state_encoder_runok = !0;
4485 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4486 hdw->state_stale = !0;
4487 queue_work(hdw->workqueue,&hdw->workpoll);
4488 }
4489}
4490
4491
681c7399
MI		 4492/* Evaluate whether or not state_decoder_run can change */
4493static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4494{
4495 if (hdw->state_decoder_run) {
4496 if (hdw->state_encoder_ok) {
4497 if (hdw->state_pipeline_req &&
62433e31
MI		 4498 !hdw->state_pipeline_pause &&
4499 hdw->state_pathway_ok) return 0;
681c7399
MI		 4500 }
4501 if (!hdw->flag_decoder_missed) {
4502 pvr2_decoder_enable(hdw,0);
4503 }
4504 hdw->state_decoder_quiescent = 0;
4505 hdw->state_decoder_run = 0;
4506 /* paranoia - solve race if timer just completed */
4507 del_timer_sync(&hdw->quiescent_timer);
4508 } else {
4509 if (!hdw->state_decoder_quiescent) {
4510 if (!timer_pending(&hdw->quiescent_timer)) {
4511 /* We don't do something about the
4512 quiescent timer until right here because
4513 we also want to catch cases where the
4514 decoder was already not running (like
4515 after initialization) as opposed to
4516 knowing that we had just stopped it.
4517 The second flag check is here to cover a
4518 race - the timer could have run and set
4519 this flag just after the previous check
4520 but before we did the pending check. */
4521 if (!hdw->state_decoder_quiescent) {
4522 hdw->quiescent_timer.expires =
83ce57aa
MI		 4523 jiffies +
4524 (HZ * TIME_MSEC_DECODER_WAIT
4525 / 1000);
681c7399
MI		 4526 add_timer(&hdw->quiescent_timer);
4527 }
4528 }
4529 /* Don't allow decoder to start again until it has
4530 been quiesced first. This little detail should
4531 hopefully further stabilize the encoder. */
4532 return 0;
4533 }
62433e31
MI		 4534 if (!hdw->state_pathway_ok ||
4535 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4536 !hdw->state_pipeline_req ||
681c7399
MI		 4537 hdw->state_pipeline_pause ||
4538 !hdw->state_pipeline_config ||
4539 !hdw->state_encoder_config ||
4540 !hdw->state_encoder_ok) return 0;
4541 del_timer_sync(&hdw->quiescent_timer);
4542 if (hdw->flag_decoder_missed) return 0;
4543 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4544 hdw->state_decoder_quiescent = 0;
4545 hdw->state_decoder_run = !0;
4546 }
4547 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4548 trace_stbit("state_decoder_run",hdw->state_decoder_run);
4549 return !0;
4550}
4551
4552
4553/* Evaluate whether or not state_usbstream_run can change */
4554static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4555{
4556 if (hdw->state_usbstream_run) {
72998b71 4557 int fl = !0;
62433e31 4558 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
72998b71
MI		 4559 fl = (hdw->state_encoder_ok &&
4560 hdw->state_encoder_run);
4561 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4562 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4563 fl = hdw->state_encoder_ok;
4564 }
4565 if (fl &&
4566 hdw->state_pipeline_req &&
4567 !hdw->state_pipeline_pause &&
4568 hdw->state_pathway_ok) {
4569 return 0;
681c7399
MI		 4570 }
4571 pvr2_hdw_cmd_usbstream(hdw,0);
4572 hdw->state_usbstream_run = 0;
4573 } else {
62433e31
MI		 4574 if (!hdw->state_pipeline_req ||
4575 hdw->state_pipeline_pause ||
4576 !hdw->state_pathway_ok) return 0;
4577 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4578 if (!hdw->state_encoder_ok ||
4579 !hdw->state_encoder_run) return 0;
72998b71
MI		 4580 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4581 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4582 if (!hdw->state_encoder_ok) return 0;
d913d630
MI		 4583 if (hdw->state_encoder_run) return 0;
4584 if (hdw->hdw_desc->digital_control_scheme ==
4585 PVR2_DIGITAL_SCHEME_ONAIR) {
4586 /* OnAir digital receivers won't stream
4587 unless the analog encoder has run first.
4588 Why? I have no idea. But don't even
4589 try until we know the analog side is
4590 known to have run. */
4591 if (!hdw->state_encoder_runok) return 0;
4592 }
62433e31 4593 }
681c7399
MI		 4594 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4595 hdw->state_usbstream_run = !0;
4596 }
4597 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4598 return !0;
4599}
4600
4601
4602/* Attempt to configure pipeline, if needed */
4603static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4604{
4605 if (hdw->state_pipeline_config ||
4606 hdw->state_pipeline_pause) return 0;
4607 pvr2_hdw_commit_execute(hdw);
4608 return !0;
4609}
4610
4611
4612/* Update pipeline idle and pipeline pause tracking states based on other
4613 inputs. This must be called whenever the other relevant inputs have
4614 changed. */
4615static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4616{
4617 unsigned int st;
4618 int updatedFl = 0;
4619 /* Update pipeline state */
4620 st = !(hdw->state_encoder_run ||
4621 hdw->state_decoder_run ||
4622 hdw->state_usbstream_run ||
4623 (!hdw->state_decoder_quiescent));
4624 if (!st != !hdw->state_pipeline_idle) {
4625 hdw->state_pipeline_idle = st;
4626 updatedFl = !0;
4627 }
4628 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4629 hdw->state_pipeline_pause = 0;
4630 updatedFl = !0;
4631 }
4632 return updatedFl;
4633}
4634
4635
4636typedef int (*state_eval_func)(struct pvr2_hdw *);
4637
4638/* Set of functions to be run to evaluate various states in the driver. */
ebff0330 4639static const state_eval_func eval_funcs[] = {
62433e31 4640 state_eval_pathway_ok,
681c7399
MI		 4641 state_eval_pipeline_config,
4642 state_eval_encoder_ok,
4643 state_eval_encoder_config,
4644 state_eval_decoder_run,
4645 state_eval_encoder_run,
4646 state_eval_usbstream_run,
4647};
4648
4649
4650/* Process various states and return true if we did anything interesting. */
4651static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4652{
4653 unsigned int i;
4654 int state_updated = 0;
4655 int check_flag;
4656
4657 if (!hdw->state_stale) return 0;
4658 if ((hdw->fw1_state != FW1_STATE_OK) ||
4659 !hdw->flag_ok) {
4660 hdw->state_stale = 0;
4661 return !0;
4662 }
4663 /* This loop is the heart of the entire driver. It keeps trying to
4664 evaluate various bits of driver state until nothing changes for
4665 one full iteration. Each "bit of state" tracks some global
4666 aspect of the driver, e.g. whether decoder should run, if
4667 pipeline is configured, usb streaming is on, etc. We separately
4668 evaluate each of those questions based on other driver state to
4669 arrive at the correct running configuration. */
4670 do {
4671 check_flag = 0;
4672 state_update_pipeline_state(hdw);
4673 /* Iterate over each bit of state */
4674 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4675 if ((*eval_funcs[i])(hdw)) {
4676 check_flag = !0;
4677 state_updated = !0;
4678 state_update_pipeline_state(hdw);
4679 }
4680 }
4681 } while (check_flag && hdw->flag_ok);
4682 hdw->state_stale = 0;
4683 trace_stbit("state_stale",hdw->state_stale);
4684 return state_updated;
4685}
4686
4687
1cb03b76
MI		 4688static unsigned int print_input_mask(unsigned int msk,
4689 char *buf,unsigned int acnt)
4690{
4691 unsigned int idx,ccnt;
4692 unsigned int tcnt = 0;
4693 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4694 if (!((1 << idx) & msk)) continue;
4695 ccnt = scnprintf(buf+tcnt,
4696 acnt-tcnt,
4697 "%s%s",
4698 (tcnt ? ", " : ""),
4699 control_values_input[idx]);
4700 tcnt += ccnt;
4701 }
4702 return tcnt;
4703}
4704
4705
62433e31
MI		 4706static const char *pvr2_pathway_state_name(int id)
4707{
4708 switch (id) {
4709 case PVR2_PATHWAY_ANALOG: return "analog";
4710 case PVR2_PATHWAY_DIGITAL: return "digital";
4711 default: return "unknown";
4712 }
4713}
4714
4715
681c7399
MI		 4716static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4717 char *buf,unsigned int acnt)
4718{
4719 switch (which) {
4720 case 0:
4721 return scnprintf(
4722 buf,acnt,
e9db1ff2 4723 "driver:%s%s%s%s%s <mode=%s>",
681c7399
MI		 4724 (hdw->flag_ok ? " <ok>" : " <fail>"),
4725 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4726 (hdw->flag_disconnected ? " <disconnected>" :
4727 " <connected>"),
4728 (hdw->flag_tripped ? " <tripped>" : ""),
62433e31
MI		 4729 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4730 pvr2_pathway_state_name(hdw->pathway_state));
4731
681c7399
MI		 4732 case 1:
4733 return scnprintf(
4734 buf,acnt,
4735 "pipeline:%s%s%s%s",
4736 (hdw->state_pipeline_idle ? " <idle>" : ""),
4737 (hdw->state_pipeline_config ?
4738 " <configok>" : " <stale>"),
4739 (hdw->state_pipeline_req ? " <req>" : ""),
4740 (hdw->state_pipeline_pause ? " <pause>" : ""));
4741 case 2:
4742 return scnprintf(
4743 buf,acnt,
62433e31 4744 "worker:%s%s%s%s%s%s%s",
681c7399
MI		 4745 (hdw->state_decoder_run ?
4746 " <decode:run>" :
4747 (hdw->state_decoder_quiescent ?
4748 "" : " <decode:stop>")),
4749 (hdw->state_decoder_quiescent ?
4750 " <decode:quiescent>" : ""),
4751 (hdw->state_encoder_ok ?
4752 "" : " <encode:init>"),
4753 (hdw->state_encoder_run ?
d913d630
MI		 4754 (hdw->state_encoder_runok ?
4755 " <encode:run>" :
4756 " <encode:firstrun>") :
4757 (hdw->state_encoder_runok ?
4758 " <encode:stop>" :
4759 " <encode:virgin>")),
681c7399
MI		 4760 (hdw->state_encoder_config ?
4761 " <encode:configok>" :
4762 (hdw->state_encoder_waitok ?
b9a37d91 4763 "" : " <encode:waitok>")),
681c7399 4764 (hdw->state_usbstream_run ?
62433e31
MI		 4765 " <usb:run>" : " <usb:stop>"),
4766 (hdw->state_pathway_ok ?
e9db1ff2 4767 " <pathway:ok>" : ""));
681c7399
MI		 4768 case 3:
4769 return scnprintf(
4770 buf,acnt,
4771 "state: %s",
4772 pvr2_get_state_name(hdw->master_state));
ad0992e9 4773 case 4: {
1cb03b76
MI		 4774 unsigned int tcnt = 0;
4775 unsigned int ccnt;
4776
4777 ccnt = scnprintf(buf,
4778 acnt,
4779 "Hardware supported inputs: ");
4780 tcnt += ccnt;
4781 tcnt += print_input_mask(hdw->input_avail_mask,
4782 buf+tcnt,
4783 acnt-tcnt);
4784 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4785 ccnt = scnprintf(buf+tcnt,
4786 acnt-tcnt,
4787 "; allowed inputs: ");
4788 tcnt += ccnt;
4789 tcnt += print_input_mask(hdw->input_allowed_mask,
4790 buf+tcnt,
4791 acnt-tcnt);
4792 }
4793 return tcnt;
4794 }
4795 case 5: {
ad0992e9
MI		 4796 struct pvr2_stream_stats stats;
4797 if (!hdw->vid_stream) break;
4798 pvr2_stream_get_stats(hdw->vid_stream,
4799 &stats,
4800 0);
4801 return scnprintf(
4802 buf,acnt,
4803 "Bytes streamed=%u"
4804 " URBs: queued=%u idle=%u ready=%u"
4805 " processed=%u failed=%u",
4806 stats.bytes_processed,
4807 stats.buffers_in_queue,
4808 stats.buffers_in_idle,
4809 stats.buffers_in_ready,
4810 stats.buffers_processed,
4811 stats.buffers_failed);
4812 }
2eb563b7
MI		 4813 default: break;
4814 }
4815 return 0;
4816}
4817
4818
4819/* Generate report containing info about attached sub-devices and attached
4820 i2c clients, including an indication of which attached i2c clients are
4821 actually sub-devices. */
4822static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4823 char *buf, unsigned int acnt)
4824{
4825 struct v4l2_subdev *sd;
4826 unsigned int tcnt = 0;
4827 unsigned int ccnt;
4828 struct i2c_client *client;
4829 struct list_head *item;
4830 void *cd;
4831 const char *p;
4832 unsigned int id;
4833
4834 ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers:");
4835 tcnt += ccnt;
4836 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4837 id = sd->grp_id;
4838 p = NULL;
4839 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4840 if (p) {
4841 ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s", p);
4842 tcnt += ccnt;
4843 } else {
4844 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4845 " (unknown id=%u)", id);
4846 tcnt += ccnt;
4847 }
4848 }
4849 ccnt = scnprintf(buf + tcnt, acnt - tcnt, "\n");
4850 tcnt += ccnt;
4851
4852 ccnt = scnprintf(buf + tcnt, acnt - tcnt, "I2C clients:\n");
4853 tcnt += ccnt;
4854
4855 mutex_lock(&hdw->i2c_adap.clist_lock);
4856 list_for_each(item, &hdw->i2c_adap.clients) {
4857 client = list_entry(item, struct i2c_client, list);
4858 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4859 " %s: i2c=%02x", client->name, client->addr);
858f910e 4860 tcnt += ccnt;
2eb563b7 4861 cd = i2c_get_clientdata(client);
858f910e 4862 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
2eb563b7
MI		 4863 if (cd == sd) {
4864 id = sd->grp_id;
4865 p = NULL;
4866 if (id < ARRAY_SIZE(module_names)) {
4867 p = module_names[id];
4868 }
4869 if (p) {
4870 ccnt = scnprintf(buf + tcnt,
4871 acnt - tcnt,
4872 " subdev=%s", p);
4873 tcnt += ccnt;
4874 } else {
4875 ccnt = scnprintf(buf + tcnt,
4876 acnt - tcnt,
4877 " subdev= id %u)",
4878 id);
4879 tcnt += ccnt;
4880 }
4881 break;
5f757ddd 4882 }
858f910e 4883 }
2eb563b7
MI		 4884 ccnt = scnprintf(buf + tcnt, acnt - tcnt, "\n");
4885 tcnt += ccnt;
681c7399 4886 }
2eb563b7
MI		 4887 mutex_unlock(&hdw->i2c_adap.clist_lock);
4888 return tcnt;
681c7399
MI		 4889}
4890
4891
4892unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4893 char *buf,unsigned int acnt)
4894{
4895 unsigned int bcnt,ccnt,idx;
4896 bcnt = 0;
4897 LOCK_TAKE(hdw->big_lock);
4898 for (idx = 0; ; idx++) {
4899 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4900 if (!ccnt) break;
4901 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4902 if (!acnt) break;
4903 buf[0] = '\n'; ccnt = 1;
4904 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4905 }
2eb563b7
MI		 4906 ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4907 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
681c7399
MI		 4908 LOCK_GIVE(hdw->big_lock);
4909 return bcnt;
4910}
4911
4912
4913static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4914{
2eb563b7
MI		 4915 char buf[256];
4916 unsigned int idx, ccnt;
4917 unsigned int lcnt, ucnt;
681c7399
MI		 4918
4919 for (idx = 0; ; idx++) {
4920 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4921 if (!ccnt) break;
4922 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4923 }
2eb563b7
MI		 4924 ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
4925 ucnt = 0;
4926 while (ucnt < ccnt) {
4927 lcnt = 0;
4928 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4929 lcnt++;
4930 }
4931 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4932 ucnt += lcnt + 1;
4933 }
681c7399
MI		 4934}
4935
4936
4937/* Evaluate and update the driver's current state, taking various actions
4938 as appropriate for the update. */
4939static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4940{
4941 unsigned int st;
4942 int state_updated = 0;
4943 int callback_flag = 0;
1b9c18c5 4944 int analog_mode;
681c7399
MI		 4945
4946 pvr2_trace(PVR2_TRACE_STBITS,
4947 "Drive state check START");
4948 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4949 pvr2_hdw_state_log_state(hdw);
4950 }
4951
4952 /* Process all state and get back over disposition */
4953 state_updated = pvr2_hdw_state_update(hdw);
4954
1b9c18c5
MI		 4955 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4956
681c7399
MI		 4957 /* Update master state based upon all other states. */
4958 if (!hdw->flag_ok) {
4959 st = PVR2_STATE_DEAD;
4960 } else if (hdw->fw1_state != FW1_STATE_OK) {
4961 st = PVR2_STATE_COLD;
72998b71
MI		 4962 } else if ((analog_mode ||
4963 hdw->hdw_desc->flag_digital_requires_cx23416) &&
4964 !hdw->state_encoder_ok) {
681c7399 4965 st = PVR2_STATE_WARM;
1b9c18c5
MI		 4966 } else if (hdw->flag_tripped ||
4967 (analog_mode && hdw->flag_decoder_missed)) {
681c7399 4968 st = PVR2_STATE_ERROR;
62433e31 4969 } else if (hdw->state_usbstream_run &&
1b9c18c5 4970 (!analog_mode ||
62433e31 4971 (hdw->state_encoder_run && hdw->state_decoder_run))) {
681c7399
MI		 4972 st = PVR2_STATE_RUN;
4973 } else {
4974 st = PVR2_STATE_READY;
4975 }
4976 if (hdw->master_state != st) {
4977 pvr2_trace(PVR2_TRACE_STATE,
4978 "Device state change from %s to %s",
4979 pvr2_get_state_name(hdw->master_state),
4980 pvr2_get_state_name(st));
40381cb0 4981 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
681c7399
MI		 4982 hdw->master_state = st;
4983 state_updated = !0;
4984 callback_flag = !0;
4985 }
4986 if (state_updated) {
4987 /* Trigger anyone waiting on any state changes here. */
4988 wake_up(&hdw->state_wait_data);
4989 }
4990
4991 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4992 pvr2_hdw_state_log_state(hdw);
4993 }
4994 pvr2_trace(PVR2_TRACE_STBITS,
4995 "Drive state check DONE callback=%d",callback_flag);
4996
4997 return callback_flag;
4998}
4999
5000
5001/* Cause kernel thread to check / update driver state */
5002static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
5003{
5004 if (hdw->state_stale) return;
5005 hdw->state_stale = !0;
5006 trace_stbit("state_stale",hdw->state_stale);
5007 queue_work(hdw->workqueue,&hdw->workpoll);
5008}
5009
5010
d855497e
MI		 5011int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
5012{
5013 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5014}
5015
5016
5017int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5018{
5019 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5020}
5021
5022
5023int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5024{
5025 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5026}
5027
5028
5029int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5030{
5031 u32 cval,nval;
5032 int ret;
5033 if (~msk) {
5034 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5035 if (ret) return ret;
5036 nval = (cval & ~msk) | (val & msk);
5037 pvr2_trace(PVR2_TRACE_GPIO,
5038 "GPIO direction changing 0x%x:0x%x"
5039 " from 0x%x to 0x%x",
5040 msk,val,cval,nval);
5041 } else {
5042 nval = val;
5043 pvr2_trace(PVR2_TRACE_GPIO,
5044 "GPIO direction changing to 0x%x",nval);
5045 }
5046 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5047}
5048
5049
5050int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5051{
5052 u32 cval,nval;
5053 int ret;
5054 if (~msk) {
5055 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5056 if (ret) return ret;
5057 nval = (cval & ~msk) | (val & msk);
5058 pvr2_trace(PVR2_TRACE_GPIO,
5059 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5060 msk,val,cval,nval);
5061 } else {
5062 nval = val;
5063 pvr2_trace(PVR2_TRACE_GPIO,
5064 "GPIO output changing to 0x%x",nval);
5065 }
5066 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5067}
5068
5069
a51f5000
MI		 5070void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5071{
40f07111
MI		 5072 struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5073 memset(vtp, 0, sizeof(*vtp));
2641df36 5074 hdw->tuner_signal_stale = 0;
40f07111
MI		 5075 /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5076 using v4l2-subdev - therefore we can't support that AT ALL right
5077 now. (Of course, no sub-drivers seem to implement it either.
5078 But now it's a a chicken and egg problem...) */
5079 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5080 &hdw->tuner_signal_info);
2641df36 5081 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
40f07111
MI		 5082 " type=%u strength=%u audio=0x%x cap=0x%x"
5083 " low=%u hi=%u",
5084 vtp->type,
5085 vtp->signal, vtp->rxsubchans, vtp->capability,
5086 vtp->rangelow, vtp->rangehigh);
2641df36
MI		 5087
5088 /* We have to do this to avoid getting into constant polling if
5089 there's nobody to answer a poll of cropcap info. */
5090 hdw->cropcap_stale = 0;
a51f5000
MI		 5091}
5092
5093
7fb20fa3
MI		 5094unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5095{
5096 return hdw->input_avail_mask;
5097}
5098
5099
1cb03b76
MI		 5100unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5101{
5102 return hdw->input_allowed_mask;
5103}
5104
5105
5106static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5107{
5108 if (hdw->input_val != v) {
5109 hdw->input_val = v;
5110 hdw->input_dirty = !0;
5111 }
5112
5113 /* Handle side effects - if we switch to a mode that needs the RF
5114 tuner, then select the right frequency choice as well and mark
5115 it dirty. */
5116 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5117 hdw->freqSelector = 0;
5118 hdw->freqDirty = !0;
5119 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5120 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5121 hdw->freqSelector = 1;
5122 hdw->freqDirty = !0;
5123 }
5124 return 0;
5125}
5126
5127
5128int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5129 unsigned int change_mask,
5130 unsigned int change_val)
5131{
5132 int ret = 0;
5133 unsigned int nv,m,idx;
5134 LOCK_TAKE(hdw->big_lock);
5135 do {
5136 nv = hdw->input_allowed_mask & ~change_mask;
5137 nv |= (change_val & change_mask);
5138 nv &= hdw->input_avail_mask;
5139 if (!nv) {
5140 /* No legal modes left; return error instead. */
5141 ret = -EPERM;
5142 break;
5143 }
5144 hdw->input_allowed_mask = nv;
5145 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5146 /* Current mode is still in the allowed mask, so
5147 we're done. */
5148 break;
5149 }
5150 /* Select and switch to a mode that is still in the allowed
5151 mask */
5152 if (!hdw->input_allowed_mask) {
5153 /* Nothing legal; give up */
5154 break;
5155 }
5156 m = hdw->input_allowed_mask;
5157 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5158 if (!((1 << idx) & m)) continue;
5159 pvr2_hdw_set_input(hdw,idx);
5160 break;
5161 }
5162 } while (0);
5163 LOCK_GIVE(hdw->big_lock);
5164 return ret;
5165}
5166
5167
e61b6fc5 5168/* Find I2C address of eeprom */
07e337ee 5169static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 5170{
5171 int result;
5172 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 5173 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 5174 result = pvr2_send_request(hdw,
5175 hdw->cmd_buffer,1,
5176 hdw->cmd_buffer,1);
5177 if (result < 0) break;
5178 result = hdw->cmd_buffer[0];
5179 } while(0); LOCK_GIVE(hdw->ctl_lock);
5180 return result;
5181}
5182
5183
32ffa9ae 5184int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
aecde8b5
HV		 5185 struct v4l2_dbg_match *match, u64 reg_id,
5186 int setFl, u64 *val_ptr)
32ffa9ae
MI		 5187{
5188#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 5189 struct v4l2_dbg_register req;
6d98816f
MI		 5190 int stat = 0;
5191 int okFl = 0;
32ffa9ae 5192
201f5c9c
MI		 5193 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5194
aecde8b5 5195 req.match = *match;
32ffa9ae
MI		 5196 req.reg = reg_id;
5197 if (setFl) req.val = *val_ptr;
d8f5b9ba
MI		 5198 /* It would be nice to know if a sub-device answered the request */
5199 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5200 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 5201 if (okFl) {
5202 return stat;
5203 }
32ffa9ae
MI		 5204 return -EINVAL;
5205#else
5206 return -ENOSYS;
5207#endif
5208}
5209
5210
d855497e
MI		 5211/*
5212 Stuff for Emacs to see, in order to encourage consistent editing style:
5213 *** Local Variables: ***
5214 *** mode: c ***
5215 *** fill-column: 75 ***
5216 *** tab-width: 8 ***
5217 *** c-basic-offset: 8 ***
5218 *** End: ***
5219 */
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