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V4L/DVB: pvrusb2: Enforce a 300msec stabilization interval during stream strart
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
d855497e
MI		 3 *
4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21#include <linux/errno.h>
22#include <linux/string.h>
23#include <linux/slab.h>
24#include <linux/firmware.h>
d855497e 25#include <linux/videodev2.h>
32ffa9ae 26#include <media/v4l2-common.h>
75212a02 27#include <media/tuner.h>
d855497e
MI		 28#include "pvrusb2.h"
29#include "pvrusb2-std.h"
30#include "pvrusb2-util.h"
31#include "pvrusb2-hdw.h"
32#include "pvrusb2-i2c-core.h"
d855497e
MI		 33#include "pvrusb2-eeprom.h"
34#include "pvrusb2-hdw-internal.h"
35#include "pvrusb2-encoder.h"
36#include "pvrusb2-debug.h"
8d364363 37#include "pvrusb2-fx2-cmd.h"
5f6dae80 38#include "pvrusb2-wm8775.h"
6f956512 39#include "pvrusb2-video-v4l.h"
634ba268 40#include "pvrusb2-cx2584x-v4l.h"
2a6b627f 41#include "pvrusb2-cs53l32a.h"
76891d65 42#include "pvrusb2-audio.h"
d855497e 43
1bde0289
MI		 44#define TV_MIN_FREQ 55250000L
45#define TV_MAX_FREQ 850000000L
25d8527a 46
83ce57aa
MI		 47/* This defines a minimum interval that the decoder must remain quiet
48 before we are allowed to start it running. */
49#define TIME_MSEC_DECODER_WAIT 50
50
6e931375
MI		 51/* This defines a minimum interval that the decoder must be allowed to run
52 before we can safely begin using its streaming output. */
53#define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
54
83ce57aa 55/* This defines a minimum interval that the encoder must remain quiet
fa98e594
MI		 56 before we are allowed to configure it. I had this originally set to
57 50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
58 things work better when it's set to 100msec. */
59#define TIME_MSEC_ENCODER_WAIT 100
83ce57aa
MI		 60
61/* This defines the minimum interval that the encoder must successfully run
62 before we consider that the encoder has run at least once since its
63 firmware has been loaded. This measurement is in important for cases
64 where we can't do something until we know that the encoder has been run
65 at least once. */
66#define TIME_MSEC_ENCODER_OK 250
67
a0fd1cb1 68static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 69static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e 70
ff699e6b 71static int ctlchg;
ff699e6b 72static int procreload;
d855497e
MI		 73static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
74static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
75static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
ff699e6b 76static int init_pause_msec;
d855497e
MI		 77
78module_param(ctlchg, int, S_IRUGO|S_IWUSR);
79MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
80module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
81MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
d855497e
MI		 82module_param(procreload, int, S_IRUGO|S_IWUSR);
83MODULE_PARM_DESC(procreload,
84 "Attempt init failure recovery with firmware reload");
85module_param_array(tuner, int, NULL, 0444);
86MODULE_PARM_DESC(tuner,"specify installed tuner type");
87module_param_array(video_std, int, NULL, 0444);
88MODULE_PARM_DESC(video_std,"specify initial video standard");
89module_param_array(tolerance, int, NULL, 0444);
90MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
91
6f441ed7
MI		 92/* US Broadcast channel 3 (61.25 MHz), to help with testing */
93static int default_tv_freq = 61250000L;
5a4f5da6
MK		 94/* 104.3 MHz, a usable FM station for my area */
95static int default_radio_freq = 104300000L;
96
97module_param_named(tv_freq, default_tv_freq, int, 0444);
98MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
99module_param_named(radio_freq, default_radio_freq, int, 0444);
100MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
101
d855497e
MI		 102#define PVR2_CTL_WRITE_ENDPOINT 0x01
103#define PVR2_CTL_READ_ENDPOINT 0x81
104
105#define PVR2_GPIO_IN 0x9008
106#define PVR2_GPIO_OUT 0x900c
107#define PVR2_GPIO_DIR 0x9020
108
109#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
110
111#define PVR2_FIRMWARE_ENDPOINT 0x02
112
113/* size of a firmware chunk */
114#define FIRMWARE_CHUNK_SIZE 0x2000
115
edb9dcb8
MI		 116typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
117 struct v4l2_subdev *);
118
119static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
4ecbc28d 120 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
6f956512 121 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
76891d65 122 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
634ba268 123 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
2a6b627f 124 [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
edb9dcb8
MI		 125};
126
e9c64a78
MI		 127static const char *module_names[] = {
128 [PVR2_CLIENT_ID_MSP3400] = "msp3400",
129 [PVR2_CLIENT_ID_CX25840] = "cx25840",
130 [PVR2_CLIENT_ID_SAA7115] = "saa7115",
131 [PVR2_CLIENT_ID_TUNER] = "tuner",
bb65242a 132 [PVR2_CLIENT_ID_DEMOD] = "tuner",
851981a1 133 [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
5f6dae80 134 [PVR2_CLIENT_ID_WM8775] = "wm8775",
e9c64a78
MI		 135};
136
137
138static const unsigned char *module_i2c_addresses[] = {
139 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
bb65242a 140 [PVR2_CLIENT_ID_DEMOD] = "\x43",
1dfe6c77
MI		 141 [PVR2_CLIENT_ID_MSP3400] = "\x40",
142 [PVR2_CLIENT_ID_SAA7115] = "\x21",
ae111f76 143 [PVR2_CLIENT_ID_WM8775] = "\x1b",
0b467014 144 [PVR2_CLIENT_ID_CX25840] = "\x44",
23334a22 145 [PVR2_CLIENT_ID_CS53L32A] = "\x11",
e9c64a78
MI		 146};
147
148
27eab384
MI		 149static const char *ir_scheme_names[] = {
150 [PVR2_IR_SCHEME_NONE] = "none",
151 [PVR2_IR_SCHEME_29XXX] = "29xxx",
152 [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
153 [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
154 [PVR2_IR_SCHEME_ZILOG] = "Zilog",
155};
156
157
b30d2441
MI		 158/* Define the list of additional controls we'll dynamically construct based
159 on query of the cx2341x module. */
160struct pvr2_mpeg_ids {
161 const char *strid;
162 int id;
163};
164static const struct pvr2_mpeg_ids mpeg_ids[] = {
165 {
166 .strid = "audio_layer",
167 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
168 },{
169 .strid = "audio_bitrate",
170 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
171 },{
172 /* Already using audio_mode elsewhere :-( */
173 .strid = "mpeg_audio_mode",
174 .id = V4L2_CID_MPEG_AUDIO_MODE,
175 },{
176 .strid = "mpeg_audio_mode_extension",
177 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
178 },{
179 .strid = "audio_emphasis",
180 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
181 },{
182 .strid = "audio_crc",
183 .id = V4L2_CID_MPEG_AUDIO_CRC,
184 },{
185 .strid = "video_aspect",
186 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
187 },{
188 .strid = "video_b_frames",
189 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
190 },{
191 .strid = "video_gop_size",
192 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
193 },{
194 .strid = "video_gop_closure",
195 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 196 },{
197 .strid = "video_bitrate_mode",
198 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
199 },{
200 .strid = "video_bitrate",
201 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
202 },{
203 .strid = "video_bitrate_peak",
204 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
205 },{
206 .strid = "video_temporal_decimation",
207 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
208 },{
209 .strid = "stream_type",
210 .id = V4L2_CID_MPEG_STREAM_TYPE,
211 },{
212 .strid = "video_spatial_filter_mode",
213 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
214 },{
215 .strid = "video_spatial_filter",
216 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
217 },{
218 .strid = "video_luma_spatial_filter_type",
219 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
220 },{
221 .strid = "video_chroma_spatial_filter_type",
222 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
223 },{
224 .strid = "video_temporal_filter_mode",
225 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
226 },{
227 .strid = "video_temporal_filter",
228 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
229 },{
230 .strid = "video_median_filter_type",
231 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
232 },{
233 .strid = "video_luma_median_filter_top",
234 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
235 },{
236 .strid = "video_luma_median_filter_bottom",
237 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
238 },{
239 .strid = "video_chroma_median_filter_top",
240 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
241 },{
242 .strid = "video_chroma_median_filter_bottom",
243 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
244 }
245};
eca8ebfc 246#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 247
434449f4 248
d855497e 249static const char *control_values_srate[] = {
434449f4
MI		 250 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
251 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
252 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 253};
254
255
d855497e 256
d855497e
MI		 257static const char *control_values_input[] = {
258 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
29bf5b1d 259 [PVR2_CVAL_INPUT_DTV] = "dtv",
d855497e
MI		 260 [PVR2_CVAL_INPUT_RADIO] = "radio",
261 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
262 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
263};
264
265
266static const char *control_values_audiomode[] = {
267 [V4L2_TUNER_MODE_MONO] = "Mono",
268 [V4L2_TUNER_MODE_STEREO] = "Stereo",
269 [V4L2_TUNER_MODE_LANG1] = "Lang1",
270 [V4L2_TUNER_MODE_LANG2] = "Lang2",
271 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
272};
273
274
275static const char *control_values_hsm[] = {
276 [PVR2_CVAL_HSM_FAIL] = "Fail",
277 [PVR2_CVAL_HSM_HIGH] = "High",
278 [PVR2_CVAL_HSM_FULL] = "Full",
279};
280
281
681c7399
MI		 282static const char *pvr2_state_names[] = {
283 [PVR2_STATE_NONE] = "none",
284 [PVR2_STATE_DEAD] = "dead",
285 [PVR2_STATE_COLD] = "cold",
286 [PVR2_STATE_WARM] = "warm",
287 [PVR2_STATE_ERROR] = "error",
288 [PVR2_STATE_READY] = "ready",
289 [PVR2_STATE_RUN] = "run",
d855497e
MI		 290};
291
681c7399 292
694dca2b 293struct pvr2_fx2cmd_descdef {
1c9d10d4
MI		 294 unsigned char id;
295 unsigned char *desc;
296};
297
694dca2b 298static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
1c9d10d4
MI		 299 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
300 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
31335b13 301 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
1c9d10d4
MI		 302 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
303 {FX2CMD_REG_WRITE, "write encoder register"},
304 {FX2CMD_REG_READ, "read encoder register"},
305 {FX2CMD_MEMSEL, "encoder memsel"},
306 {FX2CMD_I2C_WRITE, "i2c write"},
307 {FX2CMD_I2C_READ, "i2c read"},
308 {FX2CMD_GET_USB_SPEED, "get USB speed"},
309 {FX2CMD_STREAMING_ON, "stream on"},
310 {FX2CMD_STREAMING_OFF, "stream off"},
311 {FX2CMD_FWPOST1, "fwpost1"},
312 {FX2CMD_POWER_OFF, "power off"},
313 {FX2CMD_POWER_ON, "power on"},
314 {FX2CMD_DEEP_RESET, "deep reset"},
315 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
316 {FX2CMD_GET_IR_CODE, "get IR code"},
317 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
318 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
319 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
320 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
321 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
322 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
323 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
324};
325
326
1cb03b76 327static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
681c7399
MI		 328static void pvr2_hdw_state_sched(struct pvr2_hdw *);
329static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 330static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399 331static void pvr2_hdw_worker_poll(struct work_struct *work);
681c7399
MI		 332static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
333static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
334static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 335static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 336static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 337static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 338static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
339static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
681c7399 340static void pvr2_hdw_quiescent_timeout(unsigned long);
6e931375 341static void pvr2_hdw_decoder_stabilization_timeout(unsigned long);
681c7399 342static void pvr2_hdw_encoder_wait_timeout(unsigned long);
d913d630 343static void pvr2_hdw_encoder_run_timeout(unsigned long);
1c9d10d4 344static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
07e337ee
AB		 345static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
346 unsigned int timeout,int probe_fl,
347 void *write_data,unsigned int write_len,
348 void *read_data,unsigned int read_len);
432907f7 349static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
d855497e 350
681c7399
MI		 351
352static void trace_stbit(const char *name,int val)
353{
354 pvr2_trace(PVR2_TRACE_STBITS,
355 "State bit %s <-- %s",
356 name,(val ? "true" : "false"));
357}
358
d855497e
MI		 359static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
360{
361 struct pvr2_hdw *hdw = cptr->hdw;
362 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
363 *vp = hdw->freqTable[hdw->freqProgSlot-1];
364 } else {
365 *vp = 0;
366 }
367 return 0;
368}
369
370static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
371{
372 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 373 unsigned int slotId = hdw->freqProgSlot;
374 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
375 hdw->freqTable[slotId-1] = v;
376 /* Handle side effects correctly - if we're tuned to this
377 slot, then forgot the slot id relation since the stored
378 frequency has been changed. */
379 if (hdw->freqSelector) {
380 if (hdw->freqSlotRadio == slotId) {
381 hdw->freqSlotRadio = 0;
382 }
383 } else {
384 if (hdw->freqSlotTelevision == slotId) {
385 hdw->freqSlotTelevision = 0;
386 }
387 }
d855497e
MI		 388 }
389 return 0;
390}
391
392static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
393{
394 *vp = cptr->hdw->freqProgSlot;
395 return 0;
396}
397
398static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
399{
400 struct pvr2_hdw *hdw = cptr->hdw;
401 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
402 hdw->freqProgSlot = v;
403 }
404 return 0;
405}
406
407static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
408{
1bde0289
MI		 409 struct pvr2_hdw *hdw = cptr->hdw;
410 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 411 return 0;
412}
413
1bde0289 414static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 415{
416 unsigned freq = 0;
417 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 418 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
419 if (slotId > 0) {
420 freq = hdw->freqTable[slotId-1];
421 if (!freq) return 0;
422 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 423 }
1bde0289
MI		 424 if (hdw->freqSelector) {
425 hdw->freqSlotRadio = slotId;
426 } else {
427 hdw->freqSlotTelevision = slotId;
d855497e
MI		 428 }
429 return 0;
430}
431
432static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
433{
1bde0289 434 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 435 return 0;
436}
437
438static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
439{
440 return cptr->hdw->freqDirty != 0;
441}
442
443static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
444{
445 cptr->hdw->freqDirty = 0;
446}
447
448static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
449{
1bde0289 450 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 451 return 0;
452}
453
e784bfb9 454static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
455{
432907f7
MI		 456 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
457 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
458 if (stat != 0) {
432907f7 459 return stat;
e784bfb9 460 }
432907f7 461 *left = cap->bounds.left;
e784bfb9 462 return 0;
463}
464
465static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
466{
432907f7
MI		 467 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
468 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
469 if (stat != 0) {
432907f7
MI		 470 return stat;
471 }
472 *left = cap->bounds.left;
473 if (cap->bounds.width > cptr->hdw->cropw_val) {
432907f7 474 *left += cap->bounds.width - cptr->hdw->cropw_val;
e784bfb9 475 }
476 return 0;
477}
478
479static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
480{
432907f7
MI		 481 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
482 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
483 if (stat != 0) {
432907f7 484 return stat;
e784bfb9 485 }
432907f7 486 *top = cap->bounds.top;
e784bfb9 487 return 0;
488}
489
432907f7 490static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
3ad9fc37 491{
432907f7
MI		 492 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
493 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
494 if (stat != 0) {
432907f7
MI		 495 return stat;
496 }
497 *top = cap->bounds.top;
498 if (cap->bounds.height > cptr->hdw->croph_val) {
432907f7 499 *top += cap->bounds.height - cptr->hdw->croph_val;
3ad9fc37
MI		 500 }
501 return 0;
502}
503
432907f7
MI		 504static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
505{
506 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
507 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
508 if (stat != 0) {
432907f7
MI		 509 return stat;
510 }
511 *val = 0;
512 if (cap->bounds.width > cptr->hdw->cropl_val) {
432907f7
MI		 513 *val = cap->bounds.width - cptr->hdw->cropl_val;
514 }
515 return 0;
516}
517
518static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
519{
520 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
521 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
522 if (stat != 0) {
432907f7
MI		 523 return stat;
524 }
525 *val = 0;
526 if (cap->bounds.height > cptr->hdw->cropt_val) {
432907f7
MI		 527 *val = cap->bounds.height - cptr->hdw->cropt_val;
528 }
529 return 0;
530}
531
532static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
533{
534 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
535 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
536 if (stat != 0) {
432907f7
MI		 537 return stat;
538 }
539 *val = cap->bounds.left;
540 return 0;
541}
542
543static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
544{
545 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
546 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
547 if (stat != 0) {
432907f7
MI		 548 return stat;
549 }
550 *val = cap->bounds.top;
551 return 0;
552}
553
554static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
555{
556 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
557 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
558 if (stat != 0) {
432907f7
MI		 559 return stat;
560 }
561 *val = cap->bounds.width;
562 return 0;
563}
564
565static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
566{
567 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
568 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
569 if (stat != 0) {
432907f7
MI		 570 return stat;
571 }
572 *val = cap->bounds.height;
573 return 0;
574}
575
576static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
577{
578 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
579 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
580 if (stat != 0) {
432907f7
MI		 581 return stat;
582 }
583 *val = cap->defrect.left;
584 return 0;
585}
586
587static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
588{
589 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
590 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
591 if (stat != 0) {
432907f7
MI		 592 return stat;
593 }
594 *val = cap->defrect.top;
595 return 0;
596}
597
598static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
599{
600 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
601 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
602 if (stat != 0) {
432907f7
MI		 603 return stat;
604 }
605 *val = cap->defrect.width;
606 return 0;
607}
608
609static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
610{
611 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
612 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
613 if (stat != 0) {
432907f7
MI		 614 return stat;
615 }
616 *val = cap->defrect.height;
617 return 0;
618}
619
620static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
621{
622 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
623 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
624 if (stat != 0) {
432907f7
MI		 625 return stat;
626 }
627 *val = cap->pixelaspect.numerator;
628 return 0;
629}
630
631static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
632{
633 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
634 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
635 if (stat != 0) {
432907f7
MI		 636 return stat;
637 }
638 *val = cap->pixelaspect.denominator;
639 return 0;
640}
641
642static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
e784bfb9 643{
432907f7
MI		 644 /* Actual maximum depends on the video standard in effect. */
645 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
646 *vp = 480;
e784bfb9 647 } else {
432907f7 648 *vp = 576;
e784bfb9 649 }
650 return 0;
651}
652
3ad9fc37
MI		 653static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
654{
989eb154
MI		 655 /* Actual minimum depends on device digitizer type. */
656 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 657 *vp = 75;
658 } else {
659 *vp = 17;
660 }
661 return 0;
662}
663
1bde0289 664static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 665{
1bde0289
MI		 666 *vp = cptr->hdw->input_val;
667 return 0;
668}
669
29bf5b1d
MI		 670static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
671{
1cb03b76 672 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
29bf5b1d
MI		 673}
674
1bde0289
MI		 675static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
676{
1cb03b76 677 return pvr2_hdw_set_input(cptr->hdw,v);
1bde0289
MI		 678}
679
680static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
681{
682 return cptr->hdw->input_dirty != 0;
683}
684
685static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
686{
687 cptr->hdw->input_dirty = 0;
688}
689
5549f54f 690
25d8527a
PK		 691static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
692{
644afdb9
MI		 693 unsigned long fv;
694 struct pvr2_hdw *hdw = cptr->hdw;
695 if (hdw->tuner_signal_stale) {
a51f5000 696 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 697 }
698 fv = hdw->tuner_signal_info.rangehigh;
699 if (!fv) {
700 /* Safety fallback */
25d8527a 701 *vp = TV_MAX_FREQ;
644afdb9 702 return 0;
25d8527a 703 }
644afdb9
MI		 704 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
705 fv = (fv * 125) / 2;
706 } else {
707 fv = fv * 62500;
708 }
709 *vp = fv;
25d8527a
PK		 710 return 0;
711}
712
713static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
714{
644afdb9
MI		 715 unsigned long fv;
716 struct pvr2_hdw *hdw = cptr->hdw;
717 if (hdw->tuner_signal_stale) {
a51f5000 718 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 719 }
720 fv = hdw->tuner_signal_info.rangelow;
721 if (!fv) {
722 /* Safety fallback */
25d8527a 723 *vp = TV_MIN_FREQ;
644afdb9
MI		 724 return 0;
725 }
726 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
727 fv = (fv * 125) / 2;
728 } else {
729 fv = fv * 62500;
25d8527a 730 }
644afdb9 731 *vp = fv;
25d8527a
PK		 732 return 0;
733}
734
b30d2441
MI		 735static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
736{
737 return cptr->hdw->enc_stale != 0;
738}
739
740static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
741{
742 cptr->hdw->enc_stale = 0;
681c7399 743 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 744}
745
746static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
747{
748 int ret;
749 struct v4l2_ext_controls cs;
750 struct v4l2_ext_control c1;
751 memset(&cs,0,sizeof(cs));
752 memset(&c1,0,sizeof(c1));
753 cs.controls = &c1;
754 cs.count = 1;
755 c1.id = cptr->info->v4l_id;
01f1e44f 756 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 757 VIDIOC_G_EXT_CTRLS);
758 if (ret) return ret;
759 *vp = c1.value;
760 return 0;
761}
762
763static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
764{
765 int ret;
681c7399 766 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 767 struct v4l2_ext_controls cs;
768 struct v4l2_ext_control c1;
769 memset(&cs,0,sizeof(cs));
770 memset(&c1,0,sizeof(c1));
771 cs.controls = &c1;
772 cs.count = 1;
773 c1.id = cptr->info->v4l_id;
774 c1.value = v;
681c7399
MI		 775 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
776 hdw->state_encoder_run, &cs,
b30d2441 777 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 778 if (ret == -EBUSY) {
779 /* Oops. cx2341x is telling us it's not safe to change
780 this control while we're capturing. Make a note of this
781 fact so that the pipeline will be stopped the next time
782 controls are committed. Then go on ahead and store this
783 change anyway. */
784 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
785 0, &cs,
786 VIDIOC_S_EXT_CTRLS);
787 if (!ret) hdw->enc_unsafe_stale = !0;
788 }
b30d2441 789 if (ret) return ret;
681c7399 790 hdw->enc_stale = !0;
b30d2441
MI		 791 return 0;
792}
793
794static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
795{
796 struct v4l2_queryctrl qctrl;
797 struct pvr2_ctl_info *info;
798 qctrl.id = cptr->info->v4l_id;
799 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
800 /* Strip out the const so we can adjust a function pointer. It's
801 OK to do this here because we know this is a dynamically created
802 control, so the underlying storage for the info pointer is (a)
803 private to us, and (b) not in read-only storage. Either we do
804 this or we significantly complicate the underlying control
805 implementation. */
806 info = (struct pvr2_ctl_info *)(cptr->info);
807 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
808 if (info->set_value) {
a0fd1cb1 809 info->set_value = NULL;
b30d2441
MI		 810 }
811 } else {
812 if (!(info->set_value)) {
813 info->set_value = ctrl_cx2341x_set;
814 }
815 }
816 return qctrl.flags;
817}
818
d855497e
MI		 819static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
820{
681c7399
MI		 821 *vp = cptr->hdw->state_pipeline_req;
822 return 0;
823}
824
825static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
826{
827 *vp = cptr->hdw->master_state;
d855497e
MI		 828 return 0;
829}
830
831static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
832{
833 int result = pvr2_hdw_is_hsm(cptr->hdw);
834 *vp = PVR2_CVAL_HSM_FULL;
835 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
836 if (result) *vp = PVR2_CVAL_HSM_HIGH;
837 return 0;
838}
839
840static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
841{
842 *vp = cptr->hdw->std_mask_avail;
843 return 0;
844}
845
846static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
847{
848 struct pvr2_hdw *hdw = cptr->hdw;
849 v4l2_std_id ns;
850 ns = hdw->std_mask_avail;
851 ns = (ns & ~m) | (v & m);
852 if (ns == hdw->std_mask_avail) return 0;
853 hdw->std_mask_avail = ns;
854 pvr2_hdw_internal_set_std_avail(hdw);
855 pvr2_hdw_internal_find_stdenum(hdw);
856 return 0;
857}
858
859static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
860 char *bufPtr,unsigned int bufSize,
861 unsigned int *len)
862{
863 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
864 return 0;
865}
866
867static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
868 const char *bufPtr,unsigned int bufSize,
869 int *mskp,int *valp)
870{
871 int ret;
872 v4l2_std_id id;
873 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
874 if (ret < 0) return ret;
875 if (mskp) *mskp = id;
876 if (valp) *valp = id;
877 return 0;
878}
879
880static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
881{
882 *vp = cptr->hdw->std_mask_cur;
883 return 0;
884}
885
886static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
887{
888 struct pvr2_hdw *hdw = cptr->hdw;
889 v4l2_std_id ns;
890 ns = hdw->std_mask_cur;
891 ns = (ns & ~m) | (v & m);
892 if (ns == hdw->std_mask_cur) return 0;
893 hdw->std_mask_cur = ns;
894 hdw->std_dirty = !0;
895 pvr2_hdw_internal_find_stdenum(hdw);
896 return 0;
897}
898
899static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
900{
901 return cptr->hdw->std_dirty != 0;
902}
903
904static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
905{
906 cptr->hdw->std_dirty = 0;
907}
908
909static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
910{
18103c57 911 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 912 pvr2_hdw_status_poll(hdw);
18103c57
MI		 913 *vp = hdw->tuner_signal_info.signal;
914 return 0;
915}
916
917static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
918{
919 int val = 0;
920 unsigned int subchan;
921 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 922 pvr2_hdw_status_poll(hdw);
18103c57
MI		 923 subchan = hdw->tuner_signal_info.rxsubchans;
924 if (subchan & V4L2_TUNER_SUB_MONO) {
925 val |= (1 << V4L2_TUNER_MODE_MONO);
926 }
927 if (subchan & V4L2_TUNER_SUB_STEREO) {
928 val |= (1 << V4L2_TUNER_MODE_STEREO);
929 }
930 if (subchan & V4L2_TUNER_SUB_LANG1) {
931 val |= (1 << V4L2_TUNER_MODE_LANG1);
932 }
933 if (subchan & V4L2_TUNER_SUB_LANG2) {
934 val |= (1 << V4L2_TUNER_MODE_LANG2);
935 }
936 *vp = val;
d855497e
MI		 937 return 0;
938}
939
d855497e
MI		 940
941static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
942{
943 struct pvr2_hdw *hdw = cptr->hdw;
944 if (v < 0) return -EINVAL;
945 if (v > hdw->std_enum_cnt) return -EINVAL;
946 hdw->std_enum_cur = v;
947 if (!v) return 0;
948 v--;
949 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
950 hdw->std_mask_cur = hdw->std_defs[v].id;
951 hdw->std_dirty = !0;
952 return 0;
953}
954
955
956static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
957{
958 *vp = cptr->hdw->std_enum_cur;
959 return 0;
960}
961
962
963static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
964{
965 return cptr->hdw->std_dirty != 0;
966}
967
968
969static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
970{
971 cptr->hdw->std_dirty = 0;
972}
973
974
975#define DEFINT(vmin,vmax) \
976 .type = pvr2_ctl_int, \
977 .def.type_int.min_value = vmin, \
978 .def.type_int.max_value = vmax
979
980#define DEFENUM(tab) \
981 .type = pvr2_ctl_enum, \
27c7b710 982 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 983 .def.type_enum.value_names = tab
984
33213963
MI		 985#define DEFBOOL \
986 .type = pvr2_ctl_bool
987
d855497e
MI		 988#define DEFMASK(msk,tab) \
989 .type = pvr2_ctl_bitmask, \
990 .def.type_bitmask.valid_bits = msk, \
991 .def.type_bitmask.bit_names = tab
992
993#define DEFREF(vname) \
994 .set_value = ctrl_set_##vname, \
995 .get_value = ctrl_get_##vname, \
996 .is_dirty = ctrl_isdirty_##vname, \
997 .clear_dirty = ctrl_cleardirty_##vname
998
999
1000#define VCREATE_FUNCS(vname) \
1001static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
1002{*vp = cptr->hdw->vname##_val; return 0;} \
1003static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
1004{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
1005static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
1006{return cptr->hdw->vname##_dirty != 0;} \
1007static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
1008{cptr->hdw->vname##_dirty = 0;}
1009
1010VCREATE_FUNCS(brightness)
1011VCREATE_FUNCS(contrast)
1012VCREATE_FUNCS(saturation)
1013VCREATE_FUNCS(hue)
1014VCREATE_FUNCS(volume)
1015VCREATE_FUNCS(balance)
1016VCREATE_FUNCS(bass)
1017VCREATE_FUNCS(treble)
1018VCREATE_FUNCS(mute)
e784bfb9 1019VCREATE_FUNCS(cropl)
1020VCREATE_FUNCS(cropt)
1021VCREATE_FUNCS(cropw)
1022VCREATE_FUNCS(croph)
c05c0462
MI		 1023VCREATE_FUNCS(audiomode)
1024VCREATE_FUNCS(res_hor)
1025VCREATE_FUNCS(res_ver)
d855497e 1026VCREATE_FUNCS(srate)
d855497e 1027
d855497e
MI		 1028/* Table definition of all controls which can be manipulated */
1029static const struct pvr2_ctl_info control_defs[] = {
1030 {
1031 .v4l_id = V4L2_CID_BRIGHTNESS,
1032 .desc = "Brightness",
1033 .name = "brightness",
1034 .default_value = 128,
1035 DEFREF(brightness),
1036 DEFINT(0,255),
1037 },{
1038 .v4l_id = V4L2_CID_CONTRAST,
1039 .desc = "Contrast",
1040 .name = "contrast",
1041 .default_value = 68,
1042 DEFREF(contrast),
1043 DEFINT(0,127),
1044 },{
1045 .v4l_id = V4L2_CID_SATURATION,
1046 .desc = "Saturation",
1047 .name = "saturation",
1048 .default_value = 64,
1049 DEFREF(saturation),
1050 DEFINT(0,127),
1051 },{
1052 .v4l_id = V4L2_CID_HUE,
1053 .desc = "Hue",
1054 .name = "hue",
1055 .default_value = 0,
1056 DEFREF(hue),
1057 DEFINT(-128,127),
1058 },{
1059 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1060 .desc = "Volume",
1061 .name = "volume",
139eecf9 1062 .default_value = 62000,
d855497e
MI		 1063 DEFREF(volume),
1064 DEFINT(0,65535),
1065 },{
1066 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1067 .desc = "Balance",
1068 .name = "balance",
1069 .default_value = 0,
1070 DEFREF(balance),
1071 DEFINT(-32768,32767),
1072 },{
1073 .v4l_id = V4L2_CID_AUDIO_BASS,
1074 .desc = "Bass",
1075 .name = "bass",
1076 .default_value = 0,
1077 DEFREF(bass),
1078 DEFINT(-32768,32767),
1079 },{
1080 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1081 .desc = "Treble",
1082 .name = "treble",
1083 .default_value = 0,
1084 DEFREF(treble),
1085 DEFINT(-32768,32767),
1086 },{
1087 .v4l_id = V4L2_CID_AUDIO_MUTE,
1088 .desc = "Mute",
1089 .name = "mute",
1090 .default_value = 0,
1091 DEFREF(mute),
33213963 1092 DEFBOOL,
e784bfb9 1093 }, {
432907f7 1094 .desc = "Capture crop left margin",
e784bfb9 1095 .name = "crop_left",
1096 .internal_id = PVR2_CID_CROPL,
1097 .default_value = 0,
1098 DEFREF(cropl),
1099 DEFINT(-129, 340),
1100 .get_min_value = ctrl_cropl_min_get,
1101 .get_max_value = ctrl_cropl_max_get,
432907f7 1102 .get_def_value = ctrl_get_cropcapdl,
e784bfb9 1103 }, {
432907f7 1104 .desc = "Capture crop top margin",
e784bfb9 1105 .name = "crop_top",
1106 .internal_id = PVR2_CID_CROPT,
1107 .default_value = 0,
1108 DEFREF(cropt),
1109 DEFINT(-35, 544),
1110 .get_min_value = ctrl_cropt_min_get,
1111 .get_max_value = ctrl_cropt_max_get,
432907f7 1112 .get_def_value = ctrl_get_cropcapdt,
e784bfb9 1113 }, {
432907f7 1114 .desc = "Capture crop width",
e784bfb9 1115 .name = "crop_width",
1116 .internal_id = PVR2_CID_CROPW,
1117 .default_value = 720,
1118 DEFREF(cropw),
432907f7
MI		 1119 .get_max_value = ctrl_cropw_max_get,
1120 .get_def_value = ctrl_get_cropcapdw,
e784bfb9 1121 }, {
432907f7 1122 .desc = "Capture crop height",
e784bfb9 1123 .name = "crop_height",
1124 .internal_id = PVR2_CID_CROPH,
1125 .default_value = 480,
1126 DEFREF(croph),
432907f7
MI		 1127 .get_max_value = ctrl_croph_max_get,
1128 .get_def_value = ctrl_get_cropcapdh,
1129 }, {
1130 .desc = "Capture capability pixel aspect numerator",
1131 .name = "cropcap_pixel_numerator",
1132 .internal_id = PVR2_CID_CROPCAPPAN,
1133 .get_value = ctrl_get_cropcappan,
1134 }, {
1135 .desc = "Capture capability pixel aspect denominator",
1136 .name = "cropcap_pixel_denominator",
1137 .internal_id = PVR2_CID_CROPCAPPAD,
1138 .get_value = ctrl_get_cropcappad,
1139 }, {
1140 .desc = "Capture capability bounds top",
1141 .name = "cropcap_bounds_top",
1142 .internal_id = PVR2_CID_CROPCAPBT,
1143 .get_value = ctrl_get_cropcapbt,
1144 }, {
1145 .desc = "Capture capability bounds left",
1146 .name = "cropcap_bounds_left",
1147 .internal_id = PVR2_CID_CROPCAPBL,
1148 .get_value = ctrl_get_cropcapbl,
1149 }, {
1150 .desc = "Capture capability bounds width",
1151 .name = "cropcap_bounds_width",
1152 .internal_id = PVR2_CID_CROPCAPBW,
1153 .get_value = ctrl_get_cropcapbw,
1154 }, {
1155 .desc = "Capture capability bounds height",
1156 .name = "cropcap_bounds_height",
1157 .internal_id = PVR2_CID_CROPCAPBH,
1158 .get_value = ctrl_get_cropcapbh,
c05c0462
MI		 1159 },{
1160 .desc = "Video Source",
1161 .name = "input",
1162 .internal_id = PVR2_CID_INPUT,
1163 .default_value = PVR2_CVAL_INPUT_TV,
29bf5b1d 1164 .check_value = ctrl_check_input,
c05c0462
MI		 1165 DEFREF(input),
1166 DEFENUM(control_values_input),
1167 },{
1168 .desc = "Audio Mode",
1169 .name = "audio_mode",
1170 .internal_id = PVR2_CID_AUDIOMODE,
1171 .default_value = V4L2_TUNER_MODE_STEREO,
1172 DEFREF(audiomode),
1173 DEFENUM(control_values_audiomode),
1174 },{
1175 .desc = "Horizontal capture resolution",
1176 .name = "resolution_hor",
1177 .internal_id = PVR2_CID_HRES,
1178 .default_value = 720,
1179 DEFREF(res_hor),
3ad9fc37 1180 DEFINT(19,720),
c05c0462
MI		 1181 },{
1182 .desc = "Vertical capture resolution",
1183 .name = "resolution_ver",
1184 .internal_id = PVR2_CID_VRES,
1185 .default_value = 480,
1186 DEFREF(res_ver),
3ad9fc37
MI		 1187 DEFINT(17,576),
1188 /* Hook in check for video standard and adjust maximum
1189 depending on the standard. */
1190 .get_max_value = ctrl_vres_max_get,
1191 .get_min_value = ctrl_vres_min_get,
d855497e 1192 },{
b30d2441 1193 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 1194 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1195 .desc = "Audio Sampling Frequency",
d855497e 1196 .name = "srate",
d855497e
MI		 1197 DEFREF(srate),
1198 DEFENUM(control_values_srate),
d855497e
MI		 1199 },{
1200 .desc = "Tuner Frequency (Hz)",
1201 .name = "frequency",
1202 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 1203 .default_value = 0,
d855497e
MI		 1204 .set_value = ctrl_freq_set,
1205 .get_value = ctrl_freq_get,
1206 .is_dirty = ctrl_freq_is_dirty,
1207 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 1208 DEFINT(0,0),
25d8527a
PK		 1209 /* Hook in check for input value (tv/radio) and adjust
1210 max/min values accordingly */
1211 .get_max_value = ctrl_freq_max_get,
1212 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1213 },{
1214 .desc = "Channel",
1215 .name = "channel",
1216 .set_value = ctrl_channel_set,
1217 .get_value = ctrl_channel_get,
1218 DEFINT(0,FREQTABLE_SIZE),
1219 },{
1220 .desc = "Channel Program Frequency",
1221 .name = "freq_table_value",
1222 .set_value = ctrl_channelfreq_set,
1223 .get_value = ctrl_channelfreq_get,
644afdb9 1224 DEFINT(0,0),
1bde0289
MI		 1225 /* Hook in check for input value (tv/radio) and adjust
1226 max/min values accordingly */
1bde0289
MI		 1227 .get_max_value = ctrl_freq_max_get,
1228 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1229 },{
1230 .desc = "Channel Program ID",
1231 .name = "freq_table_channel",
1232 .set_value = ctrl_channelprog_set,
1233 .get_value = ctrl_channelprog_get,
1234 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 1235 },{
1236 .desc = "Streaming Enabled",
1237 .name = "streaming_enabled",
1238 .get_value = ctrl_streamingenabled_get,
33213963 1239 DEFBOOL,
d855497e
MI		 1240 },{
1241 .desc = "USB Speed",
1242 .name = "usb_speed",
1243 .get_value = ctrl_hsm_get,
1244 DEFENUM(control_values_hsm),
681c7399
MI		 1245 },{
1246 .desc = "Master State",
1247 .name = "master_state",
1248 .get_value = ctrl_masterstate_get,
1249 DEFENUM(pvr2_state_names),
d855497e
MI		 1250 },{
1251 .desc = "Signal Present",
1252 .name = "signal_present",
1253 .get_value = ctrl_signal_get,
18103c57
MI		 1254 DEFINT(0,65535),
1255 },{
1256 .desc = "Audio Modes Present",
1257 .name = "audio_modes_present",
1258 .get_value = ctrl_audio_modes_present_get,
1259 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1260 v4l. Nothing outside of this module cares about this,
1261 but I reuse it in order to also reuse the
1262 control_values_audiomode string table. */
1263 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1264 (1 << V4L2_TUNER_MODE_STEREO)|
1265 (1 << V4L2_TUNER_MODE_LANG1)|
1266 (1 << V4L2_TUNER_MODE_LANG2)),
1267 control_values_audiomode),
d855497e
MI		 1268 },{
1269 .desc = "Video Standards Available Mask",
1270 .name = "video_standard_mask_available",
1271 .internal_id = PVR2_CID_STDAVAIL,
1272 .skip_init = !0,
1273 .get_value = ctrl_stdavail_get,
1274 .set_value = ctrl_stdavail_set,
1275 .val_to_sym = ctrl_std_val_to_sym,
1276 .sym_to_val = ctrl_std_sym_to_val,
1277 .type = pvr2_ctl_bitmask,
1278 },{
1279 .desc = "Video Standards In Use Mask",
1280 .name = "video_standard_mask_active",
1281 .internal_id = PVR2_CID_STDCUR,
1282 .skip_init = !0,
1283 .get_value = ctrl_stdcur_get,
1284 .set_value = ctrl_stdcur_set,
1285 .is_dirty = ctrl_stdcur_is_dirty,
1286 .clear_dirty = ctrl_stdcur_clear_dirty,
1287 .val_to_sym = ctrl_std_val_to_sym,
1288 .sym_to_val = ctrl_std_sym_to_val,
1289 .type = pvr2_ctl_bitmask,
d855497e
MI		 1290 },{
1291 .desc = "Video Standard Name",
1292 .name = "video_standard",
1293 .internal_id = PVR2_CID_STDENUM,
1294 .skip_init = !0,
1295 .get_value = ctrl_stdenumcur_get,
1296 .set_value = ctrl_stdenumcur_set,
1297 .is_dirty = ctrl_stdenumcur_is_dirty,
1298 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1299 .type = pvr2_ctl_enum,
1300 }
1301};
1302
eca8ebfc 1303#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 1304
1305
1306const char *pvr2_config_get_name(enum pvr2_config cfg)
1307{
1308 switch (cfg) {
1309 case pvr2_config_empty: return "empty";
1310 case pvr2_config_mpeg: return "mpeg";
1311 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 1312 case pvr2_config_pcm: return "pcm";
1313 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 1314 }
1315 return "<unknown>";
1316}
1317
1318
1319struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1320{
1321 return hdw->usb_dev;
1322}
1323
1324
1325unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1326{
1327 return hdw->serial_number;
1328}
1329
31a18547
MI		 1330
1331const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1332{
1333 return hdw->bus_info;
1334}
1335
1336
13a88797
MI		 1337const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1338{
1339 return hdw->identifier;
1340}
1341
1342
1bde0289
MI		 1343unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1344{
1345 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1346}
1347
1348/* Set the currently tuned frequency and account for all possible
1349 driver-core side effects of this action. */
f55a8712 1350static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1bde0289 1351{
7c74e57e 1352 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 1353 if (hdw->freqSelector) {
1354 /* Swing over to radio frequency selection */
1355 hdw->freqSelector = 0;
1356 hdw->freqDirty = !0;
1357 }
1bde0289
MI		 1358 if (hdw->freqValRadio != val) {
1359 hdw->freqValRadio = val;
1360 hdw->freqSlotRadio = 0;
7c74e57e 1361 hdw->freqDirty = !0;
1bde0289 1362 }
7c74e57e 1363 } else {
1bde0289
MI		 1364 if (!(hdw->freqSelector)) {
1365 /* Swing over to television frequency selection */
1366 hdw->freqSelector = 1;
1367 hdw->freqDirty = !0;
1368 }
1bde0289
MI		 1369 if (hdw->freqValTelevision != val) {
1370 hdw->freqValTelevision = val;
1371 hdw->freqSlotTelevision = 0;
7c74e57e 1372 hdw->freqDirty = !0;
1bde0289 1373 }
1bde0289
MI		 1374 }
1375}
1376
d855497e
MI		 1377int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1378{
1379 return hdw->unit_number;
1380}
1381
1382
1383/* Attempt to locate one of the given set of files. Messages are logged
1384 appropriate to what has been found. The return value will be 0 or
1385 greater on success (it will be the index of the file name found) and
1386 fw_entry will be filled in. Otherwise a negative error is returned on
1387 failure. If the return value is -ENOENT then no viable firmware file
1388 could be located. */
1389static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1390 const struct firmware **fw_entry,
1391 const char *fwtypename,
1392 unsigned int fwcount,
1393 const char *fwnames[])
1394{
1395 unsigned int idx;
1396 int ret = -EINVAL;
1397 for (idx = 0; idx < fwcount; idx++) {
1398 ret = request_firmware(fw_entry,
1399 fwnames[idx],
1400 &hdw->usb_dev->dev);
1401 if (!ret) {
1402 trace_firmware("Located %s firmware: %s;"
1403 " uploading...",
1404 fwtypename,
1405 fwnames[idx]);
1406 return idx;
1407 }
1408 if (ret == -ENOENT) continue;
1409 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1410 "request_firmware fatal error with code=%d",ret);
1411 return ret;
1412 }
1413 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1414 "***WARNING***"
1415 " Device %s firmware"
1416 " seems to be missing.",
1417 fwtypename);
1418 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1419 "Did you install the pvrusb2 firmware files"
1420 " in their proper location?");
1421 if (fwcount == 1) {
1422 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1423 "request_firmware unable to locate %s file %s",
1424 fwtypename,fwnames[0]);
1425 } else {
1426 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1427 "request_firmware unable to locate"
1428 " one of the following %s files:",
1429 fwtypename);
1430 for (idx = 0; idx < fwcount; idx++) {
1431 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1432 "request_firmware: Failed to find %s",
1433 fwnames[idx]);
1434 }
1435 }
1436 return ret;
1437}
1438
1439
1440/*
1441 * pvr2_upload_firmware1().
1442 *
1443 * Send the 8051 firmware to the device. After the upload, arrange for
1444 * device to re-enumerate.
1445 *
1446 * NOTE : the pointer to the firmware data given by request_firmware()
1447 * is not suitable for an usb transaction.
1448 *
1449 */
07e337ee 1450static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1451{
a0fd1cb1 1452 const struct firmware *fw_entry = NULL;
d855497e
MI		 1453 void *fw_ptr;
1454 unsigned int pipe;
9081d901 1455 unsigned int fwsize;
d855497e
MI		 1456 int ret;
1457 u16 address;
1d643a37 1458
989eb154 1459 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1460 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1461 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1462 "Connected device type defines"
1463 " no firmware to upload; ignoring firmware");
1464 return -ENOTTY;
1d643a37
MI		 1465 }
1466
d855497e
MI		 1467 hdw->fw1_state = FW1_STATE_FAILED; // default result
1468
1469 trace_firmware("pvr2_upload_firmware1");
1470
1471 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1472 hdw->hdw_desc->fx2_firmware.cnt,
1473 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1474 if (ret < 0) {
1475 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1476 return ret;
1477 }
1478
d855497e
MI		 1479 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1480
1481 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
9081d901 1482 fwsize = fw_entry->size;
d855497e 1483
9081d901
MI		 1484 if ((fwsize != 0x2000) &&
1485 (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
c21c2db4
MI		 1486 if (hdw->hdw_desc->flag_fx2_16kb) {
1487 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1488 "Wrong fx2 firmware size"
1489 " (expected 8192 or 16384, got %u)",
9081d901 1490 fwsize);
c21c2db4
MI		 1491 } else {
1492 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1493 "Wrong fx2 firmware size"
1494 " (expected 8192, got %u)",
9081d901 1495 fwsize);
c21c2db4 1496 }
d855497e
MI		 1497 release_firmware(fw_entry);
1498 return -ENOMEM;
1499 }
1500
1501 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1502 if (fw_ptr == NULL){
1503 release_firmware(fw_entry);
1504 return -ENOMEM;
1505 }
1506
1507 /* We have to hold the CPU during firmware upload. */
1508 pvr2_hdw_cpureset_assert(hdw,1);
1509
1510 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1511 chunk. */
1512
1513 ret = 0;
9081d901 1514 for (address = 0; address < fwsize; address += 0x800) {
d855497e
MI		 1515 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1516 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1517 0, fw_ptr, 0x800, HZ);
1518 }
1519
1520 trace_firmware("Upload done, releasing device's CPU");
1521
1522 /* Now release the CPU. It will disconnect and reconnect later. */
1523 pvr2_hdw_cpureset_assert(hdw,0);
1524
1525 kfree(fw_ptr);
1526 release_firmware(fw_entry);
1527
1528 trace_firmware("Upload done (%d bytes sent)",ret);
1529
75727460
GF		 1530 /* We should have written fwsize bytes */
1531 if (ret == fwsize) {
d855497e
MI		 1532 hdw->fw1_state = FW1_STATE_RELOAD;
1533 return 0;
1534 }
1535
1536 return -EIO;
1537}
1538
1539
1540/*
1541 * pvr2_upload_firmware2()
1542 *
1543 * This uploads encoder firmware on endpoint 2.
1544 *
1545 */
1546
1547int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1548{
a0fd1cb1 1549 const struct firmware *fw_entry = NULL;
d855497e 1550 void *fw_ptr;
90060d32 1551 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1552 int actual_length;
1553 int ret = 0;
1554 int fwidx;
1555 static const char *fw_files[] = {
1556 CX2341X_FIRM_ENC_FILENAME,
1557 };
1558
989eb154 1559 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1560 return 0;
1561 }
1562
d855497e
MI		 1563 trace_firmware("pvr2_upload_firmware2");
1564
1565 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1566 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1567 if (ret < 0) return ret;
1568 fwidx = ret;
1569 ret = 0;
b30d2441
MI		 1570 /* Since we're about to completely reinitialize the encoder,
1571 invalidate our cached copy of its configuration state. Next
1572 time we configure the encoder, then we'll fully configure it. */
1573 hdw->enc_cur_valid = 0;
d855497e 1574
d913d630
MI		 1575 /* Encoder is about to be reset so note that as far as we're
1576 concerned now, the encoder has never been run. */
1577 del_timer_sync(&hdw->encoder_run_timer);
1578 if (hdw->state_encoder_runok) {
1579 hdw->state_encoder_runok = 0;
1580 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1581 }
1582
d855497e
MI		 1583 /* First prepare firmware loading */
1584 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1585 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1586 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1587 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1588 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1589 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1590 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1591 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1592 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1593 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1594 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1595 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1596 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1597 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1598 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1599 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1c9d10d4
MI		 1600 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1601 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1602
1603 if (ret) {
1604 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1605 "firmware2 upload prep failed, ret=%d",ret);
1606 release_firmware(fw_entry);
21684ba9 1607 goto done;
d855497e
MI		 1608 }
1609
1610 /* Now send firmware */
1611
1612 fw_len = fw_entry->size;
1613
90060d32 1614 if (fw_len % sizeof(u32)) {
d855497e
MI		 1615 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1616 "size of %s firmware"
48dc30a1 1617 " must be a multiple of %zu bytes",
90060d32 1618 fw_files[fwidx],sizeof(u32));
d855497e 1619 release_firmware(fw_entry);
21684ba9
MI		 1620 ret = -EINVAL;
1621 goto done;
d855497e
MI		 1622 }
1623
1624 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1625 if (fw_ptr == NULL){
1626 release_firmware(fw_entry);
1627 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1628 "failed to allocate memory for firmware2 upload");
21684ba9
MI		 1629 ret = -ENOMEM;
1630 goto done;
d855497e
MI		 1631 }
1632
1633 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1634
90060d32
MI		 1635 fw_done = 0;
1636 for (fw_done = 0; fw_done < fw_len;) {
1637 bcnt = fw_len - fw_done;
1638 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1639 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1640 /* Usbsnoop log shows that we must swap bytes... */
5f33df14
MI		 1641 /* Some background info: The data being swapped here is a
1642 firmware image destined for the mpeg encoder chip that
1643 lives at the other end of a USB endpoint. The encoder
1644 chip always talks in 32 bit chunks and its storage is
1645 organized into 32 bit words. However from the file
1646 system to the encoder chip everything is purely a byte
1647 stream. The firmware file's contents are always 32 bit
1648 swapped from what the encoder expects. Thus the need
1649 always exists to swap the bytes regardless of the endian
1650 type of the host processor and therefore swab32() makes
1651 the most sense. */
90060d32 1652 for (icnt = 0; icnt < bcnt/4 ; icnt++)
513edce6 1653 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
90060d32
MI		 1654
1655 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1656 &actual_length, HZ);
90060d32
MI		 1657 ret |= (actual_length != bcnt);
1658 if (ret) break;
1659 fw_done += bcnt;
d855497e
MI		 1660 }
1661
1662 trace_firmware("upload of %s : %i / %i ",
1663 fw_files[fwidx],fw_done,fw_len);
1664
1665 kfree(fw_ptr);
1666 release_firmware(fw_entry);
1667
1668 if (ret) {
1669 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1670 "firmware2 upload transfer failure");
21684ba9 1671 goto done;
d855497e
MI		 1672 }
1673
1674 /* Finish upload */
1675
1676 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1677 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1c9d10d4 1678 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1679
1680 if (ret) {
1681 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1682 "firmware2 upload post-proc failure");
d855497e 1683 }
21684ba9
MI		 1684
1685 done:
1df59f0b
MI		 1686 if (hdw->hdw_desc->signal_routing_scheme ==
1687 PVR2_ROUTING_SCHEME_GOTVIEW) {
1688 /* Ensure that GPIO 11 is set to output for GOTVIEW
1689 hardware. */
1690 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1691 }
d855497e
MI		 1692 return ret;
1693}
1694
1695
681c7399
MI		 1696static const char *pvr2_get_state_name(unsigned int st)
1697{
1698 if (st < ARRAY_SIZE(pvr2_state_names)) {
1699 return pvr2_state_names[st];
d855497e 1700 }
681c7399 1701 return "???";
d855497e
MI		 1702}
1703
681c7399 1704static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1705{
af78e16b
MI		 1706 /* Even though we really only care about the video decoder chip at
1707 this point, we'll broadcast stream on/off to all sub-devices
1708 anyway, just in case somebody else wants to hear the
1709 command... */
e260508d
MI		 1710 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1711 (enablefl ? "on" : "off"));
af78e16b 1712 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
3ccc646b 1713 v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
af78e16b
MI		 1714 if (hdw->decoder_client_id) {
1715 /* We get here if the encoder has been noticed. Otherwise
1716 we'll issue a warning to the user (which should
1717 normally never happen). */
1718 return 0;
1719 }
1720 if (!hdw->flag_decoder_missed) {
1721 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1722 "WARNING: No decoder present");
1723 hdw->flag_decoder_missed = !0;
1724 trace_stbit("flag_decoder_missed",
1725 hdw->flag_decoder_missed);
1726 }
1727 return -EIO;
d855497e
MI		 1728}
1729
1730
681c7399 1731int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1732{
681c7399 1733 return hdw->master_state;
d855497e
MI		 1734}
1735
1736
681c7399 1737static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1738{
681c7399
MI		 1739 if (!hdw->flag_tripped) return 0;
1740 hdw->flag_tripped = 0;
1741 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1742 "Clearing driver error statuss");
1743 return !0;
d855497e
MI		 1744}
1745
1746
681c7399 1747int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1748{
681c7399 1749 int fl;
d855497e 1750 LOCK_TAKE(hdw->big_lock); do {
681c7399 1751 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1752 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1753 if (fl) pvr2_hdw_state_sched(hdw);
1754 return 0;
d855497e
MI		 1755}
1756
1757
d855497e
MI		 1758
1759
1760int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1761{
681c7399 1762 return hdw->state_pipeline_req != 0;
d855497e
MI		 1763}
1764
1765
1766int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1767{
681c7399 1768 int ret,st;
d855497e 1769 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1770 pvr2_hdw_untrip_unlocked(hdw);
1771 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1772 hdw->state_pipeline_req = enable_flag != 0;
1773 pvr2_trace(PVR2_TRACE_START_STOP,
1774 "/*--TRACE_STREAM--*/ %s",
1775 enable_flag ? "enable" : "disable");
1776 }
1777 pvr2_hdw_state_sched(hdw);
d855497e 1778 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1779 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1780 if (enable_flag) {
1781 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1782 if (st != PVR2_STATE_READY) return -EIO;
1783 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1784 }
1785 }
d855497e
MI		 1786 return 0;
1787}
1788
1789
1790int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1791{
681c7399 1792 int fl;
d855497e 1793 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1794 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1795 hdw->desired_stream_type = config;
1796 hdw->state_pipeline_config = 0;
1797 trace_stbit("state_pipeline_config",
1798 hdw->state_pipeline_config);
1799 pvr2_hdw_state_sched(hdw);
1800 }
d855497e 1801 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1802 if (fl) return 0;
1803 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1804}
1805
1806
1807static int get_default_tuner_type(struct pvr2_hdw *hdw)
1808{
1809 int unit_number = hdw->unit_number;
1810 int tp = -1;
1811 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1812 tp = tuner[unit_number];
1813 }
1814 if (tp < 0) return -EINVAL;
1815 hdw->tuner_type = tp;
aaf7884d 1816 hdw->tuner_updated = !0;
d855497e
MI		 1817 return 0;
1818}
1819
1820
1821static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1822{
1823 int unit_number = hdw->unit_number;
1824 int tp = 0;
1825 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1826 tp = video_std[unit_number];
6a540254 1827 if (tp) return tp;
d855497e 1828 }
6a540254 1829 return 0;
d855497e
MI		 1830}
1831
1832
1833static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1834{
1835 int unit_number = hdw->unit_number;
1836 int tp = 0;
1837 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1838 tp = tolerance[unit_number];
1839 }
1840 return tp;
1841}
1842
1843
1844static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1845{
1846 /* Try a harmless request to fetch the eeprom's address over
1847 endpoint 1. See what happens. Only the full FX2 image can
1848 respond to this. If this probe fails then likely the FX2
1849 firmware needs be loaded. */
1850 int result;
1851 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1852 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1853 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1854 hdw->cmd_buffer,1,
1855 hdw->cmd_buffer,1);
1856 if (result < 0) break;
1857 } while(0); LOCK_GIVE(hdw->ctl_lock);
1858 if (result) {
1859 pvr2_trace(PVR2_TRACE_INIT,
1860 "Probe of device endpoint 1 result status %d",
1861 result);
1862 } else {
1863 pvr2_trace(PVR2_TRACE_INIT,
1864 "Probe of device endpoint 1 succeeded");
1865 }
1866 return result == 0;
1867}
1868
9f66d4ea
MI		 1869struct pvr2_std_hack {
1870 v4l2_std_id pat; /* Pattern to match */
1871 v4l2_std_id msk; /* Which bits we care about */
1872 v4l2_std_id std; /* What additional standards or default to set */
1873};
1874
1875/* This data structure labels specific combinations of standards from
1876 tveeprom that we'll try to recognize. If we recognize one, then assume
1877 a specified default standard to use. This is here because tveeprom only
1878 tells us about available standards not the intended default standard (if
1879 any) for the device in question. We guess the default based on what has
1880 been reported as available. Note that this is only for guessing a
1881 default - which can always be overridden explicitly - and if the user
1882 has otherwise named a default then that default will always be used in
1883 place of this table. */
ebff0330 1884static const struct pvr2_std_hack std_eeprom_maps[] = {
9f66d4ea
MI		 1885 { /* PAL(B/G) */
1886 .pat = V4L2_STD_B|V4L2_STD_GH,
1887 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1888 },
1889 { /* NTSC(M) */
1890 .pat = V4L2_STD_MN,
1891 .std = V4L2_STD_NTSC_M,
1892 },
1893 { /* PAL(I) */
1894 .pat = V4L2_STD_PAL_I,
1895 .std = V4L2_STD_PAL_I,
1896 },
1897 { /* SECAM(L/L') */
1898 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1899 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1900 },
1901 { /* PAL(D/D1/K) */
1902 .pat = V4L2_STD_DK,
ea2562d9 1903 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
9f66d4ea
MI		 1904 },
1905};
1906
d855497e
MI		 1907static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1908{
1909 char buf[40];
1910 unsigned int bcnt;
3d290bdb 1911 v4l2_std_id std1,std2,std3;
d855497e
MI		 1912
1913 std1 = get_default_standard(hdw);
3d290bdb 1914 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
d855497e
MI		 1915
1916 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1917 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1918 "Supported video standard(s) reported available"
1919 " in hardware: %.*s",
d855497e
MI		 1920 bcnt,buf);
1921
1922 hdw->std_mask_avail = hdw->std_mask_eeprom;
1923
3d290bdb 1924 std2 = (std1|std3) & ~hdw->std_mask_avail;
d855497e
MI		 1925 if (std2) {
1926 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1927 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1928 "Expanding supported video standards"
1929 " to include: %.*s",
1930 bcnt,buf);
1931 hdw->std_mask_avail |= std2;
1932 }
1933
1934 pvr2_hdw_internal_set_std_avail(hdw);
1935
1936 if (std1) {
1937 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1938 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1939 "Initial video standard forced to %.*s",
1940 bcnt,buf);
1941 hdw->std_mask_cur = std1;
1942 hdw->std_dirty = !0;
1943 pvr2_hdw_internal_find_stdenum(hdw);
1944 return;
1945 }
3d290bdb
MI		 1946 if (std3) {
1947 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1948 pvr2_trace(PVR2_TRACE_STD,
1949 "Initial video standard"
1950 " (determined by device type): %.*s",bcnt,buf);
1951 hdw->std_mask_cur = std3;
1952 hdw->std_dirty = !0;
1953 pvr2_hdw_internal_find_stdenum(hdw);
1954 return;
1955 }
d855497e 1956
9f66d4ea
MI		 1957 {
1958 unsigned int idx;
1959 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1960 if (std_eeprom_maps[idx].msk ?
1961 ((std_eeprom_maps[idx].pat ^
1962 hdw->std_mask_eeprom) &
1963 std_eeprom_maps[idx].msk) :
1964 (std_eeprom_maps[idx].pat !=
1965 hdw->std_mask_eeprom)) continue;
1966 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1967 std_eeprom_maps[idx].std);
56585386 1968 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1969 "Initial video standard guessed as %.*s",
1970 bcnt,buf);
1971 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1972 hdw->std_dirty = !0;
1973 pvr2_hdw_internal_find_stdenum(hdw);
1974 return;
1975 }
1976 }
1977
d855497e
MI		 1978 if (hdw->std_enum_cnt > 1) {
1979 // Autoselect the first listed standard
1980 hdw->std_enum_cur = 1;
1981 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1982 hdw->std_dirty = !0;
56585386 1983 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1984 "Initial video standard auto-selected to %s",
1985 hdw->std_defs[hdw->std_enum_cur-1].name);
1986 return;
1987 }
1988
0885ba1d 1989 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1990 "Unable to select a viable initial video standard");
1991}
1992
1993
e9c64a78
MI		 1994static unsigned int pvr2_copy_i2c_addr_list(
1995 unsigned short *dst, const unsigned char *src,
1996 unsigned int dst_max)
1997{
3ab8d295 1998 unsigned int cnt = 0;
e9c64a78
MI		 1999 if (!src) return 0;
2000 while (src[cnt] && (cnt + 1) < dst_max) {
2001 dst[cnt] = src[cnt];
2002 cnt++;
2003 }
2004 dst[cnt] = I2C_CLIENT_END;
2005 return cnt;
2006}
2007
2008
e17d787c
MI		 2009static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
2010{
2011 /*
2012 Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
2013 for cx25840 causes that module to correctly set up its video
2014 scaling. This is really a problem in the cx25840 module itself,
2015 but we work around it here. The problem has not been seen in
2016 ivtv because there VBI is supported and set up. We don't do VBI
2017 here (at least not yet) and thus we never attempted to even set
2018 it up.
2019 */
2020 struct v4l2_format fmt;
2021 if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
2022 /* We're not using a cx25840 so don't enable the hack */
2023 return;
2024 }
2025
2026 pvr2_trace(PVR2_TRACE_INIT,
2027 "Module ID %u:"
2028 " Executing cx25840 VBI hack",
2029 hdw->decoder_client_id);
2030 memset(&fmt, 0, sizeof(fmt));
2031 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2032 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
2033 video, s_fmt, &fmt);
2034}
2035
2036
1ab5e74f
MI		 2037static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
2038 const struct pvr2_device_client_desc *cd)
e9c64a78
MI		 2039{
2040 const char *fname;
2041 unsigned char mid;
2042 struct v4l2_subdev *sd;
2043 unsigned int i2ccnt;
2044 const unsigned char *p;
2045 /* Arbitrary count - max # i2c addresses we will probe */
2046 unsigned short i2caddr[25];
2047
2048 mid = cd->module_id;
2049 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2050 if (!fname) {
2051 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
27108147
MI		 2052 "Module ID %u for device %s has no name?"
2053 " The driver might have a configuration problem.",
e9c64a78
MI		 2054 mid,
2055 hdw->hdw_desc->description);
1ab5e74f 2056 return -EINVAL;
e9c64a78 2057 }
bd14d4f8
MI		 2058 pvr2_trace(PVR2_TRACE_INIT,
2059 "Module ID %u (%s) for device %s being loaded...",
2060 mid, fname,
2061 hdw->hdw_desc->description);
e9c64a78
MI		 2062
2063 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2064 ARRAY_SIZE(i2caddr));
2065 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2066 module_i2c_addresses[mid] : NULL) != NULL)) {
2067 /* Second chance: Try default i2c address list */
2068 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2069 ARRAY_SIZE(i2caddr));
bd14d4f8
MI		 2070 if (i2ccnt) {
2071 pvr2_trace(PVR2_TRACE_INIT,
2072 "Module ID %u:"
2073 " Using default i2c address list",
2074 mid);
2075 }
e9c64a78
MI		 2076 }
2077
2078 if (!i2ccnt) {
2079 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f 2080 "Module ID %u (%s) for device %s:"
27108147
MI		 2081 " No i2c addresses."
2082 " The driver might have a configuration problem.",
1ab5e74f
MI		 2083 mid, fname, hdw->hdw_desc->description);
2084 return -EINVAL;
e9c64a78
MI		 2085 }
2086
53dacb15
HV		 2087 /* Note how the 2nd and 3rd arguments are the same for
2088 * v4l2_i2c_new_subdev(). Why?
e9c64a78
MI		 2089 * Well the 2nd argument is the module name to load, while the 3rd
2090 * argument is documented in the framework as being the "chipid" -
2091 * and every other place where I can find examples of this, the
2092 * "chipid" appears to just be the module name again. So here we
2093 * just do the same thing. */
2094 if (i2ccnt == 1) {
bd14d4f8
MI		 2095 pvr2_trace(PVR2_TRACE_INIT,
2096 "Module ID %u:"
2097 " Setting up with specified i2c address 0x%x",
2098 mid, i2caddr[0]);
e6574f2f 2099 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
e9c64a78 2100 fname, fname,
53dacb15 2101 i2caddr[0], NULL);
e9c64a78 2102 } else {
bd14d4f8
MI		 2103 pvr2_trace(PVR2_TRACE_INIT,
2104 "Module ID %u:"
2105 " Setting up with address probe list",
2106 mid);
53dacb15 2107 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
e9c64a78 2108 fname, fname,
53dacb15 2109 0, i2caddr);
e9c64a78
MI		 2110 }
2111
446dfdc6
MI		 2112 if (!sd) {
2113 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
27108147
MI		 2114 "Module ID %u (%s) for device %s failed to load."
2115 " Possible missing sub-device kernel module or"
2116 " initialization failure within module.",
1ab5e74f
MI		 2117 mid, fname, hdw->hdw_desc->description);
2118 return -EIO;
446dfdc6
MI		 2119 }
2120
2121 /* Tag this sub-device instance with the module ID we know about.
2122 In other places we'll use that tag to determine if the instance
2123 requires special handling. */
2124 sd->grp_id = mid;
2125
bd14d4f8 2126 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
a932f507 2127
e9c64a78 2128
00e5f736
MI		 2129 /* client-specific setup... */
2130 switch (mid) {
2131 case PVR2_CLIENT_ID_CX25840:
00e5f736
MI		 2132 case PVR2_CLIENT_ID_SAA7115:
2133 hdw->decoder_client_id = mid;
2134 break;
2135 default: break;
2136 }
1ab5e74f
MI		 2137
2138 return 0;
e9c64a78
MI		 2139}
2140
2141
2142static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2143{
2144 unsigned int idx;
2145 const struct pvr2_string_table *cm;
2146 const struct pvr2_device_client_table *ct;
1ab5e74f 2147 int okFl = !0;
e9c64a78
MI		 2148
2149 cm = &hdw->hdw_desc->client_modules;
2150 for (idx = 0; idx < cm->cnt; idx++) {
2151 request_module(cm->lst[idx]);
2152 }
2153
2154 ct = &hdw->hdw_desc->client_table;
2155 for (idx = 0; idx < ct->cnt; idx++) {
bd14d4f8 2156 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
e9c64a78 2157 }
27108147
MI		 2158 if (!okFl) {
2159 hdw->flag_modulefail = !0;
2160 pvr2_hdw_render_useless(hdw);
2161 }
e9c64a78
MI		 2162}
2163
2164
d855497e
MI		 2165static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2166{
2167 int ret;
2168 unsigned int idx;
2169 struct pvr2_ctrl *cptr;
2170 int reloadFl = 0;
989eb154 2171 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 2172 if (!reloadFl) {
2173 reloadFl =
2174 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2175 == 0);
2176 if (reloadFl) {
2177 pvr2_trace(PVR2_TRACE_INIT,
2178 "USB endpoint config looks strange"
2179 "; possibly firmware needs to be"
2180 " loaded");
2181 }
d855497e 2182 }
1d643a37
MI		 2183 if (!reloadFl) {
2184 reloadFl = !pvr2_hdw_check_firmware(hdw);
2185 if (reloadFl) {
2186 pvr2_trace(PVR2_TRACE_INIT,
2187 "Check for FX2 firmware failed"
2188 "; possibly firmware needs to be"
2189 " loaded");
2190 }
d855497e 2191 }
1d643a37
MI		 2192 if (reloadFl) {
2193 if (pvr2_upload_firmware1(hdw) != 0) {
2194 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2195 "Failure uploading firmware1");
2196 }
2197 return;
d855497e 2198 }
d855497e
MI		 2199 }
2200 hdw->fw1_state = FW1_STATE_OK;
2201
d855497e
MI		 2202 if (!pvr2_hdw_dev_ok(hdw)) return;
2203
27764726
MI		 2204 hdw->force_dirty = !0;
2205
989eb154 2206 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 2207 pvr2_hdw_cmd_powerup(hdw);
2208 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 2209 }
2210
31335b13 2211 /* Take the IR chip out of reset, if appropriate */
27eab384 2212 if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
31335b13
MI		 2213 pvr2_issue_simple_cmd(hdw,
2214 FX2CMD_HCW_ZILOG_RESET |
2215 (1 << 8) |
2216 ((0) << 16));
2217 }
2218
d855497e
MI		 2219 // This step MUST happen after the earlier powerup step.
2220 pvr2_i2c_core_init(hdw);
2221 if (!pvr2_hdw_dev_ok(hdw)) return;
2222
e9c64a78 2223 pvr2_hdw_load_modules(hdw);
1ab5e74f 2224 if (!pvr2_hdw_dev_ok(hdw)) return;
e9c64a78 2225
cc26b076 2226 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
5c6cb4e2 2227
c05c0462 2228 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 2229 cptr = hdw->controls + idx;
2230 if (cptr->info->skip_init) continue;
2231 if (!cptr->info->set_value) continue;
2232 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2233 }
2234
e17d787c
MI		 2235 pvr2_hdw_cx25840_vbi_hack(hdw);
2236
1bde0289
MI		 2237 /* Set up special default values for the television and radio
2238 frequencies here. It's not really important what these defaults
2239 are, but I set them to something usable in the Chicago area just
2240 to make driver testing a little easier. */
2241
5a4f5da6
MK		 2242 hdw->freqValTelevision = default_tv_freq;
2243 hdw->freqValRadio = default_radio_freq;
1bde0289 2244
d855497e
MI		 2245 // Do not use pvr2_reset_ctl_endpoints() here. It is not
2246 // thread-safe against the normal pvr2_send_request() mechanism.
2247 // (We should make it thread safe).
2248
aaf7884d
MI		 2249 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2250 ret = pvr2_hdw_get_eeprom_addr(hdw);
d855497e 2251 if (!pvr2_hdw_dev_ok(hdw)) return;
aaf7884d
MI		 2252 if (ret < 0) {
2253 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2254 "Unable to determine location of eeprom,"
2255 " skipping");
2256 } else {
2257 hdw->eeprom_addr = ret;
2258 pvr2_eeprom_analyze(hdw);
2259 if (!pvr2_hdw_dev_ok(hdw)) return;
2260 }
2261 } else {
2262 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2263 hdw->tuner_updated = !0;
2264 hdw->std_mask_eeprom = V4L2_STD_ALL;
d855497e
MI		 2265 }
2266
13a88797
MI		 2267 if (hdw->serial_number) {
2268 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2269 "sn-%lu", hdw->serial_number);
2270 } else if (hdw->unit_number >= 0) {
2271 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2272 "unit-%c",
2273 hdw->unit_number + 'a');
2274 } else {
2275 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2276 "unit-??");
2277 }
2278 hdw->identifier[idx] = 0;
2279
d855497e
MI		 2280 pvr2_hdw_setup_std(hdw);
2281
2282 if (!get_default_tuner_type(hdw)) {
2283 pvr2_trace(PVR2_TRACE_INIT,
2284 "pvr2_hdw_setup: Tuner type overridden to %d",
2285 hdw->tuner_type);
2286 }
2287
d855497e
MI		 2288
2289 if (!pvr2_hdw_dev_ok(hdw)) return;
2290
1df59f0b
MI		 2291 if (hdw->hdw_desc->signal_routing_scheme ==
2292 PVR2_ROUTING_SCHEME_GOTVIEW) {
2293 /* Ensure that GPIO 11 is set to output for GOTVIEW
2294 hardware. */
2295 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2296 }
2297
681c7399 2298 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 2299
2300 hdw->vid_stream = pvr2_stream_create();
2301 if (!pvr2_hdw_dev_ok(hdw)) return;
2302 pvr2_trace(PVR2_TRACE_INIT,
2303 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2304 if (hdw->vid_stream) {
2305 idx = get_default_error_tolerance(hdw);
2306 if (idx) {
2307 pvr2_trace(PVR2_TRACE_INIT,
2308 "pvr2_hdw_setup: video stream %p"
2309 " setting tolerance %u",
2310 hdw->vid_stream,idx);
2311 }
2312 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2313 PVR2_VID_ENDPOINT,idx);
2314 }
2315
2316 if (!pvr2_hdw_dev_ok(hdw)) return;
2317
d855497e 2318 hdw->flag_init_ok = !0;
681c7399
MI		 2319
2320 pvr2_hdw_state_sched(hdw);
d855497e
MI		 2321}
2322
2323
681c7399
MI		 2324/* Set up the structure and attempt to put the device into a usable state.
2325 This can be a time-consuming operation, which is why it is not done
2326 internally as part of the create() step. */
2327static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 2328{
2329 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 2330 do {
d855497e
MI		 2331 pvr2_hdw_setup_low(hdw);
2332 pvr2_trace(PVR2_TRACE_INIT,
2333 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 2334 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 2335 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 2336 if (hdw->flag_init_ok) {
d855497e
MI		 2337 pvr2_trace(
2338 PVR2_TRACE_INFO,
2339 "Device initialization"
2340 " completed successfully.");
2341 break;
2342 }
2343 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2344 pvr2_trace(
2345 PVR2_TRACE_INFO,
2346 "Device microcontroller firmware"
2347 " (re)loaded; it should now reset"
2348 " and reconnect.");
2349 break;
2350 }
2351 pvr2_trace(
2352 PVR2_TRACE_ERROR_LEGS,
2353 "Device initialization was not successful.");
2354 if (hdw->fw1_state == FW1_STATE_MISSING) {
2355 pvr2_trace(
2356 PVR2_TRACE_ERROR_LEGS,
2357 "Giving up since device"
2358 " microcontroller firmware"
2359 " appears to be missing.");
2360 break;
2361 }
2362 }
27108147
MI		 2363 if (hdw->flag_modulefail) {
2364 pvr2_trace(
2365 PVR2_TRACE_ERROR_LEGS,
2366 "***WARNING*** pvrusb2 driver initialization"
2367 " failed due to the failure of one or more"
2368 " sub-device kernel modules.");
2369 pvr2_trace(
2370 PVR2_TRACE_ERROR_LEGS,
2371 "You need to resolve the failing condition"
2372 " before this driver can function. There"
2373 " should be some earlier messages giving more"
2374 " information about the problem.");
515ebf79 2375 break;
27108147 2376 }
d855497e
MI		 2377 if (procreload) {
2378 pvr2_trace(
2379 PVR2_TRACE_ERROR_LEGS,
2380 "Attempting pvrusb2 recovery by reloading"
2381 " primary firmware.");
2382 pvr2_trace(
2383 PVR2_TRACE_ERROR_LEGS,
2384 "If this works, device should disconnect"
2385 " and reconnect in a sane state.");
2386 hdw->fw1_state = FW1_STATE_UNKNOWN;
2387 pvr2_upload_firmware1(hdw);
2388 } else {
2389 pvr2_trace(
2390 PVR2_TRACE_ERROR_LEGS,
2391 "***WARNING*** pvrusb2 device hardware"
2392 " appears to be jammed"
2393 " and I can't clear it.");
2394 pvr2_trace(
2395 PVR2_TRACE_ERROR_LEGS,
2396 "You might need to power cycle"
2397 " the pvrusb2 device"
2398 " in order to recover.");
2399 }
681c7399 2400 } while (0);
d855497e 2401 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 2402}
2403
2404
c4a8828d
MI		 2405/* Perform second stage initialization. Set callback pointer first so that
2406 we can avoid a possible initialization race (if the kernel thread runs
2407 before the callback has been set). */
794b1607
MI		 2408int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2409 void (*callback_func)(void *),
2410 void *callback_data)
c4a8828d
MI		 2411{
2412 LOCK_TAKE(hdw->big_lock); do {
97f26ff6
MI		 2413 if (hdw->flag_disconnected) {
2414 /* Handle a race here: If we're already
2415 disconnected by this point, then give up. If we
2416 get past this then we'll remain connected for
2417 the duration of initialization since the entire
2418 initialization sequence is now protected by the
2419 big_lock. */
2420 break;
2421 }
c4a8828d
MI		 2422 hdw->state_data = callback_data;
2423 hdw->state_func = callback_func;
97f26ff6 2424 pvr2_hdw_setup(hdw);
c4a8828d 2425 } while (0); LOCK_GIVE(hdw->big_lock);
794b1607 2426 return hdw->flag_init_ok;
c4a8828d
MI		 2427}
2428
2429
2430/* Create, set up, and return a structure for interacting with the
2431 underlying hardware. */
d855497e
MI		 2432struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2433 const struct usb_device_id *devid)
2434{
7fb20fa3 2435 unsigned int idx,cnt1,cnt2,m;
fe15f136 2436 struct pvr2_hdw *hdw = NULL;
d855497e
MI		 2437 int valid_std_mask;
2438 struct pvr2_ctrl *cptr;
b72b7bf5 2439 struct usb_device *usb_dev;
989eb154 2440 const struct pvr2_device_desc *hdw_desc;
d855497e 2441 __u8 ifnum;
b30d2441
MI		 2442 struct v4l2_queryctrl qctrl;
2443 struct pvr2_ctl_info *ciptr;
d855497e 2444
b72b7bf5
MI		 2445 usb_dev = interface_to_usbdev(intf);
2446
d130fa8a 2447 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
d855497e 2448
fe15f136
MI		 2449 if (hdw_desc == NULL) {
2450 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2451 " No device description pointer,"
2452 " unable to continue.");
2453 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2454 " please contact Mike Isely <isely@pobox.com>"
2455 " to get it included in the driver\n");
2456 goto fail;
2457 }
2458
ca545f7c 2459 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 2460 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 2461 hdw,hdw_desc->description);
e67e376b 2462 pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
00970beb 2463 hdw_desc->description);
d855497e 2464 if (!hdw) goto fail;
681c7399
MI		 2465
2466 init_timer(&hdw->quiescent_timer);
2467 hdw->quiescent_timer.data = (unsigned long)hdw;
2468 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2469
6e931375
MI		 2470 init_timer(&hdw->decoder_stabilization_timer);
2471 hdw->decoder_stabilization_timer.data = (unsigned long)hdw;
2472 hdw->decoder_stabilization_timer.function =
2473 pvr2_hdw_decoder_stabilization_timeout;
2474
681c7399
MI		 2475 init_timer(&hdw->encoder_wait_timer);
2476 hdw->encoder_wait_timer.data = (unsigned long)hdw;
2477 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2478
d913d630
MI		 2479 init_timer(&hdw->encoder_run_timer);
2480 hdw->encoder_run_timer.data = (unsigned long)hdw;
2481 hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2482
681c7399
MI		 2483 hdw->master_state = PVR2_STATE_DEAD;
2484
2485 init_waitqueue_head(&hdw->state_wait_data);
2486
18103c57 2487 hdw->tuner_signal_stale = !0;
b30d2441 2488 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 2489
7fb20fa3
MI		 2490 /* Calculate which inputs are OK */
2491 m = 0;
2492 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
e8f5bacf
MI		 2493 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2494 m |= 1 << PVR2_CVAL_INPUT_DTV;
2495 }
7fb20fa3
MI		 2496 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2497 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2498 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2499 hdw->input_avail_mask = m;
1cb03b76 2500 hdw->input_allowed_mask = hdw->input_avail_mask;
7fb20fa3 2501
62433e31
MI		 2502 /* If not a hybrid device, pathway_state never changes. So
2503 initialize it here to what it should forever be. */
2504 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2505 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2506 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2507 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2508 }
2509
c05c0462 2510 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 2511 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 2512 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 2513 GFP_KERNEL);
2514 if (!hdw->controls) goto fail;
989eb154 2515 hdw->hdw_desc = hdw_desc;
27eab384 2516 hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
c05c0462
MI		 2517 for (idx = 0; idx < hdw->control_cnt; idx++) {
2518 cptr = hdw->controls + idx;
2519 cptr->hdw = hdw;
2520 }
d855497e
MI		 2521 for (idx = 0; idx < 32; idx++) {
2522 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2523 }
c05c0462 2524 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 2525 cptr = hdw->controls + idx;
d855497e
MI		 2526 cptr->info = control_defs+idx;
2527 }
dbc40a0e
MI		 2528
2529 /* Ensure that default input choice is a valid one. */
2530 m = hdw->input_avail_mask;
2531 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2532 if (!((1 << idx) & m)) continue;
2533 hdw->input_val = idx;
2534 break;
2535 }
2536
b30d2441 2537 /* Define and configure additional controls from cx2341x module. */
ca545f7c 2538 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 2539 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2540 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 2541 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2542 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2543 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2544 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2545 ciptr->name = mpeg_ids[idx].strid;
2546 ciptr->v4l_id = mpeg_ids[idx].id;
2547 ciptr->skip_init = !0;
2548 ciptr->get_value = ctrl_cx2341x_get;
2549 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2550 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2551 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2552 qctrl.id = ciptr->v4l_id;
2553 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2554 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2555 ciptr->set_value = ctrl_cx2341x_set;
2556 }
2557 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2558 PVR2_CTLD_INFO_DESC_SIZE);
2559 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2560 ciptr->default_value = qctrl.default_value;
2561 switch (qctrl.type) {
2562 default:
2563 case V4L2_CTRL_TYPE_INTEGER:
2564 ciptr->type = pvr2_ctl_int;
2565 ciptr->def.type_int.min_value = qctrl.minimum;
2566 ciptr->def.type_int.max_value = qctrl.maximum;
2567 break;
2568 case V4L2_CTRL_TYPE_BOOLEAN:
2569 ciptr->type = pvr2_ctl_bool;
2570 break;
2571 case V4L2_CTRL_TYPE_MENU:
2572 ciptr->type = pvr2_ctl_enum;
2573 ciptr->def.type_enum.value_names =
e0e31cdb
HV		 2574 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2575 ciptr->v4l_id);
b30d2441
MI		 2576 for (cnt1 = 0;
2577 ciptr->def.type_enum.value_names[cnt1] != NULL;
2578 cnt1++) { }
2579 ciptr->def.type_enum.count = cnt1;
2580 break;
2581 }
2582 cptr->info = ciptr;
2583 }
d855497e
MI		 2584
2585 // Initialize video standard enum dynamic control
2586 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2587 if (cptr) {
2588 memcpy(&hdw->std_info_enum,cptr->info,
2589 sizeof(hdw->std_info_enum));
2590 cptr->info = &hdw->std_info_enum;
2591
2592 }
2593 // Initialize control data regarding video standard masks
2594 valid_std_mask = pvr2_std_get_usable();
2595 for (idx = 0; idx < 32; idx++) {
2596 if (!(valid_std_mask & (1 << idx))) continue;
2597 cnt1 = pvr2_std_id_to_str(
2598 hdw->std_mask_names[idx],
2599 sizeof(hdw->std_mask_names[idx])-1,
2600 1 << idx);
2601 hdw->std_mask_names[idx][cnt1] = 0;
2602 }
2603 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2604 if (cptr) {
2605 memcpy(&hdw->std_info_avail,cptr->info,
2606 sizeof(hdw->std_info_avail));
2607 cptr->info = &hdw->std_info_avail;
2608 hdw->std_info_avail.def.type_bitmask.bit_names =
2609 hdw->std_mask_ptrs;
2610 hdw->std_info_avail.def.type_bitmask.valid_bits =
2611 valid_std_mask;
2612 }
2613 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2614 if (cptr) {
2615 memcpy(&hdw->std_info_cur,cptr->info,
2616 sizeof(hdw->std_info_cur));
2617 cptr->info = &hdw->std_info_cur;
2618 hdw->std_info_cur.def.type_bitmask.bit_names =
2619 hdw->std_mask_ptrs;
2620 hdw->std_info_avail.def.type_bitmask.valid_bits =
2621 valid_std_mask;
2622 }
2623
432907f7 2624 hdw->cropcap_stale = !0;
d855497e
MI		 2625 hdw->eeprom_addr = -1;
2626 hdw->unit_number = -1;
8079384e
MI		 2627 hdw->v4l_minor_number_video = -1;
2628 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 2629 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 2630 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2631 if (!hdw->ctl_write_buffer) goto fail;
2632 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2633 if (!hdw->ctl_read_buffer) goto fail;
2634 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2635 if (!hdw->ctl_write_urb) goto fail;
2636 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2637 if (!hdw->ctl_read_urb) goto fail;
2638
70ad6383 2639 if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
b72b7bf5
MI		 2640 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2641 "Error registering with v4l core, giving up");
2642 goto fail;
2643 }
8df0c87c 2644 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2645 for (idx = 0; idx < PVR_NUM; idx++) {
2646 if (unit_pointers[idx]) continue;
2647 hdw->unit_number = idx;
2648 unit_pointers[idx] = hdw;
2649 break;
2650 }
8df0c87c 2651 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 2652
2653 cnt1 = 0;
2654 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2655 cnt1 += cnt2;
2656 if (hdw->unit_number >= 0) {
2657 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2658 ('a' + hdw->unit_number));
2659 cnt1 += cnt2;
2660 }
2661 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2662 hdw->name[cnt1] = 0;
2663
681c7399
MI		 2664 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2665 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
681c7399 2666
d855497e
MI		 2667 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2668 hdw->unit_number,hdw->name);
2669
2670 hdw->tuner_type = -1;
2671 hdw->flag_ok = !0;
d855497e
MI		 2672
2673 hdw->usb_intf = intf;
b72b7bf5 2674 hdw->usb_dev = usb_dev;
d855497e 2675
87e3495c 2676 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
31a18547 2677
d855497e
MI		 2678 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2679 usb_set_interface(hdw->usb_dev,ifnum,0);
2680
2681 mutex_init(&hdw->ctl_lock_mutex);
2682 mutex_init(&hdw->big_lock_mutex);
2683
2684 return hdw;
2685 fail:
2686 if (hdw) {
681c7399 2687 del_timer_sync(&hdw->quiescent_timer);
6e931375 2688 del_timer_sync(&hdw->decoder_stabilization_timer);
d913d630 2689 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 2690 del_timer_sync(&hdw->encoder_wait_timer);
2691 if (hdw->workqueue) {
2692 flush_workqueue(hdw->workqueue);
2693 destroy_workqueue(hdw->workqueue);
2694 hdw->workqueue = NULL;
2695 }
5e55d2ce
MK		 2696 usb_free_urb(hdw->ctl_read_urb);
2697 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2698 kfree(hdw->ctl_read_buffer);
2699 kfree(hdw->ctl_write_buffer);
2700 kfree(hdw->controls);
2701 kfree(hdw->mpeg_ctrl_info);
681c7399
MI		 2702 kfree(hdw->std_defs);
2703 kfree(hdw->std_enum_names);
d855497e
MI		 2704 kfree(hdw);
2705 }
a0fd1cb1 2706 return NULL;
d855497e
MI		 2707}
2708
2709
2710/* Remove _all_ associations between this driver and the underlying USB
2711 layer. */
07e337ee 2712static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2713{
2714 if (hdw->flag_disconnected) return;
2715 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2716 if (hdw->ctl_read_urb) {
2717 usb_kill_urb(hdw->ctl_read_urb);
2718 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2719 hdw->ctl_read_urb = NULL;
d855497e
MI		 2720 }
2721 if (hdw->ctl_write_urb) {
2722 usb_kill_urb(hdw->ctl_write_urb);
2723 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2724 hdw->ctl_write_urb = NULL;
d855497e
MI		 2725 }
2726 if (hdw->ctl_read_buffer) {
2727 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2728 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2729 }
2730 if (hdw->ctl_write_buffer) {
2731 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2732 hdw->ctl_write_buffer = NULL;
d855497e 2733 }
d855497e 2734 hdw->flag_disconnected = !0;
b72b7bf5
MI		 2735 /* If we don't do this, then there will be a dangling struct device
2736 reference to our disappearing device persisting inside the V4L
2737 core... */
dc070bcc 2738 v4l2_device_disconnect(&hdw->v4l2_dev);
a0fd1cb1
MI		 2739 hdw->usb_dev = NULL;
2740 hdw->usb_intf = NULL;
681c7399 2741 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2742}
2743
2744
2745/* Destroy hardware interaction structure */
2746void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2747{
401c27ce 2748 if (!hdw) return;
d855497e 2749 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2750 if (hdw->workqueue) {
2751 flush_workqueue(hdw->workqueue);
2752 destroy_workqueue(hdw->workqueue);
2753 hdw->workqueue = NULL;
2754 }
8f59100a 2755 del_timer_sync(&hdw->quiescent_timer);
6e931375 2756 del_timer_sync(&hdw->decoder_stabilization_timer);
d913d630 2757 del_timer_sync(&hdw->encoder_run_timer);
8f59100a 2758 del_timer_sync(&hdw->encoder_wait_timer);
d855497e
MI		 2759 if (hdw->fw_buffer) {
2760 kfree(hdw->fw_buffer);
a0fd1cb1 2761 hdw->fw_buffer = NULL;
d855497e
MI		 2762 }
2763 if (hdw->vid_stream) {
2764 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2765 hdw->vid_stream = NULL;
d855497e 2766 }
d855497e 2767 pvr2_i2c_core_done(hdw);
b72b7bf5 2768 v4l2_device_unregister(&hdw->v4l2_dev);
d855497e 2769 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2770 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2771 if ((hdw->unit_number >= 0) &&
2772 (hdw->unit_number < PVR_NUM) &&
2773 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2774 unit_pointers[hdw->unit_number] = NULL;
d855497e 2775 }
8df0c87c 2776 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2777 kfree(hdw->controls);
2778 kfree(hdw->mpeg_ctrl_info);
2779 kfree(hdw->std_defs);
2780 kfree(hdw->std_enum_names);
d855497e
MI		 2781 kfree(hdw);
2782}
2783
2784
d855497e
MI		 2785int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2786{
2787 return (hdw && hdw->flag_ok);
2788}
2789
2790
2791/* Called when hardware has been unplugged */
2792void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2793{
2794 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2795 LOCK_TAKE(hdw->big_lock);
2796 LOCK_TAKE(hdw->ctl_lock);
2797 pvr2_hdw_remove_usb_stuff(hdw);
2798 LOCK_GIVE(hdw->ctl_lock);
2799 LOCK_GIVE(hdw->big_lock);
2800}
2801
2802
2803// Attempt to autoselect an appropriate value for std_enum_cur given
2804// whatever is currently in std_mask_cur
07e337ee 2805static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2806{
2807 unsigned int idx;
2808 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2809 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2810 hdw->std_enum_cur = idx;
2811 return;
2812 }
2813 }
2814 hdw->std_enum_cur = 0;
2815}
2816
2817
2818// Calculate correct set of enumerated standards based on currently known
2819// set of available standards bits.
07e337ee 2820static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2821{
2822 struct v4l2_standard *newstd;
2823 unsigned int std_cnt;
2824 unsigned int idx;
2825
2826 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2827
2828 if (hdw->std_defs) {
2829 kfree(hdw->std_defs);
a0fd1cb1 2830 hdw->std_defs = NULL;
d855497e
MI		 2831 }
2832 hdw->std_enum_cnt = 0;
2833 if (hdw->std_enum_names) {
2834 kfree(hdw->std_enum_names);
a0fd1cb1 2835 hdw->std_enum_names = NULL;
d855497e
MI		 2836 }
2837
2838 if (!std_cnt) {
2839 pvr2_trace(
2840 PVR2_TRACE_ERROR_LEGS,
2841 "WARNING: Failed to identify any viable standards");
2842 }
2843 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2844 hdw->std_enum_names[0] = "none";
2845 for (idx = 0; idx < std_cnt; idx++) {
2846 hdw->std_enum_names[idx+1] =
2847 newstd[idx].name;
2848 }
2849 // Set up the dynamic control for this standard
2850 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2851 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2852 hdw->std_defs = newstd;
2853 hdw->std_enum_cnt = std_cnt+1;
2854 hdw->std_enum_cur = 0;
2855 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2856}
2857
2858
2859int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2860 struct v4l2_standard *std,
2861 unsigned int idx)
2862{
2863 int ret = -EINVAL;
2864 if (!idx) return ret;
2865 LOCK_TAKE(hdw->big_lock); do {
2866 if (idx >= hdw->std_enum_cnt) break;
2867 idx--;
2868 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2869 ret = 0;
2870 } while (0); LOCK_GIVE(hdw->big_lock);
2871 return ret;
2872}
2873
2874
2875/* Get the number of defined controls */
2876unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2877{
c05c0462 2878 return hdw->control_cnt;
d855497e
MI		 2879}
2880
2881
2882/* Retrieve a control handle given its index (0..count-1) */
2883struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2884 unsigned int idx)
2885{
a0fd1cb1 2886 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2887 return hdw->controls + idx;
2888}
2889
2890
2891/* Retrieve a control handle given its index (0..count-1) */
2892struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2893 unsigned int ctl_id)
2894{
2895 struct pvr2_ctrl *cptr;
2896 unsigned int idx;
2897 int i;
2898
2899 /* This could be made a lot more efficient, but for now... */
c05c0462 2900 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2901 cptr = hdw->controls + idx;
2902 i = cptr->info->internal_id;
2903 if (i && (i == ctl_id)) return cptr;
2904 }
a0fd1cb1 2905 return NULL;
d855497e
MI		 2906}
2907
2908
a761f431 2909/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2910struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2911{
2912 struct pvr2_ctrl *cptr;
2913 unsigned int idx;
2914 int i;
2915
2916 /* This could be made a lot more efficient, but for now... */
c05c0462 2917 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2918 cptr = hdw->controls + idx;
2919 i = cptr->info->v4l_id;
2920 if (i && (i == ctl_id)) return cptr;
2921 }
a0fd1cb1 2922 return NULL;
d855497e
MI		 2923}
2924
2925
a761f431
MI		 2926/* Given a V4L ID for its immediate predecessor, retrieve the control
2927 structure associated with it. */
2928struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2929 unsigned int ctl_id)
2930{
2931 struct pvr2_ctrl *cptr,*cp2;
2932 unsigned int idx;
2933 int i;
2934
2935 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2936 cp2 = NULL;
a761f431
MI		 2937 for (idx = 0; idx < hdw->control_cnt; idx++) {
2938 cptr = hdw->controls + idx;
2939 i = cptr->info->v4l_id;
2940 if (!i) continue;
2941 if (i <= ctl_id) continue;
2942 if (cp2 && (cp2->info->v4l_id < i)) continue;
2943 cp2 = cptr;
2944 }
2945 return cp2;
a0fd1cb1 2946 return NULL;
a761f431
MI		 2947}
2948
2949
d855497e
MI		 2950static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2951{
2952 switch (tp) {
2953 case pvr2_ctl_int: return "integer";
2954 case pvr2_ctl_enum: return "enum";
33213963 2955 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2956 case pvr2_ctl_bitmask: return "bitmask";
2957 }
2958 return "";
2959}
2960
2961
2641df36
MI		 2962static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2963 const char *name, int val)
2964{
2965 struct v4l2_control ctrl;
2966 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2967 memset(&ctrl, 0, sizeof(ctrl));
2968 ctrl.id = id;
2969 ctrl.value = val;
2970 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2971}
2972
2973#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
27764726 2974 if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \
2641df36
MI		 2975 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2976 }
2977
5ceaad14 2978/* Execute whatever commands are required to update the state of all the
2641df36 2979 sub-devices so that they match our current control values. */
5ceaad14
MI		 2980static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2981{
edb9dcb8
MI		 2982 struct v4l2_subdev *sd;
2983 unsigned int id;
2984 pvr2_subdev_update_func fp;
2985
75212a02
MI		 2986 pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2987
27764726 2988 if (hdw->tuner_updated || hdw->force_dirty) {
75212a02
MI		 2989 struct tuner_setup setup;
2990 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2991 hdw->tuner_type);
2992 if (((int)(hdw->tuner_type)) >= 0) {
fcd62cf7 2993 memset(&setup, 0, sizeof(setup));
75212a02
MI		 2994 setup.addr = ADDR_UNSET;
2995 setup.type = hdw->tuner_type;
2996 setup.mode_mask = T_RADIO | T_ANALOG_TV;
2997 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2998 tuner, s_type_addr, &setup);
2999 }
3000 }
3001
27764726 3002 if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
b481880b 3003 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2641df36
MI		 3004 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3005 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3006 tuner, s_radio);
3007 } else {
3008 v4l2_std_id vs;
3009 vs = hdw->std_mask_cur;
3010 v4l2_device_call_all(&hdw->v4l2_dev, 0,
f41737ec 3011 core, s_std, vs);
a6862da2 3012 pvr2_hdw_cx25840_vbi_hack(hdw);
2641df36
MI		 3013 }
3014 hdw->tuner_signal_stale = !0;
3015 hdw->cropcap_stale = !0;
3016 }
3017
3018 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
3019 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
3020 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
3021 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
3022 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
3023 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
3024 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
3025 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
3026 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
3027
27764726 3028 if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2641df36
MI		 3029 struct v4l2_tuner vt;
3030 memset(&vt, 0, sizeof(vt));
3031 vt.audmode = hdw->audiomode_val;
3032 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
3033 }
3034
27764726 3035 if (hdw->freqDirty || hdw->force_dirty) {
2641df36
MI		 3036 unsigned long fv;
3037 struct v4l2_frequency freq;
3038 fv = pvr2_hdw_get_cur_freq(hdw);
3039 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
3040 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
3041 memset(&freq, 0, sizeof(freq));
3042 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
3043 /* ((fv * 1000) / 62500) */
3044 freq.frequency = (fv * 2) / 125;
3045 } else {
3046 freq.frequency = fv / 62500;
3047 }
3048 /* tuner-core currently doesn't seem to care about this, but
3049 let's set it anyway for completeness. */
3050 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3051 freq.type = V4L2_TUNER_RADIO;
3052 } else {
3053 freq.type = V4L2_TUNER_ANALOG_TV;
3054 }
3055 freq.tuner = 0;
3056 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
3057 s_frequency, &freq);
3058 }
3059
27764726 3060 if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
2641df36
MI		 3061 struct v4l2_format fmt;
3062 memset(&fmt, 0, sizeof(fmt));
3063 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
3064 fmt.fmt.pix.width = hdw->res_hor_val;
3065 fmt.fmt.pix.height = hdw->res_ver_val;
7dfdf1ee 3066 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
2641df36
MI		 3067 fmt.fmt.pix.width, fmt.fmt.pix.height);
3068 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
3069 }
3070
27764726 3071 if (hdw->srate_dirty || hdw->force_dirty) {
01c59df8
MI		 3072 u32 val;
3073 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3074 hdw->srate_val);
3075 switch (hdw->srate_val) {
3076 default:
3077 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3078 val = 48000;
3079 break;
3080 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3081 val = 44100;
3082 break;
3083 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3084 val = 32000;
3085 break;
3086 }
3087 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3088 audio, s_clock_freq, val);
3089 }
3090
2641df36
MI		 3091 /* Unable to set crop parameters; there is apparently no equivalent
3092 for VIDIOC_S_CROP */
3093
edb9dcb8
MI		 3094 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3095 id = sd->grp_id;
3096 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3097 fp = pvr2_module_update_functions[id];
3098 if (!fp) continue;
3099 (*fp)(hdw, sd);
3100 }
2641df36 3101
27764726 3102 if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
2641df36
MI		 3103 pvr2_hdw_status_poll(hdw);
3104 }
5ceaad14
MI		 3105}
3106
3107
681c7399
MI		 3108/* Figure out if we need to commit control changes. If so, mark internal
3109 state flags to indicate this fact and return true. Otherwise do nothing
3110 else and return false. */
3111static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 3112{
d855497e
MI		 3113 unsigned int idx;
3114 struct pvr2_ctrl *cptr;
3115 int value;
27764726 3116 int commit_flag = hdw->force_dirty;
d855497e
MI		 3117 char buf[100];
3118 unsigned int bcnt,ccnt;
3119
c05c0462 3120 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e 3121 cptr = hdw->controls + idx;
5fa1247a 3122 if (!cptr->info->is_dirty) continue;
d855497e 3123 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 3124 commit_flag = !0;
d855497e 3125
fe23a280 3126 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 3127 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3128 cptr->info->name);
3129 value = 0;
3130 cptr->info->get_value(cptr,&value);
3131 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3132 buf+bcnt,
3133 sizeof(buf)-bcnt,&ccnt);
3134 bcnt += ccnt;
3135 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3136 get_ctrl_typename(cptr->info->type));
3137 pvr2_trace(PVR2_TRACE_CTL,
3138 "/*--TRACE_COMMIT--*/ %.*s",
3139 bcnt,buf);
3140 }
3141
3142 if (!commit_flag) {
3143 /* Nothing has changed */
3144 return 0;
3145 }
3146
681c7399
MI		 3147 hdw->state_pipeline_config = 0;
3148 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3149 pvr2_hdw_state_sched(hdw);
3150
3151 return !0;
3152}
3153
3154
3155/* Perform all operations needed to commit all control changes. This must
3156 be performed in synchronization with the pipeline state and is thus
3157 expected to be called as part of the driver's worker thread. Return
3158 true if commit successful, otherwise return false to indicate that
3159 commit isn't possible at this time. */
3160static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3161{
3162 unsigned int idx;
3163 struct pvr2_ctrl *cptr;
3164 int disruptive_change;
3165
ab062fe3
MI		 3166 /* Handle some required side effects when the video standard is
3167 changed.... */
d855497e 3168 if (hdw->std_dirty) {
d855497e 3169 int nvres;
00528d9c 3170 int gop_size;
d855497e
MI		 3171 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3172 nvres = 480;
00528d9c 3173 gop_size = 15;
d855497e
MI		 3174 } else {
3175 nvres = 576;
00528d9c 3176 gop_size = 12;
d855497e 3177 }
00528d9c
MI		 3178 /* Rewrite the vertical resolution to be appropriate to the
3179 video standard that has been selected. */
d855497e
MI		 3180 if (nvres != hdw->res_ver_val) {
3181 hdw->res_ver_val = nvres;
3182 hdw->res_ver_dirty = !0;
3183 }
00528d9c
MI		 3184 /* Rewrite the GOP size to be appropriate to the video
3185 standard that has been selected. */
3186 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3187 struct v4l2_ext_controls cs;
3188 struct v4l2_ext_control c1;
3189 memset(&cs, 0, sizeof(cs));
3190 memset(&c1, 0, sizeof(c1));
3191 cs.controls = &c1;
3192 cs.count = 1;
3193 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3194 c1.value = gop_size;
3195 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3196 VIDIOC_S_EXT_CTRLS);
3197 }
d855497e
MI		 3198 }
3199
38d9a2cf 3200 if (hdw->input_dirty && hdw->state_pathway_ok &&
62433e31
MI		 3201 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3202 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3203 hdw->pathway_state)) {
3204 /* Change of mode being asked for... */
3205 hdw->state_pathway_ok = 0;
e9db1ff2 3206 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 3207 }
3208 if (!hdw->state_pathway_ok) {
3209 /* Can't commit anything until pathway is ok. */
3210 return 0;
3211 }
e784bfb9 3212 /* The broadcast decoder can only scale down, so if
3213 * res_*_dirty && crop window < output format ==> enlarge crop.
3214 *
3215 * The mpeg encoder receives fields of res_hor_val dots and
3216 * res_ver_val halflines. Limits: hor<=720, ver<=576.
3217 */
3218 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3219 hdw->cropw_val = hdw->res_hor_val;
3220 hdw->cropw_dirty = !0;
3221 } else if (hdw->cropw_dirty) {
3222 hdw->res_hor_dirty = !0; /* must rescale */
3223 hdw->res_hor_val = min(720, hdw->cropw_val);
3224 }
3225 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3226 hdw->croph_val = hdw->res_ver_val;
3227 hdw->croph_dirty = !0;
3228 } else if (hdw->croph_dirty) {
3229 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3230 hdw->res_ver_dirty = !0;
3231 hdw->res_ver_val = min(nvres, hdw->croph_val);
3232 }
3233
681c7399
MI		 3234 /* If any of the below has changed, then we can't do the update
3235 while the pipeline is running. Pipeline must be paused first
3236 and decoder -> encoder connection be made quiescent before we
3237 can proceed. */
3238 disruptive_change =
3239 (hdw->std_dirty ||
3240 hdw->enc_unsafe_stale ||
3241 hdw->srate_dirty ||
3242 hdw->res_ver_dirty ||
3243 hdw->res_hor_dirty ||
755879c6
MI		 3244 hdw->cropw_dirty ||
3245 hdw->croph_dirty ||
681c7399
MI		 3246 hdw->input_dirty ||
3247 (hdw->active_stream_type != hdw->desired_stream_type));
3248 if (disruptive_change && !hdw->state_pipeline_idle) {
3249 /* Pipeline is not idle; we can't proceed. Arrange to
3250 cause pipeline to stop so that we can try this again
3251 later.... */
3252 hdw->state_pipeline_pause = !0;
3253 return 0;
275b2e28
PK		 3254 }
3255
b30d2441
MI		 3256 if (hdw->srate_dirty) {
3257 /* Write new sample rate into control structure since
3258 * the master copy is stale. We must track srate
3259 * separate from the mpeg control structure because
3260 * other logic also uses this value. */
3261 struct v4l2_ext_controls cs;
3262 struct v4l2_ext_control c1;
3263 memset(&cs,0,sizeof(cs));
3264 memset(&c1,0,sizeof(c1));
3265 cs.controls = &c1;
3266 cs.count = 1;
3267 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3268 c1.value = hdw->srate_val;
01f1e44f 3269 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 3270 }
c05c0462 3271
681c7399
MI		 3272 if (hdw->active_stream_type != hdw->desired_stream_type) {
3273 /* Handle any side effects of stream config here */
3274 hdw->active_stream_type = hdw->desired_stream_type;
3275 }
3276
1df59f0b
MI		 3277 if (hdw->hdw_desc->signal_routing_scheme ==
3278 PVR2_ROUTING_SCHEME_GOTVIEW) {
3279 u32 b;
3280 /* Handle GOTVIEW audio switching */
3281 pvr2_hdw_gpio_get_out(hdw,&b);
3282 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3283 /* Set GPIO 11 */
3284 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3285 } else {
3286 /* Clear GPIO 11 */
3287 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3288 }
3289 }
3290
e68a619a
MI		 3291 /* Check and update state for all sub-devices. */
3292 pvr2_subdev_update(hdw);
3293
75212a02 3294 hdw->tuner_updated = 0;
27764726 3295 hdw->force_dirty = 0;
5ceaad14
MI		 3296 for (idx = 0; idx < hdw->control_cnt; idx++) {
3297 cptr = hdw->controls + idx;
3298 if (!cptr->info->clear_dirty) continue;
3299 cptr->info->clear_dirty(cptr);
3300 }
3301
62433e31
MI		 3302 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3303 hdw->state_encoder_run) {
3304 /* If encoder isn't running or it can't be touched, then
3305 this will get worked out later when we start the
3306 encoder. */
681c7399
MI		 3307 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3308 }
d855497e 3309
681c7399 3310 hdw->state_pipeline_config = !0;
432907f7
MI		 3311 /* Hardware state may have changed in a way to cause the cropping
3312 capabilities to have changed. So mark it stale, which will
3313 cause a later re-fetch. */
681c7399
MI		 3314 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3315 return !0;
d855497e
MI		 3316}
3317
3318
3319int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3320{
681c7399
MI		 3321 int fl;
3322 LOCK_TAKE(hdw->big_lock);
3323 fl = pvr2_hdw_commit_setup(hdw);
3324 LOCK_GIVE(hdw->big_lock);
3325 if (!fl) return 0;
3326 return pvr2_hdw_wait(hdw,0);
3327}
3328
3329
681c7399 3330static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 3331{
681c7399
MI		 3332 int fl = 0;
3333 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 3334 LOCK_TAKE(hdw->big_lock); do {
681c7399 3335 fl = pvr2_hdw_state_eval(hdw);
d855497e 3336 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 3337 if (fl && hdw->state_func) {
3338 hdw->state_func(hdw->state_data);
3339 }
d855497e
MI		 3340}
3341
3342
681c7399 3343static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 3344{
681c7399
MI		 3345 return wait_event_interruptible(
3346 hdw->state_wait_data,
3347 (hdw->state_stale == 0) &&
3348 (!state || (hdw->master_state != state)));
3349}
3350
3351
d855497e
MI		 3352/* Return name for this driver instance */
3353const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3354{
3355 return hdw->name;
3356}
3357
3358
78a47101
MI		 3359const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3360{
3361 return hdw->hdw_desc->description;
3362}
3363
3364
3365const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3366{
3367 return hdw->hdw_desc->shortname;
3368}
3369
3370
d855497e
MI		 3371int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3372{
3373 int result;
3374 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3375 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 3376 result = pvr2_send_request(hdw,
3377 hdw->cmd_buffer,1,
3378 hdw->cmd_buffer,1);
3379 if (result < 0) break;
3380 result = (hdw->cmd_buffer[0] != 0);
3381 } while(0); LOCK_GIVE(hdw->ctl_lock);
3382 return result;
3383}
3384
3385
18103c57
MI		 3386/* Execute poll of tuner status */
3387void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 3388{
d855497e 3389 LOCK_TAKE(hdw->big_lock); do {
a51f5000 3390 pvr2_hdw_status_poll(hdw);
d855497e 3391 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 3392}
3393
3394
432907f7
MI		 3395static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3396{
3397 if (!hdw->cropcap_stale) {
432907f7
MI		 3398 return 0;
3399 }
a51f5000 3400 pvr2_hdw_status_poll(hdw);
432907f7 3401 if (hdw->cropcap_stale) {
432907f7
MI		 3402 return -EIO;
3403 }
3404 return 0;
3405}
3406
3407
3408/* Return information about cropping capabilities */
3409int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3410{
3411 int stat = 0;
3412 LOCK_TAKE(hdw->big_lock);
3413 stat = pvr2_hdw_check_cropcap(hdw);
3414 if (!stat) {
432907f7
MI		 3415 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3416 }
3417 LOCK_GIVE(hdw->big_lock);
3418 return stat;
3419}
3420
3421
18103c57
MI		 3422/* Return information about the tuner */
3423int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3424{
3425 LOCK_TAKE(hdw->big_lock); do {
3426 if (hdw->tuner_signal_stale) {
a51f5000 3427 pvr2_hdw_status_poll(hdw);
18103c57
MI		 3428 }
3429 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3430 } while (0); LOCK_GIVE(hdw->big_lock);
3431 return 0;
d855497e
MI		 3432}
3433
3434
3435/* Get handle to video output stream */
3436struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3437{
3438 return hp->vid_stream;
3439}
3440
3441
3442void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3443{
4f1a3e5b 3444 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e 3445 LOCK_TAKE(hdw->big_lock); do {
4f1a3e5b 3446 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
ed3261a8 3447 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
b30d2441 3448 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 3449 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 3450 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 3451 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 3452 } while (0); LOCK_GIVE(hdw->big_lock);
3453}
3454
4db666cc
MI		 3455
3456/* Grab EEPROM contents, needed for direct method. */
3457#define EEPROM_SIZE 8192
3458#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3459static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3460{
3461 struct i2c_msg msg[2];
3462 u8 *eeprom;
3463 u8 iadd[2];
3464 u8 addr;
3465 u16 eepromSize;
3466 unsigned int offs;
3467 int ret;
3468 int mode16 = 0;
3469 unsigned pcnt,tcnt;
3470 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3471 if (!eeprom) {
3472 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3473 "Failed to allocate memory"
3474 " required to read eeprom");
3475 return NULL;
3476 }
3477
3478 trace_eeprom("Value for eeprom addr from controller was 0x%x",
3479 hdw->eeprom_addr);
3480 addr = hdw->eeprom_addr;
3481 /* Seems that if the high bit is set, then the *real* eeprom
3482 address is shifted right now bit position (noticed this in
3483 newer PVR USB2 hardware) */
3484 if (addr & 0x80) addr >>= 1;
3485
3486 /* FX2 documentation states that a 16bit-addressed eeprom is
3487 expected if the I2C address is an odd number (yeah, this is
3488 strange but it's what they do) */
3489 mode16 = (addr & 1);
3490 eepromSize = (mode16 ? EEPROM_SIZE : 256);
3491 trace_eeprom("Examining %d byte eeprom at location 0x%x"
3492 " using %d bit addressing",eepromSize,addr,
3493 mode16 ? 16 : 8);
3494
3495 msg[0].addr = addr;
3496 msg[0].flags = 0;
3497 msg[0].len = mode16 ? 2 : 1;
3498 msg[0].buf = iadd;
3499 msg[1].addr = addr;
3500 msg[1].flags = I2C_M_RD;
3501
3502 /* We have to do the actual eeprom data fetch ourselves, because
3503 (1) we're only fetching part of the eeprom, and (2) if we were
3504 getting the whole thing our I2C driver can't grab it in one
3505 pass - which is what tveeprom is otherwise going to attempt */
3506 memset(eeprom,0,EEPROM_SIZE);
3507 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3508 pcnt = 16;
3509 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3510 offs = tcnt + (eepromSize - EEPROM_SIZE);
3511 if (mode16) {
3512 iadd[0] = offs >> 8;
3513 iadd[1] = offs;
3514 } else {
3515 iadd[0] = offs;
3516 }
3517 msg[1].len = pcnt;
3518 msg[1].buf = eeprom+tcnt;
3519 if ((ret = i2c_transfer(&hdw->i2c_adap,
3520 msg,ARRAY_SIZE(msg))) != 2) {
3521 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3522 "eeprom fetch set offs err=%d",ret);
3523 kfree(eeprom);
3524 return NULL;
3525 }
3526 }
3527 return eeprom;
3528}
3529
3530
3531void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
568efaa2 3532 int mode,
4db666cc 3533 int enable_flag)
d855497e
MI		 3534{
3535 int ret;
3536 u16 address;
3537 unsigned int pipe;
3538 LOCK_TAKE(hdw->big_lock); do {
5fa1247a 3539 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
d855497e
MI		 3540
3541 if (!enable_flag) {
3542 pvr2_trace(PVR2_TRACE_FIRMWARE,
3543 "Cleaning up after CPU firmware fetch");
3544 kfree(hdw->fw_buffer);
a0fd1cb1 3545 hdw->fw_buffer = NULL;
d855497e 3546 hdw->fw_size = 0;
4db666cc
MI		 3547 if (hdw->fw_cpu_flag) {
3548 /* Now release the CPU. It will disconnect
3549 and reconnect later. */
3550 pvr2_hdw_cpureset_assert(hdw,0);
3551 }
d855497e
MI		 3552 break;
3553 }
3554
568efaa2 3555 hdw->fw_cpu_flag = (mode != 2);
4db666cc 3556 if (hdw->fw_cpu_flag) {
568efaa2 3557 hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
4db666cc 3558 pvr2_trace(PVR2_TRACE_FIRMWARE,
568efaa2
MI		 3559 "Preparing to suck out CPU firmware"
3560 " (size=%u)", hdw->fw_size);
4db666cc
MI		 3561 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3562 if (!hdw->fw_buffer) {
3563 hdw->fw_size = 0;
3564 break;
3565 }
d855497e 3566
4db666cc
MI		 3567 /* We have to hold the CPU during firmware upload. */
3568 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 3569
4db666cc
MI		 3570 /* download the firmware from address 0000-1fff in 2048
3571 (=0x800) bytes chunk. */
d855497e 3572
4db666cc
MI		 3573 pvr2_trace(PVR2_TRACE_FIRMWARE,
3574 "Grabbing CPU firmware");
3575 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3576 for(address = 0; address < hdw->fw_size;
3577 address += 0x800) {
3578 ret = usb_control_msg(hdw->usb_dev,pipe,
3579 0xa0,0xc0,
3580 address,0,
3581 hdw->fw_buffer+address,
3582 0x800,HZ);
3583 if (ret < 0) break;
3584 }
d855497e 3585
4db666cc
MI		 3586 pvr2_trace(PVR2_TRACE_FIRMWARE,
3587 "Done grabbing CPU firmware");
3588 } else {
3589 pvr2_trace(PVR2_TRACE_FIRMWARE,
3590 "Sucking down EEPROM contents");
3591 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3592 if (!hdw->fw_buffer) {
3593 pvr2_trace(PVR2_TRACE_FIRMWARE,
3594 "EEPROM content suck failed.");
3595 break;
3596 }
3597 hdw->fw_size = EEPROM_SIZE;
3598 pvr2_trace(PVR2_TRACE_FIRMWARE,
3599 "Done sucking down EEPROM contents");
3600 }
d855497e
MI		 3601
3602 } while (0); LOCK_GIVE(hdw->big_lock);
3603}
3604
3605
3606/* Return true if we're in a mode for retrieval CPU firmware */
3607int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3608{
5fa1247a 3609 return hdw->fw_buffer != NULL;
d855497e
MI		 3610}
3611
3612
3613int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3614 char *buf,unsigned int cnt)
3615{
3616 int ret = -EINVAL;
3617 LOCK_TAKE(hdw->big_lock); do {
3618 if (!buf) break;
3619 if (!cnt) break;
3620
3621 if (!hdw->fw_buffer) {
3622 ret = -EIO;
3623 break;
3624 }
3625
3626 if (offs >= hdw->fw_size) {
3627 pvr2_trace(PVR2_TRACE_FIRMWARE,
3628 "Read firmware data offs=%d EOF",
3629 offs);
3630 ret = 0;
3631 break;
3632 }
3633
3634 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3635
3636 memcpy(buf,hdw->fw_buffer+offs,cnt);
3637
3638 pvr2_trace(PVR2_TRACE_FIRMWARE,
3639 "Read firmware data offs=%d cnt=%d",
3640 offs,cnt);
3641 ret = cnt;
3642 } while (0); LOCK_GIVE(hdw->big_lock);
3643
3644 return ret;
3645}
3646
3647
fd5a75fe 3648int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 3649 enum pvr2_v4l_type index)
d855497e 3650{
fd5a75fe 3651 switch (index) {
8079384e
MI		 3652 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3653 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3654 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 3655 default: return -1;
3656 }
d855497e
MI		 3657}
3658
3659
2fdf3d9c 3660/* Store a v4l minor device number */
fd5a75fe 3661void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 3662 enum pvr2_v4l_type index,int v)
d855497e 3663{
fd5a75fe 3664 switch (index) {
8079384e
MI		 3665 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3666 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3667 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 3668 default: break;
3669 }
d855497e
MI		 3670}
3671
3672
7d12e780 3673static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 3674{
3675 struct pvr2_hdw *hdw = urb->context;
3676 hdw->ctl_write_pend_flag = 0;
3677 if (hdw->ctl_read_pend_flag) return;
3678 complete(&hdw->ctl_done);
3679}
3680
3681
7d12e780 3682static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 3683{
3684 struct pvr2_hdw *hdw = urb->context;
3685 hdw->ctl_read_pend_flag = 0;
3686 if (hdw->ctl_write_pend_flag) return;
3687 complete(&hdw->ctl_done);
3688}
3689
3690
3691static void pvr2_ctl_timeout(unsigned long data)
3692{
3693 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3694 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3695 hdw->ctl_timeout_flag = !0;
5e55d2ce 3696 if (hdw->ctl_write_pend_flag)
d855497e 3697 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 3698 if (hdw->ctl_read_pend_flag)
d855497e 3699 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 3700 }
3701}
3702
3703
e61b6fc5
MI		 3704/* Issue a command and get a response from the device. This extended
3705 version includes a probe flag (which if set means that device errors
3706 should not be logged or treated as fatal) and a timeout in jiffies.
3707 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 3708static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3709 unsigned int timeout,int probe_fl,
3710 void *write_data,unsigned int write_len,
3711 void *read_data,unsigned int read_len)
d855497e
MI		 3712{
3713 unsigned int idx;
3714 int status = 0;
3715 struct timer_list timer;
3716 if (!hdw->ctl_lock_held) {
3717 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3718 "Attempted to execute control transfer"
3719 " without lock!!");
3720 return -EDEADLK;
3721 }
681c7399 3722 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 3723 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3724 "Attempted to execute control transfer"
3725 " when device not ok");
3726 return -EIO;
3727 }
3728 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3729 if (!probe_fl) {
3730 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3731 "Attempted to execute control transfer"
3732 " when USB is disconnected");
3733 }
3734 return -ENOTTY;
3735 }
3736
3737 /* Ensure that we have sane parameters */
3738 if (!write_data) write_len = 0;
3739 if (!read_data) read_len = 0;
3740 if (write_len > PVR2_CTL_BUFFSIZE) {
3741 pvr2_trace(
3742 PVR2_TRACE_ERROR_LEGS,
3743 "Attempted to execute %d byte"
3744 " control-write transfer (limit=%d)",
3745 write_len,PVR2_CTL_BUFFSIZE);
3746 return -EINVAL;
3747 }
3748 if (read_len > PVR2_CTL_BUFFSIZE) {
3749 pvr2_trace(
3750 PVR2_TRACE_ERROR_LEGS,
3751 "Attempted to execute %d byte"
3752 " control-read transfer (limit=%d)",
3753 write_len,PVR2_CTL_BUFFSIZE);
3754 return -EINVAL;
3755 }
3756 if ((!write_len) && (!read_len)) {
3757 pvr2_trace(
3758 PVR2_TRACE_ERROR_LEGS,
3759 "Attempted to execute null control transfer?");
3760 return -EINVAL;
3761 }
3762
3763
3764 hdw->cmd_debug_state = 1;
3765 if (write_len) {
3766 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3767 } else {
3768 hdw->cmd_debug_code = 0;
3769 }
3770 hdw->cmd_debug_write_len = write_len;
3771 hdw->cmd_debug_read_len = read_len;
3772
3773 /* Initialize common stuff */
3774 init_completion(&hdw->ctl_done);
3775 hdw->ctl_timeout_flag = 0;
3776 hdw->ctl_write_pend_flag = 0;
3777 hdw->ctl_read_pend_flag = 0;
3778 init_timer(&timer);
3779 timer.expires = jiffies + timeout;
3780 timer.data = (unsigned long)hdw;
3781 timer.function = pvr2_ctl_timeout;
3782
3783 if (write_len) {
3784 hdw->cmd_debug_state = 2;
3785 /* Transfer write data to internal buffer */
3786 for (idx = 0; idx < write_len; idx++) {
3787 hdw->ctl_write_buffer[idx] =
3788 ((unsigned char *)write_data)[idx];
3789 }
3790 /* Initiate a write request */
3791 usb_fill_bulk_urb(hdw->ctl_write_urb,
3792 hdw->usb_dev,
3793 usb_sndbulkpipe(hdw->usb_dev,
3794 PVR2_CTL_WRITE_ENDPOINT),
3795 hdw->ctl_write_buffer,
3796 write_len,
3797 pvr2_ctl_write_complete,
3798 hdw);
3799 hdw->ctl_write_urb->actual_length = 0;
3800 hdw->ctl_write_pend_flag = !0;
3801 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3802 if (status < 0) {
3803 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3804 "Failed to submit write-control"
3805 " URB status=%d",status);
3806 hdw->ctl_write_pend_flag = 0;
3807 goto done;
3808 }
3809 }
3810
3811 if (read_len) {
3812 hdw->cmd_debug_state = 3;
3813 memset(hdw->ctl_read_buffer,0x43,read_len);
3814 /* Initiate a read request */
3815 usb_fill_bulk_urb(hdw->ctl_read_urb,
3816 hdw->usb_dev,
3817 usb_rcvbulkpipe(hdw->usb_dev,
3818 PVR2_CTL_READ_ENDPOINT),
3819 hdw->ctl_read_buffer,
3820 read_len,
3821 pvr2_ctl_read_complete,
3822 hdw);
3823 hdw->ctl_read_urb->actual_length = 0;
3824 hdw->ctl_read_pend_flag = !0;
3825 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3826 if (status < 0) {
3827 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3828 "Failed to submit read-control"
3829 " URB status=%d",status);
3830 hdw->ctl_read_pend_flag = 0;
3831 goto done;
3832 }
3833 }
3834
3835 /* Start timer */
3836 add_timer(&timer);
3837
3838 /* Now wait for all I/O to complete */
3839 hdw->cmd_debug_state = 4;
3840 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3841 wait_for_completion(&hdw->ctl_done);
3842 }
3843 hdw->cmd_debug_state = 5;
3844
3845 /* Stop timer */
3846 del_timer_sync(&timer);
3847
3848 hdw->cmd_debug_state = 6;
3849 status = 0;
3850
3851 if (hdw->ctl_timeout_flag) {
3852 status = -ETIMEDOUT;
3853 if (!probe_fl) {
3854 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3855 "Timed out control-write");
3856 }
3857 goto done;
3858 }
3859
3860 if (write_len) {
3861 /* Validate results of write request */
3862 if ((hdw->ctl_write_urb->status != 0) &&
3863 (hdw->ctl_write_urb->status != -ENOENT) &&
3864 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3865 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3866 /* USB subsystem is reporting some kind of failure
3867 on the write */
3868 status = hdw->ctl_write_urb->status;
3869 if (!probe_fl) {
3870 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3871 "control-write URB failure,"
3872 " status=%d",
3873 status);
3874 }
3875 goto done;
3876 }
3877 if (hdw->ctl_write_urb->actual_length < write_len) {
3878 /* Failed to write enough data */
3879 status = -EIO;
3880 if (!probe_fl) {
3881 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3882 "control-write URB short,"
3883 " expected=%d got=%d",
3884 write_len,
3885 hdw->ctl_write_urb->actual_length);
3886 }
3887 goto done;
3888 }
3889 }
3890 if (read_len) {
3891 /* Validate results of read request */
3892 if ((hdw->ctl_read_urb->status != 0) &&
3893 (hdw->ctl_read_urb->status != -ENOENT) &&
3894 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3895 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3896 /* USB subsystem is reporting some kind of failure
3897 on the read */
3898 status = hdw->ctl_read_urb->status;
3899 if (!probe_fl) {
3900 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3901 "control-read URB failure,"
3902 " status=%d",
3903 status);
3904 }
3905 goto done;
3906 }
3907 if (hdw->ctl_read_urb->actual_length < read_len) {
3908 /* Failed to read enough data */
3909 status = -EIO;
3910 if (!probe_fl) {
3911 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3912 "control-read URB short,"
3913 " expected=%d got=%d",
3914 read_len,
3915 hdw->ctl_read_urb->actual_length);
3916 }
3917 goto done;
3918 }
3919 /* Transfer retrieved data out from internal buffer */
3920 for (idx = 0; idx < read_len; idx++) {
3921 ((unsigned char *)read_data)[idx] =
3922 hdw->ctl_read_buffer[idx];
3923 }
3924 }
3925
3926 done:
3927
3928 hdw->cmd_debug_state = 0;
3929 if ((status < 0) && (!probe_fl)) {
681c7399 3930 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3931 }
3932 return status;
3933}
3934
3935
3936int pvr2_send_request(struct pvr2_hdw *hdw,
3937 void *write_data,unsigned int write_len,
3938 void *read_data,unsigned int read_len)
3939{
3940 return pvr2_send_request_ex(hdw,HZ*4,0,
3941 write_data,write_len,
3942 read_data,read_len);
3943}
3944
1c9d10d4
MI		 3945
3946static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3947{
3948 int ret;
3949 unsigned int cnt = 1;
3950 unsigned int args = 0;
3951 LOCK_TAKE(hdw->ctl_lock);
3952 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3953 args = (cmdcode >> 8) & 0xffu;
3954 args = (args > 2) ? 2 : args;
3955 if (args) {
3956 cnt += args;
3957 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3958 if (args > 1) {
3959 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3960 }
3961 }
3962 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3963 unsigned int idx;
3964 unsigned int ccnt,bcnt;
3965 char tbuf[50];
3966 cmdcode &= 0xffu;
3967 bcnt = 0;
3968 ccnt = scnprintf(tbuf+bcnt,
3969 sizeof(tbuf)-bcnt,
3970 "Sending FX2 command 0x%x",cmdcode);
3971 bcnt += ccnt;
3972 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3973 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3974 ccnt = scnprintf(tbuf+bcnt,
3975 sizeof(tbuf)-bcnt,
3976 " \"%s\"",
3977 pvr2_fx2cmd_desc[idx].desc);
3978 bcnt += ccnt;
3979 break;
3980 }
3981 }
3982 if (args) {
3983 ccnt = scnprintf(tbuf+bcnt,
3984 sizeof(tbuf)-bcnt,
3985 " (%u",hdw->cmd_buffer[1]);
3986 bcnt += ccnt;
3987 if (args > 1) {
3988 ccnt = scnprintf(tbuf+bcnt,
3989 sizeof(tbuf)-bcnt,
3990 ",%u",hdw->cmd_buffer[2]);
3991 bcnt += ccnt;
3992 }
3993 ccnt = scnprintf(tbuf+bcnt,
3994 sizeof(tbuf)-bcnt,
3995 ")");
3996 bcnt += ccnt;
3997 }
3998 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3999 }
4000 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
4001 LOCK_GIVE(hdw->ctl_lock);
4002 return ret;
4003}
4004
4005
d855497e
MI		 4006int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
4007{
4008 int ret;
4009
4010 LOCK_TAKE(hdw->ctl_lock);
4011
8d364363 4012 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 4013 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
4014 hdw->cmd_buffer[5] = 0;
4015 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4016 hdw->cmd_buffer[7] = reg & 0xff;
4017
4018
4019 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
4020
4021 LOCK_GIVE(hdw->ctl_lock);
4022
4023 return ret;
4024}
4025
4026
07e337ee 4027static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 4028{
4029 int ret = 0;
4030
4031 LOCK_TAKE(hdw->ctl_lock);
4032
8d364363 4033 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 4034 hdw->cmd_buffer[1] = 0;
4035 hdw->cmd_buffer[2] = 0;
4036 hdw->cmd_buffer[3] = 0;
4037 hdw->cmd_buffer[4] = 0;
4038 hdw->cmd_buffer[5] = 0;
4039 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4040 hdw->cmd_buffer[7] = reg & 0xff;
4041
4042 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
4043 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
4044
4045 LOCK_GIVE(hdw->ctl_lock);
4046
4047 return ret;
4048}
4049
4050
681c7399 4051void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 4052{
4053 if (!hdw->flag_ok) return;
681c7399
MI		 4054 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4055 "Device being rendered inoperable");
d855497e 4056 if (hdw->vid_stream) {
a0fd1cb1 4057 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 4058 }
681c7399
MI		 4059 hdw->flag_ok = 0;
4060 trace_stbit("flag_ok",hdw->flag_ok);
4061 pvr2_hdw_state_sched(hdw);
d855497e
MI		 4062}
4063
4064
4065void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4066{
4067 int ret;
4068 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 4069 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
011b15df 4070 if (ret == 0) {
d855497e
MI		 4071 ret = usb_reset_device(hdw->usb_dev);
4072 usb_unlock_device(hdw->usb_dev);
4073 } else {
4074 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4075 "Failed to lock USB device ret=%d",ret);
4076 }
4077 if (init_pause_msec) {
4078 pvr2_trace(PVR2_TRACE_INFO,
4079 "Waiting %u msec for hardware to settle",
4080 init_pause_msec);
4081 msleep(init_pause_msec);
4082 }
4083
4084}
4085
4086
4087void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4088{
4089 char da[1];
4090 unsigned int pipe;
4091 int ret;
4092
4093 if (!hdw->usb_dev) return;
4094
4095 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4096
4097 da[0] = val ? 0x01 : 0x00;
4098
4099 /* Write the CPUCS register on the 8051. The lsb of the register
4100 is the reset bit; a 1 asserts reset while a 0 clears it. */
4101 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4102 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4103 if (ret < 0) {
4104 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4105 "cpureset_assert(%d) error=%d",val,ret);
4106 pvr2_hdw_render_useless(hdw);
4107 }
4108}
4109
4110
4111int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4112{
1c9d10d4 4113 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
d855497e
MI		 4114}
4115
4116
e1edb19a
MK		 4117int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4118{
1c9d10d4 4119 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
e1edb19a
MK		 4120}
4121
1c9d10d4 4122
e1edb19a
MK		 4123int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4124{
1c9d10d4 4125 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
e1edb19a
MK		 4126}
4127
d855497e
MI		 4128
4129int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4130{
af78e16b
MI		 4131 pvr2_trace(PVR2_TRACE_INIT,
4132 "Requesting decoder reset");
af78e16b
MI		 4133 if (hdw->decoder_client_id) {
4134 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4135 core, reset, 0);
e17d787c 4136 pvr2_hdw_cx25840_vbi_hack(hdw);
af78e16b 4137 return 0;
d855497e 4138 }
d855497e 4139 pvr2_trace(PVR2_TRACE_INIT,
af78e16b
MI		 4140 "Unable to reset decoder: nothing attached");
4141 return -ENOTTY;
d855497e
MI		 4142}
4143
4144
62433e31 4145static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
84147f3d 4146{
1c9d10d4
MI		 4147 hdw->flag_ok = !0;
4148 return pvr2_issue_simple_cmd(hdw,
4149 FX2CMD_HCW_DEMOD_RESETIN |
4150 (1 << 8) |
4151 ((onoff ? 1 : 0) << 16));
84147f3d
MI		 4152}
4153
84147f3d 4154
62433e31 4155static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
84147f3d 4156{
1c9d10d4
MI		 4157 hdw->flag_ok = !0;
4158 return pvr2_issue_simple_cmd(hdw,(onoff ?
4159 FX2CMD_ONAIR_DTV_POWER_ON :
4160 FX2CMD_ONAIR_DTV_POWER_OFF));
84147f3d
MI		 4161}
4162
62433e31
MI		 4163
4164static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4165 int onoff)
84147f3d 4166{
1c9d10d4
MI		 4167 return pvr2_issue_simple_cmd(hdw,(onoff ?
4168 FX2CMD_ONAIR_DTV_STREAMING_ON :
4169 FX2CMD_ONAIR_DTV_STREAMING_OFF));
84147f3d
MI		 4170}
4171
62433e31
MI		 4172
4173static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4174{
4175 int cmode;
4176 /* Compare digital/analog desired setting with current setting. If
4177 they don't match, fix it... */
4178 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4179 if (cmode == hdw->pathway_state) {
4180 /* They match; nothing to do */
4181 return;
4182 }
4183
4184 switch (hdw->hdw_desc->digital_control_scheme) {
4185 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4186 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4187 if (cmode == PVR2_PATHWAY_ANALOG) {
4188 /* If moving to analog mode, also force the decoder
4189 to reset. If no decoder is attached, then it's
4190 ok to ignore this because if/when the decoder
4191 attaches, it will reset itself at that time. */
4192 pvr2_hdw_cmd_decoder_reset(hdw);
4193 }
4194 break;
4195 case PVR2_DIGITAL_SCHEME_ONAIR:
4196 /* Supposedly we should always have the power on whether in
4197 digital or analog mode. But for now do what appears to
4198 work... */
bb0c2fe0 4199 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
62433e31
MI		 4200 break;
4201 default: break;
4202 }
4203
1b9c18c5 4204 pvr2_hdw_untrip_unlocked(hdw);
62433e31
MI		 4205 hdw->pathway_state = cmode;
4206}
4207
4208
e9b59f6e 4209static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
c55a97d7
MI		 4210{
4211 /* change some GPIO data
4212 *
4213 * note: bit d7 of dir appears to control the LED,
4214 * so we shut it off here.
4215 *
c55a97d7 4216 */
40381cb0 4217 if (onoff) {
c55a97d7 4218 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
40381cb0 4219 } else {
c55a97d7 4220 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
40381cb0 4221 }
c55a97d7 4222 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
40381cb0 4223}
c55a97d7 4224
40381cb0
MI		 4225
4226typedef void (*led_method_func)(struct pvr2_hdw *,int);
4227
4228static led_method_func led_methods[] = {
4229 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4230};
4231
4232
4233/* Toggle LED */
4234static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4235{
4236 unsigned int scheme_id;
4237 led_method_func fp;
4238
4239 if ((!onoff) == (!hdw->led_on)) return;
4240
4241 hdw->led_on = onoff != 0;
4242
4243 scheme_id = hdw->hdw_desc->led_scheme;
4244 if (scheme_id < ARRAY_SIZE(led_methods)) {
4245 fp = led_methods[scheme_id];
4246 } else {
4247 fp = NULL;
4248 }
4249
4250 if (fp) (*fp)(hdw,onoff);
c55a97d7
MI		 4251}
4252
4253
e61b6fc5 4254/* Stop / start video stream transport */
07e337ee 4255static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e 4256{
bb0c2fe0
MI		 4257 int ret;
4258
4259 /* If we're in analog mode, then just issue the usual analog
4260 command. */
4261 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4262 return pvr2_issue_simple_cmd(hdw,
4263 (runFl ?
4264 FX2CMD_STREAMING_ON :
4265 FX2CMD_STREAMING_OFF));
4266 /*Note: Not reached */
4267 }
4268
4269 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4270 /* Whoops, we don't know what mode we're in... */
4271 return -EINVAL;
4272 }
4273
4274 /* To get here we have to be in digital mode. The mechanism here
4275 is unfortunately different for different vendors. So we switch
4276 on the device's digital scheme attribute in order to figure out
4277 what to do. */
4278 switch (hdw->hdw_desc->digital_control_scheme) {
4279 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4280 return pvr2_issue_simple_cmd(hdw,
4281 (runFl ?
4282 FX2CMD_HCW_DTV_STREAMING_ON :
4283 FX2CMD_HCW_DTV_STREAMING_OFF));
4284 case PVR2_DIGITAL_SCHEME_ONAIR:
4285 ret = pvr2_issue_simple_cmd(hdw,
4286 (runFl ?
4287 FX2CMD_STREAMING_ON :
4288 FX2CMD_STREAMING_OFF));
4289 if (ret) return ret;
4290 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4291 default:
4292 return -EINVAL;
62433e31 4293 }
d855497e
MI		 4294}
4295
4296
62433e31
MI		 4297/* Evaluate whether or not state_pathway_ok can change */
4298static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4299{
4300 if (hdw->state_pathway_ok) {
4301 /* Nothing to do if pathway is already ok */
4302 return 0;
4303 }
4304 if (!hdw->state_pipeline_idle) {
4305 /* Not allowed to change anything if pipeline is not idle */
4306 return 0;
4307 }
4308 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4309 hdw->state_pathway_ok = !0;
e9db1ff2 4310 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 4311 return !0;
4312}
4313
4314
681c7399
MI		 4315/* Evaluate whether or not state_encoder_ok can change */
4316static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4317{
4318 if (hdw->state_encoder_ok) return 0;
4319 if (hdw->flag_tripped) return 0;
4320 if (hdw->state_encoder_run) return 0;
4321 if (hdw->state_encoder_config) return 0;
4322 if (hdw->state_decoder_run) return 0;
4323 if (hdw->state_usbstream_run) return 0;
72998b71
MI		 4324 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4325 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4326 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4327 return 0;
4328 }
4329
681c7399
MI		 4330 if (pvr2_upload_firmware2(hdw) < 0) {
4331 hdw->flag_tripped = !0;
4332 trace_stbit("flag_tripped",hdw->flag_tripped);
4333 return !0;
4334 }
4335 hdw->state_encoder_ok = !0;
4336 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4337 return !0;
4338}
4339
4340
4341/* Evaluate whether or not state_encoder_config can change */
4342static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4343{
4344 if (hdw->state_encoder_config) {
4345 if (hdw->state_encoder_ok) {
4346 if (hdw->state_pipeline_req &&
4347 !hdw->state_pipeline_pause) return 0;
4348 }
4349 hdw->state_encoder_config = 0;
4350 hdw->state_encoder_waitok = 0;
4351 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4352 /* paranoia - solve race if timer just completed */
4353 del_timer_sync(&hdw->encoder_wait_timer);
4354 } else {
62433e31
MI		 4355 if (!hdw->state_pathway_ok ||
4356 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4357 !hdw->state_encoder_ok ||
681c7399
MI		 4358 !hdw->state_pipeline_idle ||
4359 hdw->state_pipeline_pause ||
4360 !hdw->state_pipeline_req ||
4361 !hdw->state_pipeline_config) {
4362 /* We must reset the enforced wait interval if
4363 anything has happened that might have disturbed
4364 the encoder. This should be a rare case. */
4365 if (timer_pending(&hdw->encoder_wait_timer)) {
4366 del_timer_sync(&hdw->encoder_wait_timer);
4367 }
4368 if (hdw->state_encoder_waitok) {
4369 /* Must clear the state - therefore we did
4370 something to a state bit and must also
4371 return true. */
4372 hdw->state_encoder_waitok = 0;
4373 trace_stbit("state_encoder_waitok",
4374 hdw->state_encoder_waitok);
4375 return !0;
4376 }
4377 return 0;
4378 }
4379 if (!hdw->state_encoder_waitok) {
4380 if (!timer_pending(&hdw->encoder_wait_timer)) {
4381 /* waitok flag wasn't set and timer isn't
4382 running. Check flag once more to avoid
4383 a race then start the timer. This is
4384 the point when we measure out a minimal
4385 quiet interval before doing something to
4386 the encoder. */
4387 if (!hdw->state_encoder_waitok) {
4388 hdw->encoder_wait_timer.expires =
83ce57aa
MI		 4389 jiffies +
4390 (HZ * TIME_MSEC_ENCODER_WAIT
4391 / 1000);
681c7399
MI		 4392 add_timer(&hdw->encoder_wait_timer);
4393 }
4394 }
4395 /* We can't continue until we know we have been
4396 quiet for the interval measured by this
4397 timer. */
4398 return 0;
4399 }
4400 pvr2_encoder_configure(hdw);
4401 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4402 }
4403 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4404 return !0;
4405}
4406
4407
d913d630
MI		 4408/* Return true if the encoder should not be running. */
4409static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4410{
4411 if (!hdw->state_encoder_ok) {
4412 /* Encoder isn't healthy at the moment, so stop it. */
4413 return !0;
4414 }
4415 if (!hdw->state_pathway_ok) {
4416 /* Mode is not understood at the moment (i.e. it wants to
4417 change), so encoder must be stopped. */
4418 return !0;
4419 }
4420
4421 switch (hdw->pathway_state) {
4422 case PVR2_PATHWAY_ANALOG:
4423 if (!hdw->state_decoder_run) {
4424 /* We're in analog mode and the decoder is not
4425 running; thus the encoder should be stopped as
4426 well. */
4427 return !0;
4428 }
4429 break;
4430 case PVR2_PATHWAY_DIGITAL:
4431 if (hdw->state_encoder_runok) {
4432 /* This is a funny case. We're in digital mode so
4433 really the encoder should be stopped. However
4434 if it really is running, only kill it after
4435 runok has been set. This gives a chance for the
4436 onair quirk to function (encoder must run
4437 briefly first, at least once, before onair
4438 digital streaming can work). */
4439 return !0;
4440 }
4441 break;
4442 default:
4443 /* Unknown mode; so encoder should be stopped. */
4444 return !0;
4445 }
4446
4447 /* If we get here, we haven't found a reason to stop the
4448 encoder. */
4449 return 0;
4450}
4451
4452
4453/* Return true if the encoder should be running. */
4454static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4455{
4456 if (!hdw->state_encoder_ok) {
4457 /* Don't run the encoder if it isn't healthy... */
4458 return 0;
4459 }
4460 if (!hdw->state_pathway_ok) {
4461 /* Don't run the encoder if we don't (yet) know what mode
4462 we need to be in... */
4463 return 0;
4464 }
4465
4466 switch (hdw->pathway_state) {
4467 case PVR2_PATHWAY_ANALOG:
6e931375 4468 if (hdw->state_decoder_run && hdw->state_decoder_ready) {
d913d630
MI		 4469 /* In analog mode, if the decoder is running, then
4470 run the encoder. */
4471 return !0;
4472 }
4473 break;
4474 case PVR2_PATHWAY_DIGITAL:
4475 if ((hdw->hdw_desc->digital_control_scheme ==
4476 PVR2_DIGITAL_SCHEME_ONAIR) &&
4477 !hdw->state_encoder_runok) {
4478 /* This is a quirk. OnAir hardware won't stream
4479 digital until the encoder has been run at least
4480 once, for a minimal period of time (empiricially
4481 measured to be 1/4 second). So if we're on
4482 OnAir hardware and the encoder has never been
4483 run at all, then start the encoder. Normal
4484 state machine logic in the driver will
4485 automatically handle the remaining bits. */
4486 return !0;
4487 }
4488 break;
4489 default:
4490 /* For completeness (unknown mode; encoder won't run ever) */
4491 break;
4492 }
4493 /* If we get here, then we haven't found any reason to run the
4494 encoder, so don't run it. */
4495 return 0;
4496}
4497
4498
681c7399
MI		 4499/* Evaluate whether or not state_encoder_run can change */
4500static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4501{
4502 if (hdw->state_encoder_run) {
d913d630 4503 if (!state_check_disable_encoder_run(hdw)) return 0;
681c7399 4504 if (hdw->state_encoder_ok) {
d913d630 4505 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 4506 if (pvr2_encoder_stop(hdw) < 0) return !0;
4507 }
4508 hdw->state_encoder_run = 0;
4509 } else {
d913d630 4510 if (!state_check_enable_encoder_run(hdw)) return 0;
681c7399
MI		 4511 if (pvr2_encoder_start(hdw) < 0) return !0;
4512 hdw->state_encoder_run = !0;
d913d630
MI		 4513 if (!hdw->state_encoder_runok) {
4514 hdw->encoder_run_timer.expires =
83ce57aa 4515 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
d913d630
MI		 4516 add_timer(&hdw->encoder_run_timer);
4517 }
681c7399
MI		 4518 }
4519 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4520 return !0;
4521}
4522
4523
4524/* Timeout function for quiescent timer. */
4525static void pvr2_hdw_quiescent_timeout(unsigned long data)
4526{
4527 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4528 hdw->state_decoder_quiescent = !0;
4529 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4530 hdw->state_stale = !0;
4531 queue_work(hdw->workqueue,&hdw->workpoll);
4532}
4533
4534
6e931375
MI		 4535/* Timeout function for decoder stabilization timer. */
4536static void pvr2_hdw_decoder_stabilization_timeout(unsigned long data)
4537{
4538 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4539 hdw->state_decoder_ready = !0;
4540 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4541 hdw->state_stale = !0;
4542 queue_work(hdw->workqueue, &hdw->workpoll);
4543}
4544
4545
681c7399
MI		 4546/* Timeout function for encoder wait timer. */
4547static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4548{
4549 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4550 hdw->state_encoder_waitok = !0;
4551 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4552 hdw->state_stale = !0;
4553 queue_work(hdw->workqueue,&hdw->workpoll);
4554}
4555
4556
d913d630
MI		 4557/* Timeout function for encoder run timer. */
4558static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4559{
4560 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4561 if (!hdw->state_encoder_runok) {
4562 hdw->state_encoder_runok = !0;
4563 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4564 hdw->state_stale = !0;
4565 queue_work(hdw->workqueue,&hdw->workpoll);
4566 }
4567}
4568
4569
681c7399
MI		 4570/* Evaluate whether or not state_decoder_run can change */
4571static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4572{
4573 if (hdw->state_decoder_run) {
4574 if (hdw->state_encoder_ok) {
4575 if (hdw->state_pipeline_req &&
62433e31
MI		 4576 !hdw->state_pipeline_pause &&
4577 hdw->state_pathway_ok) return 0;
681c7399
MI		 4578 }
4579 if (!hdw->flag_decoder_missed) {
4580 pvr2_decoder_enable(hdw,0);
4581 }
4582 hdw->state_decoder_quiescent = 0;
4583 hdw->state_decoder_run = 0;
6e931375 4584 /* paranoia - solve race if timer(s) just completed */
681c7399 4585 del_timer_sync(&hdw->quiescent_timer);
6e931375
MI		 4586 /* Kill the stabilization timer, in case we're killing the
4587 encoder before the previous stabilization interval has
4588 been properly timed. */
4589 del_timer_sync(&hdw->decoder_stabilization_timer);
4590 hdw->state_decoder_ready = 0;
681c7399
MI		 4591 } else {
4592 if (!hdw->state_decoder_quiescent) {
4593 if (!timer_pending(&hdw->quiescent_timer)) {
4594 /* We don't do something about the
4595 quiescent timer until right here because
4596 we also want to catch cases where the
4597 decoder was already not running (like
4598 after initialization) as opposed to
4599 knowing that we had just stopped it.
4600 The second flag check is here to cover a
4601 race - the timer could have run and set
4602 this flag just after the previous check
4603 but before we did the pending check. */
4604 if (!hdw->state_decoder_quiescent) {
4605 hdw->quiescent_timer.expires =
83ce57aa
MI		 4606 jiffies +
4607 (HZ * TIME_MSEC_DECODER_WAIT
4608 / 1000);
681c7399
MI		 4609 add_timer(&hdw->quiescent_timer);
4610 }
4611 }
4612 /* Don't allow decoder to start again until it has
4613 been quiesced first. This little detail should
4614 hopefully further stabilize the encoder. */
4615 return 0;
4616 }
62433e31
MI		 4617 if (!hdw->state_pathway_ok ||
4618 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4619 !hdw->state_pipeline_req ||
681c7399
MI		 4620 hdw->state_pipeline_pause ||
4621 !hdw->state_pipeline_config ||
4622 !hdw->state_encoder_config ||
4623 !hdw->state_encoder_ok) return 0;
4624 del_timer_sync(&hdw->quiescent_timer);
4625 if (hdw->flag_decoder_missed) return 0;
4626 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4627 hdw->state_decoder_quiescent = 0;
6e931375 4628 hdw->state_decoder_ready = 0;
681c7399 4629 hdw->state_decoder_run = !0;
6e931375
MI		 4630 hdw->decoder_stabilization_timer.expires =
4631 jiffies +
4632 (HZ * TIME_MSEC_DECODER_STABILIZATION_WAIT / 1000);
4633 add_timer(&hdw->decoder_stabilization_timer);
681c7399
MI		 4634 }
4635 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4636 trace_stbit("state_decoder_run",hdw->state_decoder_run);
6e931375 4637 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
681c7399
MI		 4638 return !0;
4639}
4640
4641
4642/* Evaluate whether or not state_usbstream_run can change */
4643static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4644{
4645 if (hdw->state_usbstream_run) {
72998b71 4646 int fl = !0;
62433e31 4647 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
72998b71
MI		 4648 fl = (hdw->state_encoder_ok &&
4649 hdw->state_encoder_run);
4650 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4651 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4652 fl = hdw->state_encoder_ok;
4653 }
4654 if (fl &&
4655 hdw->state_pipeline_req &&
4656 !hdw->state_pipeline_pause &&
4657 hdw->state_pathway_ok) {
4658 return 0;
681c7399
MI		 4659 }
4660 pvr2_hdw_cmd_usbstream(hdw,0);
4661 hdw->state_usbstream_run = 0;
4662 } else {
62433e31
MI		 4663 if (!hdw->state_pipeline_req ||
4664 hdw->state_pipeline_pause ||
4665 !hdw->state_pathway_ok) return 0;
4666 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4667 if (!hdw->state_encoder_ok ||
4668 !hdw->state_encoder_run) return 0;
72998b71
MI		 4669 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4670 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4671 if (!hdw->state_encoder_ok) return 0;
d913d630
MI		 4672 if (hdw->state_encoder_run) return 0;
4673 if (hdw->hdw_desc->digital_control_scheme ==
4674 PVR2_DIGITAL_SCHEME_ONAIR) {
4675 /* OnAir digital receivers won't stream
4676 unless the analog encoder has run first.
4677 Why? I have no idea. But don't even
4678 try until we know the analog side is
4679 known to have run. */
4680 if (!hdw->state_encoder_runok) return 0;
4681 }
62433e31 4682 }
681c7399
MI		 4683 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4684 hdw->state_usbstream_run = !0;
4685 }
4686 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4687 return !0;
4688}
4689
4690
4691/* Attempt to configure pipeline, if needed */
4692static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4693{
4694 if (hdw->state_pipeline_config ||
4695 hdw->state_pipeline_pause) return 0;
4696 pvr2_hdw_commit_execute(hdw);
4697 return !0;
4698}
4699
4700
4701/* Update pipeline idle and pipeline pause tracking states based on other
4702 inputs. This must be called whenever the other relevant inputs have
4703 changed. */
4704static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4705{
4706 unsigned int st;
4707 int updatedFl = 0;
4708 /* Update pipeline state */
4709 st = !(hdw->state_encoder_run ||
4710 hdw->state_decoder_run ||
4711 hdw->state_usbstream_run ||
4712 (!hdw->state_decoder_quiescent));
4713 if (!st != !hdw->state_pipeline_idle) {
4714 hdw->state_pipeline_idle = st;
4715 updatedFl = !0;
4716 }
4717 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4718 hdw->state_pipeline_pause = 0;
4719 updatedFl = !0;
4720 }
4721 return updatedFl;
4722}
4723
4724
4725typedef int (*state_eval_func)(struct pvr2_hdw *);
4726
4727/* Set of functions to be run to evaluate various states in the driver. */
ebff0330 4728static const state_eval_func eval_funcs[] = {
62433e31 4729 state_eval_pathway_ok,
681c7399
MI		 4730 state_eval_pipeline_config,
4731 state_eval_encoder_ok,
4732 state_eval_encoder_config,
4733 state_eval_decoder_run,
4734 state_eval_encoder_run,
4735 state_eval_usbstream_run,
4736};
4737
4738
4739/* Process various states and return true if we did anything interesting. */
4740static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4741{
4742 unsigned int i;
4743 int state_updated = 0;
4744 int check_flag;
4745
4746 if (!hdw->state_stale) return 0;
4747 if ((hdw->fw1_state != FW1_STATE_OK) ||
4748 !hdw->flag_ok) {
4749 hdw->state_stale = 0;
4750 return !0;
4751 }
4752 /* This loop is the heart of the entire driver. It keeps trying to
4753 evaluate various bits of driver state until nothing changes for
4754 one full iteration. Each "bit of state" tracks some global
4755 aspect of the driver, e.g. whether decoder should run, if
4756 pipeline is configured, usb streaming is on, etc. We separately
4757 evaluate each of those questions based on other driver state to
4758 arrive at the correct running configuration. */
4759 do {
4760 check_flag = 0;
4761 state_update_pipeline_state(hdw);
4762 /* Iterate over each bit of state */
4763 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4764 if ((*eval_funcs[i])(hdw)) {
4765 check_flag = !0;
4766 state_updated = !0;
4767 state_update_pipeline_state(hdw);
4768 }
4769 }
4770 } while (check_flag && hdw->flag_ok);
4771 hdw->state_stale = 0;
4772 trace_stbit("state_stale",hdw->state_stale);
4773 return state_updated;
4774}
4775
4776
1cb03b76
MI		 4777static unsigned int print_input_mask(unsigned int msk,
4778 char *buf,unsigned int acnt)
4779{
4780 unsigned int idx,ccnt;
4781 unsigned int tcnt = 0;
4782 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4783 if (!((1 << idx) & msk)) continue;
4784 ccnt = scnprintf(buf+tcnt,
4785 acnt-tcnt,
4786 "%s%s",
4787 (tcnt ? ", " : ""),
4788 control_values_input[idx]);
4789 tcnt += ccnt;
4790 }
4791 return tcnt;
4792}
4793
4794
62433e31
MI		 4795static const char *pvr2_pathway_state_name(int id)
4796{
4797 switch (id) {
4798 case PVR2_PATHWAY_ANALOG: return "analog";
4799 case PVR2_PATHWAY_DIGITAL: return "digital";
4800 default: return "unknown";
4801 }
4802}
4803
4804
681c7399
MI		 4805static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4806 char *buf,unsigned int acnt)
4807{
4808 switch (which) {
4809 case 0:
4810 return scnprintf(
4811 buf,acnt,
e9db1ff2 4812 "driver:%s%s%s%s%s <mode=%s>",
681c7399
MI		 4813 (hdw->flag_ok ? " <ok>" : " <fail>"),
4814 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4815 (hdw->flag_disconnected ? " <disconnected>" :
4816 " <connected>"),
4817 (hdw->flag_tripped ? " <tripped>" : ""),
62433e31
MI		 4818 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4819 pvr2_pathway_state_name(hdw->pathway_state));
4820
681c7399
MI		 4821 case 1:
4822 return scnprintf(
4823 buf,acnt,
4824 "pipeline:%s%s%s%s",
4825 (hdw->state_pipeline_idle ? " <idle>" : ""),
4826 (hdw->state_pipeline_config ?
4827 " <configok>" : " <stale>"),
4828 (hdw->state_pipeline_req ? " <req>" : ""),
4829 (hdw->state_pipeline_pause ? " <pause>" : ""));
4830 case 2:
4831 return scnprintf(
4832 buf,acnt,
62433e31 4833 "worker:%s%s%s%s%s%s%s",
681c7399 4834 (hdw->state_decoder_run ?
6e931375
MI		 4835 (hdw->state_decoder_ready ?
4836 "<decode:run>" : " <decode:start>") :
681c7399
MI		 4837 (hdw->state_decoder_quiescent ?
4838 "" : " <decode:stop>")),
4839 (hdw->state_decoder_quiescent ?
4840 " <decode:quiescent>" : ""),
4841 (hdw->state_encoder_ok ?
4842 "" : " <encode:init>"),
4843 (hdw->state_encoder_run ?
d913d630
MI		 4844 (hdw->state_encoder_runok ?
4845 " <encode:run>" :
4846 " <encode:firstrun>") :
4847 (hdw->state_encoder_runok ?
4848 " <encode:stop>" :
4849 " <encode:virgin>")),
681c7399
MI		 4850 (hdw->state_encoder_config ?
4851 " <encode:configok>" :
4852 (hdw->state_encoder_waitok ?
b9a37d91 4853 "" : " <encode:waitok>")),
681c7399 4854 (hdw->state_usbstream_run ?
62433e31
MI		 4855 " <usb:run>" : " <usb:stop>"),
4856 (hdw->state_pathway_ok ?
e9db1ff2 4857 " <pathway:ok>" : ""));
681c7399
MI		 4858 case 3:
4859 return scnprintf(
4860 buf,acnt,
4861 "state: %s",
4862 pvr2_get_state_name(hdw->master_state));
ad0992e9 4863 case 4: {
1cb03b76
MI		 4864 unsigned int tcnt = 0;
4865 unsigned int ccnt;
4866
4867 ccnt = scnprintf(buf,
4868 acnt,
4869 "Hardware supported inputs: ");
4870 tcnt += ccnt;
4871 tcnt += print_input_mask(hdw->input_avail_mask,
4872 buf+tcnt,
4873 acnt-tcnt);
4874 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4875 ccnt = scnprintf(buf+tcnt,
4876 acnt-tcnt,
4877 "; allowed inputs: ");
4878 tcnt += ccnt;
4879 tcnt += print_input_mask(hdw->input_allowed_mask,
4880 buf+tcnt,
4881 acnt-tcnt);
4882 }
4883 return tcnt;
4884 }
4885 case 5: {
ad0992e9
MI		 4886 struct pvr2_stream_stats stats;
4887 if (!hdw->vid_stream) break;
4888 pvr2_stream_get_stats(hdw->vid_stream,
4889 &stats,
4890 0);
4891 return scnprintf(
4892 buf,acnt,
4893 "Bytes streamed=%u"
4894 " URBs: queued=%u idle=%u ready=%u"
4895 " processed=%u failed=%u",
4896 stats.bytes_processed,
4897 stats.buffers_in_queue,
4898 stats.buffers_in_idle,
4899 stats.buffers_in_ready,
4900 stats.buffers_processed,
4901 stats.buffers_failed);
4902 }
27eab384
MI		 4903 case 6: {
4904 unsigned int id = hdw->ir_scheme_active;
4905 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4906 (id >= ARRAY_SIZE(ir_scheme_names) ?
4907 "?" : ir_scheme_names[id]));
4908 }
2eb563b7
MI		 4909 default: break;
4910 }
4911 return 0;
4912}
4913
4914
4915/* Generate report containing info about attached sub-devices and attached
4916 i2c clients, including an indication of which attached i2c clients are
4917 actually sub-devices. */
4918static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4919 char *buf, unsigned int acnt)
4920{
4921 struct v4l2_subdev *sd;
4922 unsigned int tcnt = 0;
4923 unsigned int ccnt;
4924 struct i2c_client *client;
2eb563b7
MI		 4925 const char *p;
4926 unsigned int id;
4927
fa7ce764 4928 ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
2eb563b7
MI		 4929 tcnt += ccnt;
4930 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4931 id = sd->grp_id;
4932 p = NULL;
4933 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4934 if (p) {
fa7ce764 4935 ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s:", p);
2eb563b7
MI		 4936 tcnt += ccnt;
4937 } else {
4938 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
fa7ce764 4939 " (unknown id=%u):", id);
2eb563b7
MI		 4940 tcnt += ccnt;
4941 }
fa7ce764
JD		 4942 client = v4l2_get_subdevdata(sd);
4943 if (client) {
4944 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4945 " %s @ %02x\n", client->name,
4946 client->addr);
4947 tcnt += ccnt;
4948 } else {
4949 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4950 " no i2c client\n");
4951 tcnt += ccnt;
858f910e 4952 }
681c7399 4953 }
2eb563b7 4954 return tcnt;
681c7399
MI		 4955}
4956
4957
4958unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4959 char *buf,unsigned int acnt)
4960{
4961 unsigned int bcnt,ccnt,idx;
4962 bcnt = 0;
4963 LOCK_TAKE(hdw->big_lock);
4964 for (idx = 0; ; idx++) {
4965 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4966 if (!ccnt) break;
4967 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4968 if (!acnt) break;
4969 buf[0] = '\n'; ccnt = 1;
4970 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4971 }
2eb563b7
MI		 4972 ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4973 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
681c7399
MI		 4974 LOCK_GIVE(hdw->big_lock);
4975 return bcnt;
4976}
4977
4978
4979static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4980{
2eb563b7
MI		 4981 char buf[256];
4982 unsigned int idx, ccnt;
4983 unsigned int lcnt, ucnt;
681c7399
MI		 4984
4985 for (idx = 0; ; idx++) {
4986 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4987 if (!ccnt) break;
4988 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4989 }
2eb563b7
MI		 4990 ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
4991 ucnt = 0;
4992 while (ucnt < ccnt) {
4993 lcnt = 0;
4994 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4995 lcnt++;
4996 }
4997 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4998 ucnt += lcnt + 1;
4999 }
681c7399
MI		 5000}
5001
5002
5003/* Evaluate and update the driver's current state, taking various actions
5004 as appropriate for the update. */
5005static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
5006{
5007 unsigned int st;
5008 int state_updated = 0;
5009 int callback_flag = 0;
1b9c18c5 5010 int analog_mode;
681c7399
MI		 5011
5012 pvr2_trace(PVR2_TRACE_STBITS,
5013 "Drive state check START");
5014 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5015 pvr2_hdw_state_log_state(hdw);
5016 }
5017
5018 /* Process all state and get back over disposition */
5019 state_updated = pvr2_hdw_state_update(hdw);
5020
1b9c18c5
MI		 5021 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
5022
681c7399
MI		 5023 /* Update master state based upon all other states. */
5024 if (!hdw->flag_ok) {
5025 st = PVR2_STATE_DEAD;
5026 } else if (hdw->fw1_state != FW1_STATE_OK) {
5027 st = PVR2_STATE_COLD;
72998b71
MI		 5028 } else if ((analog_mode ||
5029 hdw->hdw_desc->flag_digital_requires_cx23416) &&
5030 !hdw->state_encoder_ok) {
681c7399 5031 st = PVR2_STATE_WARM;
1b9c18c5
MI		 5032 } else if (hdw->flag_tripped ||
5033 (analog_mode && hdw->flag_decoder_missed)) {
681c7399 5034 st = PVR2_STATE_ERROR;
62433e31 5035 } else if (hdw->state_usbstream_run &&
1b9c18c5 5036 (!analog_mode ||
62433e31 5037 (hdw->state_encoder_run && hdw->state_decoder_run))) {
681c7399
MI		 5038 st = PVR2_STATE_RUN;
5039 } else {
5040 st = PVR2_STATE_READY;
5041 }
5042 if (hdw->master_state != st) {
5043 pvr2_trace(PVR2_TRACE_STATE,
5044 "Device state change from %s to %s",
5045 pvr2_get_state_name(hdw->master_state),
5046 pvr2_get_state_name(st));
40381cb0 5047 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
681c7399
MI		 5048 hdw->master_state = st;
5049 state_updated = !0;
5050 callback_flag = !0;
5051 }
5052 if (state_updated) {
5053 /* Trigger anyone waiting on any state changes here. */
5054 wake_up(&hdw->state_wait_data);
5055 }
5056
5057 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5058 pvr2_hdw_state_log_state(hdw);
5059 }
5060 pvr2_trace(PVR2_TRACE_STBITS,
5061 "Drive state check DONE callback=%d",callback_flag);
5062
5063 return callback_flag;
5064}
5065
5066
5067/* Cause kernel thread to check / update driver state */
5068static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
5069{
5070 if (hdw->state_stale) return;
5071 hdw->state_stale = !0;
5072 trace_stbit("state_stale",hdw->state_stale);
5073 queue_work(hdw->workqueue,&hdw->workpoll);
5074}
5075
5076
d855497e
MI		 5077int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
5078{
5079 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5080}
5081
5082
5083int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5084{
5085 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5086}
5087
5088
5089int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5090{
5091 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5092}
5093
5094
5095int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5096{
5097 u32 cval,nval;
5098 int ret;
5099 if (~msk) {
5100 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5101 if (ret) return ret;
5102 nval = (cval & ~msk) | (val & msk);
5103 pvr2_trace(PVR2_TRACE_GPIO,
5104 "GPIO direction changing 0x%x:0x%x"
5105 " from 0x%x to 0x%x",
5106 msk,val,cval,nval);
5107 } else {
5108 nval = val;
5109 pvr2_trace(PVR2_TRACE_GPIO,
5110 "GPIO direction changing to 0x%x",nval);
5111 }
5112 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5113}
5114
5115
5116int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5117{
5118 u32 cval,nval;
5119 int ret;
5120 if (~msk) {
5121 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5122 if (ret) return ret;
5123 nval = (cval & ~msk) | (val & msk);
5124 pvr2_trace(PVR2_TRACE_GPIO,
5125 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5126 msk,val,cval,nval);
5127 } else {
5128 nval = val;
5129 pvr2_trace(PVR2_TRACE_GPIO,
5130 "GPIO output changing to 0x%x",nval);
5131 }
5132 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5133}
5134
5135
a51f5000
MI		 5136void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5137{
40f07111
MI		 5138 struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5139 memset(vtp, 0, sizeof(*vtp));
2641df36 5140 hdw->tuner_signal_stale = 0;
40f07111
MI		 5141 /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5142 using v4l2-subdev - therefore we can't support that AT ALL right
5143 now. (Of course, no sub-drivers seem to implement it either.
5144 But now it's a a chicken and egg problem...) */
5145 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5146 &hdw->tuner_signal_info);
2641df36 5147 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
40f07111
MI		 5148 " type=%u strength=%u audio=0x%x cap=0x%x"
5149 " low=%u hi=%u",
5150 vtp->type,
5151 vtp->signal, vtp->rxsubchans, vtp->capability,
5152 vtp->rangelow, vtp->rangehigh);
2641df36
MI		 5153
5154 /* We have to do this to avoid getting into constant polling if
5155 there's nobody to answer a poll of cropcap info. */
5156 hdw->cropcap_stale = 0;
a51f5000
MI		 5157}
5158
5159
7fb20fa3
MI		 5160unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5161{
5162 return hdw->input_avail_mask;
5163}
5164
5165
1cb03b76
MI		 5166unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5167{
5168 return hdw->input_allowed_mask;
5169}
5170
5171
5172static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5173{
5174 if (hdw->input_val != v) {
5175 hdw->input_val = v;
5176 hdw->input_dirty = !0;
5177 }
5178
5179 /* Handle side effects - if we switch to a mode that needs the RF
5180 tuner, then select the right frequency choice as well and mark
5181 it dirty. */
5182 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5183 hdw->freqSelector = 0;
5184 hdw->freqDirty = !0;
5185 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5186 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5187 hdw->freqSelector = 1;
5188 hdw->freqDirty = !0;
5189 }
5190 return 0;
5191}
5192
5193
5194int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5195 unsigned int change_mask,
5196 unsigned int change_val)
5197{
5198 int ret = 0;
5199 unsigned int nv,m,idx;
5200 LOCK_TAKE(hdw->big_lock);
5201 do {
5202 nv = hdw->input_allowed_mask & ~change_mask;
5203 nv |= (change_val & change_mask);
5204 nv &= hdw->input_avail_mask;
5205 if (!nv) {
5206 /* No legal modes left; return error instead. */
5207 ret = -EPERM;
5208 break;
5209 }
5210 hdw->input_allowed_mask = nv;
5211 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5212 /* Current mode is still in the allowed mask, so
5213 we're done. */
5214 break;
5215 }
5216 /* Select and switch to a mode that is still in the allowed
5217 mask */
5218 if (!hdw->input_allowed_mask) {
5219 /* Nothing legal; give up */
5220 break;
5221 }
5222 m = hdw->input_allowed_mask;
5223 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5224 if (!((1 << idx) & m)) continue;
5225 pvr2_hdw_set_input(hdw,idx);
5226 break;
5227 }
5228 } while (0);
5229 LOCK_GIVE(hdw->big_lock);
5230 return ret;
5231}
5232
5233
e61b6fc5 5234/* Find I2C address of eeprom */
07e337ee 5235static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 5236{
5237 int result;
5238 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 5239 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 5240 result = pvr2_send_request(hdw,
5241 hdw->cmd_buffer,1,
5242 hdw->cmd_buffer,1);
5243 if (result < 0) break;
5244 result = hdw->cmd_buffer[0];
5245 } while(0); LOCK_GIVE(hdw->ctl_lock);
5246 return result;
5247}
5248
5249
32ffa9ae 5250int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
aecde8b5
HV		 5251 struct v4l2_dbg_match *match, u64 reg_id,
5252 int setFl, u64 *val_ptr)
32ffa9ae
MI		 5253{
5254#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 5255 struct v4l2_dbg_register req;
6d98816f
MI		 5256 int stat = 0;
5257 int okFl = 0;
32ffa9ae 5258
201f5c9c
MI		 5259 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5260
aecde8b5 5261 req.match = *match;
32ffa9ae
MI		 5262 req.reg = reg_id;
5263 if (setFl) req.val = *val_ptr;
d8f5b9ba
MI		 5264 /* It would be nice to know if a sub-device answered the request */
5265 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5266 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 5267 if (okFl) {
5268 return stat;
5269 }
32ffa9ae
MI		 5270 return -EINVAL;
5271#else
5272 return -ENOSYS;
5273#endif
5274}
5275
5276
d855497e
MI		 5277/*
5278 Stuff for Emacs to see, in order to encourage consistent editing style:
5279 *** Local Variables: ***
5280 *** mode: c ***
5281 *** fill-column: 75 ***
5282 *** tab-width: 8 ***
5283 *** c-basic-offset: 8 ***
5284 *** End: ***
5285 */
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