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V4L/DVB (5036): Pvrusb2: Fix for min/max control value checking
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
3 * $Id$
4 *
5 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#include <linux/errno.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/firmware.h>
d855497e 26#include <linux/videodev2.h>
32ffa9ae 27#include <media/v4l2-common.h>
b2bbaa93 28#include <asm/semaphore.h>
d855497e
MI		 29#include "pvrusb2.h"
30#include "pvrusb2-std.h"
31#include "pvrusb2-util.h"
32#include "pvrusb2-hdw.h"
33#include "pvrusb2-i2c-core.h"
34#include "pvrusb2-tuner.h"
35#include "pvrusb2-eeprom.h"
36#include "pvrusb2-hdw-internal.h"
37#include "pvrusb2-encoder.h"
38#include "pvrusb2-debug.h"
39
25d8527a
PK		 40#define TV_MIN_FREQ 55250000L
41#define TV_MAX_FREQ 850000000L
42
43#define RADIO_MIN_FREQ 1392000L //87MHz
44#define RADIO_MAX_FREQ 1728000L //108MHz
45
d855497e
MI		 46struct usb_device_id pvr2_device_table[] = {
47 [PVR2_HDW_TYPE_29XXX] = { USB_DEVICE(0x2040, 0x2900) },
d855497e 48 [PVR2_HDW_TYPE_24XXX] = { USB_DEVICE(0x2040, 0x2400) },
d855497e
MI		 49 { }
50};
51
52MODULE_DEVICE_TABLE(usb, pvr2_device_table);
53
54static const char *pvr2_device_names[] = {
55 [PVR2_HDW_TYPE_29XXX] = "WinTV PVR USB2 Model Category 29xxxx",
d855497e 56 [PVR2_HDW_TYPE_24XXX] = "WinTV PVR USB2 Model Category 24xxxx",
d855497e
MI		 57};
58
59struct pvr2_string_table {
60 const char **lst;
61 unsigned int cnt;
62};
63
d855497e
MI		 64// Names of other client modules to request for 24xxx model hardware
65static const char *pvr2_client_24xxx[] = {
66 "cx25840",
67 "tuner",
d855497e
MI		 68 "wm8775",
69};
d855497e
MI		 70
71// Names of other client modules to request for 29xxx model hardware
72static const char *pvr2_client_29xxx[] = {
73 "msp3400",
74 "saa7115",
75 "tuner",
d855497e
MI		 76};
77
78static struct pvr2_string_table pvr2_client_lists[] = {
79 [PVR2_HDW_TYPE_29XXX] = {
80 pvr2_client_29xxx,
81 sizeof(pvr2_client_29xxx)/sizeof(pvr2_client_29xxx[0]),
82 },
d855497e
MI		 83 [PVR2_HDW_TYPE_24XXX] = {
84 pvr2_client_24xxx,
85 sizeof(pvr2_client_24xxx)/sizeof(pvr2_client_24xxx[0]),
86 },
d855497e
MI		 87};
88
a0fd1cb1 89static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
07e337ee 90static DECLARE_MUTEX(pvr2_unit_sem);
d855497e
MI		 91
92static int ctlchg = 0;
93static int initusbreset = 1;
94static int procreload = 0;
95static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
96static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
97static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
98static int init_pause_msec = 0;
99
100module_param(ctlchg, int, S_IRUGO|S_IWUSR);
101MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
102module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
103MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
104module_param(initusbreset, int, S_IRUGO|S_IWUSR);
105MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
106module_param(procreload, int, S_IRUGO|S_IWUSR);
107MODULE_PARM_DESC(procreload,
108 "Attempt init failure recovery with firmware reload");
109module_param_array(tuner, int, NULL, 0444);
110MODULE_PARM_DESC(tuner,"specify installed tuner type");
111module_param_array(video_std, int, NULL, 0444);
112MODULE_PARM_DESC(video_std,"specify initial video standard");
113module_param_array(tolerance, int, NULL, 0444);
114MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
115
116#define PVR2_CTL_WRITE_ENDPOINT 0x01
117#define PVR2_CTL_READ_ENDPOINT 0x81
118
119#define PVR2_GPIO_IN 0x9008
120#define PVR2_GPIO_OUT 0x900c
121#define PVR2_GPIO_DIR 0x9020
122
123#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
124
125#define PVR2_FIRMWARE_ENDPOINT 0x02
126
127/* size of a firmware chunk */
128#define FIRMWARE_CHUNK_SIZE 0x2000
129
b30d2441
MI		 130/* Define the list of additional controls we'll dynamically construct based
131 on query of the cx2341x module. */
132struct pvr2_mpeg_ids {
133 const char *strid;
134 int id;
135};
136static const struct pvr2_mpeg_ids mpeg_ids[] = {
137 {
138 .strid = "audio_layer",
139 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
140 },{
141 .strid = "audio_bitrate",
142 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
143 },{
144 /* Already using audio_mode elsewhere :-( */
145 .strid = "mpeg_audio_mode",
146 .id = V4L2_CID_MPEG_AUDIO_MODE,
147 },{
148 .strid = "mpeg_audio_mode_extension",
149 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
150 },{
151 .strid = "audio_emphasis",
152 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
153 },{
154 .strid = "audio_crc",
155 .id = V4L2_CID_MPEG_AUDIO_CRC,
156 },{
157 .strid = "video_aspect",
158 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
159 },{
160 .strid = "video_b_frames",
161 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
162 },{
163 .strid = "video_gop_size",
164 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
165 },{
166 .strid = "video_gop_closure",
167 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 168 },{
169 .strid = "video_bitrate_mode",
170 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
171 },{
172 .strid = "video_bitrate",
173 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
174 },{
175 .strid = "video_bitrate_peak",
176 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
177 },{
178 .strid = "video_temporal_decimation",
179 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
180 },{
181 .strid = "stream_type",
182 .id = V4L2_CID_MPEG_STREAM_TYPE,
183 },{
184 .strid = "video_spatial_filter_mode",
185 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
186 },{
187 .strid = "video_spatial_filter",
188 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
189 },{
190 .strid = "video_luma_spatial_filter_type",
191 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
192 },{
193 .strid = "video_chroma_spatial_filter_type",
194 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
195 },{
196 .strid = "video_temporal_filter_mode",
197 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
198 },{
199 .strid = "video_temporal_filter",
200 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
201 },{
202 .strid = "video_median_filter_type",
203 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
204 },{
205 .strid = "video_luma_median_filter_top",
206 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
207 },{
208 .strid = "video_luma_median_filter_bottom",
209 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
210 },{
211 .strid = "video_chroma_median_filter_top",
212 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
213 },{
214 .strid = "video_chroma_median_filter_bottom",
215 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
216 }
217};
218#define MPEGDEF_COUNT (sizeof(mpeg_ids)/sizeof(mpeg_ids[0]))
c05c0462 219
434449f4 220
d855497e 221static const char *control_values_srate[] = {
434449f4
MI		 222 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
223 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
224 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 225};
226
227
d855497e 228
d855497e
MI		 229static const char *control_values_input[] = {
230 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
231 [PVR2_CVAL_INPUT_RADIO] = "radio",
232 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
233 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
234};
235
236
237static const char *control_values_audiomode[] = {
238 [V4L2_TUNER_MODE_MONO] = "Mono",
239 [V4L2_TUNER_MODE_STEREO] = "Stereo",
240 [V4L2_TUNER_MODE_LANG1] = "Lang1",
241 [V4L2_TUNER_MODE_LANG2] = "Lang2",
242 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
243};
244
245
246static const char *control_values_hsm[] = {
247 [PVR2_CVAL_HSM_FAIL] = "Fail",
248 [PVR2_CVAL_HSM_HIGH] = "High",
249 [PVR2_CVAL_HSM_FULL] = "Full",
250};
251
252
253static const char *control_values_subsystem[] = {
254 [PVR2_SUBSYS_B_ENC_FIRMWARE] = "enc_firmware",
255 [PVR2_SUBSYS_B_ENC_CFG] = "enc_config",
256 [PVR2_SUBSYS_B_DIGITIZER_RUN] = "digitizer_run",
257 [PVR2_SUBSYS_B_USBSTREAM_RUN] = "usbstream_run",
258 [PVR2_SUBSYS_B_ENC_RUN] = "enc_run",
259};
260
07e337ee
AB		 261static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
262static int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw);
263static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
264static unsigned int pvr2_hdw_get_signal_status_internal(struct pvr2_hdw *hdw);
265static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
266static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
267static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw);
268static void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
269 unsigned long msk,
270 unsigned long val);
271static void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
272 unsigned long msk,
273 unsigned long val);
274static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
275 unsigned int timeout,int probe_fl,
276 void *write_data,unsigned int write_len,
277 void *read_data,unsigned int read_len);
278static int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res);
279static int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res);
d855497e
MI		 280
281static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
282{
283 struct pvr2_hdw *hdw = cptr->hdw;
284 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
285 *vp = hdw->freqTable[hdw->freqProgSlot-1];
286 } else {
287 *vp = 0;
288 }
289 return 0;
290}
291
292static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
293{
294 struct pvr2_hdw *hdw = cptr->hdw;
295 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
296 hdw->freqTable[hdw->freqProgSlot-1] = v;
297 }
298 return 0;
299}
300
301static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
302{
303 *vp = cptr->hdw->freqProgSlot;
304 return 0;
305}
306
307static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
308{
309 struct pvr2_hdw *hdw = cptr->hdw;
310 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
311 hdw->freqProgSlot = v;
312 }
313 return 0;
314}
315
316static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
317{
318 *vp = cptr->hdw->freqSlot;
319 return 0;
320}
321
322static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int v)
323{
324 unsigned freq = 0;
325 struct pvr2_hdw *hdw = cptr->hdw;
326 hdw->freqSlot = v;
327 if ((hdw->freqSlot > 0) && (hdw->freqSlot <= FREQTABLE_SIZE)) {
328 freq = hdw->freqTable[hdw->freqSlot-1];
329 }
330 if (freq && (freq != hdw->freqVal)) {
331 hdw->freqVal = freq;
332 hdw->freqDirty = !0;
333 }
334 return 0;
335}
336
337static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
338{
339 *vp = cptr->hdw->freqVal;
340 return 0;
341}
342
343static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
344{
345 return cptr->hdw->freqDirty != 0;
346}
347
348static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
349{
350 cptr->hdw->freqDirty = 0;
351}
352
353static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
354{
355 struct pvr2_hdw *hdw = cptr->hdw;
356 hdw->freqVal = v;
357 hdw->freqDirty = !0;
358 hdw->freqSlot = 0;
359 return 0;
360}
361
3ad9fc37
MI		 362static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
363{
364 /* Actual maximum depends on the video standard in effect. */
365 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
366 *vp = 480;
367 } else {
368 *vp = 576;
369 }
370 return 0;
371}
372
373static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
374{
375 /* Actual minimum depends on device type. */
376 if (cptr->hdw->hdw_type == PVR2_HDW_TYPE_24XXX) {
377 *vp = 75;
378 } else {
379 *vp = 17;
380 }
381 return 0;
382}
383
25d8527a
PK		 384static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
385{
386 /* Actual maximum depends on radio/tv mode */
387 if (cptr->hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
388 *vp = RADIO_MAX_FREQ;
389 } else {
390 *vp = TV_MAX_FREQ;
391 }
392 return 0;
393}
394
395static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
396{
397 /* Actual minimum depends on radio/tv mode */
398 if (cptr->hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
399 *vp = RADIO_MIN_FREQ;
400 } else {
401 *vp = TV_MIN_FREQ;
402 }
403 return 0;
404}
405
b30d2441
MI		 406static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
407{
408 return cptr->hdw->enc_stale != 0;
409}
410
411static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
412{
413 cptr->hdw->enc_stale = 0;
414}
415
416static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
417{
418 int ret;
419 struct v4l2_ext_controls cs;
420 struct v4l2_ext_control c1;
421 memset(&cs,0,sizeof(cs));
422 memset(&c1,0,sizeof(c1));
423 cs.controls = &c1;
424 cs.count = 1;
425 c1.id = cptr->info->v4l_id;
426 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state,&cs,
427 VIDIOC_G_EXT_CTRLS);
428 if (ret) return ret;
429 *vp = c1.value;
430 return 0;
431}
432
433static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
434{
435 int ret;
436 struct v4l2_ext_controls cs;
437 struct v4l2_ext_control c1;
438 memset(&cs,0,sizeof(cs));
439 memset(&c1,0,sizeof(c1));
440 cs.controls = &c1;
441 cs.count = 1;
442 c1.id = cptr->info->v4l_id;
443 c1.value = v;
444 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state,&cs,
445 VIDIOC_S_EXT_CTRLS);
446 if (ret) return ret;
447 cptr->hdw->enc_stale = !0;
448 return 0;
449}
450
451static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
452{
453 struct v4l2_queryctrl qctrl;
454 struct pvr2_ctl_info *info;
455 qctrl.id = cptr->info->v4l_id;
456 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
457 /* Strip out the const so we can adjust a function pointer. It's
458 OK to do this here because we know this is a dynamically created
459 control, so the underlying storage for the info pointer is (a)
460 private to us, and (b) not in read-only storage. Either we do
461 this or we significantly complicate the underlying control
462 implementation. */
463 info = (struct pvr2_ctl_info *)(cptr->info);
464 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
465 if (info->set_value) {
a0fd1cb1 466 info->set_value = NULL;
b30d2441
MI		 467 }
468 } else {
469 if (!(info->set_value)) {
470 info->set_value = ctrl_cx2341x_set;
471 }
472 }
473 return qctrl.flags;
474}
475
d855497e
MI		 476static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
477{
478 *vp = cptr->hdw->flag_streaming_enabled;
479 return 0;
480}
481
482static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
483{
484 int result = pvr2_hdw_is_hsm(cptr->hdw);
485 *vp = PVR2_CVAL_HSM_FULL;
486 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
487 if (result) *vp = PVR2_CVAL_HSM_HIGH;
488 return 0;
489}
490
491static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
492{
493 *vp = cptr->hdw->std_mask_avail;
494 return 0;
495}
496
497static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
498{
499 struct pvr2_hdw *hdw = cptr->hdw;
500 v4l2_std_id ns;
501 ns = hdw->std_mask_avail;
502 ns = (ns & ~m) | (v & m);
503 if (ns == hdw->std_mask_avail) return 0;
504 hdw->std_mask_avail = ns;
505 pvr2_hdw_internal_set_std_avail(hdw);
506 pvr2_hdw_internal_find_stdenum(hdw);
507 return 0;
508}
509
510static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
511 char *bufPtr,unsigned int bufSize,
512 unsigned int *len)
513{
514 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
515 return 0;
516}
517
518static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
519 const char *bufPtr,unsigned int bufSize,
520 int *mskp,int *valp)
521{
522 int ret;
523 v4l2_std_id id;
524 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
525 if (ret < 0) return ret;
526 if (mskp) *mskp = id;
527 if (valp) *valp = id;
528 return 0;
529}
530
531static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
532{
533 *vp = cptr->hdw->std_mask_cur;
534 return 0;
535}
536
537static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
538{
539 struct pvr2_hdw *hdw = cptr->hdw;
540 v4l2_std_id ns;
541 ns = hdw->std_mask_cur;
542 ns = (ns & ~m) | (v & m);
543 if (ns == hdw->std_mask_cur) return 0;
544 hdw->std_mask_cur = ns;
545 hdw->std_dirty = !0;
546 pvr2_hdw_internal_find_stdenum(hdw);
547 return 0;
548}
549
550static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
551{
552 return cptr->hdw->std_dirty != 0;
553}
554
555static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
556{
557 cptr->hdw->std_dirty = 0;
558}
559
560static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
561{
562 *vp = ((pvr2_hdw_get_signal_status_internal(cptr->hdw) &
563 PVR2_SIGNAL_OK) ? 1 : 0);
564 return 0;
565}
566
567static int ctrl_subsys_get(struct pvr2_ctrl *cptr,int *vp)
568{
569 *vp = cptr->hdw->subsys_enabled_mask;
570 return 0;
571}
572
573static int ctrl_subsys_set(struct pvr2_ctrl *cptr,int m,int v)
574{
575 pvr2_hdw_subsys_bit_chg_no_lock(cptr->hdw,m,v);
576 return 0;
577}
578
579static int ctrl_subsys_stream_get(struct pvr2_ctrl *cptr,int *vp)
580{
581 *vp = cptr->hdw->subsys_stream_mask;
582 return 0;
583}
584
585static int ctrl_subsys_stream_set(struct pvr2_ctrl *cptr,int m,int v)
586{
587 pvr2_hdw_subsys_stream_bit_chg_no_lock(cptr->hdw,m,v);
588 return 0;
589}
590
591static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
592{
593 struct pvr2_hdw *hdw = cptr->hdw;
594 if (v < 0) return -EINVAL;
595 if (v > hdw->std_enum_cnt) return -EINVAL;
596 hdw->std_enum_cur = v;
597 if (!v) return 0;
598 v--;
599 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
600 hdw->std_mask_cur = hdw->std_defs[v].id;
601 hdw->std_dirty = !0;
602 return 0;
603}
604
605
606static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
607{
608 *vp = cptr->hdw->std_enum_cur;
609 return 0;
610}
611
612
613static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
614{
615 return cptr->hdw->std_dirty != 0;
616}
617
618
619static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
620{
621 cptr->hdw->std_dirty = 0;
622}
623
624
625#define DEFINT(vmin,vmax) \
626 .type = pvr2_ctl_int, \
627 .def.type_int.min_value = vmin, \
628 .def.type_int.max_value = vmax
629
630#define DEFENUM(tab) \
631 .type = pvr2_ctl_enum, \
632 .def.type_enum.count = (sizeof(tab)/sizeof((tab)[0])), \
633 .def.type_enum.value_names = tab
634
33213963
MI		 635#define DEFBOOL \
636 .type = pvr2_ctl_bool
637
d855497e
MI		 638#define DEFMASK(msk,tab) \
639 .type = pvr2_ctl_bitmask, \
640 .def.type_bitmask.valid_bits = msk, \
641 .def.type_bitmask.bit_names = tab
642
643#define DEFREF(vname) \
644 .set_value = ctrl_set_##vname, \
645 .get_value = ctrl_get_##vname, \
646 .is_dirty = ctrl_isdirty_##vname, \
647 .clear_dirty = ctrl_cleardirty_##vname
648
649
650#define VCREATE_FUNCS(vname) \
651static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
652{*vp = cptr->hdw->vname##_val; return 0;} \
653static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
654{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
655static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
656{return cptr->hdw->vname##_dirty != 0;} \
657static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
658{cptr->hdw->vname##_dirty = 0;}
659
660VCREATE_FUNCS(brightness)
661VCREATE_FUNCS(contrast)
662VCREATE_FUNCS(saturation)
663VCREATE_FUNCS(hue)
664VCREATE_FUNCS(volume)
665VCREATE_FUNCS(balance)
666VCREATE_FUNCS(bass)
667VCREATE_FUNCS(treble)
668VCREATE_FUNCS(mute)
c05c0462
MI		 669VCREATE_FUNCS(input)
670VCREATE_FUNCS(audiomode)
671VCREATE_FUNCS(res_hor)
672VCREATE_FUNCS(res_ver)
d855497e 673VCREATE_FUNCS(srate)
d855497e 674
d855497e
MI		 675/* Table definition of all controls which can be manipulated */
676static const struct pvr2_ctl_info control_defs[] = {
677 {
678 .v4l_id = V4L2_CID_BRIGHTNESS,
679 .desc = "Brightness",
680 .name = "brightness",
681 .default_value = 128,
682 DEFREF(brightness),
683 DEFINT(0,255),
684 },{
685 .v4l_id = V4L2_CID_CONTRAST,
686 .desc = "Contrast",
687 .name = "contrast",
688 .default_value = 68,
689 DEFREF(contrast),
690 DEFINT(0,127),
691 },{
692 .v4l_id = V4L2_CID_SATURATION,
693 .desc = "Saturation",
694 .name = "saturation",
695 .default_value = 64,
696 DEFREF(saturation),
697 DEFINT(0,127),
698 },{
699 .v4l_id = V4L2_CID_HUE,
700 .desc = "Hue",
701 .name = "hue",
702 .default_value = 0,
703 DEFREF(hue),
704 DEFINT(-128,127),
705 },{
706 .v4l_id = V4L2_CID_AUDIO_VOLUME,
707 .desc = "Volume",
708 .name = "volume",
709 .default_value = 65535,
710 DEFREF(volume),
711 DEFINT(0,65535),
712 },{
713 .v4l_id = V4L2_CID_AUDIO_BALANCE,
714 .desc = "Balance",
715 .name = "balance",
716 .default_value = 0,
717 DEFREF(balance),
718 DEFINT(-32768,32767),
719 },{
720 .v4l_id = V4L2_CID_AUDIO_BASS,
721 .desc = "Bass",
722 .name = "bass",
723 .default_value = 0,
724 DEFREF(bass),
725 DEFINT(-32768,32767),
726 },{
727 .v4l_id = V4L2_CID_AUDIO_TREBLE,
728 .desc = "Treble",
729 .name = "treble",
730 .default_value = 0,
731 DEFREF(treble),
732 DEFINT(-32768,32767),
733 },{
734 .v4l_id = V4L2_CID_AUDIO_MUTE,
735 .desc = "Mute",
736 .name = "mute",
737 .default_value = 0,
738 DEFREF(mute),
33213963 739 DEFBOOL,
c05c0462
MI		 740 },{
741 .desc = "Video Source",
742 .name = "input",
743 .internal_id = PVR2_CID_INPUT,
744 .default_value = PVR2_CVAL_INPUT_TV,
745 DEFREF(input),
746 DEFENUM(control_values_input),
747 },{
748 .desc = "Audio Mode",
749 .name = "audio_mode",
750 .internal_id = PVR2_CID_AUDIOMODE,
751 .default_value = V4L2_TUNER_MODE_STEREO,
752 DEFREF(audiomode),
753 DEFENUM(control_values_audiomode),
754 },{
755 .desc = "Horizontal capture resolution",
756 .name = "resolution_hor",
757 .internal_id = PVR2_CID_HRES,
758 .default_value = 720,
759 DEFREF(res_hor),
3ad9fc37 760 DEFINT(19,720),
c05c0462
MI		 761 },{
762 .desc = "Vertical capture resolution",
763 .name = "resolution_ver",
764 .internal_id = PVR2_CID_VRES,
765 .default_value = 480,
766 DEFREF(res_ver),
3ad9fc37
MI		 767 DEFINT(17,576),
768 /* Hook in check for video standard and adjust maximum
769 depending on the standard. */
770 .get_max_value = ctrl_vres_max_get,
771 .get_min_value = ctrl_vres_min_get,
d855497e 772 },{
b30d2441 773 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 774 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
775 .desc = "Audio Sampling Frequency",
d855497e 776 .name = "srate",
d855497e
MI		 777 DEFREF(srate),
778 DEFENUM(control_values_srate),
d855497e
MI		 779 },{
780 .desc = "Tuner Frequency (Hz)",
781 .name = "frequency",
782 .internal_id = PVR2_CID_FREQUENCY,
783 .default_value = 175250000L,
784 .set_value = ctrl_freq_set,
785 .get_value = ctrl_freq_get,
786 .is_dirty = ctrl_freq_is_dirty,
787 .clear_dirty = ctrl_freq_clear_dirty,
25d8527a
PK		 788 DEFINT(TV_MIN_FREQ,TV_MAX_FREQ),
789 /* Hook in check for input value (tv/radio) and adjust
790 max/min values accordingly */
791 .get_max_value = ctrl_freq_max_get,
792 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 793 },{
794 .desc = "Channel",
795 .name = "channel",
796 .set_value = ctrl_channel_set,
797 .get_value = ctrl_channel_get,
798 DEFINT(0,FREQTABLE_SIZE),
799 },{
800 .desc = "Channel Program Frequency",
801 .name = "freq_table_value",
802 .set_value = ctrl_channelfreq_set,
803 .get_value = ctrl_channelfreq_get,
25d8527a 804 DEFINT(TV_MIN_FREQ,TV_MAX_FREQ),
d855497e
MI		 805 },{
806 .desc = "Channel Program ID",
807 .name = "freq_table_channel",
808 .set_value = ctrl_channelprog_set,
809 .get_value = ctrl_channelprog_get,
810 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 811 },{
812 .desc = "Streaming Enabled",
813 .name = "streaming_enabled",
814 .get_value = ctrl_streamingenabled_get,
33213963 815 DEFBOOL,
d855497e
MI		 816 },{
817 .desc = "USB Speed",
818 .name = "usb_speed",
819 .get_value = ctrl_hsm_get,
820 DEFENUM(control_values_hsm),
821 },{
822 .desc = "Signal Present",
823 .name = "signal_present",
824 .get_value = ctrl_signal_get,
33213963 825 DEFBOOL,
d855497e
MI		 826 },{
827 .desc = "Video Standards Available Mask",
828 .name = "video_standard_mask_available",
829 .internal_id = PVR2_CID_STDAVAIL,
830 .skip_init = !0,
831 .get_value = ctrl_stdavail_get,
832 .set_value = ctrl_stdavail_set,
833 .val_to_sym = ctrl_std_val_to_sym,
834 .sym_to_val = ctrl_std_sym_to_val,
835 .type = pvr2_ctl_bitmask,
836 },{
837 .desc = "Video Standards In Use Mask",
838 .name = "video_standard_mask_active",
839 .internal_id = PVR2_CID_STDCUR,
840 .skip_init = !0,
841 .get_value = ctrl_stdcur_get,
842 .set_value = ctrl_stdcur_set,
843 .is_dirty = ctrl_stdcur_is_dirty,
844 .clear_dirty = ctrl_stdcur_clear_dirty,
845 .val_to_sym = ctrl_std_val_to_sym,
846 .sym_to_val = ctrl_std_sym_to_val,
847 .type = pvr2_ctl_bitmask,
848 },{
849 .desc = "Subsystem enabled mask",
850 .name = "debug_subsys_mask",
851 .skip_init = !0,
852 .get_value = ctrl_subsys_get,
853 .set_value = ctrl_subsys_set,
854 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
855 },{
856 .desc = "Subsystem stream mask",
857 .name = "debug_subsys_stream_mask",
858 .skip_init = !0,
859 .get_value = ctrl_subsys_stream_get,
860 .set_value = ctrl_subsys_stream_set,
861 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
862 },{
863 .desc = "Video Standard Name",
864 .name = "video_standard",
865 .internal_id = PVR2_CID_STDENUM,
866 .skip_init = !0,
867 .get_value = ctrl_stdenumcur_get,
868 .set_value = ctrl_stdenumcur_set,
869 .is_dirty = ctrl_stdenumcur_is_dirty,
870 .clear_dirty = ctrl_stdenumcur_clear_dirty,
871 .type = pvr2_ctl_enum,
872 }
873};
874
c05c0462 875#define CTRLDEF_COUNT (sizeof(control_defs)/sizeof(control_defs[0]))
d855497e
MI		 876
877
878const char *pvr2_config_get_name(enum pvr2_config cfg)
879{
880 switch (cfg) {
881 case pvr2_config_empty: return "empty";
882 case pvr2_config_mpeg: return "mpeg";
883 case pvr2_config_vbi: return "vbi";
884 case pvr2_config_radio: return "radio";
885 }
886 return "<unknown>";
887}
888
889
890struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
891{
892 return hdw->usb_dev;
893}
894
895
896unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
897{
898 return hdw->serial_number;
899}
900
d855497e
MI		 901int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
902{
903 return hdw->unit_number;
904}
905
906
907/* Attempt to locate one of the given set of files. Messages are logged
908 appropriate to what has been found. The return value will be 0 or
909 greater on success (it will be the index of the file name found) and
910 fw_entry will be filled in. Otherwise a negative error is returned on
911 failure. If the return value is -ENOENT then no viable firmware file
912 could be located. */
913static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
914 const struct firmware **fw_entry,
915 const char *fwtypename,
916 unsigned int fwcount,
917 const char *fwnames[])
918{
919 unsigned int idx;
920 int ret = -EINVAL;
921 for (idx = 0; idx < fwcount; idx++) {
922 ret = request_firmware(fw_entry,
923 fwnames[idx],
924 &hdw->usb_dev->dev);
925 if (!ret) {
926 trace_firmware("Located %s firmware: %s;"
927 " uploading...",
928 fwtypename,
929 fwnames[idx]);
930 return idx;
931 }
932 if (ret == -ENOENT) continue;
933 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
934 "request_firmware fatal error with code=%d",ret);
935 return ret;
936 }
937 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
938 "***WARNING***"
939 " Device %s firmware"
940 " seems to be missing.",
941 fwtypename);
942 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
943 "Did you install the pvrusb2 firmware files"
944 " in their proper location?");
945 if (fwcount == 1) {
946 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
947 "request_firmware unable to locate %s file %s",
948 fwtypename,fwnames[0]);
949 } else {
950 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
951 "request_firmware unable to locate"
952 " one of the following %s files:",
953 fwtypename);
954 for (idx = 0; idx < fwcount; idx++) {
955 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
956 "request_firmware: Failed to find %s",
957 fwnames[idx]);
958 }
959 }
960 return ret;
961}
962
963
964/*
965 * pvr2_upload_firmware1().
966 *
967 * Send the 8051 firmware to the device. After the upload, arrange for
968 * device to re-enumerate.
969 *
970 * NOTE : the pointer to the firmware data given by request_firmware()
971 * is not suitable for an usb transaction.
972 *
973 */
07e337ee 974static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 975{
a0fd1cb1 976 const struct firmware *fw_entry = NULL;
d855497e
MI		 977 void *fw_ptr;
978 unsigned int pipe;
979 int ret;
980 u16 address;
981 static const char *fw_files_29xxx[] = {
982 "v4l-pvrusb2-29xxx-01.fw",
983 };
d855497e
MI		 984 static const char *fw_files_24xxx[] = {
985 "v4l-pvrusb2-24xxx-01.fw",
986 };
d855497e
MI		 987 static const struct pvr2_string_table fw_file_defs[] = {
988 [PVR2_HDW_TYPE_29XXX] = {
989 fw_files_29xxx,
990 sizeof(fw_files_29xxx)/sizeof(fw_files_29xxx[0]),
991 },
d855497e
MI		 992 [PVR2_HDW_TYPE_24XXX] = {
993 fw_files_24xxx,
994 sizeof(fw_files_24xxx)/sizeof(fw_files_24xxx[0]),
995 },
d855497e
MI		 996 };
997 hdw->fw1_state = FW1_STATE_FAILED; // default result
998
999 trace_firmware("pvr2_upload_firmware1");
1000
1001 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1002 fw_file_defs[hdw->hdw_type].cnt,
1003 fw_file_defs[hdw->hdw_type].lst);
1004 if (ret < 0) {
1005 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1006 return ret;
1007 }
1008
1009 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1010 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1011
1012 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1013
1014 if (fw_entry->size != 0x2000){
1015 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1016 release_firmware(fw_entry);
1017 return -ENOMEM;
1018 }
1019
1020 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1021 if (fw_ptr == NULL){
1022 release_firmware(fw_entry);
1023 return -ENOMEM;
1024 }
1025
1026 /* We have to hold the CPU during firmware upload. */
1027 pvr2_hdw_cpureset_assert(hdw,1);
1028
1029 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1030 chunk. */
1031
1032 ret = 0;
1033 for(address = 0; address < fw_entry->size; address += 0x800) {
1034 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1035 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1036 0, fw_ptr, 0x800, HZ);
1037 }
1038
1039 trace_firmware("Upload done, releasing device's CPU");
1040
1041 /* Now release the CPU. It will disconnect and reconnect later. */
1042 pvr2_hdw_cpureset_assert(hdw,0);
1043
1044 kfree(fw_ptr);
1045 release_firmware(fw_entry);
1046
1047 trace_firmware("Upload done (%d bytes sent)",ret);
1048
1049 /* We should have written 8192 bytes */
1050 if (ret == 8192) {
1051 hdw->fw1_state = FW1_STATE_RELOAD;
1052 return 0;
1053 }
1054
1055 return -EIO;
1056}
1057
1058
1059/*
1060 * pvr2_upload_firmware2()
1061 *
1062 * This uploads encoder firmware on endpoint 2.
1063 *
1064 */
1065
1066int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1067{
a0fd1cb1 1068 const struct firmware *fw_entry = NULL;
d855497e
MI		 1069 void *fw_ptr;
1070 unsigned int pipe, fw_len, fw_done;
1071 int actual_length;
1072 int ret = 0;
1073 int fwidx;
1074 static const char *fw_files[] = {
1075 CX2341X_FIRM_ENC_FILENAME,
1076 };
1077
1078 trace_firmware("pvr2_upload_firmware2");
1079
1080 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1081 sizeof(fw_files)/sizeof(fw_files[0]),
1082 fw_files);
1083 if (ret < 0) return ret;
1084 fwidx = ret;
1085 ret = 0;
b30d2441
MI		 1086 /* Since we're about to completely reinitialize the encoder,
1087 invalidate our cached copy of its configuration state. Next
1088 time we configure the encoder, then we'll fully configure it. */
1089 hdw->enc_cur_valid = 0;
d855497e
MI		 1090
1091 /* First prepare firmware loading */
1092 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1093 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1094 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1095 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1096 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1097 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1098 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1099 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1100 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1101 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1102 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1103 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1104 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1105 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1106 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1107 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1108 ret |= pvr2_write_u8(hdw, 0x52, 0);
1109 ret |= pvr2_write_u16(hdw, 0x0600, 0);
1110
1111 if (ret) {
1112 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1113 "firmware2 upload prep failed, ret=%d",ret);
1114 release_firmware(fw_entry);
1115 return ret;
1116 }
1117
1118 /* Now send firmware */
1119
1120 fw_len = fw_entry->size;
1121
1122 if (fw_len % FIRMWARE_CHUNK_SIZE) {
1123 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1124 "size of %s firmware"
1125 " must be a multiple of 8192B",
1126 fw_files[fwidx]);
1127 release_firmware(fw_entry);
1128 return -1;
1129 }
1130
1131 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1132 if (fw_ptr == NULL){
1133 release_firmware(fw_entry);
1134 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1135 "failed to allocate memory for firmware2 upload");
1136 return -ENOMEM;
1137 }
1138
1139 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1140
1141 for (fw_done = 0 ; (fw_done < fw_len) && !ret ;
1142 fw_done += FIRMWARE_CHUNK_SIZE ) {
1143 int i;
1144 memcpy(fw_ptr, fw_entry->data + fw_done, FIRMWARE_CHUNK_SIZE);
1145 /* Usbsnoop log shows that we must swap bytes... */
1146 for (i = 0; i < FIRMWARE_CHUNK_SIZE/4 ; i++)
1147 ((u32 *)fw_ptr)[i] = ___swab32(((u32 *)fw_ptr)[i]);
1148
1149 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,
1150 FIRMWARE_CHUNK_SIZE,
1151 &actual_length, HZ);
1152 ret |= (actual_length != FIRMWARE_CHUNK_SIZE);
1153 }
1154
1155 trace_firmware("upload of %s : %i / %i ",
1156 fw_files[fwidx],fw_done,fw_len);
1157
1158 kfree(fw_ptr);
1159 release_firmware(fw_entry);
1160
1161 if (ret) {
1162 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1163 "firmware2 upload transfer failure");
1164 return ret;
1165 }
1166
1167 /* Finish upload */
1168
1169 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1170 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1171 ret |= pvr2_write_u16(hdw, 0x0600, 0);
1172
1173 if (ret) {
1174 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1175 "firmware2 upload post-proc failure");
1176 } else {
1177 hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_FIRMWARE);
1178 }
1179 return ret;
1180}
1181
1182
1183#define FIRMWARE_RECOVERY_BITS \
1184 ((1<<PVR2_SUBSYS_B_ENC_CFG) | \
1185 (1<<PVR2_SUBSYS_B_ENC_RUN) | \
1186 (1<<PVR2_SUBSYS_B_ENC_FIRMWARE) | \
1187 (1<<PVR2_SUBSYS_B_USBSTREAM_RUN))
1188
1189/*
1190
1191 This single function is key to pretty much everything. The pvrusb2
1192 device can logically be viewed as a series of subsystems which can be
1193 stopped / started or unconfigured / configured. To get things streaming,
1194 one must configure everything and start everything, but there may be
1195 various reasons over time to deconfigure something or stop something.
1196 This function handles all of this activity. Everything EVERYWHERE that
1197 must affect a subsystem eventually comes here to do the work.
1198
1199 The current state of all subsystems is represented by a single bit mask,
1200 known as subsys_enabled_mask. The bit positions are defined by the
1201 PVR2_SUBSYS_xxxx macros, with one subsystem per bit position. At any
1202 time the set of configured or active subsystems can be queried just by
1203 looking at that mask. To change bits in that mask, this function here
1204 must be called. The "msk" argument indicates which bit positions to
1205 change, and the "val" argument defines the new values for the positions
1206 defined by "msk".
1207
1208 There is a priority ordering of starting / stopping things, and for
1209 multiple requested changes, this function implements that ordering.
1210 (Thus we will act on a request to load encoder firmware before we
1211 configure the encoder.) In addition to priority ordering, there is a
1212 recovery strategy implemented here. If a particular step fails and we
1213 detect that failure, this function will clear the affected subsystem bits
1214 and restart. Thus we have a means for recovering from a dead encoder:
1215 Clear all bits that correspond to subsystems that we need to restart /
1216 reconfigure and start over.
1217
1218*/
07e337ee
AB		 1219static void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
1220 unsigned long msk,
1221 unsigned long val)
d855497e
MI		 1222{
1223 unsigned long nmsk;
1224 unsigned long vmsk;
1225 int ret;
1226 unsigned int tryCount = 0;
1227
1228 if (!hdw->flag_ok) return;
1229
1230 msk &= PVR2_SUBSYS_ALL;
eb8e0ee4
MI		 1231 nmsk = (hdw->subsys_enabled_mask & ~msk) | (val & msk);
1232 nmsk &= PVR2_SUBSYS_ALL;
d855497e
MI		 1233
1234 for (;;) {
1235 tryCount++;
eb8e0ee4
MI		 1236 if (!((nmsk ^ hdw->subsys_enabled_mask) &
1237 PVR2_SUBSYS_ALL)) break;
d855497e
MI		 1238 if (tryCount > 4) {
1239 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1240 "Too many retries when configuring device;"
1241 " giving up");
1242 pvr2_hdw_render_useless(hdw);
1243 break;
1244 }
1245 if (tryCount > 1) {
1246 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1247 "Retrying device reconfiguration");
1248 }
1249 pvr2_trace(PVR2_TRACE_INIT,
1250 "subsys mask changing 0x%lx:0x%lx"
1251 " from 0x%lx to 0x%lx",
1252 msk,val,hdw->subsys_enabled_mask,nmsk);
1253
1254 vmsk = (nmsk ^ hdw->subsys_enabled_mask) &
1255 hdw->subsys_enabled_mask;
1256 if (vmsk) {
1257 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1258 pvr2_trace(PVR2_TRACE_CTL,
1259 "/*---TRACE_CTL----*/"
1260 " pvr2_encoder_stop");
1261 ret = pvr2_encoder_stop(hdw);
1262 if (ret) {
1263 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1264 "Error recovery initiated");
1265 hdw->subsys_enabled_mask &=
1266 ~FIRMWARE_RECOVERY_BITS;
1267 continue;
1268 }
1269 }
1270 if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1271 pvr2_trace(PVR2_TRACE_CTL,
1272 "/*---TRACE_CTL----*/"
1273 " pvr2_hdw_cmd_usbstream(0)");
1274 pvr2_hdw_cmd_usbstream(hdw,0);
1275 }
1276 if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1277 pvr2_trace(PVR2_TRACE_CTL,
1278 "/*---TRACE_CTL----*/"
1279 " decoder disable");
1280 if (hdw->decoder_ctrl) {
1281 hdw->decoder_ctrl->enable(
1282 hdw->decoder_ctrl->ctxt,0);
1283 } else {
1284 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1285 "WARNING:"
1286 " No decoder present");
1287 }
1288 hdw->subsys_enabled_mask &=
1289 ~(1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1290 }
1291 if (vmsk & PVR2_SUBSYS_CFG_ALL) {
1292 hdw->subsys_enabled_mask &=
1293 ~(vmsk & PVR2_SUBSYS_CFG_ALL);
1294 }
1295 }
1296 vmsk = (nmsk ^ hdw->subsys_enabled_mask) & nmsk;
1297 if (vmsk) {
1298 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_FIRMWARE)) {
1299 pvr2_trace(PVR2_TRACE_CTL,
1300 "/*---TRACE_CTL----*/"
1301 " pvr2_upload_firmware2");
1302 ret = pvr2_upload_firmware2(hdw);
1303 if (ret) {
1304 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1305 "Failure uploading encoder"
1306 " firmware");
1307 pvr2_hdw_render_useless(hdw);
1308 break;
1309 }
1310 }
1311 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_CFG)) {
1312 pvr2_trace(PVR2_TRACE_CTL,
1313 "/*---TRACE_CTL----*/"
1314 " pvr2_encoder_configure");
1315 ret = pvr2_encoder_configure(hdw);
1316 if (ret) {
1317 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1318 "Error recovery initiated");
1319 hdw->subsys_enabled_mask &=
1320 ~FIRMWARE_RECOVERY_BITS;
1321 continue;
1322 }
1323 }
1324 if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1325 pvr2_trace(PVR2_TRACE_CTL,
1326 "/*---TRACE_CTL----*/"
1327 " decoder enable");
1328 if (hdw->decoder_ctrl) {
1329 hdw->decoder_ctrl->enable(
1330 hdw->decoder_ctrl->ctxt,!0);
1331 } else {
1332 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1333 "WARNING:"
1334 " No decoder present");
1335 }
1336 hdw->subsys_enabled_mask |=
1337 (1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1338 }
1339 if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1340 pvr2_trace(PVR2_TRACE_CTL,
1341 "/*---TRACE_CTL----*/"
1342 " pvr2_hdw_cmd_usbstream(1)");
1343 pvr2_hdw_cmd_usbstream(hdw,!0);
1344 }
1345 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1346 pvr2_trace(PVR2_TRACE_CTL,
1347 "/*---TRACE_CTL----*/"
1348 " pvr2_encoder_start");
1349 ret = pvr2_encoder_start(hdw);
1350 if (ret) {
1351 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1352 "Error recovery initiated");
1353 hdw->subsys_enabled_mask &=
1354 ~FIRMWARE_RECOVERY_BITS;
1355 continue;
1356 }
1357 }
1358 }
1359 }
1360}
1361
1362
1363void pvr2_hdw_subsys_bit_chg(struct pvr2_hdw *hdw,
1364 unsigned long msk,unsigned long val)
1365{
1366 LOCK_TAKE(hdw->big_lock); do {
1367 pvr2_hdw_subsys_bit_chg_no_lock(hdw,msk,val);
1368 } while (0); LOCK_GIVE(hdw->big_lock);
1369}
1370
1371
d855497e
MI		 1372unsigned long pvr2_hdw_subsys_get(struct pvr2_hdw *hdw)
1373{
1374 return hdw->subsys_enabled_mask;
1375}
1376
1377
1378unsigned long pvr2_hdw_subsys_stream_get(struct pvr2_hdw *hdw)
1379{
1380 return hdw->subsys_stream_mask;
1381}
1382
1383
07e337ee
AB		 1384static void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
1385 unsigned long msk,
1386 unsigned long val)
d855497e
MI		 1387{
1388 unsigned long val2;
1389 msk &= PVR2_SUBSYS_ALL;
1390 val2 = ((hdw->subsys_stream_mask & ~msk) | (val & msk));
1391 pvr2_trace(PVR2_TRACE_INIT,
1392 "stream mask changing 0x%lx:0x%lx from 0x%lx to 0x%lx",
1393 msk,val,hdw->subsys_stream_mask,val2);
1394 hdw->subsys_stream_mask = val2;
1395}
1396
1397
1398void pvr2_hdw_subsys_stream_bit_chg(struct pvr2_hdw *hdw,
1399 unsigned long msk,
1400 unsigned long val)
1401{
1402 LOCK_TAKE(hdw->big_lock); do {
1403 pvr2_hdw_subsys_stream_bit_chg_no_lock(hdw,msk,val);
1404 } while (0); LOCK_GIVE(hdw->big_lock);
1405}
1406
1407
07e337ee 1408static int pvr2_hdw_set_streaming_no_lock(struct pvr2_hdw *hdw,int enableFl)
d855497e
MI		 1409{
1410 if ((!enableFl) == !(hdw->flag_streaming_enabled)) return 0;
1411 if (enableFl) {
1412 pvr2_trace(PVR2_TRACE_START_STOP,
1413 "/*--TRACE_STREAM--*/ enable");
1414 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,~0);
1415 } else {
1416 pvr2_trace(PVR2_TRACE_START_STOP,
1417 "/*--TRACE_STREAM--*/ disable");
1418 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1419 }
1420 if (!hdw->flag_ok) return -EIO;
1421 hdw->flag_streaming_enabled = enableFl != 0;
1422 return 0;
1423}
1424
1425
1426int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1427{
1428 return hdw->flag_streaming_enabled != 0;
1429}
1430
1431
1432int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1433{
1434 int ret;
1435 LOCK_TAKE(hdw->big_lock); do {
1436 ret = pvr2_hdw_set_streaming_no_lock(hdw,enable_flag);
1437 } while (0); LOCK_GIVE(hdw->big_lock);
1438 return ret;
1439}
1440
1441
07e337ee
AB		 1442static int pvr2_hdw_set_stream_type_no_lock(struct pvr2_hdw *hdw,
1443 enum pvr2_config config)
d855497e
MI		 1444{
1445 unsigned long sm = hdw->subsys_enabled_mask;
1446 if (!hdw->flag_ok) return -EIO;
1447 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1448 hdw->config = config;
1449 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,sm);
1450 return 0;
1451}
1452
1453
1454int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1455{
1456 int ret;
1457 if (!hdw->flag_ok) return -EIO;
1458 LOCK_TAKE(hdw->big_lock);
1459 ret = pvr2_hdw_set_stream_type_no_lock(hdw,config);
1460 LOCK_GIVE(hdw->big_lock);
1461 return ret;
1462}
1463
1464
1465static int get_default_tuner_type(struct pvr2_hdw *hdw)
1466{
1467 int unit_number = hdw->unit_number;
1468 int tp = -1;
1469 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1470 tp = tuner[unit_number];
1471 }
1472 if (tp < 0) return -EINVAL;
1473 hdw->tuner_type = tp;
1474 return 0;
1475}
1476
1477
1478static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1479{
1480 int unit_number = hdw->unit_number;
1481 int tp = 0;
1482 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1483 tp = video_std[unit_number];
1484 }
1485 return tp;
1486}
1487
1488
1489static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1490{
1491 int unit_number = hdw->unit_number;
1492 int tp = 0;
1493 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1494 tp = tolerance[unit_number];
1495 }
1496 return tp;
1497}
1498
1499
1500static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1501{
1502 /* Try a harmless request to fetch the eeprom's address over
1503 endpoint 1. See what happens. Only the full FX2 image can
1504 respond to this. If this probe fails then likely the FX2
1505 firmware needs be loaded. */
1506 int result;
1507 LOCK_TAKE(hdw->ctl_lock); do {
1508 hdw->cmd_buffer[0] = 0xeb;
1509 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1510 hdw->cmd_buffer,1,
1511 hdw->cmd_buffer,1);
1512 if (result < 0) break;
1513 } while(0); LOCK_GIVE(hdw->ctl_lock);
1514 if (result) {
1515 pvr2_trace(PVR2_TRACE_INIT,
1516 "Probe of device endpoint 1 result status %d",
1517 result);
1518 } else {
1519 pvr2_trace(PVR2_TRACE_INIT,
1520 "Probe of device endpoint 1 succeeded");
1521 }
1522 return result == 0;
1523}
1524
1525static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1526{
1527 char buf[40];
1528 unsigned int bcnt;
1529 v4l2_std_id std1,std2;
1530
1531 std1 = get_default_standard(hdw);
1532
1533 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1534 pvr2_trace(PVR2_TRACE_INIT,
1535 "Supported video standard(s) reported by eeprom: %.*s",
1536 bcnt,buf);
1537
1538 hdw->std_mask_avail = hdw->std_mask_eeprom;
1539
1540 std2 = std1 & ~hdw->std_mask_avail;
1541 if (std2) {
1542 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1543 pvr2_trace(PVR2_TRACE_INIT,
1544 "Expanding supported video standards"
1545 " to include: %.*s",
1546 bcnt,buf);
1547 hdw->std_mask_avail |= std2;
1548 }
1549
1550 pvr2_hdw_internal_set_std_avail(hdw);
1551
1552 if (std1) {
1553 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1554 pvr2_trace(PVR2_TRACE_INIT,
1555 "Initial video standard forced to %.*s",
1556 bcnt,buf);
1557 hdw->std_mask_cur = std1;
1558 hdw->std_dirty = !0;
1559 pvr2_hdw_internal_find_stdenum(hdw);
1560 return;
1561 }
1562
1563 if (hdw->std_enum_cnt > 1) {
1564 // Autoselect the first listed standard
1565 hdw->std_enum_cur = 1;
1566 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1567 hdw->std_dirty = !0;
1568 pvr2_trace(PVR2_TRACE_INIT,
1569 "Initial video standard auto-selected to %s",
1570 hdw->std_defs[hdw->std_enum_cur-1].name);
1571 return;
1572 }
1573
0885ba1d 1574 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1575 "Unable to select a viable initial video standard");
1576}
1577
1578
1579static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1580{
1581 int ret;
1582 unsigned int idx;
1583 struct pvr2_ctrl *cptr;
1584 int reloadFl = 0;
1585 if (!reloadFl) {
1586 reloadFl = (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1587 == 0);
1588 if (reloadFl) {
1589 pvr2_trace(PVR2_TRACE_INIT,
1590 "USB endpoint config looks strange"
1591 "; possibly firmware needs to be loaded");
1592 }
1593 }
1594 if (!reloadFl) {
1595 reloadFl = !pvr2_hdw_check_firmware(hdw);
1596 if (reloadFl) {
1597 pvr2_trace(PVR2_TRACE_INIT,
1598 "Check for FX2 firmware failed"
1599 "; possibly firmware needs to be loaded");
1600 }
1601 }
1602 if (reloadFl) {
1603 if (pvr2_upload_firmware1(hdw) != 0) {
1604 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1605 "Failure uploading firmware1");
1606 }
1607 return;
1608 }
1609 hdw->fw1_state = FW1_STATE_OK;
1610
1611 if (initusbreset) {
1612 pvr2_hdw_device_reset(hdw);
1613 }
1614 if (!pvr2_hdw_dev_ok(hdw)) return;
1615
1616 for (idx = 0; idx < pvr2_client_lists[hdw->hdw_type].cnt; idx++) {
1617 request_module(pvr2_client_lists[hdw->hdw_type].lst[idx]);
1618 }
1619
1620 pvr2_hdw_cmd_powerup(hdw);
1621 if (!pvr2_hdw_dev_ok(hdw)) return;
1622
1623 if (pvr2_upload_firmware2(hdw)){
1624 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"device unstable!!");
1625 pvr2_hdw_render_useless(hdw);
1626 return;
1627 }
1628
1629 // This step MUST happen after the earlier powerup step.
1630 pvr2_i2c_core_init(hdw);
1631 if (!pvr2_hdw_dev_ok(hdw)) return;
1632
c05c0462 1633 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 1634 cptr = hdw->controls + idx;
1635 if (cptr->info->skip_init) continue;
1636 if (!cptr->info->set_value) continue;
1637 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1638 }
1639
1640 // Do not use pvr2_reset_ctl_endpoints() here. It is not
1641 // thread-safe against the normal pvr2_send_request() mechanism.
1642 // (We should make it thread safe).
1643
1644 ret = pvr2_hdw_get_eeprom_addr(hdw);
1645 if (!pvr2_hdw_dev_ok(hdw)) return;
1646 if (ret < 0) {
1647 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1648 "Unable to determine location of eeprom, skipping");
1649 } else {
1650 hdw->eeprom_addr = ret;
1651 pvr2_eeprom_analyze(hdw);
1652 if (!pvr2_hdw_dev_ok(hdw)) return;
1653 }
1654
1655 pvr2_hdw_setup_std(hdw);
1656
1657 if (!get_default_tuner_type(hdw)) {
1658 pvr2_trace(PVR2_TRACE_INIT,
1659 "pvr2_hdw_setup: Tuner type overridden to %d",
1660 hdw->tuner_type);
1661 }
1662
1663 hdw->tuner_updated = !0;
1664 pvr2_i2c_core_check_stale(hdw);
1665 hdw->tuner_updated = 0;
1666
1667 if (!pvr2_hdw_dev_ok(hdw)) return;
1668
1669 pvr2_hdw_commit_ctl_internal(hdw);
1670 if (!pvr2_hdw_dev_ok(hdw)) return;
1671
1672 hdw->vid_stream = pvr2_stream_create();
1673 if (!pvr2_hdw_dev_ok(hdw)) return;
1674 pvr2_trace(PVR2_TRACE_INIT,
1675 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1676 if (hdw->vid_stream) {
1677 idx = get_default_error_tolerance(hdw);
1678 if (idx) {
1679 pvr2_trace(PVR2_TRACE_INIT,
1680 "pvr2_hdw_setup: video stream %p"
1681 " setting tolerance %u",
1682 hdw->vid_stream,idx);
1683 }
1684 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1685 PVR2_VID_ENDPOINT,idx);
1686 }
1687
1688 if (!pvr2_hdw_dev_ok(hdw)) return;
1689
1690 /* Make sure everything is up to date */
1691 pvr2_i2c_core_sync(hdw);
1692
1693 if (!pvr2_hdw_dev_ok(hdw)) return;
1694
1695 hdw->flag_init_ok = !0;
1696}
1697
1698
1699int pvr2_hdw_setup(struct pvr2_hdw *hdw)
1700{
1701 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1702 LOCK_TAKE(hdw->big_lock); do {
1703 pvr2_hdw_setup_low(hdw);
1704 pvr2_trace(PVR2_TRACE_INIT,
1705 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1706 hdw,hdw->flag_ok,hdw->flag_init_ok);
1707 if (pvr2_hdw_dev_ok(hdw)) {
1708 if (pvr2_hdw_init_ok(hdw)) {
1709 pvr2_trace(
1710 PVR2_TRACE_INFO,
1711 "Device initialization"
1712 " completed successfully.");
1713 break;
1714 }
1715 if (hdw->fw1_state == FW1_STATE_RELOAD) {
1716 pvr2_trace(
1717 PVR2_TRACE_INFO,
1718 "Device microcontroller firmware"
1719 " (re)loaded; it should now reset"
1720 " and reconnect.");
1721 break;
1722 }
1723 pvr2_trace(
1724 PVR2_TRACE_ERROR_LEGS,
1725 "Device initialization was not successful.");
1726 if (hdw->fw1_state == FW1_STATE_MISSING) {
1727 pvr2_trace(
1728 PVR2_TRACE_ERROR_LEGS,
1729 "Giving up since device"
1730 " microcontroller firmware"
1731 " appears to be missing.");
1732 break;
1733 }
1734 }
1735 if (procreload) {
1736 pvr2_trace(
1737 PVR2_TRACE_ERROR_LEGS,
1738 "Attempting pvrusb2 recovery by reloading"
1739 " primary firmware.");
1740 pvr2_trace(
1741 PVR2_TRACE_ERROR_LEGS,
1742 "If this works, device should disconnect"
1743 " and reconnect in a sane state.");
1744 hdw->fw1_state = FW1_STATE_UNKNOWN;
1745 pvr2_upload_firmware1(hdw);
1746 } else {
1747 pvr2_trace(
1748 PVR2_TRACE_ERROR_LEGS,
1749 "***WARNING*** pvrusb2 device hardware"
1750 " appears to be jammed"
1751 " and I can't clear it.");
1752 pvr2_trace(
1753 PVR2_TRACE_ERROR_LEGS,
1754 "You might need to power cycle"
1755 " the pvrusb2 device"
1756 " in order to recover.");
1757 }
1758 } while (0); LOCK_GIVE(hdw->big_lock);
1759 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1760 return hdw->flag_init_ok;
1761}
1762
1763
1764/* Create and return a structure for interacting with the underlying
1765 hardware */
1766struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1767 const struct usb_device_id *devid)
1768{
1769 unsigned int idx,cnt1,cnt2;
1770 struct pvr2_hdw *hdw;
1771 unsigned int hdw_type;
1772 int valid_std_mask;
1773 struct pvr2_ctrl *cptr;
1774 __u8 ifnum;
b30d2441
MI		 1775 struct v4l2_queryctrl qctrl;
1776 struct pvr2_ctl_info *ciptr;
d855497e
MI		 1777
1778 hdw_type = devid - pvr2_device_table;
1779 if (hdw_type >=
1780 sizeof(pvr2_device_names)/sizeof(pvr2_device_names[0])) {
1781 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1782 "Bogus device type of %u reported",hdw_type);
a0fd1cb1 1783 return NULL;
d855497e
MI		 1784 }
1785
1786 hdw = kmalloc(sizeof(*hdw),GFP_KERNEL);
1787 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1788 hdw,pvr2_device_names[hdw_type]);
1789 if (!hdw) goto fail;
1790 memset(hdw,0,sizeof(*hdw));
b30d2441 1791 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 1792
c05c0462 1793 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 1794 hdw->control_cnt += MPEGDEF_COUNT;
c05c0462 1795 hdw->controls = kmalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 1796 GFP_KERNEL);
1797 if (!hdw->controls) goto fail;
c05c0462 1798 memset(hdw->controls,0,sizeof(struct pvr2_ctrl) * hdw->control_cnt);
d855497e 1799 hdw->hdw_type = hdw_type;
c05c0462
MI		 1800 for (idx = 0; idx < hdw->control_cnt; idx++) {
1801 cptr = hdw->controls + idx;
1802 cptr->hdw = hdw;
1803 }
d855497e
MI		 1804 for (idx = 0; idx < 32; idx++) {
1805 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1806 }
c05c0462 1807 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 1808 cptr = hdw->controls + idx;
d855497e
MI		 1809 cptr->info = control_defs+idx;
1810 }
b30d2441
MI		 1811 /* Define and configure additional controls from cx2341x module. */
1812 hdw->mpeg_ctrl_info = kmalloc(
1813 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1814 if (!hdw->mpeg_ctrl_info) goto fail;
1815 memset(hdw->mpeg_ctrl_info,0,
1816 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT);
1817 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1818 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1819 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1820 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1821 ciptr->name = mpeg_ids[idx].strid;
1822 ciptr->v4l_id = mpeg_ids[idx].id;
1823 ciptr->skip_init = !0;
1824 ciptr->get_value = ctrl_cx2341x_get;
1825 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1826 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1827 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1828 qctrl.id = ciptr->v4l_id;
1829 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1830 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1831 ciptr->set_value = ctrl_cx2341x_set;
1832 }
1833 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1834 PVR2_CTLD_INFO_DESC_SIZE);
1835 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
1836 ciptr->default_value = qctrl.default_value;
1837 switch (qctrl.type) {
1838 default:
1839 case V4L2_CTRL_TYPE_INTEGER:
1840 ciptr->type = pvr2_ctl_int;
1841 ciptr->def.type_int.min_value = qctrl.minimum;
1842 ciptr->def.type_int.max_value = qctrl.maximum;
1843 break;
1844 case V4L2_CTRL_TYPE_BOOLEAN:
1845 ciptr->type = pvr2_ctl_bool;
1846 break;
1847 case V4L2_CTRL_TYPE_MENU:
1848 ciptr->type = pvr2_ctl_enum;
1849 ciptr->def.type_enum.value_names =
1850 cx2341x_ctrl_get_menu(ciptr->v4l_id);
1851 for (cnt1 = 0;
1852 ciptr->def.type_enum.value_names[cnt1] != NULL;
1853 cnt1++) { }
1854 ciptr->def.type_enum.count = cnt1;
1855 break;
1856 }
1857 cptr->info = ciptr;
1858 }
d855497e
MI		 1859
1860 // Initialize video standard enum dynamic control
1861 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1862 if (cptr) {
1863 memcpy(&hdw->std_info_enum,cptr->info,
1864 sizeof(hdw->std_info_enum));
1865 cptr->info = &hdw->std_info_enum;
1866
1867 }
1868 // Initialize control data regarding video standard masks
1869 valid_std_mask = pvr2_std_get_usable();
1870 for (idx = 0; idx < 32; idx++) {
1871 if (!(valid_std_mask & (1 << idx))) continue;
1872 cnt1 = pvr2_std_id_to_str(
1873 hdw->std_mask_names[idx],
1874 sizeof(hdw->std_mask_names[idx])-1,
1875 1 << idx);
1876 hdw->std_mask_names[idx][cnt1] = 0;
1877 }
1878 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1879 if (cptr) {
1880 memcpy(&hdw->std_info_avail,cptr->info,
1881 sizeof(hdw->std_info_avail));
1882 cptr->info = &hdw->std_info_avail;
1883 hdw->std_info_avail.def.type_bitmask.bit_names =
1884 hdw->std_mask_ptrs;
1885 hdw->std_info_avail.def.type_bitmask.valid_bits =
1886 valid_std_mask;
1887 }
1888 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1889 if (cptr) {
1890 memcpy(&hdw->std_info_cur,cptr->info,
1891 sizeof(hdw->std_info_cur));
1892 cptr->info = &hdw->std_info_cur;
1893 hdw->std_info_cur.def.type_bitmask.bit_names =
1894 hdw->std_mask_ptrs;
1895 hdw->std_info_avail.def.type_bitmask.valid_bits =
1896 valid_std_mask;
1897 }
1898
1899 hdw->eeprom_addr = -1;
1900 hdw->unit_number = -1;
1901 hdw->v4l_minor_number = -1;
1902 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1903 if (!hdw->ctl_write_buffer) goto fail;
1904 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1905 if (!hdw->ctl_read_buffer) goto fail;
1906 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
1907 if (!hdw->ctl_write_urb) goto fail;
1908 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
1909 if (!hdw->ctl_read_urb) goto fail;
1910
1911 down(&pvr2_unit_sem); do {
1912 for (idx = 0; idx < PVR_NUM; idx++) {
1913 if (unit_pointers[idx]) continue;
1914 hdw->unit_number = idx;
1915 unit_pointers[idx] = hdw;
1916 break;
1917 }
1918 } while (0); up(&pvr2_unit_sem);
1919
1920 cnt1 = 0;
1921 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
1922 cnt1 += cnt2;
1923 if (hdw->unit_number >= 0) {
1924 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
1925 ('a' + hdw->unit_number));
1926 cnt1 += cnt2;
1927 }
1928 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
1929 hdw->name[cnt1] = 0;
1930
1931 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
1932 hdw->unit_number,hdw->name);
1933
1934 hdw->tuner_type = -1;
1935 hdw->flag_ok = !0;
1936 /* Initialize the mask of subsystems that we will shut down when we
1937 stop streaming. */
1938 hdw->subsys_stream_mask = PVR2_SUBSYS_RUN_ALL;
1939 hdw->subsys_stream_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
1940
1941 pvr2_trace(PVR2_TRACE_INIT,"subsys_stream_mask: 0x%lx",
1942 hdw->subsys_stream_mask);
1943
1944 hdw->usb_intf = intf;
1945 hdw->usb_dev = interface_to_usbdev(intf);
1946
1947 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
1948 usb_set_interface(hdw->usb_dev,ifnum,0);
1949
1950 mutex_init(&hdw->ctl_lock_mutex);
1951 mutex_init(&hdw->big_lock_mutex);
1952
1953 return hdw;
1954 fail:
1955 if (hdw) {
5e55d2ce
MK		 1956 usb_free_urb(hdw->ctl_read_urb);
1957 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 1958 kfree(hdw->ctl_read_buffer);
1959 kfree(hdw->ctl_write_buffer);
1960 kfree(hdw->controls);
1961 kfree(hdw->mpeg_ctrl_info);
d855497e
MI		 1962 kfree(hdw);
1963 }
a0fd1cb1 1964 return NULL;
d855497e
MI		 1965}
1966
1967
1968/* Remove _all_ associations between this driver and the underlying USB
1969 layer. */
07e337ee 1970static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 1971{
1972 if (hdw->flag_disconnected) return;
1973 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
1974 if (hdw->ctl_read_urb) {
1975 usb_kill_urb(hdw->ctl_read_urb);
1976 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 1977 hdw->ctl_read_urb = NULL;
d855497e
MI		 1978 }
1979 if (hdw->ctl_write_urb) {
1980 usb_kill_urb(hdw->ctl_write_urb);
1981 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 1982 hdw->ctl_write_urb = NULL;
d855497e
MI		 1983 }
1984 if (hdw->ctl_read_buffer) {
1985 kfree(hdw->ctl_read_buffer);
a0fd1cb1 1986 hdw->ctl_read_buffer = NULL;
d855497e
MI		 1987 }
1988 if (hdw->ctl_write_buffer) {
1989 kfree(hdw->ctl_write_buffer);
a0fd1cb1 1990 hdw->ctl_write_buffer = NULL;
d855497e
MI		 1991 }
1992 pvr2_hdw_render_useless_unlocked(hdw);
1993 hdw->flag_disconnected = !0;
a0fd1cb1
MI		 1994 hdw->usb_dev = NULL;
1995 hdw->usb_intf = NULL;
d855497e
MI		 1996}
1997
1998
1999/* Destroy hardware interaction structure */
2000void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2001{
2002 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2003 if (hdw->fw_buffer) {
2004 kfree(hdw->fw_buffer);
a0fd1cb1 2005 hdw->fw_buffer = NULL;
d855497e
MI		 2006 }
2007 if (hdw->vid_stream) {
2008 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2009 hdw->vid_stream = NULL;
d855497e
MI		 2010 }
2011 if (hdw->audio_stat) {
2012 hdw->audio_stat->detach(hdw->audio_stat->ctxt);
2013 }
2014 if (hdw->decoder_ctrl) {
2015 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2016 }
2017 pvr2_i2c_core_done(hdw);
2018 pvr2_hdw_remove_usb_stuff(hdw);
2019 down(&pvr2_unit_sem); do {
2020 if ((hdw->unit_number >= 0) &&
2021 (hdw->unit_number < PVR_NUM) &&
2022 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2023 unit_pointers[hdw->unit_number] = NULL;
d855497e
MI		 2024 }
2025 } while (0); up(&pvr2_unit_sem);
22071a42
MK		 2026 kfree(hdw->controls);
2027 kfree(hdw->mpeg_ctrl_info);
2028 kfree(hdw->std_defs);
2029 kfree(hdw->std_enum_names);
d855497e
MI		 2030 kfree(hdw);
2031}
2032
2033
2034int pvr2_hdw_init_ok(struct pvr2_hdw *hdw)
2035{
2036 return hdw->flag_init_ok;
2037}
2038
2039
2040int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2041{
2042 return (hdw && hdw->flag_ok);
2043}
2044
2045
2046/* Called when hardware has been unplugged */
2047void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2048{
2049 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2050 LOCK_TAKE(hdw->big_lock);
2051 LOCK_TAKE(hdw->ctl_lock);
2052 pvr2_hdw_remove_usb_stuff(hdw);
2053 LOCK_GIVE(hdw->ctl_lock);
2054 LOCK_GIVE(hdw->big_lock);
2055}
2056
2057
2058// Attempt to autoselect an appropriate value for std_enum_cur given
2059// whatever is currently in std_mask_cur
07e337ee 2060static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2061{
2062 unsigned int idx;
2063 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2064 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2065 hdw->std_enum_cur = idx;
2066 return;
2067 }
2068 }
2069 hdw->std_enum_cur = 0;
2070}
2071
2072
2073// Calculate correct set of enumerated standards based on currently known
2074// set of available standards bits.
07e337ee 2075static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2076{
2077 struct v4l2_standard *newstd;
2078 unsigned int std_cnt;
2079 unsigned int idx;
2080
2081 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2082
2083 if (hdw->std_defs) {
2084 kfree(hdw->std_defs);
a0fd1cb1 2085 hdw->std_defs = NULL;
d855497e
MI		 2086 }
2087 hdw->std_enum_cnt = 0;
2088 if (hdw->std_enum_names) {
2089 kfree(hdw->std_enum_names);
a0fd1cb1 2090 hdw->std_enum_names = NULL;
d855497e
MI		 2091 }
2092
2093 if (!std_cnt) {
2094 pvr2_trace(
2095 PVR2_TRACE_ERROR_LEGS,
2096 "WARNING: Failed to identify any viable standards");
2097 }
2098 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2099 hdw->std_enum_names[0] = "none";
2100 for (idx = 0; idx < std_cnt; idx++) {
2101 hdw->std_enum_names[idx+1] =
2102 newstd[idx].name;
2103 }
2104 // Set up the dynamic control for this standard
2105 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2106 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2107 hdw->std_defs = newstd;
2108 hdw->std_enum_cnt = std_cnt+1;
2109 hdw->std_enum_cur = 0;
2110 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2111}
2112
2113
2114int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2115 struct v4l2_standard *std,
2116 unsigned int idx)
2117{
2118 int ret = -EINVAL;
2119 if (!idx) return ret;
2120 LOCK_TAKE(hdw->big_lock); do {
2121 if (idx >= hdw->std_enum_cnt) break;
2122 idx--;
2123 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2124 ret = 0;
2125 } while (0); LOCK_GIVE(hdw->big_lock);
2126 return ret;
2127}
2128
2129
2130/* Get the number of defined controls */
2131unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2132{
c05c0462 2133 return hdw->control_cnt;
d855497e
MI		 2134}
2135
2136
2137/* Retrieve a control handle given its index (0..count-1) */
2138struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2139 unsigned int idx)
2140{
a0fd1cb1 2141 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2142 return hdw->controls + idx;
2143}
2144
2145
2146/* Retrieve a control handle given its index (0..count-1) */
2147struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2148 unsigned int ctl_id)
2149{
2150 struct pvr2_ctrl *cptr;
2151 unsigned int idx;
2152 int i;
2153
2154 /* This could be made a lot more efficient, but for now... */
c05c0462 2155 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2156 cptr = hdw->controls + idx;
2157 i = cptr->info->internal_id;
2158 if (i && (i == ctl_id)) return cptr;
2159 }
a0fd1cb1 2160 return NULL;
d855497e
MI		 2161}
2162
2163
a761f431 2164/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2165struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2166{
2167 struct pvr2_ctrl *cptr;
2168 unsigned int idx;
2169 int i;
2170
2171 /* This could be made a lot more efficient, but for now... */
c05c0462 2172 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2173 cptr = hdw->controls + idx;
2174 i = cptr->info->v4l_id;
2175 if (i && (i == ctl_id)) return cptr;
2176 }
a0fd1cb1 2177 return NULL;
d855497e
MI		 2178}
2179
2180
a761f431
MI		 2181/* Given a V4L ID for its immediate predecessor, retrieve the control
2182 structure associated with it. */
2183struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2184 unsigned int ctl_id)
2185{
2186 struct pvr2_ctrl *cptr,*cp2;
2187 unsigned int idx;
2188 int i;
2189
2190 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2191 cp2 = NULL;
a761f431
MI		 2192 for (idx = 0; idx < hdw->control_cnt; idx++) {
2193 cptr = hdw->controls + idx;
2194 i = cptr->info->v4l_id;
2195 if (!i) continue;
2196 if (i <= ctl_id) continue;
2197 if (cp2 && (cp2->info->v4l_id < i)) continue;
2198 cp2 = cptr;
2199 }
2200 return cp2;
a0fd1cb1 2201 return NULL;
a761f431
MI		 2202}
2203
2204
d855497e
MI		 2205static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2206{
2207 switch (tp) {
2208 case pvr2_ctl_int: return "integer";
2209 case pvr2_ctl_enum: return "enum";
33213963 2210 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2211 case pvr2_ctl_bitmask: return "bitmask";
2212 }
2213 return "";
2214}
2215
2216
2217/* Commit all control changes made up to this point. Subsystems can be
2218 indirectly affected by these changes. For a given set of things being
2219 committed, we'll clear the affected subsystem bits and then once we're
2220 done committing everything we'll make a request to restore the subsystem
2221 state(s) back to their previous value before this function was called.
2222 Thus we can automatically reconfigure affected pieces of the driver as
2223 controls are changed. */
07e337ee 2224static int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw)
d855497e
MI		 2225{
2226 unsigned long saved_subsys_mask = hdw->subsys_enabled_mask;
2227 unsigned long stale_subsys_mask = 0;
2228 unsigned int idx;
2229 struct pvr2_ctrl *cptr;
2230 int value;
2231 int commit_flag = 0;
2232 char buf[100];
2233 unsigned int bcnt,ccnt;
2234
c05c0462 2235 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2236 cptr = hdw->controls + idx;
2237 if (cptr->info->is_dirty == 0) continue;
2238 if (!cptr->info->is_dirty(cptr)) continue;
2239 if (!commit_flag) {
2240 commit_flag = !0;
2241 }
2242
2243 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2244 cptr->info->name);
2245 value = 0;
2246 cptr->info->get_value(cptr,&value);
2247 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2248 buf+bcnt,
2249 sizeof(buf)-bcnt,&ccnt);
2250 bcnt += ccnt;
2251 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2252 get_ctrl_typename(cptr->info->type));
2253 pvr2_trace(PVR2_TRACE_CTL,
2254 "/*--TRACE_COMMIT--*/ %.*s",
2255 bcnt,buf);
2256 }
2257
2258 if (!commit_flag) {
2259 /* Nothing has changed */
2260 return 0;
2261 }
2262
2263 /* When video standard changes, reset the hres and vres values -
2264 but if the user has pending changes there, then let the changes
2265 take priority. */
2266 if (hdw->std_dirty) {
2267 /* Rewrite the vertical resolution to be appropriate to the
2268 video standard that has been selected. */
2269 int nvres;
2270 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2271 nvres = 480;
2272 } else {
2273 nvres = 576;
2274 }
2275 if (nvres != hdw->res_ver_val) {
2276 hdw->res_ver_val = nvres;
2277 hdw->res_ver_dirty = !0;
2278 }
d855497e
MI		 2279 }
2280
2281 if (hdw->std_dirty ||
434449f4
MI		 2282 hdw->enc_stale ||
2283 hdw->srate_dirty ||
2284 hdw->res_ver_dirty ||
2285 hdw->res_hor_dirty ||
b46cfa80 2286 0) {
d855497e
MI		 2287 /* If any of this changes, then the encoder needs to be
2288 reconfigured, and we need to reset the stream. */
2289 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
d855497e
MI		 2290 }
2291
275b2e28
PK		 2292 if (hdw->input_dirty) {
2293 /* pk: If input changes to or from radio, then the encoder
2294 needs to be restarted (for ENC_MUTE_VIDEO to work) */
2295 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_RUN);
2296 }
2297
2298
b30d2441
MI		 2299 if (hdw->srate_dirty) {
2300 /* Write new sample rate into control structure since
2301 * the master copy is stale. We must track srate
2302 * separate from the mpeg control structure because
2303 * other logic also uses this value. */
2304 struct v4l2_ext_controls cs;
2305 struct v4l2_ext_control c1;
2306 memset(&cs,0,sizeof(cs));
2307 memset(&c1,0,sizeof(c1));
2308 cs.controls = &c1;
2309 cs.count = 1;
2310 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2311 c1.value = hdw->srate_val;
2312 cx2341x_ext_ctrls(&hdw->enc_ctl_state,&cs,VIDIOC_S_EXT_CTRLS);
2313 }
c05c0462 2314
d855497e
MI		 2315 /* Scan i2c core at this point - before we clear all the dirty
2316 bits. Various parts of the i2c core will notice dirty bits as
2317 appropriate and arrange to broadcast or directly send updates to
2318 the client drivers in order to keep everything in sync */
2319 pvr2_i2c_core_check_stale(hdw);
2320
c05c0462 2321 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2322 cptr = hdw->controls + idx;
2323 if (!cptr->info->clear_dirty) continue;
2324 cptr->info->clear_dirty(cptr);
2325 }
2326
2327 /* Now execute i2c core update */
2328 pvr2_i2c_core_sync(hdw);
2329
2330 pvr2_hdw_subsys_bit_chg_no_lock(hdw,stale_subsys_mask,0);
2331 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,saved_subsys_mask);
2332
2333 return 0;
2334}
2335
2336
2337int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2338{
2339 LOCK_TAKE(hdw->big_lock); do {
2340 pvr2_hdw_commit_ctl_internal(hdw);
2341 } while (0); LOCK_GIVE(hdw->big_lock);
2342 return 0;
2343}
2344
2345
2346void pvr2_hdw_poll(struct pvr2_hdw *hdw)
2347{
2348 LOCK_TAKE(hdw->big_lock); do {
2349 pvr2_i2c_core_sync(hdw);
2350 } while (0); LOCK_GIVE(hdw->big_lock);
2351}
2352
2353
2354void pvr2_hdw_setup_poll_trigger(struct pvr2_hdw *hdw,
2355 void (*func)(void *),
2356 void *data)
2357{
2358 LOCK_TAKE(hdw->big_lock); do {
2359 hdw->poll_trigger_func = func;
2360 hdw->poll_trigger_data = data;
2361 } while (0); LOCK_GIVE(hdw->big_lock);
2362}
2363
2364
2365void pvr2_hdw_poll_trigger_unlocked(struct pvr2_hdw *hdw)
2366{
2367 if (hdw->poll_trigger_func) {
2368 hdw->poll_trigger_func(hdw->poll_trigger_data);
2369 }
2370}
2371
d855497e
MI		 2372/* Return name for this driver instance */
2373const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2374{
2375 return hdw->name;
2376}
2377
2378
2379/* Return bit mask indicating signal status */
07e337ee 2380static unsigned int pvr2_hdw_get_signal_status_internal(struct pvr2_hdw *hdw)
d855497e
MI		 2381{
2382 unsigned int msk = 0;
2383 switch (hdw->input_val) {
2384 case PVR2_CVAL_INPUT_TV:
2385 case PVR2_CVAL_INPUT_RADIO:
2386 if (hdw->decoder_ctrl &&
2387 hdw->decoder_ctrl->tuned(hdw->decoder_ctrl->ctxt)) {
2388 msk |= PVR2_SIGNAL_OK;
2389 if (hdw->audio_stat &&
2390 hdw->audio_stat->status(hdw->audio_stat->ctxt)) {
2391 if (hdw->flag_stereo) {
2392 msk |= PVR2_SIGNAL_STEREO;
2393 }
2394 if (hdw->flag_bilingual) {
2395 msk |= PVR2_SIGNAL_SAP;
2396 }
2397 }
2398 }
2399 break;
2400 default:
2401 msk |= PVR2_SIGNAL_OK | PVR2_SIGNAL_STEREO;
2402 }
2403 return msk;
2404}
2405
2406
2407int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2408{
2409 int result;
2410 LOCK_TAKE(hdw->ctl_lock); do {
2411 hdw->cmd_buffer[0] = 0x0b;
2412 result = pvr2_send_request(hdw,
2413 hdw->cmd_buffer,1,
2414 hdw->cmd_buffer,1);
2415 if (result < 0) break;
2416 result = (hdw->cmd_buffer[0] != 0);
2417 } while(0); LOCK_GIVE(hdw->ctl_lock);
2418 return result;
2419}
2420
2421
2422/* Return bit mask indicating signal status */
2423unsigned int pvr2_hdw_get_signal_status(struct pvr2_hdw *hdw)
2424{
2425 unsigned int msk = 0;
2426 LOCK_TAKE(hdw->big_lock); do {
2427 msk = pvr2_hdw_get_signal_status_internal(hdw);
2428 } while (0); LOCK_GIVE(hdw->big_lock);
2429 return msk;
2430}
2431
2432
2433/* Get handle to video output stream */
2434struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2435{
2436 return hp->vid_stream;
2437}
2438
2439
2440void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2441{
4f1a3e5b 2442 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e
MI		 2443 LOCK_TAKE(hdw->big_lock); do {
2444 hdw->log_requested = !0;
4f1a3e5b 2445 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
d855497e
MI		 2446 pvr2_i2c_core_check_stale(hdw);
2447 hdw->log_requested = 0;
2448 pvr2_i2c_core_sync(hdw);
b30d2441 2449 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 2450 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
4f1a3e5b 2451 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 2452 } while (0); LOCK_GIVE(hdw->big_lock);
2453}
2454
2455void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw, int enable_flag)
2456{
2457 int ret;
2458 u16 address;
2459 unsigned int pipe;
2460 LOCK_TAKE(hdw->big_lock); do {
2461 if ((hdw->fw_buffer == 0) == !enable_flag) break;
2462
2463 if (!enable_flag) {
2464 pvr2_trace(PVR2_TRACE_FIRMWARE,
2465 "Cleaning up after CPU firmware fetch");
2466 kfree(hdw->fw_buffer);
a0fd1cb1 2467 hdw->fw_buffer = NULL;
d855497e
MI		 2468 hdw->fw_size = 0;
2469 /* Now release the CPU. It will disconnect and
2470 reconnect later. */
2471 pvr2_hdw_cpureset_assert(hdw,0);
2472 break;
2473 }
2474
2475 pvr2_trace(PVR2_TRACE_FIRMWARE,
2476 "Preparing to suck out CPU firmware");
2477 hdw->fw_size = 0x2000;
2478 hdw->fw_buffer = kmalloc(hdw->fw_size,GFP_KERNEL);
2479 if (!hdw->fw_buffer) {
2480 hdw->fw_size = 0;
2481 break;
2482 }
2483
2484 memset(hdw->fw_buffer,0,hdw->fw_size);
2485
2486 /* We have to hold the CPU during firmware upload. */
2487 pvr2_hdw_cpureset_assert(hdw,1);
2488
2489 /* download the firmware from address 0000-1fff in 2048
2490 (=0x800) bytes chunk. */
2491
2492 pvr2_trace(PVR2_TRACE_FIRMWARE,"Grabbing CPU firmware");
2493 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2494 for(address = 0; address < hdw->fw_size; address += 0x800) {
2495 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0xc0,
2496 address,0,
2497 hdw->fw_buffer+address,0x800,HZ);
2498 if (ret < 0) break;
2499 }
2500
2501 pvr2_trace(PVR2_TRACE_FIRMWARE,"Done grabbing CPU firmware");
2502
2503 } while (0); LOCK_GIVE(hdw->big_lock);
2504}
2505
2506
2507/* Return true if we're in a mode for retrieval CPU firmware */
2508int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2509{
2510 return hdw->fw_buffer != 0;
2511}
2512
2513
2514int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2515 char *buf,unsigned int cnt)
2516{
2517 int ret = -EINVAL;
2518 LOCK_TAKE(hdw->big_lock); do {
2519 if (!buf) break;
2520 if (!cnt) break;
2521
2522 if (!hdw->fw_buffer) {
2523 ret = -EIO;
2524 break;
2525 }
2526
2527 if (offs >= hdw->fw_size) {
2528 pvr2_trace(PVR2_TRACE_FIRMWARE,
2529 "Read firmware data offs=%d EOF",
2530 offs);
2531 ret = 0;
2532 break;
2533 }
2534
2535 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2536
2537 memcpy(buf,hdw->fw_buffer+offs,cnt);
2538
2539 pvr2_trace(PVR2_TRACE_FIRMWARE,
2540 "Read firmware data offs=%d cnt=%d",
2541 offs,cnt);
2542 ret = cnt;
2543 } while (0); LOCK_GIVE(hdw->big_lock);
2544
2545 return ret;
2546}
2547
2548
2549int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw)
2550{
2551 return hdw->v4l_minor_number;
2552}
2553
2554
2555/* Store the v4l minor device number */
2556void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,int v)
2557{
2558 hdw->v4l_minor_number = v;
2559}
2560
2561
7d12e780 2562static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 2563{
2564 struct pvr2_hdw *hdw = urb->context;
2565 hdw->ctl_write_pend_flag = 0;
2566 if (hdw->ctl_read_pend_flag) return;
2567 complete(&hdw->ctl_done);
2568}
2569
2570
7d12e780 2571static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 2572{
2573 struct pvr2_hdw *hdw = urb->context;
2574 hdw->ctl_read_pend_flag = 0;
2575 if (hdw->ctl_write_pend_flag) return;
2576 complete(&hdw->ctl_done);
2577}
2578
2579
2580static void pvr2_ctl_timeout(unsigned long data)
2581{
2582 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2583 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2584 hdw->ctl_timeout_flag = !0;
5e55d2ce 2585 if (hdw->ctl_write_pend_flag)
d855497e 2586 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 2587 if (hdw->ctl_read_pend_flag)
d855497e 2588 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 2589 }
2590}
2591
2592
e61b6fc5
MI		 2593/* Issue a command and get a response from the device. This extended
2594 version includes a probe flag (which if set means that device errors
2595 should not be logged or treated as fatal) and a timeout in jiffies.
2596 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 2597static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2598 unsigned int timeout,int probe_fl,
2599 void *write_data,unsigned int write_len,
2600 void *read_data,unsigned int read_len)
d855497e
MI		 2601{
2602 unsigned int idx;
2603 int status = 0;
2604 struct timer_list timer;
2605 if (!hdw->ctl_lock_held) {
2606 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2607 "Attempted to execute control transfer"
2608 " without lock!!");
2609 return -EDEADLK;
2610 }
2611 if ((!hdw->flag_ok) && !probe_fl) {
2612 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2613 "Attempted to execute control transfer"
2614 " when device not ok");
2615 return -EIO;
2616 }
2617 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2618 if (!probe_fl) {
2619 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2620 "Attempted to execute control transfer"
2621 " when USB is disconnected");
2622 }
2623 return -ENOTTY;
2624 }
2625
2626 /* Ensure that we have sane parameters */
2627 if (!write_data) write_len = 0;
2628 if (!read_data) read_len = 0;
2629 if (write_len > PVR2_CTL_BUFFSIZE) {
2630 pvr2_trace(
2631 PVR2_TRACE_ERROR_LEGS,
2632 "Attempted to execute %d byte"
2633 " control-write transfer (limit=%d)",
2634 write_len,PVR2_CTL_BUFFSIZE);
2635 return -EINVAL;
2636 }
2637 if (read_len > PVR2_CTL_BUFFSIZE) {
2638 pvr2_trace(
2639 PVR2_TRACE_ERROR_LEGS,
2640 "Attempted to execute %d byte"
2641 " control-read transfer (limit=%d)",
2642 write_len,PVR2_CTL_BUFFSIZE);
2643 return -EINVAL;
2644 }
2645 if ((!write_len) && (!read_len)) {
2646 pvr2_trace(
2647 PVR2_TRACE_ERROR_LEGS,
2648 "Attempted to execute null control transfer?");
2649 return -EINVAL;
2650 }
2651
2652
2653 hdw->cmd_debug_state = 1;
2654 if (write_len) {
2655 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2656 } else {
2657 hdw->cmd_debug_code = 0;
2658 }
2659 hdw->cmd_debug_write_len = write_len;
2660 hdw->cmd_debug_read_len = read_len;
2661
2662 /* Initialize common stuff */
2663 init_completion(&hdw->ctl_done);
2664 hdw->ctl_timeout_flag = 0;
2665 hdw->ctl_write_pend_flag = 0;
2666 hdw->ctl_read_pend_flag = 0;
2667 init_timer(&timer);
2668 timer.expires = jiffies + timeout;
2669 timer.data = (unsigned long)hdw;
2670 timer.function = pvr2_ctl_timeout;
2671
2672 if (write_len) {
2673 hdw->cmd_debug_state = 2;
2674 /* Transfer write data to internal buffer */
2675 for (idx = 0; idx < write_len; idx++) {
2676 hdw->ctl_write_buffer[idx] =
2677 ((unsigned char *)write_data)[idx];
2678 }
2679 /* Initiate a write request */
2680 usb_fill_bulk_urb(hdw->ctl_write_urb,
2681 hdw->usb_dev,
2682 usb_sndbulkpipe(hdw->usb_dev,
2683 PVR2_CTL_WRITE_ENDPOINT),
2684 hdw->ctl_write_buffer,
2685 write_len,
2686 pvr2_ctl_write_complete,
2687 hdw);
2688 hdw->ctl_write_urb->actual_length = 0;
2689 hdw->ctl_write_pend_flag = !0;
2690 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2691 if (status < 0) {
2692 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2693 "Failed to submit write-control"
2694 " URB status=%d",status);
2695 hdw->ctl_write_pend_flag = 0;
2696 goto done;
2697 }
2698 }
2699
2700 if (read_len) {
2701 hdw->cmd_debug_state = 3;
2702 memset(hdw->ctl_read_buffer,0x43,read_len);
2703 /* Initiate a read request */
2704 usb_fill_bulk_urb(hdw->ctl_read_urb,
2705 hdw->usb_dev,
2706 usb_rcvbulkpipe(hdw->usb_dev,
2707 PVR2_CTL_READ_ENDPOINT),
2708 hdw->ctl_read_buffer,
2709 read_len,
2710 pvr2_ctl_read_complete,
2711 hdw);
2712 hdw->ctl_read_urb->actual_length = 0;
2713 hdw->ctl_read_pend_flag = !0;
2714 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2715 if (status < 0) {
2716 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2717 "Failed to submit read-control"
2718 " URB status=%d",status);
2719 hdw->ctl_read_pend_flag = 0;
2720 goto done;
2721 }
2722 }
2723
2724 /* Start timer */
2725 add_timer(&timer);
2726
2727 /* Now wait for all I/O to complete */
2728 hdw->cmd_debug_state = 4;
2729 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2730 wait_for_completion(&hdw->ctl_done);
2731 }
2732 hdw->cmd_debug_state = 5;
2733
2734 /* Stop timer */
2735 del_timer_sync(&timer);
2736
2737 hdw->cmd_debug_state = 6;
2738 status = 0;
2739
2740 if (hdw->ctl_timeout_flag) {
2741 status = -ETIMEDOUT;
2742 if (!probe_fl) {
2743 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2744 "Timed out control-write");
2745 }
2746 goto done;
2747 }
2748
2749 if (write_len) {
2750 /* Validate results of write request */
2751 if ((hdw->ctl_write_urb->status != 0) &&
2752 (hdw->ctl_write_urb->status != -ENOENT) &&
2753 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2754 (hdw->ctl_write_urb->status != -ECONNRESET)) {
2755 /* USB subsystem is reporting some kind of failure
2756 on the write */
2757 status = hdw->ctl_write_urb->status;
2758 if (!probe_fl) {
2759 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2760 "control-write URB failure,"
2761 " status=%d",
2762 status);
2763 }
2764 goto done;
2765 }
2766 if (hdw->ctl_write_urb->actual_length < write_len) {
2767 /* Failed to write enough data */
2768 status = -EIO;
2769 if (!probe_fl) {
2770 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2771 "control-write URB short,"
2772 " expected=%d got=%d",
2773 write_len,
2774 hdw->ctl_write_urb->actual_length);
2775 }
2776 goto done;
2777 }
2778 }
2779 if (read_len) {
2780 /* Validate results of read request */
2781 if ((hdw->ctl_read_urb->status != 0) &&
2782 (hdw->ctl_read_urb->status != -ENOENT) &&
2783 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
2784 (hdw->ctl_read_urb->status != -ECONNRESET)) {
2785 /* USB subsystem is reporting some kind of failure
2786 on the read */
2787 status = hdw->ctl_read_urb->status;
2788 if (!probe_fl) {
2789 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2790 "control-read URB failure,"
2791 " status=%d",
2792 status);
2793 }
2794 goto done;
2795 }
2796 if (hdw->ctl_read_urb->actual_length < read_len) {
2797 /* Failed to read enough data */
2798 status = -EIO;
2799 if (!probe_fl) {
2800 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2801 "control-read URB short,"
2802 " expected=%d got=%d",
2803 read_len,
2804 hdw->ctl_read_urb->actual_length);
2805 }
2806 goto done;
2807 }
2808 /* Transfer retrieved data out from internal buffer */
2809 for (idx = 0; idx < read_len; idx++) {
2810 ((unsigned char *)read_data)[idx] =
2811 hdw->ctl_read_buffer[idx];
2812 }
2813 }
2814
2815 done:
2816
2817 hdw->cmd_debug_state = 0;
2818 if ((status < 0) && (!probe_fl)) {
2819 pvr2_hdw_render_useless_unlocked(hdw);
2820 }
2821 return status;
2822}
2823
2824
2825int pvr2_send_request(struct pvr2_hdw *hdw,
2826 void *write_data,unsigned int write_len,
2827 void *read_data,unsigned int read_len)
2828{
2829 return pvr2_send_request_ex(hdw,HZ*4,0,
2830 write_data,write_len,
2831 read_data,read_len);
2832}
2833
2834int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
2835{
2836 int ret;
2837
2838 LOCK_TAKE(hdw->ctl_lock);
2839
2840 hdw->cmd_buffer[0] = 0x04; /* write register prefix */
2841 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
2842 hdw->cmd_buffer[5] = 0;
2843 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2844 hdw->cmd_buffer[7] = reg & 0xff;
2845
2846
2847 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
2848
2849 LOCK_GIVE(hdw->ctl_lock);
2850
2851 return ret;
2852}
2853
2854
07e337ee 2855static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 2856{
2857 int ret = 0;
2858
2859 LOCK_TAKE(hdw->ctl_lock);
2860
2861 hdw->cmd_buffer[0] = 0x05; /* read register prefix */
2862 hdw->cmd_buffer[1] = 0;
2863 hdw->cmd_buffer[2] = 0;
2864 hdw->cmd_buffer[3] = 0;
2865 hdw->cmd_buffer[4] = 0;
2866 hdw->cmd_buffer[5] = 0;
2867 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2868 hdw->cmd_buffer[7] = reg & 0xff;
2869
2870 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
2871 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
2872
2873 LOCK_GIVE(hdw->ctl_lock);
2874
2875 return ret;
2876}
2877
2878
07e337ee 2879static int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res)
d855497e
MI		 2880{
2881 int ret;
2882
2883 LOCK_TAKE(hdw->ctl_lock);
2884
2885 hdw->cmd_buffer[0] = (data >> 8) & 0xff;
2886 hdw->cmd_buffer[1] = data & 0xff;
2887
2888 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 2, hdw->cmd_buffer, res);
2889
2890 LOCK_GIVE(hdw->ctl_lock);
2891
2892 return ret;
2893}
2894
2895
07e337ee 2896static int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res)
d855497e
MI		 2897{
2898 int ret;
2899
2900 LOCK_TAKE(hdw->ctl_lock);
2901
2902 hdw->cmd_buffer[0] = data;
2903
2904 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 1, hdw->cmd_buffer, res);
2905
2906 LOCK_GIVE(hdw->ctl_lock);
2907
2908 return ret;
2909}
2910
2911
07e337ee 2912static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw)
d855497e
MI		 2913{
2914 if (!hdw->flag_ok) return;
2915 pvr2_trace(PVR2_TRACE_INIT,"render_useless");
2916 hdw->flag_ok = 0;
2917 if (hdw->vid_stream) {
a0fd1cb1 2918 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e
MI		 2919 }
2920 hdw->flag_streaming_enabled = 0;
2921 hdw->subsys_enabled_mask = 0;
2922}
2923
2924
2925void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
2926{
2927 LOCK_TAKE(hdw->ctl_lock);
2928 pvr2_hdw_render_useless_unlocked(hdw);
2929 LOCK_GIVE(hdw->ctl_lock);
2930}
2931
2932
2933void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
2934{
2935 int ret;
2936 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 2937 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
d855497e
MI		 2938 if (ret == 1) {
2939 ret = usb_reset_device(hdw->usb_dev);
2940 usb_unlock_device(hdw->usb_dev);
2941 } else {
2942 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2943 "Failed to lock USB device ret=%d",ret);
2944 }
2945 if (init_pause_msec) {
2946 pvr2_trace(PVR2_TRACE_INFO,
2947 "Waiting %u msec for hardware to settle",
2948 init_pause_msec);
2949 msleep(init_pause_msec);
2950 }
2951
2952}
2953
2954
2955void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
2956{
2957 char da[1];
2958 unsigned int pipe;
2959 int ret;
2960
2961 if (!hdw->usb_dev) return;
2962
2963 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
2964
2965 da[0] = val ? 0x01 : 0x00;
2966
2967 /* Write the CPUCS register on the 8051. The lsb of the register
2968 is the reset bit; a 1 asserts reset while a 0 clears it. */
2969 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
2970 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
2971 if (ret < 0) {
2972 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2973 "cpureset_assert(%d) error=%d",val,ret);
2974 pvr2_hdw_render_useless(hdw);
2975 }
2976}
2977
2978
2979int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
2980{
2981 int status;
2982 LOCK_TAKE(hdw->ctl_lock); do {
2983 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
2984 hdw->flag_ok = !0;
2985 hdw->cmd_buffer[0] = 0xdd;
a0fd1cb1 2986 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
d855497e
MI		 2987 } while (0); LOCK_GIVE(hdw->ctl_lock);
2988 return status;
2989}
2990
2991
2992int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
2993{
2994 int status;
2995 LOCK_TAKE(hdw->ctl_lock); do {
2996 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
2997 hdw->cmd_buffer[0] = 0xde;
a0fd1cb1 2998 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
d855497e
MI		 2999 } while (0); LOCK_GIVE(hdw->ctl_lock);
3000 return status;
3001}
3002
3003
3004int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3005{
3006 if (!hdw->decoder_ctrl) {
3007 pvr2_trace(PVR2_TRACE_INIT,
3008 "Unable to reset decoder: nothing attached");
3009 return -ENOTTY;
3010 }
3011
3012 if (!hdw->decoder_ctrl->force_reset) {
3013 pvr2_trace(PVR2_TRACE_INIT,
3014 "Unable to reset decoder: not implemented");
3015 return -ENOTTY;
3016 }
3017
3018 pvr2_trace(PVR2_TRACE_INIT,
3019 "Requesting decoder reset");
3020 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3021 return 0;
3022}
3023
3024
e61b6fc5 3025/* Stop / start video stream transport */
07e337ee 3026static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e
MI		 3027{
3028 int status;
3029 LOCK_TAKE(hdw->ctl_lock); do {
3030 hdw->cmd_buffer[0] = (runFl ? 0x36 : 0x37);
a0fd1cb1 3031 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
d855497e
MI		 3032 } while (0); LOCK_GIVE(hdw->ctl_lock);
3033 if (!status) {
3034 hdw->subsys_enabled_mask =
3035 ((hdw->subsys_enabled_mask &
3036 ~(1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) |
3037 (runFl ? (1<<PVR2_SUBSYS_B_USBSTREAM_RUN) : 0));
3038 }
3039 return status;
3040}
3041
3042
3043void pvr2_hdw_get_debug_info(const struct pvr2_hdw *hdw,
3044 struct pvr2_hdw_debug_info *ptr)
3045{
3046 ptr->big_lock_held = hdw->big_lock_held;
3047 ptr->ctl_lock_held = hdw->ctl_lock_held;
3048 ptr->flag_ok = hdw->flag_ok;
3049 ptr->flag_disconnected = hdw->flag_disconnected;
3050 ptr->flag_init_ok = hdw->flag_init_ok;
3051 ptr->flag_streaming_enabled = hdw->flag_streaming_enabled;
3052 ptr->subsys_flags = hdw->subsys_enabled_mask;
3053 ptr->cmd_debug_state = hdw->cmd_debug_state;
3054 ptr->cmd_code = hdw->cmd_debug_code;
3055 ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
3056 ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
3057 ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
3058 ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
3059 ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
3060 ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
3061 ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
3062}
3063
3064
3065int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
3066{
3067 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
3068}
3069
3070
3071int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
3072{
3073 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
3074}
3075
3076
3077int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
3078{
3079 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
3080}
3081
3082
3083int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
3084{
3085 u32 cval,nval;
3086 int ret;
3087 if (~msk) {
3088 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
3089 if (ret) return ret;
3090 nval = (cval & ~msk) | (val & msk);
3091 pvr2_trace(PVR2_TRACE_GPIO,
3092 "GPIO direction changing 0x%x:0x%x"
3093 " from 0x%x to 0x%x",
3094 msk,val,cval,nval);
3095 } else {
3096 nval = val;
3097 pvr2_trace(PVR2_TRACE_GPIO,
3098 "GPIO direction changing to 0x%x",nval);
3099 }
3100 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
3101}
3102
3103
3104int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
3105{
3106 u32 cval,nval;
3107 int ret;
3108 if (~msk) {
3109 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
3110 if (ret) return ret;
3111 nval = (cval & ~msk) | (val & msk);
3112 pvr2_trace(PVR2_TRACE_GPIO,
3113 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
3114 msk,val,cval,nval);
3115 } else {
3116 nval = val;
3117 pvr2_trace(PVR2_TRACE_GPIO,
3118 "GPIO output changing to 0x%x",nval);
3119 }
3120 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
3121}
3122
3123
e61b6fc5 3124/* Find I2C address of eeprom */
07e337ee 3125static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 3126{
3127 int result;
3128 LOCK_TAKE(hdw->ctl_lock); do {
3129 hdw->cmd_buffer[0] = 0xeb;
3130 result = pvr2_send_request(hdw,
3131 hdw->cmd_buffer,1,
3132 hdw->cmd_buffer,1);
3133 if (result < 0) break;
3134 result = hdw->cmd_buffer[0];
3135 } while(0); LOCK_GIVE(hdw->ctl_lock);
3136 return result;
3137}
3138
3139
32ffa9ae
MI		 3140int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
3141 u32 chip_id,unsigned long reg_id,
3142 int setFl,u32 *val_ptr)
3143{
3144#ifdef CONFIG_VIDEO_ADV_DEBUG
3145 struct list_head *item;
3146 struct pvr2_i2c_client *cp;
3147 struct v4l2_register req;
6d98816f
MI		 3148 int stat = 0;
3149 int okFl = 0;
32ffa9ae
MI		 3150
3151 req.i2c_id = chip_id;
3152 req.reg = reg_id;
3153 if (setFl) req.val = *val_ptr;
3154 mutex_lock(&hdw->i2c_list_lock); do {
3155 list_for_each(item,&hdw->i2c_clients) {
3156 cp = list_entry(item,struct pvr2_i2c_client,list);
3157 if (cp->client->driver->id != chip_id) continue;
3158 stat = pvr2_i2c_client_cmd(
3159 cp,(setFl ? VIDIOC_INT_S_REGISTER :
3160 VIDIOC_INT_G_REGISTER),&req);
3161 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 3162 okFl = !0;
3163 break;
32ffa9ae
MI		 3164 }
3165 } while (0); mutex_unlock(&hdw->i2c_list_lock);
6d98816f
MI		 3166 if (okFl) {
3167 return stat;
3168 }
32ffa9ae
MI		 3169 return -EINVAL;
3170#else
3171 return -ENOSYS;
3172#endif
3173}
3174
3175
d855497e
MI		 3176/*
3177 Stuff for Emacs to see, in order to encourage consistent editing style:
3178 *** Local Variables: ***
3179 *** mode: c ***
3180 *** fill-column: 75 ***
3181 *** tab-width: 8 ***
3182 *** c-basic-offset: 8 ***
3183 *** End: ***
3184 */
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