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d855497e MI |
1 | /* |
2 | * | |
3 | * $Id$ | |
4 | * | |
5 | * Copyright (C) 2005 Mike Isely <isely@pobox.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/errno.h> | |
23 | #include <linux/string.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/firmware.h> | |
d855497e | 26 | #include <linux/videodev2.h> |
32ffa9ae | 27 | #include <media/v4l2-common.h> |
d855497e MI |
28 | #include "pvrusb2.h" |
29 | #include "pvrusb2-std.h" | |
30 | #include "pvrusb2-util.h" | |
31 | #include "pvrusb2-hdw.h" | |
32 | #include "pvrusb2-i2c-core.h" | |
33 | #include "pvrusb2-tuner.h" | |
34 | #include "pvrusb2-eeprom.h" | |
35 | #include "pvrusb2-hdw-internal.h" | |
36 | #include "pvrusb2-encoder.h" | |
37 | #include "pvrusb2-debug.h" | |
8d364363 | 38 | #include "pvrusb2-fx2-cmd.h" |
d855497e | 39 | |
1bde0289 MI |
40 | #define TV_MIN_FREQ 55250000L |
41 | #define TV_MAX_FREQ 850000000L | |
25d8527a | 42 | |
a0fd1cb1 | 43 | static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL}; |
8df0c87c | 44 | static DEFINE_MUTEX(pvr2_unit_mtx); |
d855497e | 45 | |
ff699e6b | 46 | static int ctlchg; |
d855497e | 47 | static int initusbreset = 1; |
ff699e6b | 48 | static int procreload; |
d855497e MI |
49 | static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 }; |
50 | static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 }; | |
51 | static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 }; | |
ff699e6b | 52 | static int init_pause_msec; |
d855497e MI |
53 | |
54 | module_param(ctlchg, int, S_IRUGO|S_IWUSR); | |
55 | MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value"); | |
56 | module_param(init_pause_msec, int, S_IRUGO|S_IWUSR); | |
57 | MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay"); | |
58 | module_param(initusbreset, int, S_IRUGO|S_IWUSR); | |
59 | MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe"); | |
60 | module_param(procreload, int, S_IRUGO|S_IWUSR); | |
61 | MODULE_PARM_DESC(procreload, | |
62 | "Attempt init failure recovery with firmware reload"); | |
63 | module_param_array(tuner, int, NULL, 0444); | |
64 | MODULE_PARM_DESC(tuner,"specify installed tuner type"); | |
65 | module_param_array(video_std, int, NULL, 0444); | |
66 | MODULE_PARM_DESC(video_std,"specify initial video standard"); | |
67 | module_param_array(tolerance, int, NULL, 0444); | |
68 | MODULE_PARM_DESC(tolerance,"specify stream error tolerance"); | |
69 | ||
70 | #define PVR2_CTL_WRITE_ENDPOINT 0x01 | |
71 | #define PVR2_CTL_READ_ENDPOINT 0x81 | |
72 | ||
73 | #define PVR2_GPIO_IN 0x9008 | |
74 | #define PVR2_GPIO_OUT 0x900c | |
75 | #define PVR2_GPIO_DIR 0x9020 | |
76 | ||
77 | #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__) | |
78 | ||
79 | #define PVR2_FIRMWARE_ENDPOINT 0x02 | |
80 | ||
81 | /* size of a firmware chunk */ | |
82 | #define FIRMWARE_CHUNK_SIZE 0x2000 | |
83 | ||
b30d2441 MI |
84 | /* Define the list of additional controls we'll dynamically construct based |
85 | on query of the cx2341x module. */ | |
86 | struct pvr2_mpeg_ids { | |
87 | const char *strid; | |
88 | int id; | |
89 | }; | |
90 | static const struct pvr2_mpeg_ids mpeg_ids[] = { | |
91 | { | |
92 | .strid = "audio_layer", | |
93 | .id = V4L2_CID_MPEG_AUDIO_ENCODING, | |
94 | },{ | |
95 | .strid = "audio_bitrate", | |
96 | .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE, | |
97 | },{ | |
98 | /* Already using audio_mode elsewhere :-( */ | |
99 | .strid = "mpeg_audio_mode", | |
100 | .id = V4L2_CID_MPEG_AUDIO_MODE, | |
101 | },{ | |
102 | .strid = "mpeg_audio_mode_extension", | |
103 | .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION, | |
104 | },{ | |
105 | .strid = "audio_emphasis", | |
106 | .id = V4L2_CID_MPEG_AUDIO_EMPHASIS, | |
107 | },{ | |
108 | .strid = "audio_crc", | |
109 | .id = V4L2_CID_MPEG_AUDIO_CRC, | |
110 | },{ | |
111 | .strid = "video_aspect", | |
112 | .id = V4L2_CID_MPEG_VIDEO_ASPECT, | |
113 | },{ | |
114 | .strid = "video_b_frames", | |
115 | .id = V4L2_CID_MPEG_VIDEO_B_FRAMES, | |
116 | },{ | |
117 | .strid = "video_gop_size", | |
118 | .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE, | |
119 | },{ | |
120 | .strid = "video_gop_closure", | |
121 | .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE, | |
b30d2441 MI |
122 | },{ |
123 | .strid = "video_bitrate_mode", | |
124 | .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE, | |
125 | },{ | |
126 | .strid = "video_bitrate", | |
127 | .id = V4L2_CID_MPEG_VIDEO_BITRATE, | |
128 | },{ | |
129 | .strid = "video_bitrate_peak", | |
130 | .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK, | |
131 | },{ | |
132 | .strid = "video_temporal_decimation", | |
133 | .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION, | |
134 | },{ | |
135 | .strid = "stream_type", | |
136 | .id = V4L2_CID_MPEG_STREAM_TYPE, | |
137 | },{ | |
138 | .strid = "video_spatial_filter_mode", | |
139 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE, | |
140 | },{ | |
141 | .strid = "video_spatial_filter", | |
142 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER, | |
143 | },{ | |
144 | .strid = "video_luma_spatial_filter_type", | |
145 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE, | |
146 | },{ | |
147 | .strid = "video_chroma_spatial_filter_type", | |
148 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE, | |
149 | },{ | |
150 | .strid = "video_temporal_filter_mode", | |
151 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE, | |
152 | },{ | |
153 | .strid = "video_temporal_filter", | |
154 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER, | |
155 | },{ | |
156 | .strid = "video_median_filter_type", | |
157 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE, | |
158 | },{ | |
159 | .strid = "video_luma_median_filter_top", | |
160 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP, | |
161 | },{ | |
162 | .strid = "video_luma_median_filter_bottom", | |
163 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM, | |
164 | },{ | |
165 | .strid = "video_chroma_median_filter_top", | |
166 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP, | |
167 | },{ | |
168 | .strid = "video_chroma_median_filter_bottom", | |
169 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM, | |
170 | } | |
171 | }; | |
eca8ebfc | 172 | #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids) |
c05c0462 | 173 | |
434449f4 | 174 | |
d855497e | 175 | static const char *control_values_srate[] = { |
434449f4 MI |
176 | [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz", |
177 | [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz", | |
178 | [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz", | |
d855497e MI |
179 | }; |
180 | ||
181 | ||
d855497e | 182 | |
d855497e MI |
183 | static const char *control_values_input[] = { |
184 | [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/ | |
29bf5b1d | 185 | [PVR2_CVAL_INPUT_DTV] = "dtv", |
d855497e MI |
186 | [PVR2_CVAL_INPUT_RADIO] = "radio", |
187 | [PVR2_CVAL_INPUT_SVIDEO] = "s-video", | |
188 | [PVR2_CVAL_INPUT_COMPOSITE] = "composite", | |
189 | }; | |
190 | ||
191 | ||
192 | static const char *control_values_audiomode[] = { | |
193 | [V4L2_TUNER_MODE_MONO] = "Mono", | |
194 | [V4L2_TUNER_MODE_STEREO] = "Stereo", | |
195 | [V4L2_TUNER_MODE_LANG1] = "Lang1", | |
196 | [V4L2_TUNER_MODE_LANG2] = "Lang2", | |
197 | [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2", | |
198 | }; | |
199 | ||
200 | ||
201 | static const char *control_values_hsm[] = { | |
202 | [PVR2_CVAL_HSM_FAIL] = "Fail", | |
203 | [PVR2_CVAL_HSM_HIGH] = "High", | |
204 | [PVR2_CVAL_HSM_FULL] = "Full", | |
205 | }; | |
206 | ||
207 | ||
681c7399 MI |
208 | static const char *pvr2_state_names[] = { |
209 | [PVR2_STATE_NONE] = "none", | |
210 | [PVR2_STATE_DEAD] = "dead", | |
211 | [PVR2_STATE_COLD] = "cold", | |
212 | [PVR2_STATE_WARM] = "warm", | |
213 | [PVR2_STATE_ERROR] = "error", | |
214 | [PVR2_STATE_READY] = "ready", | |
215 | [PVR2_STATE_RUN] = "run", | |
d855497e MI |
216 | }; |
217 | ||
681c7399 MI |
218 | |
219 | static void pvr2_hdw_state_sched(struct pvr2_hdw *); | |
220 | static int pvr2_hdw_state_eval(struct pvr2_hdw *); | |
1bde0289 | 221 | static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long); |
681c7399 MI |
222 | static void pvr2_hdw_worker_i2c(struct work_struct *work); |
223 | static void pvr2_hdw_worker_poll(struct work_struct *work); | |
224 | static void pvr2_hdw_worker_init(struct work_struct *work); | |
225 | static int pvr2_hdw_wait(struct pvr2_hdw *,int state); | |
226 | static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *); | |
227 | static void pvr2_hdw_state_log_state(struct pvr2_hdw *); | |
07e337ee | 228 | static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl); |
681c7399 | 229 | static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw); |
07e337ee | 230 | static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw); |
07e337ee AB |
231 | static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw); |
232 | static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw); | |
681c7399 MI |
233 | static void pvr2_hdw_quiescent_timeout(unsigned long); |
234 | static void pvr2_hdw_encoder_wait_timeout(unsigned long); | |
07e337ee AB |
235 | static int pvr2_send_request_ex(struct pvr2_hdw *hdw, |
236 | unsigned int timeout,int probe_fl, | |
237 | void *write_data,unsigned int write_len, | |
238 | void *read_data,unsigned int read_len); | |
d855497e | 239 | |
681c7399 MI |
240 | |
241 | static void trace_stbit(const char *name,int val) | |
242 | { | |
243 | pvr2_trace(PVR2_TRACE_STBITS, | |
244 | "State bit %s <-- %s", | |
245 | name,(val ? "true" : "false")); | |
246 | } | |
247 | ||
d855497e MI |
248 | static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp) |
249 | { | |
250 | struct pvr2_hdw *hdw = cptr->hdw; | |
251 | if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) { | |
252 | *vp = hdw->freqTable[hdw->freqProgSlot-1]; | |
253 | } else { | |
254 | *vp = 0; | |
255 | } | |
256 | return 0; | |
257 | } | |
258 | ||
259 | static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v) | |
260 | { | |
261 | struct pvr2_hdw *hdw = cptr->hdw; | |
1bde0289 MI |
262 | unsigned int slotId = hdw->freqProgSlot; |
263 | if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) { | |
264 | hdw->freqTable[slotId-1] = v; | |
265 | /* Handle side effects correctly - if we're tuned to this | |
266 | slot, then forgot the slot id relation since the stored | |
267 | frequency has been changed. */ | |
268 | if (hdw->freqSelector) { | |
269 | if (hdw->freqSlotRadio == slotId) { | |
270 | hdw->freqSlotRadio = 0; | |
271 | } | |
272 | } else { | |
273 | if (hdw->freqSlotTelevision == slotId) { | |
274 | hdw->freqSlotTelevision = 0; | |
275 | } | |
276 | } | |
d855497e MI |
277 | } |
278 | return 0; | |
279 | } | |
280 | ||
281 | static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp) | |
282 | { | |
283 | *vp = cptr->hdw->freqProgSlot; | |
284 | return 0; | |
285 | } | |
286 | ||
287 | static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v) | |
288 | { | |
289 | struct pvr2_hdw *hdw = cptr->hdw; | |
290 | if ((v >= 0) && (v <= FREQTABLE_SIZE)) { | |
291 | hdw->freqProgSlot = v; | |
292 | } | |
293 | return 0; | |
294 | } | |
295 | ||
296 | static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp) | |
297 | { | |
1bde0289 MI |
298 | struct pvr2_hdw *hdw = cptr->hdw; |
299 | *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision; | |
d855497e MI |
300 | return 0; |
301 | } | |
302 | ||
1bde0289 | 303 | static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId) |
d855497e MI |
304 | { |
305 | unsigned freq = 0; | |
306 | struct pvr2_hdw *hdw = cptr->hdw; | |
1bde0289 MI |
307 | if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0; |
308 | if (slotId > 0) { | |
309 | freq = hdw->freqTable[slotId-1]; | |
310 | if (!freq) return 0; | |
311 | pvr2_hdw_set_cur_freq(hdw,freq); | |
d855497e | 312 | } |
1bde0289 MI |
313 | if (hdw->freqSelector) { |
314 | hdw->freqSlotRadio = slotId; | |
315 | } else { | |
316 | hdw->freqSlotTelevision = slotId; | |
d855497e MI |
317 | } |
318 | return 0; | |
319 | } | |
320 | ||
321 | static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp) | |
322 | { | |
1bde0289 | 323 | *vp = pvr2_hdw_get_cur_freq(cptr->hdw); |
d855497e MI |
324 | return 0; |
325 | } | |
326 | ||
327 | static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr) | |
328 | { | |
329 | return cptr->hdw->freqDirty != 0; | |
330 | } | |
331 | ||
332 | static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr) | |
333 | { | |
334 | cptr->hdw->freqDirty = 0; | |
335 | } | |
336 | ||
337 | static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v) | |
338 | { | |
1bde0289 | 339 | pvr2_hdw_set_cur_freq(cptr->hdw,v); |
d855497e MI |
340 | return 0; |
341 | } | |
342 | ||
3ad9fc37 MI |
343 | static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp) |
344 | { | |
345 | /* Actual maximum depends on the video standard in effect. */ | |
346 | if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) { | |
347 | *vp = 480; | |
348 | } else { | |
349 | *vp = 576; | |
350 | } | |
351 | return 0; | |
352 | } | |
353 | ||
354 | static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp) | |
355 | { | |
989eb154 MI |
356 | /* Actual minimum depends on device digitizer type. */ |
357 | if (cptr->hdw->hdw_desc->flag_has_cx25840) { | |
3ad9fc37 MI |
358 | *vp = 75; |
359 | } else { | |
360 | *vp = 17; | |
361 | } | |
362 | return 0; | |
363 | } | |
364 | ||
1bde0289 | 365 | static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp) |
5549f54f | 366 | { |
1bde0289 MI |
367 | *vp = cptr->hdw->input_val; |
368 | return 0; | |
369 | } | |
370 | ||
29bf5b1d MI |
371 | static int ctrl_check_input(struct pvr2_ctrl *cptr,int v) |
372 | { | |
7fb20fa3 | 373 | return ((1 << v) & cptr->hdw->input_avail_mask) != 0; |
29bf5b1d MI |
374 | } |
375 | ||
1bde0289 MI |
376 | static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v) |
377 | { | |
378 | struct pvr2_hdw *hdw = cptr->hdw; | |
379 | ||
380 | if (hdw->input_val != v) { | |
381 | hdw->input_val = v; | |
382 | hdw->input_dirty = !0; | |
383 | } | |
384 | ||
385 | /* Handle side effects - if we switch to a mode that needs the RF | |
386 | tuner, then select the right frequency choice as well and mark | |
387 | it dirty. */ | |
388 | if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { | |
389 | hdw->freqSelector = 0; | |
390 | hdw->freqDirty = !0; | |
29bf5b1d MI |
391 | } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) || |
392 | (hdw->input_val == PVR2_CVAL_INPUT_DTV)) { | |
1bde0289 MI |
393 | hdw->freqSelector = 1; |
394 | hdw->freqDirty = !0; | |
5549f54f | 395 | } |
1bde0289 MI |
396 | return 0; |
397 | } | |
398 | ||
399 | static int ctrl_isdirty_input(struct pvr2_ctrl *cptr) | |
400 | { | |
401 | return cptr->hdw->input_dirty != 0; | |
402 | } | |
403 | ||
404 | static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr) | |
405 | { | |
406 | cptr->hdw->input_dirty = 0; | |
407 | } | |
408 | ||
5549f54f | 409 | |
25d8527a PK |
410 | static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp) |
411 | { | |
644afdb9 MI |
412 | unsigned long fv; |
413 | struct pvr2_hdw *hdw = cptr->hdw; | |
414 | if (hdw->tuner_signal_stale) { | |
415 | pvr2_i2c_core_status_poll(hdw); | |
416 | } | |
417 | fv = hdw->tuner_signal_info.rangehigh; | |
418 | if (!fv) { | |
419 | /* Safety fallback */ | |
25d8527a | 420 | *vp = TV_MAX_FREQ; |
644afdb9 | 421 | return 0; |
25d8527a | 422 | } |
644afdb9 MI |
423 | if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) { |
424 | fv = (fv * 125) / 2; | |
425 | } else { | |
426 | fv = fv * 62500; | |
427 | } | |
428 | *vp = fv; | |
25d8527a PK |
429 | return 0; |
430 | } | |
431 | ||
432 | static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp) | |
433 | { | |
644afdb9 MI |
434 | unsigned long fv; |
435 | struct pvr2_hdw *hdw = cptr->hdw; | |
436 | if (hdw->tuner_signal_stale) { | |
437 | pvr2_i2c_core_status_poll(hdw); | |
438 | } | |
439 | fv = hdw->tuner_signal_info.rangelow; | |
440 | if (!fv) { | |
441 | /* Safety fallback */ | |
25d8527a | 442 | *vp = TV_MIN_FREQ; |
644afdb9 MI |
443 | return 0; |
444 | } | |
445 | if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) { | |
446 | fv = (fv * 125) / 2; | |
447 | } else { | |
448 | fv = fv * 62500; | |
25d8527a | 449 | } |
644afdb9 | 450 | *vp = fv; |
25d8527a PK |
451 | return 0; |
452 | } | |
453 | ||
b30d2441 MI |
454 | static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr) |
455 | { | |
456 | return cptr->hdw->enc_stale != 0; | |
457 | } | |
458 | ||
459 | static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr) | |
460 | { | |
461 | cptr->hdw->enc_stale = 0; | |
681c7399 | 462 | cptr->hdw->enc_unsafe_stale = 0; |
b30d2441 MI |
463 | } |
464 | ||
465 | static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp) | |
466 | { | |
467 | int ret; | |
468 | struct v4l2_ext_controls cs; | |
469 | struct v4l2_ext_control c1; | |
470 | memset(&cs,0,sizeof(cs)); | |
471 | memset(&c1,0,sizeof(c1)); | |
472 | cs.controls = &c1; | |
473 | cs.count = 1; | |
474 | c1.id = cptr->info->v4l_id; | |
01f1e44f | 475 | ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs, |
b30d2441 MI |
476 | VIDIOC_G_EXT_CTRLS); |
477 | if (ret) return ret; | |
478 | *vp = c1.value; | |
479 | return 0; | |
480 | } | |
481 | ||
482 | static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v) | |
483 | { | |
484 | int ret; | |
681c7399 | 485 | struct pvr2_hdw *hdw = cptr->hdw; |
b30d2441 MI |
486 | struct v4l2_ext_controls cs; |
487 | struct v4l2_ext_control c1; | |
488 | memset(&cs,0,sizeof(cs)); | |
489 | memset(&c1,0,sizeof(c1)); | |
490 | cs.controls = &c1; | |
491 | cs.count = 1; | |
492 | c1.id = cptr->info->v4l_id; | |
493 | c1.value = v; | |
681c7399 MI |
494 | ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state, |
495 | hdw->state_encoder_run, &cs, | |
b30d2441 | 496 | VIDIOC_S_EXT_CTRLS); |
681c7399 MI |
497 | if (ret == -EBUSY) { |
498 | /* Oops. cx2341x is telling us it's not safe to change | |
499 | this control while we're capturing. Make a note of this | |
500 | fact so that the pipeline will be stopped the next time | |
501 | controls are committed. Then go on ahead and store this | |
502 | change anyway. */ | |
503 | ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state, | |
504 | 0, &cs, | |
505 | VIDIOC_S_EXT_CTRLS); | |
506 | if (!ret) hdw->enc_unsafe_stale = !0; | |
507 | } | |
b30d2441 | 508 | if (ret) return ret; |
681c7399 | 509 | hdw->enc_stale = !0; |
b30d2441 MI |
510 | return 0; |
511 | } | |
512 | ||
513 | static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr) | |
514 | { | |
515 | struct v4l2_queryctrl qctrl; | |
516 | struct pvr2_ctl_info *info; | |
517 | qctrl.id = cptr->info->v4l_id; | |
518 | cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl); | |
519 | /* Strip out the const so we can adjust a function pointer. It's | |
520 | OK to do this here because we know this is a dynamically created | |
521 | control, so the underlying storage for the info pointer is (a) | |
522 | private to us, and (b) not in read-only storage. Either we do | |
523 | this or we significantly complicate the underlying control | |
524 | implementation. */ | |
525 | info = (struct pvr2_ctl_info *)(cptr->info); | |
526 | if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) { | |
527 | if (info->set_value) { | |
a0fd1cb1 | 528 | info->set_value = NULL; |
b30d2441 MI |
529 | } |
530 | } else { | |
531 | if (!(info->set_value)) { | |
532 | info->set_value = ctrl_cx2341x_set; | |
533 | } | |
534 | } | |
535 | return qctrl.flags; | |
536 | } | |
537 | ||
d855497e MI |
538 | static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp) |
539 | { | |
681c7399 MI |
540 | *vp = cptr->hdw->state_pipeline_req; |
541 | return 0; | |
542 | } | |
543 | ||
544 | static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp) | |
545 | { | |
546 | *vp = cptr->hdw->master_state; | |
d855497e MI |
547 | return 0; |
548 | } | |
549 | ||
550 | static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp) | |
551 | { | |
552 | int result = pvr2_hdw_is_hsm(cptr->hdw); | |
553 | *vp = PVR2_CVAL_HSM_FULL; | |
554 | if (result < 0) *vp = PVR2_CVAL_HSM_FAIL; | |
555 | if (result) *vp = PVR2_CVAL_HSM_HIGH; | |
556 | return 0; | |
557 | } | |
558 | ||
559 | static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp) | |
560 | { | |
561 | *vp = cptr->hdw->std_mask_avail; | |
562 | return 0; | |
563 | } | |
564 | ||
565 | static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v) | |
566 | { | |
567 | struct pvr2_hdw *hdw = cptr->hdw; | |
568 | v4l2_std_id ns; | |
569 | ns = hdw->std_mask_avail; | |
570 | ns = (ns & ~m) | (v & m); | |
571 | if (ns == hdw->std_mask_avail) return 0; | |
572 | hdw->std_mask_avail = ns; | |
573 | pvr2_hdw_internal_set_std_avail(hdw); | |
574 | pvr2_hdw_internal_find_stdenum(hdw); | |
575 | return 0; | |
576 | } | |
577 | ||
578 | static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val, | |
579 | char *bufPtr,unsigned int bufSize, | |
580 | unsigned int *len) | |
581 | { | |
582 | *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val); | |
583 | return 0; | |
584 | } | |
585 | ||
586 | static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr, | |
587 | const char *bufPtr,unsigned int bufSize, | |
588 | int *mskp,int *valp) | |
589 | { | |
590 | int ret; | |
591 | v4l2_std_id id; | |
592 | ret = pvr2_std_str_to_id(&id,bufPtr,bufSize); | |
593 | if (ret < 0) return ret; | |
594 | if (mskp) *mskp = id; | |
595 | if (valp) *valp = id; | |
596 | return 0; | |
597 | } | |
598 | ||
599 | static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp) | |
600 | { | |
601 | *vp = cptr->hdw->std_mask_cur; | |
602 | return 0; | |
603 | } | |
604 | ||
605 | static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v) | |
606 | { | |
607 | struct pvr2_hdw *hdw = cptr->hdw; | |
608 | v4l2_std_id ns; | |
609 | ns = hdw->std_mask_cur; | |
610 | ns = (ns & ~m) | (v & m); | |
611 | if (ns == hdw->std_mask_cur) return 0; | |
612 | hdw->std_mask_cur = ns; | |
613 | hdw->std_dirty = !0; | |
614 | pvr2_hdw_internal_find_stdenum(hdw); | |
615 | return 0; | |
616 | } | |
617 | ||
618 | static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr) | |
619 | { | |
620 | return cptr->hdw->std_dirty != 0; | |
621 | } | |
622 | ||
623 | static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr) | |
624 | { | |
625 | cptr->hdw->std_dirty = 0; | |
626 | } | |
627 | ||
628 | static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp) | |
629 | { | |
18103c57 MI |
630 | struct pvr2_hdw *hdw = cptr->hdw; |
631 | pvr2_i2c_core_status_poll(hdw); | |
632 | *vp = hdw->tuner_signal_info.signal; | |
633 | return 0; | |
634 | } | |
635 | ||
636 | static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp) | |
637 | { | |
638 | int val = 0; | |
639 | unsigned int subchan; | |
640 | struct pvr2_hdw *hdw = cptr->hdw; | |
644afdb9 | 641 | pvr2_i2c_core_status_poll(hdw); |
18103c57 MI |
642 | subchan = hdw->tuner_signal_info.rxsubchans; |
643 | if (subchan & V4L2_TUNER_SUB_MONO) { | |
644 | val |= (1 << V4L2_TUNER_MODE_MONO); | |
645 | } | |
646 | if (subchan & V4L2_TUNER_SUB_STEREO) { | |
647 | val |= (1 << V4L2_TUNER_MODE_STEREO); | |
648 | } | |
649 | if (subchan & V4L2_TUNER_SUB_LANG1) { | |
650 | val |= (1 << V4L2_TUNER_MODE_LANG1); | |
651 | } | |
652 | if (subchan & V4L2_TUNER_SUB_LANG2) { | |
653 | val |= (1 << V4L2_TUNER_MODE_LANG2); | |
654 | } | |
655 | *vp = val; | |
d855497e MI |
656 | return 0; |
657 | } | |
658 | ||
d855497e MI |
659 | |
660 | static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v) | |
661 | { | |
662 | struct pvr2_hdw *hdw = cptr->hdw; | |
663 | if (v < 0) return -EINVAL; | |
664 | if (v > hdw->std_enum_cnt) return -EINVAL; | |
665 | hdw->std_enum_cur = v; | |
666 | if (!v) return 0; | |
667 | v--; | |
668 | if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0; | |
669 | hdw->std_mask_cur = hdw->std_defs[v].id; | |
670 | hdw->std_dirty = !0; | |
671 | return 0; | |
672 | } | |
673 | ||
674 | ||
675 | static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp) | |
676 | { | |
677 | *vp = cptr->hdw->std_enum_cur; | |
678 | return 0; | |
679 | } | |
680 | ||
681 | ||
682 | static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr) | |
683 | { | |
684 | return cptr->hdw->std_dirty != 0; | |
685 | } | |
686 | ||
687 | ||
688 | static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr) | |
689 | { | |
690 | cptr->hdw->std_dirty = 0; | |
691 | } | |
692 | ||
693 | ||
694 | #define DEFINT(vmin,vmax) \ | |
695 | .type = pvr2_ctl_int, \ | |
696 | .def.type_int.min_value = vmin, \ | |
697 | .def.type_int.max_value = vmax | |
698 | ||
699 | #define DEFENUM(tab) \ | |
700 | .type = pvr2_ctl_enum, \ | |
27c7b710 | 701 | .def.type_enum.count = ARRAY_SIZE(tab), \ |
d855497e MI |
702 | .def.type_enum.value_names = tab |
703 | ||
33213963 MI |
704 | #define DEFBOOL \ |
705 | .type = pvr2_ctl_bool | |
706 | ||
d855497e MI |
707 | #define DEFMASK(msk,tab) \ |
708 | .type = pvr2_ctl_bitmask, \ | |
709 | .def.type_bitmask.valid_bits = msk, \ | |
710 | .def.type_bitmask.bit_names = tab | |
711 | ||
712 | #define DEFREF(vname) \ | |
713 | .set_value = ctrl_set_##vname, \ | |
714 | .get_value = ctrl_get_##vname, \ | |
715 | .is_dirty = ctrl_isdirty_##vname, \ | |
716 | .clear_dirty = ctrl_cleardirty_##vname | |
717 | ||
718 | ||
719 | #define VCREATE_FUNCS(vname) \ | |
720 | static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \ | |
721 | {*vp = cptr->hdw->vname##_val; return 0;} \ | |
722 | static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \ | |
723 | {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \ | |
724 | static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \ | |
725 | {return cptr->hdw->vname##_dirty != 0;} \ | |
726 | static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \ | |
727 | {cptr->hdw->vname##_dirty = 0;} | |
728 | ||
729 | VCREATE_FUNCS(brightness) | |
730 | VCREATE_FUNCS(contrast) | |
731 | VCREATE_FUNCS(saturation) | |
732 | VCREATE_FUNCS(hue) | |
733 | VCREATE_FUNCS(volume) | |
734 | VCREATE_FUNCS(balance) | |
735 | VCREATE_FUNCS(bass) | |
736 | VCREATE_FUNCS(treble) | |
737 | VCREATE_FUNCS(mute) | |
c05c0462 MI |
738 | VCREATE_FUNCS(audiomode) |
739 | VCREATE_FUNCS(res_hor) | |
740 | VCREATE_FUNCS(res_ver) | |
d855497e | 741 | VCREATE_FUNCS(srate) |
d855497e | 742 | |
d855497e MI |
743 | /* Table definition of all controls which can be manipulated */ |
744 | static const struct pvr2_ctl_info control_defs[] = { | |
745 | { | |
746 | .v4l_id = V4L2_CID_BRIGHTNESS, | |
747 | .desc = "Brightness", | |
748 | .name = "brightness", | |
749 | .default_value = 128, | |
750 | DEFREF(brightness), | |
751 | DEFINT(0,255), | |
752 | },{ | |
753 | .v4l_id = V4L2_CID_CONTRAST, | |
754 | .desc = "Contrast", | |
755 | .name = "contrast", | |
756 | .default_value = 68, | |
757 | DEFREF(contrast), | |
758 | DEFINT(0,127), | |
759 | },{ | |
760 | .v4l_id = V4L2_CID_SATURATION, | |
761 | .desc = "Saturation", | |
762 | .name = "saturation", | |
763 | .default_value = 64, | |
764 | DEFREF(saturation), | |
765 | DEFINT(0,127), | |
766 | },{ | |
767 | .v4l_id = V4L2_CID_HUE, | |
768 | .desc = "Hue", | |
769 | .name = "hue", | |
770 | .default_value = 0, | |
771 | DEFREF(hue), | |
772 | DEFINT(-128,127), | |
773 | },{ | |
774 | .v4l_id = V4L2_CID_AUDIO_VOLUME, | |
775 | .desc = "Volume", | |
776 | .name = "volume", | |
139eecf9 | 777 | .default_value = 62000, |
d855497e MI |
778 | DEFREF(volume), |
779 | DEFINT(0,65535), | |
780 | },{ | |
781 | .v4l_id = V4L2_CID_AUDIO_BALANCE, | |
782 | .desc = "Balance", | |
783 | .name = "balance", | |
784 | .default_value = 0, | |
785 | DEFREF(balance), | |
786 | DEFINT(-32768,32767), | |
787 | },{ | |
788 | .v4l_id = V4L2_CID_AUDIO_BASS, | |
789 | .desc = "Bass", | |
790 | .name = "bass", | |
791 | .default_value = 0, | |
792 | DEFREF(bass), | |
793 | DEFINT(-32768,32767), | |
794 | },{ | |
795 | .v4l_id = V4L2_CID_AUDIO_TREBLE, | |
796 | .desc = "Treble", | |
797 | .name = "treble", | |
798 | .default_value = 0, | |
799 | DEFREF(treble), | |
800 | DEFINT(-32768,32767), | |
801 | },{ | |
802 | .v4l_id = V4L2_CID_AUDIO_MUTE, | |
803 | .desc = "Mute", | |
804 | .name = "mute", | |
805 | .default_value = 0, | |
806 | DEFREF(mute), | |
33213963 | 807 | DEFBOOL, |
c05c0462 MI |
808 | },{ |
809 | .desc = "Video Source", | |
810 | .name = "input", | |
811 | .internal_id = PVR2_CID_INPUT, | |
812 | .default_value = PVR2_CVAL_INPUT_TV, | |
29bf5b1d | 813 | .check_value = ctrl_check_input, |
c05c0462 MI |
814 | DEFREF(input), |
815 | DEFENUM(control_values_input), | |
816 | },{ | |
817 | .desc = "Audio Mode", | |
818 | .name = "audio_mode", | |
819 | .internal_id = PVR2_CID_AUDIOMODE, | |
820 | .default_value = V4L2_TUNER_MODE_STEREO, | |
821 | DEFREF(audiomode), | |
822 | DEFENUM(control_values_audiomode), | |
823 | },{ | |
824 | .desc = "Horizontal capture resolution", | |
825 | .name = "resolution_hor", | |
826 | .internal_id = PVR2_CID_HRES, | |
827 | .default_value = 720, | |
828 | DEFREF(res_hor), | |
3ad9fc37 | 829 | DEFINT(19,720), |
c05c0462 MI |
830 | },{ |
831 | .desc = "Vertical capture resolution", | |
832 | .name = "resolution_ver", | |
833 | .internal_id = PVR2_CID_VRES, | |
834 | .default_value = 480, | |
835 | DEFREF(res_ver), | |
3ad9fc37 MI |
836 | DEFINT(17,576), |
837 | /* Hook in check for video standard and adjust maximum | |
838 | depending on the standard. */ | |
839 | .get_max_value = ctrl_vres_max_get, | |
840 | .get_min_value = ctrl_vres_min_get, | |
d855497e | 841 | },{ |
b30d2441 | 842 | .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ, |
434449f4 MI |
843 | .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000, |
844 | .desc = "Audio Sampling Frequency", | |
d855497e | 845 | .name = "srate", |
d855497e MI |
846 | DEFREF(srate), |
847 | DEFENUM(control_values_srate), | |
d855497e MI |
848 | },{ |
849 | .desc = "Tuner Frequency (Hz)", | |
850 | .name = "frequency", | |
851 | .internal_id = PVR2_CID_FREQUENCY, | |
1bde0289 | 852 | .default_value = 0, |
d855497e MI |
853 | .set_value = ctrl_freq_set, |
854 | .get_value = ctrl_freq_get, | |
855 | .is_dirty = ctrl_freq_is_dirty, | |
856 | .clear_dirty = ctrl_freq_clear_dirty, | |
644afdb9 | 857 | DEFINT(0,0), |
25d8527a PK |
858 | /* Hook in check for input value (tv/radio) and adjust |
859 | max/min values accordingly */ | |
860 | .get_max_value = ctrl_freq_max_get, | |
861 | .get_min_value = ctrl_freq_min_get, | |
d855497e MI |
862 | },{ |
863 | .desc = "Channel", | |
864 | .name = "channel", | |
865 | .set_value = ctrl_channel_set, | |
866 | .get_value = ctrl_channel_get, | |
867 | DEFINT(0,FREQTABLE_SIZE), | |
868 | },{ | |
869 | .desc = "Channel Program Frequency", | |
870 | .name = "freq_table_value", | |
871 | .set_value = ctrl_channelfreq_set, | |
872 | .get_value = ctrl_channelfreq_get, | |
644afdb9 | 873 | DEFINT(0,0), |
1bde0289 MI |
874 | /* Hook in check for input value (tv/radio) and adjust |
875 | max/min values accordingly */ | |
1bde0289 MI |
876 | .get_max_value = ctrl_freq_max_get, |
877 | .get_min_value = ctrl_freq_min_get, | |
d855497e MI |
878 | },{ |
879 | .desc = "Channel Program ID", | |
880 | .name = "freq_table_channel", | |
881 | .set_value = ctrl_channelprog_set, | |
882 | .get_value = ctrl_channelprog_get, | |
883 | DEFINT(0,FREQTABLE_SIZE), | |
d855497e MI |
884 | },{ |
885 | .desc = "Streaming Enabled", | |
886 | .name = "streaming_enabled", | |
887 | .get_value = ctrl_streamingenabled_get, | |
33213963 | 888 | DEFBOOL, |
d855497e MI |
889 | },{ |
890 | .desc = "USB Speed", | |
891 | .name = "usb_speed", | |
892 | .get_value = ctrl_hsm_get, | |
893 | DEFENUM(control_values_hsm), | |
681c7399 MI |
894 | },{ |
895 | .desc = "Master State", | |
896 | .name = "master_state", | |
897 | .get_value = ctrl_masterstate_get, | |
898 | DEFENUM(pvr2_state_names), | |
d855497e MI |
899 | },{ |
900 | .desc = "Signal Present", | |
901 | .name = "signal_present", | |
902 | .get_value = ctrl_signal_get, | |
18103c57 MI |
903 | DEFINT(0,65535), |
904 | },{ | |
905 | .desc = "Audio Modes Present", | |
906 | .name = "audio_modes_present", | |
907 | .get_value = ctrl_audio_modes_present_get, | |
908 | /* For this type we "borrow" the V4L2_TUNER_MODE enum from | |
909 | v4l. Nothing outside of this module cares about this, | |
910 | but I reuse it in order to also reuse the | |
911 | control_values_audiomode string table. */ | |
912 | DEFMASK(((1 << V4L2_TUNER_MODE_MONO)| | |
913 | (1 << V4L2_TUNER_MODE_STEREO)| | |
914 | (1 << V4L2_TUNER_MODE_LANG1)| | |
915 | (1 << V4L2_TUNER_MODE_LANG2)), | |
916 | control_values_audiomode), | |
d855497e MI |
917 | },{ |
918 | .desc = "Video Standards Available Mask", | |
919 | .name = "video_standard_mask_available", | |
920 | .internal_id = PVR2_CID_STDAVAIL, | |
921 | .skip_init = !0, | |
922 | .get_value = ctrl_stdavail_get, | |
923 | .set_value = ctrl_stdavail_set, | |
924 | .val_to_sym = ctrl_std_val_to_sym, | |
925 | .sym_to_val = ctrl_std_sym_to_val, | |
926 | .type = pvr2_ctl_bitmask, | |
927 | },{ | |
928 | .desc = "Video Standards In Use Mask", | |
929 | .name = "video_standard_mask_active", | |
930 | .internal_id = PVR2_CID_STDCUR, | |
931 | .skip_init = !0, | |
932 | .get_value = ctrl_stdcur_get, | |
933 | .set_value = ctrl_stdcur_set, | |
934 | .is_dirty = ctrl_stdcur_is_dirty, | |
935 | .clear_dirty = ctrl_stdcur_clear_dirty, | |
936 | .val_to_sym = ctrl_std_val_to_sym, | |
937 | .sym_to_val = ctrl_std_sym_to_val, | |
938 | .type = pvr2_ctl_bitmask, | |
d855497e MI |
939 | },{ |
940 | .desc = "Video Standard Name", | |
941 | .name = "video_standard", | |
942 | .internal_id = PVR2_CID_STDENUM, | |
943 | .skip_init = !0, | |
944 | .get_value = ctrl_stdenumcur_get, | |
945 | .set_value = ctrl_stdenumcur_set, | |
946 | .is_dirty = ctrl_stdenumcur_is_dirty, | |
947 | .clear_dirty = ctrl_stdenumcur_clear_dirty, | |
948 | .type = pvr2_ctl_enum, | |
949 | } | |
950 | }; | |
951 | ||
eca8ebfc | 952 | #define CTRLDEF_COUNT ARRAY_SIZE(control_defs) |
d855497e MI |
953 | |
954 | ||
955 | const char *pvr2_config_get_name(enum pvr2_config cfg) | |
956 | { | |
957 | switch (cfg) { | |
958 | case pvr2_config_empty: return "empty"; | |
959 | case pvr2_config_mpeg: return "mpeg"; | |
960 | case pvr2_config_vbi: return "vbi"; | |
16eb40d3 MI |
961 | case pvr2_config_pcm: return "pcm"; |
962 | case pvr2_config_rawvideo: return "raw video"; | |
d855497e MI |
963 | } |
964 | return "<unknown>"; | |
965 | } | |
966 | ||
967 | ||
968 | struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw) | |
969 | { | |
970 | return hdw->usb_dev; | |
971 | } | |
972 | ||
973 | ||
974 | unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw) | |
975 | { | |
976 | return hdw->serial_number; | |
977 | } | |
978 | ||
31a18547 MI |
979 | |
980 | const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw) | |
981 | { | |
982 | return hdw->bus_info; | |
983 | } | |
984 | ||
985 | ||
1bde0289 MI |
986 | unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw) |
987 | { | |
988 | return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio; | |
989 | } | |
990 | ||
991 | /* Set the currently tuned frequency and account for all possible | |
992 | driver-core side effects of this action. */ | |
993 | void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val) | |
994 | { | |
7c74e57e | 995 | if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { |
1bde0289 MI |
996 | if (hdw->freqSelector) { |
997 | /* Swing over to radio frequency selection */ | |
998 | hdw->freqSelector = 0; | |
999 | hdw->freqDirty = !0; | |
1000 | } | |
1bde0289 MI |
1001 | if (hdw->freqValRadio != val) { |
1002 | hdw->freqValRadio = val; | |
1003 | hdw->freqSlotRadio = 0; | |
7c74e57e | 1004 | hdw->freqDirty = !0; |
1bde0289 | 1005 | } |
7c74e57e | 1006 | } else { |
1bde0289 MI |
1007 | if (!(hdw->freqSelector)) { |
1008 | /* Swing over to television frequency selection */ | |
1009 | hdw->freqSelector = 1; | |
1010 | hdw->freqDirty = !0; | |
1011 | } | |
1bde0289 MI |
1012 | if (hdw->freqValTelevision != val) { |
1013 | hdw->freqValTelevision = val; | |
1014 | hdw->freqSlotTelevision = 0; | |
7c74e57e | 1015 | hdw->freqDirty = !0; |
1bde0289 | 1016 | } |
1bde0289 MI |
1017 | } |
1018 | } | |
1019 | ||
d855497e MI |
1020 | int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw) |
1021 | { | |
1022 | return hdw->unit_number; | |
1023 | } | |
1024 | ||
1025 | ||
1026 | /* Attempt to locate one of the given set of files. Messages are logged | |
1027 | appropriate to what has been found. The return value will be 0 or | |
1028 | greater on success (it will be the index of the file name found) and | |
1029 | fw_entry will be filled in. Otherwise a negative error is returned on | |
1030 | failure. If the return value is -ENOENT then no viable firmware file | |
1031 | could be located. */ | |
1032 | static int pvr2_locate_firmware(struct pvr2_hdw *hdw, | |
1033 | const struct firmware **fw_entry, | |
1034 | const char *fwtypename, | |
1035 | unsigned int fwcount, | |
1036 | const char *fwnames[]) | |
1037 | { | |
1038 | unsigned int idx; | |
1039 | int ret = -EINVAL; | |
1040 | for (idx = 0; idx < fwcount; idx++) { | |
1041 | ret = request_firmware(fw_entry, | |
1042 | fwnames[idx], | |
1043 | &hdw->usb_dev->dev); | |
1044 | if (!ret) { | |
1045 | trace_firmware("Located %s firmware: %s;" | |
1046 | " uploading...", | |
1047 | fwtypename, | |
1048 | fwnames[idx]); | |
1049 | return idx; | |
1050 | } | |
1051 | if (ret == -ENOENT) continue; | |
1052 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1053 | "request_firmware fatal error with code=%d",ret); | |
1054 | return ret; | |
1055 | } | |
1056 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1057 | "***WARNING***" | |
1058 | " Device %s firmware" | |
1059 | " seems to be missing.", | |
1060 | fwtypename); | |
1061 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1062 | "Did you install the pvrusb2 firmware files" | |
1063 | " in their proper location?"); | |
1064 | if (fwcount == 1) { | |
1065 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1066 | "request_firmware unable to locate %s file %s", | |
1067 | fwtypename,fwnames[0]); | |
1068 | } else { | |
1069 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1070 | "request_firmware unable to locate" | |
1071 | " one of the following %s files:", | |
1072 | fwtypename); | |
1073 | for (idx = 0; idx < fwcount; idx++) { | |
1074 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1075 | "request_firmware: Failed to find %s", | |
1076 | fwnames[idx]); | |
1077 | } | |
1078 | } | |
1079 | return ret; | |
1080 | } | |
1081 | ||
1082 | ||
1083 | /* | |
1084 | * pvr2_upload_firmware1(). | |
1085 | * | |
1086 | * Send the 8051 firmware to the device. After the upload, arrange for | |
1087 | * device to re-enumerate. | |
1088 | * | |
1089 | * NOTE : the pointer to the firmware data given by request_firmware() | |
1090 | * is not suitable for an usb transaction. | |
1091 | * | |
1092 | */ | |
07e337ee | 1093 | static int pvr2_upload_firmware1(struct pvr2_hdw *hdw) |
d855497e | 1094 | { |
a0fd1cb1 | 1095 | const struct firmware *fw_entry = NULL; |
d855497e MI |
1096 | void *fw_ptr; |
1097 | unsigned int pipe; | |
1098 | int ret; | |
1099 | u16 address; | |
1d643a37 | 1100 | |
989eb154 | 1101 | if (!hdw->hdw_desc->fx2_firmware.cnt) { |
1d643a37 | 1102 | hdw->fw1_state = FW1_STATE_OK; |
56dcbfa0 MI |
1103 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, |
1104 | "Connected device type defines" | |
1105 | " no firmware to upload; ignoring firmware"); | |
1106 | return -ENOTTY; | |
1d643a37 MI |
1107 | } |
1108 | ||
d855497e MI |
1109 | hdw->fw1_state = FW1_STATE_FAILED; // default result |
1110 | ||
1111 | trace_firmware("pvr2_upload_firmware1"); | |
1112 | ||
1113 | ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller", | |
989eb154 MI |
1114 | hdw->hdw_desc->fx2_firmware.cnt, |
1115 | hdw->hdw_desc->fx2_firmware.lst); | |
d855497e MI |
1116 | if (ret < 0) { |
1117 | if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING; | |
1118 | return ret; | |
1119 | } | |
1120 | ||
1121 | usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0); | |
1122 | usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f)); | |
1123 | ||
1124 | pipe = usb_sndctrlpipe(hdw->usb_dev, 0); | |
1125 | ||
1126 | if (fw_entry->size != 0x2000){ | |
1127 | pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size"); | |
1128 | release_firmware(fw_entry); | |
1129 | return -ENOMEM; | |
1130 | } | |
1131 | ||
1132 | fw_ptr = kmalloc(0x800, GFP_KERNEL); | |
1133 | if (fw_ptr == NULL){ | |
1134 | release_firmware(fw_entry); | |
1135 | return -ENOMEM; | |
1136 | } | |
1137 | ||
1138 | /* We have to hold the CPU during firmware upload. */ | |
1139 | pvr2_hdw_cpureset_assert(hdw,1); | |
1140 | ||
1141 | /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes | |
1142 | chunk. */ | |
1143 | ||
1144 | ret = 0; | |
1145 | for(address = 0; address < fw_entry->size; address += 0x800) { | |
1146 | memcpy(fw_ptr, fw_entry->data + address, 0x800); | |
1147 | ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address, | |
1148 | 0, fw_ptr, 0x800, HZ); | |
1149 | } | |
1150 | ||
1151 | trace_firmware("Upload done, releasing device's CPU"); | |
1152 | ||
1153 | /* Now release the CPU. It will disconnect and reconnect later. */ | |
1154 | pvr2_hdw_cpureset_assert(hdw,0); | |
1155 | ||
1156 | kfree(fw_ptr); | |
1157 | release_firmware(fw_entry); | |
1158 | ||
1159 | trace_firmware("Upload done (%d bytes sent)",ret); | |
1160 | ||
1161 | /* We should have written 8192 bytes */ | |
1162 | if (ret == 8192) { | |
1163 | hdw->fw1_state = FW1_STATE_RELOAD; | |
1164 | return 0; | |
1165 | } | |
1166 | ||
1167 | return -EIO; | |
1168 | } | |
1169 | ||
1170 | ||
1171 | /* | |
1172 | * pvr2_upload_firmware2() | |
1173 | * | |
1174 | * This uploads encoder firmware on endpoint 2. | |
1175 | * | |
1176 | */ | |
1177 | ||
1178 | int pvr2_upload_firmware2(struct pvr2_hdw *hdw) | |
1179 | { | |
a0fd1cb1 | 1180 | const struct firmware *fw_entry = NULL; |
d855497e | 1181 | void *fw_ptr; |
90060d32 | 1182 | unsigned int pipe, fw_len, fw_done, bcnt, icnt; |
d855497e MI |
1183 | int actual_length; |
1184 | int ret = 0; | |
1185 | int fwidx; | |
1186 | static const char *fw_files[] = { | |
1187 | CX2341X_FIRM_ENC_FILENAME, | |
1188 | }; | |
1189 | ||
989eb154 | 1190 | if (hdw->hdw_desc->flag_skip_cx23416_firmware) { |
1d643a37 MI |
1191 | return 0; |
1192 | } | |
1193 | ||
d855497e MI |
1194 | trace_firmware("pvr2_upload_firmware2"); |
1195 | ||
1196 | ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder", | |
eca8ebfc | 1197 | ARRAY_SIZE(fw_files), fw_files); |
d855497e MI |
1198 | if (ret < 0) return ret; |
1199 | fwidx = ret; | |
1200 | ret = 0; | |
b30d2441 MI |
1201 | /* Since we're about to completely reinitialize the encoder, |
1202 | invalidate our cached copy of its configuration state. Next | |
1203 | time we configure the encoder, then we'll fully configure it. */ | |
1204 | hdw->enc_cur_valid = 0; | |
d855497e MI |
1205 | |
1206 | /* First prepare firmware loading */ | |
1207 | ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/ | |
1208 | ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/ | |
1209 | ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/ | |
1210 | ret |= pvr2_hdw_cmd_deep_reset(hdw); | |
1211 | ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/ | |
1212 | ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/ | |
1213 | ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/ | |
1214 | ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/ | |
1215 | ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/ | |
1216 | ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/ | |
1217 | ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/ | |
1218 | ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/ | |
1219 | ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/ | |
1220 | ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/ | |
1221 | ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/ | |
1222 | ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/ | |
567d7115 MI |
1223 | LOCK_TAKE(hdw->ctl_lock); do { |
1224 | hdw->cmd_buffer[0] = FX2CMD_FWPOST1; | |
89952d13 | 1225 | ret |= pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0); |
567d7115 MI |
1226 | hdw->cmd_buffer[0] = FX2CMD_MEMSEL; |
1227 | hdw->cmd_buffer[1] = 0; | |
89952d13 | 1228 | ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0); |
567d7115 | 1229 | } while (0); LOCK_GIVE(hdw->ctl_lock); |
d855497e MI |
1230 | |
1231 | if (ret) { | |
1232 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1233 | "firmware2 upload prep failed, ret=%d",ret); | |
1234 | release_firmware(fw_entry); | |
1235 | return ret; | |
1236 | } | |
1237 | ||
1238 | /* Now send firmware */ | |
1239 | ||
1240 | fw_len = fw_entry->size; | |
1241 | ||
90060d32 | 1242 | if (fw_len % sizeof(u32)) { |
d855497e MI |
1243 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, |
1244 | "size of %s firmware" | |
48dc30a1 | 1245 | " must be a multiple of %zu bytes", |
90060d32 | 1246 | fw_files[fwidx],sizeof(u32)); |
d855497e MI |
1247 | release_firmware(fw_entry); |
1248 | return -1; | |
1249 | } | |
1250 | ||
1251 | fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL); | |
1252 | if (fw_ptr == NULL){ | |
1253 | release_firmware(fw_entry); | |
1254 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1255 | "failed to allocate memory for firmware2 upload"); | |
1256 | return -ENOMEM; | |
1257 | } | |
1258 | ||
1259 | pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT); | |
1260 | ||
90060d32 MI |
1261 | fw_done = 0; |
1262 | for (fw_done = 0; fw_done < fw_len;) { | |
1263 | bcnt = fw_len - fw_done; | |
1264 | if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE; | |
1265 | memcpy(fw_ptr, fw_entry->data + fw_done, bcnt); | |
1266 | /* Usbsnoop log shows that we must swap bytes... */ | |
1267 | for (icnt = 0; icnt < bcnt/4 ; icnt++) | |
1268 | ((u32 *)fw_ptr)[icnt] = | |
1269 | ___swab32(((u32 *)fw_ptr)[icnt]); | |
1270 | ||
1271 | ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt, | |
d855497e | 1272 | &actual_length, HZ); |
90060d32 MI |
1273 | ret |= (actual_length != bcnt); |
1274 | if (ret) break; | |
1275 | fw_done += bcnt; | |
d855497e MI |
1276 | } |
1277 | ||
1278 | trace_firmware("upload of %s : %i / %i ", | |
1279 | fw_files[fwidx],fw_done,fw_len); | |
1280 | ||
1281 | kfree(fw_ptr); | |
1282 | release_firmware(fw_entry); | |
1283 | ||
1284 | if (ret) { | |
1285 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1286 | "firmware2 upload transfer failure"); | |
1287 | return ret; | |
1288 | } | |
1289 | ||
1290 | /* Finish upload */ | |
1291 | ||
1292 | ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/ | |
1293 | ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/ | |
567d7115 MI |
1294 | LOCK_TAKE(hdw->ctl_lock); do { |
1295 | hdw->cmd_buffer[0] = FX2CMD_MEMSEL; | |
1296 | hdw->cmd_buffer[1] = 0; | |
89952d13 | 1297 | ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0); |
567d7115 | 1298 | } while (0); LOCK_GIVE(hdw->ctl_lock); |
d855497e MI |
1299 | |
1300 | if (ret) { | |
1301 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1302 | "firmware2 upload post-proc failure"); | |
d855497e MI |
1303 | } |
1304 | return ret; | |
1305 | } | |
1306 | ||
1307 | ||
681c7399 MI |
1308 | static const char *pvr2_get_state_name(unsigned int st) |
1309 | { | |
1310 | if (st < ARRAY_SIZE(pvr2_state_names)) { | |
1311 | return pvr2_state_names[st]; | |
d855497e | 1312 | } |
681c7399 | 1313 | return "???"; |
d855497e MI |
1314 | } |
1315 | ||
681c7399 | 1316 | static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl) |
d855497e | 1317 | { |
681c7399 MI |
1318 | if (!hdw->decoder_ctrl) { |
1319 | if (!hdw->flag_decoder_missed) { | |
1320 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1321 | "WARNING: No decoder present"); | |
1322 | hdw->flag_decoder_missed = !0; | |
1323 | trace_stbit("flag_decoder_missed", | |
1324 | hdw->flag_decoder_missed); | |
1325 | } | |
1326 | return -EIO; | |
1327 | } | |
1328 | hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl); | |
1329 | return 0; | |
d855497e MI |
1330 | } |
1331 | ||
1332 | ||
681c7399 | 1333 | void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr) |
d855497e | 1334 | { |
681c7399 MI |
1335 | if (hdw->decoder_ctrl == ptr) return; |
1336 | hdw->decoder_ctrl = ptr; | |
1337 | if (hdw->decoder_ctrl && hdw->flag_decoder_missed) { | |
1338 | hdw->flag_decoder_missed = 0; | |
1339 | trace_stbit("flag_decoder_missed", | |
1340 | hdw->flag_decoder_missed); | |
1341 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1342 | "Decoder has appeared"); | |
1343 | pvr2_hdw_state_sched(hdw); | |
1344 | } | |
d855497e MI |
1345 | } |
1346 | ||
1347 | ||
681c7399 | 1348 | int pvr2_hdw_get_state(struct pvr2_hdw *hdw) |
d855497e | 1349 | { |
681c7399 | 1350 | return hdw->master_state; |
d855497e MI |
1351 | } |
1352 | ||
1353 | ||
681c7399 | 1354 | static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw) |
d855497e | 1355 | { |
681c7399 MI |
1356 | if (!hdw->flag_tripped) return 0; |
1357 | hdw->flag_tripped = 0; | |
1358 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1359 | "Clearing driver error statuss"); | |
1360 | return !0; | |
d855497e MI |
1361 | } |
1362 | ||
1363 | ||
681c7399 | 1364 | int pvr2_hdw_untrip(struct pvr2_hdw *hdw) |
d855497e | 1365 | { |
681c7399 | 1366 | int fl; |
d855497e | 1367 | LOCK_TAKE(hdw->big_lock); do { |
681c7399 | 1368 | fl = pvr2_hdw_untrip_unlocked(hdw); |
d855497e | 1369 | } while (0); LOCK_GIVE(hdw->big_lock); |
681c7399 MI |
1370 | if (fl) pvr2_hdw_state_sched(hdw); |
1371 | return 0; | |
d855497e MI |
1372 | } |
1373 | ||
1374 | ||
681c7399 | 1375 | const char *pvr2_hdw_get_state_name(unsigned int id) |
d855497e | 1376 | { |
681c7399 MI |
1377 | if (id >= ARRAY_SIZE(pvr2_state_names)) return NULL; |
1378 | return pvr2_state_names[id]; | |
d855497e MI |
1379 | } |
1380 | ||
1381 | ||
1382 | int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw) | |
1383 | { | |
681c7399 | 1384 | return hdw->state_pipeline_req != 0; |
d855497e MI |
1385 | } |
1386 | ||
1387 | ||
1388 | int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag) | |
1389 | { | |
681c7399 | 1390 | int ret,st; |
d855497e | 1391 | LOCK_TAKE(hdw->big_lock); do { |
681c7399 MI |
1392 | pvr2_hdw_untrip_unlocked(hdw); |
1393 | if ((!enable_flag) != !(hdw->state_pipeline_req)) { | |
1394 | hdw->state_pipeline_req = enable_flag != 0; | |
1395 | pvr2_trace(PVR2_TRACE_START_STOP, | |
1396 | "/*--TRACE_STREAM--*/ %s", | |
1397 | enable_flag ? "enable" : "disable"); | |
1398 | } | |
1399 | pvr2_hdw_state_sched(hdw); | |
d855497e | 1400 | } while (0); LOCK_GIVE(hdw->big_lock); |
681c7399 MI |
1401 | if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret; |
1402 | if (enable_flag) { | |
1403 | while ((st = hdw->master_state) != PVR2_STATE_RUN) { | |
1404 | if (st != PVR2_STATE_READY) return -EIO; | |
1405 | if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret; | |
1406 | } | |
1407 | } | |
d855497e MI |
1408 | return 0; |
1409 | } | |
1410 | ||
1411 | ||
1412 | int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config) | |
1413 | { | |
681c7399 | 1414 | int fl; |
d855497e | 1415 | LOCK_TAKE(hdw->big_lock); |
681c7399 MI |
1416 | if ((fl = (hdw->desired_stream_type != config)) != 0) { |
1417 | hdw->desired_stream_type = config; | |
1418 | hdw->state_pipeline_config = 0; | |
1419 | trace_stbit("state_pipeline_config", | |
1420 | hdw->state_pipeline_config); | |
1421 | pvr2_hdw_state_sched(hdw); | |
1422 | } | |
d855497e | 1423 | LOCK_GIVE(hdw->big_lock); |
681c7399 MI |
1424 | if (fl) return 0; |
1425 | return pvr2_hdw_wait(hdw,0); | |
d855497e MI |
1426 | } |
1427 | ||
1428 | ||
1429 | static int get_default_tuner_type(struct pvr2_hdw *hdw) | |
1430 | { | |
1431 | int unit_number = hdw->unit_number; | |
1432 | int tp = -1; | |
1433 | if ((unit_number >= 0) && (unit_number < PVR_NUM)) { | |
1434 | tp = tuner[unit_number]; | |
1435 | } | |
1436 | if (tp < 0) return -EINVAL; | |
1437 | hdw->tuner_type = tp; | |
aaf7884d | 1438 | hdw->tuner_updated = !0; |
d855497e MI |
1439 | return 0; |
1440 | } | |
1441 | ||
1442 | ||
1443 | static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw) | |
1444 | { | |
1445 | int unit_number = hdw->unit_number; | |
1446 | int tp = 0; | |
1447 | if ((unit_number >= 0) && (unit_number < PVR_NUM)) { | |
1448 | tp = video_std[unit_number]; | |
6a540254 | 1449 | if (tp) return tp; |
d855497e | 1450 | } |
6a540254 | 1451 | return 0; |
d855497e MI |
1452 | } |
1453 | ||
1454 | ||
1455 | static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw) | |
1456 | { | |
1457 | int unit_number = hdw->unit_number; | |
1458 | int tp = 0; | |
1459 | if ((unit_number >= 0) && (unit_number < PVR_NUM)) { | |
1460 | tp = tolerance[unit_number]; | |
1461 | } | |
1462 | return tp; | |
1463 | } | |
1464 | ||
1465 | ||
1466 | static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw) | |
1467 | { | |
1468 | /* Try a harmless request to fetch the eeprom's address over | |
1469 | endpoint 1. See what happens. Only the full FX2 image can | |
1470 | respond to this. If this probe fails then likely the FX2 | |
1471 | firmware needs be loaded. */ | |
1472 | int result; | |
1473 | LOCK_TAKE(hdw->ctl_lock); do { | |
8d364363 | 1474 | hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR; |
d855497e MI |
1475 | result = pvr2_send_request_ex(hdw,HZ*1,!0, |
1476 | hdw->cmd_buffer,1, | |
1477 | hdw->cmd_buffer,1); | |
1478 | if (result < 0) break; | |
1479 | } while(0); LOCK_GIVE(hdw->ctl_lock); | |
1480 | if (result) { | |
1481 | pvr2_trace(PVR2_TRACE_INIT, | |
1482 | "Probe of device endpoint 1 result status %d", | |
1483 | result); | |
1484 | } else { | |
1485 | pvr2_trace(PVR2_TRACE_INIT, | |
1486 | "Probe of device endpoint 1 succeeded"); | |
1487 | } | |
1488 | return result == 0; | |
1489 | } | |
1490 | ||
9f66d4ea MI |
1491 | struct pvr2_std_hack { |
1492 | v4l2_std_id pat; /* Pattern to match */ | |
1493 | v4l2_std_id msk; /* Which bits we care about */ | |
1494 | v4l2_std_id std; /* What additional standards or default to set */ | |
1495 | }; | |
1496 | ||
1497 | /* This data structure labels specific combinations of standards from | |
1498 | tveeprom that we'll try to recognize. If we recognize one, then assume | |
1499 | a specified default standard to use. This is here because tveeprom only | |
1500 | tells us about available standards not the intended default standard (if | |
1501 | any) for the device in question. We guess the default based on what has | |
1502 | been reported as available. Note that this is only for guessing a | |
1503 | default - which can always be overridden explicitly - and if the user | |
1504 | has otherwise named a default then that default will always be used in | |
1505 | place of this table. */ | |
1506 | const static struct pvr2_std_hack std_eeprom_maps[] = { | |
1507 | { /* PAL(B/G) */ | |
1508 | .pat = V4L2_STD_B|V4L2_STD_GH, | |
1509 | .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G, | |
1510 | }, | |
1511 | { /* NTSC(M) */ | |
1512 | .pat = V4L2_STD_MN, | |
1513 | .std = V4L2_STD_NTSC_M, | |
1514 | }, | |
1515 | { /* PAL(I) */ | |
1516 | .pat = V4L2_STD_PAL_I, | |
1517 | .std = V4L2_STD_PAL_I, | |
1518 | }, | |
1519 | { /* SECAM(L/L') */ | |
1520 | .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC, | |
1521 | .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC, | |
1522 | }, | |
1523 | { /* PAL(D/D1/K) */ | |
1524 | .pat = V4L2_STD_DK, | |
ea2562d9 | 1525 | .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K, |
9f66d4ea MI |
1526 | }, |
1527 | }; | |
1528 | ||
d855497e MI |
1529 | static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw) |
1530 | { | |
1531 | char buf[40]; | |
1532 | unsigned int bcnt; | |
3d290bdb | 1533 | v4l2_std_id std1,std2,std3; |
d855497e MI |
1534 | |
1535 | std1 = get_default_standard(hdw); | |
3d290bdb | 1536 | std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask; |
d855497e MI |
1537 | |
1538 | bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom); | |
56585386 | 1539 | pvr2_trace(PVR2_TRACE_STD, |
56dcbfa0 MI |
1540 | "Supported video standard(s) reported available" |
1541 | " in hardware: %.*s", | |
d855497e MI |
1542 | bcnt,buf); |
1543 | ||
1544 | hdw->std_mask_avail = hdw->std_mask_eeprom; | |
1545 | ||
3d290bdb | 1546 | std2 = (std1|std3) & ~hdw->std_mask_avail; |
d855497e MI |
1547 | if (std2) { |
1548 | bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2); | |
56585386 | 1549 | pvr2_trace(PVR2_TRACE_STD, |
d855497e MI |
1550 | "Expanding supported video standards" |
1551 | " to include: %.*s", | |
1552 | bcnt,buf); | |
1553 | hdw->std_mask_avail |= std2; | |
1554 | } | |
1555 | ||
1556 | pvr2_hdw_internal_set_std_avail(hdw); | |
1557 | ||
1558 | if (std1) { | |
1559 | bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1); | |
56585386 | 1560 | pvr2_trace(PVR2_TRACE_STD, |
d855497e MI |
1561 | "Initial video standard forced to %.*s", |
1562 | bcnt,buf); | |
1563 | hdw->std_mask_cur = std1; | |
1564 | hdw->std_dirty = !0; | |
1565 | pvr2_hdw_internal_find_stdenum(hdw); | |
1566 | return; | |
1567 | } | |
3d290bdb MI |
1568 | if (std3) { |
1569 | bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3); | |
1570 | pvr2_trace(PVR2_TRACE_STD, | |
1571 | "Initial video standard" | |
1572 | " (determined by device type): %.*s",bcnt,buf); | |
1573 | hdw->std_mask_cur = std3; | |
1574 | hdw->std_dirty = !0; | |
1575 | pvr2_hdw_internal_find_stdenum(hdw); | |
1576 | return; | |
1577 | } | |
d855497e | 1578 | |
9f66d4ea MI |
1579 | { |
1580 | unsigned int idx; | |
1581 | for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) { | |
1582 | if (std_eeprom_maps[idx].msk ? | |
1583 | ((std_eeprom_maps[idx].pat ^ | |
1584 | hdw->std_mask_eeprom) & | |
1585 | std_eeprom_maps[idx].msk) : | |
1586 | (std_eeprom_maps[idx].pat != | |
1587 | hdw->std_mask_eeprom)) continue; | |
1588 | bcnt = pvr2_std_id_to_str(buf,sizeof(buf), | |
1589 | std_eeprom_maps[idx].std); | |
56585386 | 1590 | pvr2_trace(PVR2_TRACE_STD, |
9f66d4ea MI |
1591 | "Initial video standard guessed as %.*s", |
1592 | bcnt,buf); | |
1593 | hdw->std_mask_cur = std_eeprom_maps[idx].std; | |
1594 | hdw->std_dirty = !0; | |
1595 | pvr2_hdw_internal_find_stdenum(hdw); | |
1596 | return; | |
1597 | } | |
1598 | } | |
1599 | ||
d855497e MI |
1600 | if (hdw->std_enum_cnt > 1) { |
1601 | // Autoselect the first listed standard | |
1602 | hdw->std_enum_cur = 1; | |
1603 | hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id; | |
1604 | hdw->std_dirty = !0; | |
56585386 | 1605 | pvr2_trace(PVR2_TRACE_STD, |
d855497e MI |
1606 | "Initial video standard auto-selected to %s", |
1607 | hdw->std_defs[hdw->std_enum_cur-1].name); | |
1608 | return; | |
1609 | } | |
1610 | ||
0885ba1d | 1611 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, |
d855497e MI |
1612 | "Unable to select a viable initial video standard"); |
1613 | } | |
1614 | ||
1615 | ||
1616 | static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw) | |
1617 | { | |
1618 | int ret; | |
1619 | unsigned int idx; | |
1620 | struct pvr2_ctrl *cptr; | |
1621 | int reloadFl = 0; | |
989eb154 | 1622 | if (hdw->hdw_desc->fx2_firmware.cnt) { |
1d643a37 MI |
1623 | if (!reloadFl) { |
1624 | reloadFl = | |
1625 | (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints | |
1626 | == 0); | |
1627 | if (reloadFl) { | |
1628 | pvr2_trace(PVR2_TRACE_INIT, | |
1629 | "USB endpoint config looks strange" | |
1630 | "; possibly firmware needs to be" | |
1631 | " loaded"); | |
1632 | } | |
d855497e | 1633 | } |
1d643a37 MI |
1634 | if (!reloadFl) { |
1635 | reloadFl = !pvr2_hdw_check_firmware(hdw); | |
1636 | if (reloadFl) { | |
1637 | pvr2_trace(PVR2_TRACE_INIT, | |
1638 | "Check for FX2 firmware failed" | |
1639 | "; possibly firmware needs to be" | |
1640 | " loaded"); | |
1641 | } | |
d855497e | 1642 | } |
1d643a37 MI |
1643 | if (reloadFl) { |
1644 | if (pvr2_upload_firmware1(hdw) != 0) { | |
1645 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1646 | "Failure uploading firmware1"); | |
1647 | } | |
1648 | return; | |
d855497e | 1649 | } |
d855497e MI |
1650 | } |
1651 | hdw->fw1_state = FW1_STATE_OK; | |
1652 | ||
1653 | if (initusbreset) { | |
1654 | pvr2_hdw_device_reset(hdw); | |
1655 | } | |
1656 | if (!pvr2_hdw_dev_ok(hdw)) return; | |
1657 | ||
989eb154 MI |
1658 | for (idx = 0; idx < hdw->hdw_desc->client_modules.cnt; idx++) { |
1659 | request_module(hdw->hdw_desc->client_modules.lst[idx]); | |
d855497e MI |
1660 | } |
1661 | ||
989eb154 | 1662 | if (!hdw->hdw_desc->flag_no_powerup) { |
1d643a37 MI |
1663 | pvr2_hdw_cmd_powerup(hdw); |
1664 | if (!pvr2_hdw_dev_ok(hdw)) return; | |
d855497e MI |
1665 | } |
1666 | ||
1667 | // This step MUST happen after the earlier powerup step. | |
1668 | pvr2_i2c_core_init(hdw); | |
1669 | if (!pvr2_hdw_dev_ok(hdw)) return; | |
1670 | ||
c05c0462 | 1671 | for (idx = 0; idx < CTRLDEF_COUNT; idx++) { |
d855497e MI |
1672 | cptr = hdw->controls + idx; |
1673 | if (cptr->info->skip_init) continue; | |
1674 | if (!cptr->info->set_value) continue; | |
1675 | cptr->info->set_value(cptr,~0,cptr->info->default_value); | |
1676 | } | |
1677 | ||
1bde0289 MI |
1678 | /* Set up special default values for the television and radio |
1679 | frequencies here. It's not really important what these defaults | |
1680 | are, but I set them to something usable in the Chicago area just | |
1681 | to make driver testing a little easier. */ | |
1682 | ||
1683 | /* US Broadcast channel 7 (175.25 MHz) */ | |
1684 | hdw->freqValTelevision = 175250000L; | |
1685 | /* 104.3 MHz, a usable FM station for my area */ | |
1686 | hdw->freqValRadio = 104300000L; | |
1687 | ||
d855497e MI |
1688 | // Do not use pvr2_reset_ctl_endpoints() here. It is not |
1689 | // thread-safe against the normal pvr2_send_request() mechanism. | |
1690 | // (We should make it thread safe). | |
1691 | ||
aaf7884d MI |
1692 | if (hdw->hdw_desc->flag_has_hauppauge_rom) { |
1693 | ret = pvr2_hdw_get_eeprom_addr(hdw); | |
d855497e | 1694 | if (!pvr2_hdw_dev_ok(hdw)) return; |
aaf7884d MI |
1695 | if (ret < 0) { |
1696 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1697 | "Unable to determine location of eeprom," | |
1698 | " skipping"); | |
1699 | } else { | |
1700 | hdw->eeprom_addr = ret; | |
1701 | pvr2_eeprom_analyze(hdw); | |
1702 | if (!pvr2_hdw_dev_ok(hdw)) return; | |
1703 | } | |
1704 | } else { | |
1705 | hdw->tuner_type = hdw->hdw_desc->default_tuner_type; | |
1706 | hdw->tuner_updated = !0; | |
1707 | hdw->std_mask_eeprom = V4L2_STD_ALL; | |
d855497e MI |
1708 | } |
1709 | ||
1710 | pvr2_hdw_setup_std(hdw); | |
1711 | ||
1712 | if (!get_default_tuner_type(hdw)) { | |
1713 | pvr2_trace(PVR2_TRACE_INIT, | |
1714 | "pvr2_hdw_setup: Tuner type overridden to %d", | |
1715 | hdw->tuner_type); | |
1716 | } | |
1717 | ||
d855497e MI |
1718 | pvr2_i2c_core_check_stale(hdw); |
1719 | hdw->tuner_updated = 0; | |
1720 | ||
1721 | if (!pvr2_hdw_dev_ok(hdw)) return; | |
1722 | ||
681c7399 | 1723 | pvr2_hdw_commit_setup(hdw); |
d855497e MI |
1724 | |
1725 | hdw->vid_stream = pvr2_stream_create(); | |
1726 | if (!pvr2_hdw_dev_ok(hdw)) return; | |
1727 | pvr2_trace(PVR2_TRACE_INIT, | |
1728 | "pvr2_hdw_setup: video stream is %p",hdw->vid_stream); | |
1729 | if (hdw->vid_stream) { | |
1730 | idx = get_default_error_tolerance(hdw); | |
1731 | if (idx) { | |
1732 | pvr2_trace(PVR2_TRACE_INIT, | |
1733 | "pvr2_hdw_setup: video stream %p" | |
1734 | " setting tolerance %u", | |
1735 | hdw->vid_stream,idx); | |
1736 | } | |
1737 | pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev, | |
1738 | PVR2_VID_ENDPOINT,idx); | |
1739 | } | |
1740 | ||
1741 | if (!pvr2_hdw_dev_ok(hdw)) return; | |
1742 | ||
d855497e | 1743 | hdw->flag_init_ok = !0; |
681c7399 MI |
1744 | |
1745 | pvr2_hdw_state_sched(hdw); | |
d855497e MI |
1746 | } |
1747 | ||
1748 | ||
681c7399 MI |
1749 | /* Set up the structure and attempt to put the device into a usable state. |
1750 | This can be a time-consuming operation, which is why it is not done | |
1751 | internally as part of the create() step. */ | |
1752 | static void pvr2_hdw_setup(struct pvr2_hdw *hdw) | |
d855497e MI |
1753 | { |
1754 | pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw); | |
681c7399 | 1755 | do { |
d855497e MI |
1756 | pvr2_hdw_setup_low(hdw); |
1757 | pvr2_trace(PVR2_TRACE_INIT, | |
1758 | "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d", | |
681c7399 | 1759 | hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok); |
d855497e | 1760 | if (pvr2_hdw_dev_ok(hdw)) { |
681c7399 | 1761 | if (hdw->flag_init_ok) { |
d855497e MI |
1762 | pvr2_trace( |
1763 | PVR2_TRACE_INFO, | |
1764 | "Device initialization" | |
1765 | " completed successfully."); | |
1766 | break; | |
1767 | } | |
1768 | if (hdw->fw1_state == FW1_STATE_RELOAD) { | |
1769 | pvr2_trace( | |
1770 | PVR2_TRACE_INFO, | |
1771 | "Device microcontroller firmware" | |
1772 | " (re)loaded; it should now reset" | |
1773 | " and reconnect."); | |
1774 | break; | |
1775 | } | |
1776 | pvr2_trace( | |
1777 | PVR2_TRACE_ERROR_LEGS, | |
1778 | "Device initialization was not successful."); | |
1779 | if (hdw->fw1_state == FW1_STATE_MISSING) { | |
1780 | pvr2_trace( | |
1781 | PVR2_TRACE_ERROR_LEGS, | |
1782 | "Giving up since device" | |
1783 | " microcontroller firmware" | |
1784 | " appears to be missing."); | |
1785 | break; | |
1786 | } | |
1787 | } | |
1788 | if (procreload) { | |
1789 | pvr2_trace( | |
1790 | PVR2_TRACE_ERROR_LEGS, | |
1791 | "Attempting pvrusb2 recovery by reloading" | |
1792 | " primary firmware."); | |
1793 | pvr2_trace( | |
1794 | PVR2_TRACE_ERROR_LEGS, | |
1795 | "If this works, device should disconnect" | |
1796 | " and reconnect in a sane state."); | |
1797 | hdw->fw1_state = FW1_STATE_UNKNOWN; | |
1798 | pvr2_upload_firmware1(hdw); | |
1799 | } else { | |
1800 | pvr2_trace( | |
1801 | PVR2_TRACE_ERROR_LEGS, | |
1802 | "***WARNING*** pvrusb2 device hardware" | |
1803 | " appears to be jammed" | |
1804 | " and I can't clear it."); | |
1805 | pvr2_trace( | |
1806 | PVR2_TRACE_ERROR_LEGS, | |
1807 | "You might need to power cycle" | |
1808 | " the pvrusb2 device" | |
1809 | " in order to recover."); | |
1810 | } | |
681c7399 | 1811 | } while (0); |
d855497e | 1812 | pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw); |
d855497e MI |
1813 | } |
1814 | ||
1815 | ||
1816 | /* Create and return a structure for interacting with the underlying | |
1817 | hardware */ | |
1818 | struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf, | |
1819 | const struct usb_device_id *devid) | |
1820 | { | |
7fb20fa3 | 1821 | unsigned int idx,cnt1,cnt2,m; |
d855497e | 1822 | struct pvr2_hdw *hdw; |
d855497e MI |
1823 | int valid_std_mask; |
1824 | struct pvr2_ctrl *cptr; | |
989eb154 | 1825 | const struct pvr2_device_desc *hdw_desc; |
d855497e | 1826 | __u8 ifnum; |
b30d2441 MI |
1827 | struct v4l2_queryctrl qctrl; |
1828 | struct pvr2_ctl_info *ciptr; | |
d855497e | 1829 | |
d130fa8a | 1830 | hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info); |
d855497e | 1831 | |
ca545f7c | 1832 | hdw = kzalloc(sizeof(*hdw),GFP_KERNEL); |
d855497e | 1833 | pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"", |
989eb154 | 1834 | hdw,hdw_desc->description); |
d855497e | 1835 | if (!hdw) goto fail; |
681c7399 MI |
1836 | |
1837 | init_timer(&hdw->quiescent_timer); | |
1838 | hdw->quiescent_timer.data = (unsigned long)hdw; | |
1839 | hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout; | |
1840 | ||
1841 | init_timer(&hdw->encoder_wait_timer); | |
1842 | hdw->encoder_wait_timer.data = (unsigned long)hdw; | |
1843 | hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout; | |
1844 | ||
1845 | hdw->master_state = PVR2_STATE_DEAD; | |
1846 | ||
1847 | init_waitqueue_head(&hdw->state_wait_data); | |
1848 | ||
18103c57 | 1849 | hdw->tuner_signal_stale = !0; |
b30d2441 | 1850 | cx2341x_fill_defaults(&hdw->enc_ctl_state); |
d855497e | 1851 | |
7fb20fa3 MI |
1852 | /* Calculate which inputs are OK */ |
1853 | m = 0; | |
1854 | if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV; | |
e8f5bacf MI |
1855 | if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) { |
1856 | m |= 1 << PVR2_CVAL_INPUT_DTV; | |
1857 | } | |
7fb20fa3 MI |
1858 | if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO; |
1859 | if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE; | |
1860 | if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO; | |
1861 | hdw->input_avail_mask = m; | |
1862 | ||
62433e31 MI |
1863 | /* If not a hybrid device, pathway_state never changes. So |
1864 | initialize it here to what it should forever be. */ | |
1865 | if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) { | |
1866 | hdw->pathway_state = PVR2_PATHWAY_ANALOG; | |
1867 | } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) { | |
1868 | hdw->pathway_state = PVR2_PATHWAY_DIGITAL; | |
1869 | } | |
1870 | ||
c05c0462 | 1871 | hdw->control_cnt = CTRLDEF_COUNT; |
b30d2441 | 1872 | hdw->control_cnt += MPEGDEF_COUNT; |
ca545f7c | 1873 | hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt, |
d855497e MI |
1874 | GFP_KERNEL); |
1875 | if (!hdw->controls) goto fail; | |
989eb154 | 1876 | hdw->hdw_desc = hdw_desc; |
c05c0462 MI |
1877 | for (idx = 0; idx < hdw->control_cnt; idx++) { |
1878 | cptr = hdw->controls + idx; | |
1879 | cptr->hdw = hdw; | |
1880 | } | |
d855497e MI |
1881 | for (idx = 0; idx < 32; idx++) { |
1882 | hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx]; | |
1883 | } | |
c05c0462 | 1884 | for (idx = 0; idx < CTRLDEF_COUNT; idx++) { |
d855497e | 1885 | cptr = hdw->controls + idx; |
d855497e MI |
1886 | cptr->info = control_defs+idx; |
1887 | } | |
dbc40a0e MI |
1888 | |
1889 | /* Ensure that default input choice is a valid one. */ | |
1890 | m = hdw->input_avail_mask; | |
1891 | if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) { | |
1892 | if (!((1 << idx) & m)) continue; | |
1893 | hdw->input_val = idx; | |
1894 | break; | |
1895 | } | |
1896 | ||
b30d2441 | 1897 | /* Define and configure additional controls from cx2341x module. */ |
ca545f7c | 1898 | hdw->mpeg_ctrl_info = kzalloc( |
b30d2441 MI |
1899 | sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL); |
1900 | if (!hdw->mpeg_ctrl_info) goto fail; | |
b30d2441 MI |
1901 | for (idx = 0; idx < MPEGDEF_COUNT; idx++) { |
1902 | cptr = hdw->controls + idx + CTRLDEF_COUNT; | |
1903 | ciptr = &(hdw->mpeg_ctrl_info[idx].info); | |
1904 | ciptr->desc = hdw->mpeg_ctrl_info[idx].desc; | |
1905 | ciptr->name = mpeg_ids[idx].strid; | |
1906 | ciptr->v4l_id = mpeg_ids[idx].id; | |
1907 | ciptr->skip_init = !0; | |
1908 | ciptr->get_value = ctrl_cx2341x_get; | |
1909 | ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags; | |
1910 | ciptr->is_dirty = ctrl_cx2341x_is_dirty; | |
1911 | if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty; | |
1912 | qctrl.id = ciptr->v4l_id; | |
1913 | cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl); | |
1914 | if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) { | |
1915 | ciptr->set_value = ctrl_cx2341x_set; | |
1916 | } | |
1917 | strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name, | |
1918 | PVR2_CTLD_INFO_DESC_SIZE); | |
1919 | hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0; | |
1920 | ciptr->default_value = qctrl.default_value; | |
1921 | switch (qctrl.type) { | |
1922 | default: | |
1923 | case V4L2_CTRL_TYPE_INTEGER: | |
1924 | ciptr->type = pvr2_ctl_int; | |
1925 | ciptr->def.type_int.min_value = qctrl.minimum; | |
1926 | ciptr->def.type_int.max_value = qctrl.maximum; | |
1927 | break; | |
1928 | case V4L2_CTRL_TYPE_BOOLEAN: | |
1929 | ciptr->type = pvr2_ctl_bool; | |
1930 | break; | |
1931 | case V4L2_CTRL_TYPE_MENU: | |
1932 | ciptr->type = pvr2_ctl_enum; | |
1933 | ciptr->def.type_enum.value_names = | |
1934 | cx2341x_ctrl_get_menu(ciptr->v4l_id); | |
1935 | for (cnt1 = 0; | |
1936 | ciptr->def.type_enum.value_names[cnt1] != NULL; | |
1937 | cnt1++) { } | |
1938 | ciptr->def.type_enum.count = cnt1; | |
1939 | break; | |
1940 | } | |
1941 | cptr->info = ciptr; | |
1942 | } | |
d855497e MI |
1943 | |
1944 | // Initialize video standard enum dynamic control | |
1945 | cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM); | |
1946 | if (cptr) { | |
1947 | memcpy(&hdw->std_info_enum,cptr->info, | |
1948 | sizeof(hdw->std_info_enum)); | |
1949 | cptr->info = &hdw->std_info_enum; | |
1950 | ||
1951 | } | |
1952 | // Initialize control data regarding video standard masks | |
1953 | valid_std_mask = pvr2_std_get_usable(); | |
1954 | for (idx = 0; idx < 32; idx++) { | |
1955 | if (!(valid_std_mask & (1 << idx))) continue; | |
1956 | cnt1 = pvr2_std_id_to_str( | |
1957 | hdw->std_mask_names[idx], | |
1958 | sizeof(hdw->std_mask_names[idx])-1, | |
1959 | 1 << idx); | |
1960 | hdw->std_mask_names[idx][cnt1] = 0; | |
1961 | } | |
1962 | cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL); | |
1963 | if (cptr) { | |
1964 | memcpy(&hdw->std_info_avail,cptr->info, | |
1965 | sizeof(hdw->std_info_avail)); | |
1966 | cptr->info = &hdw->std_info_avail; | |
1967 | hdw->std_info_avail.def.type_bitmask.bit_names = | |
1968 | hdw->std_mask_ptrs; | |
1969 | hdw->std_info_avail.def.type_bitmask.valid_bits = | |
1970 | valid_std_mask; | |
1971 | } | |
1972 | cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR); | |
1973 | if (cptr) { | |
1974 | memcpy(&hdw->std_info_cur,cptr->info, | |
1975 | sizeof(hdw->std_info_cur)); | |
1976 | cptr->info = &hdw->std_info_cur; | |
1977 | hdw->std_info_cur.def.type_bitmask.bit_names = | |
1978 | hdw->std_mask_ptrs; | |
1979 | hdw->std_info_avail.def.type_bitmask.valid_bits = | |
1980 | valid_std_mask; | |
1981 | } | |
1982 | ||
1983 | hdw->eeprom_addr = -1; | |
1984 | hdw->unit_number = -1; | |
8079384e MI |
1985 | hdw->v4l_minor_number_video = -1; |
1986 | hdw->v4l_minor_number_vbi = -1; | |
fd5a75fe | 1987 | hdw->v4l_minor_number_radio = -1; |
d855497e MI |
1988 | hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL); |
1989 | if (!hdw->ctl_write_buffer) goto fail; | |
1990 | hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL); | |
1991 | if (!hdw->ctl_read_buffer) goto fail; | |
1992 | hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL); | |
1993 | if (!hdw->ctl_write_urb) goto fail; | |
1994 | hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL); | |
1995 | if (!hdw->ctl_read_urb) goto fail; | |
1996 | ||
8df0c87c | 1997 | mutex_lock(&pvr2_unit_mtx); do { |
d855497e MI |
1998 | for (idx = 0; idx < PVR_NUM; idx++) { |
1999 | if (unit_pointers[idx]) continue; | |
2000 | hdw->unit_number = idx; | |
2001 | unit_pointers[idx] = hdw; | |
2002 | break; | |
2003 | } | |
8df0c87c | 2004 | } while (0); mutex_unlock(&pvr2_unit_mtx); |
d855497e MI |
2005 | |
2006 | cnt1 = 0; | |
2007 | cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2"); | |
2008 | cnt1 += cnt2; | |
2009 | if (hdw->unit_number >= 0) { | |
2010 | cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c", | |
2011 | ('a' + hdw->unit_number)); | |
2012 | cnt1 += cnt2; | |
2013 | } | |
2014 | if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1; | |
2015 | hdw->name[cnt1] = 0; | |
2016 | ||
681c7399 MI |
2017 | hdw->workqueue = create_singlethread_workqueue(hdw->name); |
2018 | INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll); | |
2019 | INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c); | |
2020 | INIT_WORK(&hdw->workinit,pvr2_hdw_worker_init); | |
2021 | ||
d855497e MI |
2022 | pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s", |
2023 | hdw->unit_number,hdw->name); | |
2024 | ||
2025 | hdw->tuner_type = -1; | |
2026 | hdw->flag_ok = !0; | |
d855497e MI |
2027 | |
2028 | hdw->usb_intf = intf; | |
2029 | hdw->usb_dev = interface_to_usbdev(intf); | |
2030 | ||
31a18547 MI |
2031 | scnprintf(hdw->bus_info,sizeof(hdw->bus_info), |
2032 | "usb %s address %d", | |
2033 | hdw->usb_dev->dev.bus_id, | |
2034 | hdw->usb_dev->devnum); | |
2035 | ||
d855497e MI |
2036 | ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber; |
2037 | usb_set_interface(hdw->usb_dev,ifnum,0); | |
2038 | ||
2039 | mutex_init(&hdw->ctl_lock_mutex); | |
2040 | mutex_init(&hdw->big_lock_mutex); | |
2041 | ||
681c7399 | 2042 | queue_work(hdw->workqueue,&hdw->workinit); |
d855497e MI |
2043 | return hdw; |
2044 | fail: | |
2045 | if (hdw) { | |
681c7399 MI |
2046 | del_timer_sync(&hdw->quiescent_timer); |
2047 | del_timer_sync(&hdw->encoder_wait_timer); | |
2048 | if (hdw->workqueue) { | |
2049 | flush_workqueue(hdw->workqueue); | |
2050 | destroy_workqueue(hdw->workqueue); | |
2051 | hdw->workqueue = NULL; | |
2052 | } | |
5e55d2ce MK |
2053 | usb_free_urb(hdw->ctl_read_urb); |
2054 | usb_free_urb(hdw->ctl_write_urb); | |
22071a42 MK |
2055 | kfree(hdw->ctl_read_buffer); |
2056 | kfree(hdw->ctl_write_buffer); | |
2057 | kfree(hdw->controls); | |
2058 | kfree(hdw->mpeg_ctrl_info); | |
681c7399 MI |
2059 | kfree(hdw->std_defs); |
2060 | kfree(hdw->std_enum_names); | |
d855497e MI |
2061 | kfree(hdw); |
2062 | } | |
a0fd1cb1 | 2063 | return NULL; |
d855497e MI |
2064 | } |
2065 | ||
2066 | ||
2067 | /* Remove _all_ associations between this driver and the underlying USB | |
2068 | layer. */ | |
07e337ee | 2069 | static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw) |
d855497e MI |
2070 | { |
2071 | if (hdw->flag_disconnected) return; | |
2072 | pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw); | |
2073 | if (hdw->ctl_read_urb) { | |
2074 | usb_kill_urb(hdw->ctl_read_urb); | |
2075 | usb_free_urb(hdw->ctl_read_urb); | |
a0fd1cb1 | 2076 | hdw->ctl_read_urb = NULL; |
d855497e MI |
2077 | } |
2078 | if (hdw->ctl_write_urb) { | |
2079 | usb_kill_urb(hdw->ctl_write_urb); | |
2080 | usb_free_urb(hdw->ctl_write_urb); | |
a0fd1cb1 | 2081 | hdw->ctl_write_urb = NULL; |
d855497e MI |
2082 | } |
2083 | if (hdw->ctl_read_buffer) { | |
2084 | kfree(hdw->ctl_read_buffer); | |
a0fd1cb1 | 2085 | hdw->ctl_read_buffer = NULL; |
d855497e MI |
2086 | } |
2087 | if (hdw->ctl_write_buffer) { | |
2088 | kfree(hdw->ctl_write_buffer); | |
a0fd1cb1 | 2089 | hdw->ctl_write_buffer = NULL; |
d855497e | 2090 | } |
d855497e | 2091 | hdw->flag_disconnected = !0; |
a0fd1cb1 MI |
2092 | hdw->usb_dev = NULL; |
2093 | hdw->usb_intf = NULL; | |
681c7399 | 2094 | pvr2_hdw_render_useless(hdw); |
d855497e MI |
2095 | } |
2096 | ||
2097 | ||
2098 | /* Destroy hardware interaction structure */ | |
2099 | void pvr2_hdw_destroy(struct pvr2_hdw *hdw) | |
2100 | { | |
401c27ce | 2101 | if (!hdw) return; |
d855497e | 2102 | pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw); |
681c7399 MI |
2103 | del_timer_sync(&hdw->quiescent_timer); |
2104 | del_timer_sync(&hdw->encoder_wait_timer); | |
2105 | if (hdw->workqueue) { | |
2106 | flush_workqueue(hdw->workqueue); | |
2107 | destroy_workqueue(hdw->workqueue); | |
2108 | hdw->workqueue = NULL; | |
2109 | } | |
d855497e MI |
2110 | if (hdw->fw_buffer) { |
2111 | kfree(hdw->fw_buffer); | |
a0fd1cb1 | 2112 | hdw->fw_buffer = NULL; |
d855497e MI |
2113 | } |
2114 | if (hdw->vid_stream) { | |
2115 | pvr2_stream_destroy(hdw->vid_stream); | |
a0fd1cb1 | 2116 | hdw->vid_stream = NULL; |
d855497e | 2117 | } |
d855497e MI |
2118 | if (hdw->decoder_ctrl) { |
2119 | hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt); | |
2120 | } | |
2121 | pvr2_i2c_core_done(hdw); | |
2122 | pvr2_hdw_remove_usb_stuff(hdw); | |
8df0c87c | 2123 | mutex_lock(&pvr2_unit_mtx); do { |
d855497e MI |
2124 | if ((hdw->unit_number >= 0) && |
2125 | (hdw->unit_number < PVR_NUM) && | |
2126 | (unit_pointers[hdw->unit_number] == hdw)) { | |
a0fd1cb1 | 2127 | unit_pointers[hdw->unit_number] = NULL; |
d855497e | 2128 | } |
8df0c87c | 2129 | } while (0); mutex_unlock(&pvr2_unit_mtx); |
22071a42 MK |
2130 | kfree(hdw->controls); |
2131 | kfree(hdw->mpeg_ctrl_info); | |
2132 | kfree(hdw->std_defs); | |
2133 | kfree(hdw->std_enum_names); | |
d855497e MI |
2134 | kfree(hdw); |
2135 | } | |
2136 | ||
2137 | ||
d855497e MI |
2138 | int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw) |
2139 | { | |
2140 | return (hdw && hdw->flag_ok); | |
2141 | } | |
2142 | ||
2143 | ||
2144 | /* Called when hardware has been unplugged */ | |
2145 | void pvr2_hdw_disconnect(struct pvr2_hdw *hdw) | |
2146 | { | |
2147 | pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw); | |
2148 | LOCK_TAKE(hdw->big_lock); | |
2149 | LOCK_TAKE(hdw->ctl_lock); | |
2150 | pvr2_hdw_remove_usb_stuff(hdw); | |
2151 | LOCK_GIVE(hdw->ctl_lock); | |
2152 | LOCK_GIVE(hdw->big_lock); | |
2153 | } | |
2154 | ||
2155 | ||
2156 | // Attempt to autoselect an appropriate value for std_enum_cur given | |
2157 | // whatever is currently in std_mask_cur | |
07e337ee | 2158 | static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw) |
d855497e MI |
2159 | { |
2160 | unsigned int idx; | |
2161 | for (idx = 1; idx < hdw->std_enum_cnt; idx++) { | |
2162 | if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) { | |
2163 | hdw->std_enum_cur = idx; | |
2164 | return; | |
2165 | } | |
2166 | } | |
2167 | hdw->std_enum_cur = 0; | |
2168 | } | |
2169 | ||
2170 | ||
2171 | // Calculate correct set of enumerated standards based on currently known | |
2172 | // set of available standards bits. | |
07e337ee | 2173 | static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw) |
d855497e MI |
2174 | { |
2175 | struct v4l2_standard *newstd; | |
2176 | unsigned int std_cnt; | |
2177 | unsigned int idx; | |
2178 | ||
2179 | newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail); | |
2180 | ||
2181 | if (hdw->std_defs) { | |
2182 | kfree(hdw->std_defs); | |
a0fd1cb1 | 2183 | hdw->std_defs = NULL; |
d855497e MI |
2184 | } |
2185 | hdw->std_enum_cnt = 0; | |
2186 | if (hdw->std_enum_names) { | |
2187 | kfree(hdw->std_enum_names); | |
a0fd1cb1 | 2188 | hdw->std_enum_names = NULL; |
d855497e MI |
2189 | } |
2190 | ||
2191 | if (!std_cnt) { | |
2192 | pvr2_trace( | |
2193 | PVR2_TRACE_ERROR_LEGS, | |
2194 | "WARNING: Failed to identify any viable standards"); | |
2195 | } | |
2196 | hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL); | |
2197 | hdw->std_enum_names[0] = "none"; | |
2198 | for (idx = 0; idx < std_cnt; idx++) { | |
2199 | hdw->std_enum_names[idx+1] = | |
2200 | newstd[idx].name; | |
2201 | } | |
2202 | // Set up the dynamic control for this standard | |
2203 | hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names; | |
2204 | hdw->std_info_enum.def.type_enum.count = std_cnt+1; | |
2205 | hdw->std_defs = newstd; | |
2206 | hdw->std_enum_cnt = std_cnt+1; | |
2207 | hdw->std_enum_cur = 0; | |
2208 | hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail; | |
2209 | } | |
2210 | ||
2211 | ||
2212 | int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw, | |
2213 | struct v4l2_standard *std, | |
2214 | unsigned int idx) | |
2215 | { | |
2216 | int ret = -EINVAL; | |
2217 | if (!idx) return ret; | |
2218 | LOCK_TAKE(hdw->big_lock); do { | |
2219 | if (idx >= hdw->std_enum_cnt) break; | |
2220 | idx--; | |
2221 | memcpy(std,hdw->std_defs+idx,sizeof(*std)); | |
2222 | ret = 0; | |
2223 | } while (0); LOCK_GIVE(hdw->big_lock); | |
2224 | return ret; | |
2225 | } | |
2226 | ||
2227 | ||
2228 | /* Get the number of defined controls */ | |
2229 | unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw) | |
2230 | { | |
c05c0462 | 2231 | return hdw->control_cnt; |
d855497e MI |
2232 | } |
2233 | ||
2234 | ||
2235 | /* Retrieve a control handle given its index (0..count-1) */ | |
2236 | struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw, | |
2237 | unsigned int idx) | |
2238 | { | |
a0fd1cb1 | 2239 | if (idx >= hdw->control_cnt) return NULL; |
d855497e MI |
2240 | return hdw->controls + idx; |
2241 | } | |
2242 | ||
2243 | ||
2244 | /* Retrieve a control handle given its index (0..count-1) */ | |
2245 | struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw, | |
2246 | unsigned int ctl_id) | |
2247 | { | |
2248 | struct pvr2_ctrl *cptr; | |
2249 | unsigned int idx; | |
2250 | int i; | |
2251 | ||
2252 | /* This could be made a lot more efficient, but for now... */ | |
c05c0462 | 2253 | for (idx = 0; idx < hdw->control_cnt; idx++) { |
d855497e MI |
2254 | cptr = hdw->controls + idx; |
2255 | i = cptr->info->internal_id; | |
2256 | if (i && (i == ctl_id)) return cptr; | |
2257 | } | |
a0fd1cb1 | 2258 | return NULL; |
d855497e MI |
2259 | } |
2260 | ||
2261 | ||
a761f431 | 2262 | /* Given a V4L ID, retrieve the control structure associated with it. */ |
d855497e MI |
2263 | struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id) |
2264 | { | |
2265 | struct pvr2_ctrl *cptr; | |
2266 | unsigned int idx; | |
2267 | int i; | |
2268 | ||
2269 | /* This could be made a lot more efficient, but for now... */ | |
c05c0462 | 2270 | for (idx = 0; idx < hdw->control_cnt; idx++) { |
d855497e MI |
2271 | cptr = hdw->controls + idx; |
2272 | i = cptr->info->v4l_id; | |
2273 | if (i && (i == ctl_id)) return cptr; | |
2274 | } | |
a0fd1cb1 | 2275 | return NULL; |
d855497e MI |
2276 | } |
2277 | ||
2278 | ||
a761f431 MI |
2279 | /* Given a V4L ID for its immediate predecessor, retrieve the control |
2280 | structure associated with it. */ | |
2281 | struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw, | |
2282 | unsigned int ctl_id) | |
2283 | { | |
2284 | struct pvr2_ctrl *cptr,*cp2; | |
2285 | unsigned int idx; | |
2286 | int i; | |
2287 | ||
2288 | /* This could be made a lot more efficient, but for now... */ | |
a0fd1cb1 | 2289 | cp2 = NULL; |
a761f431 MI |
2290 | for (idx = 0; idx < hdw->control_cnt; idx++) { |
2291 | cptr = hdw->controls + idx; | |
2292 | i = cptr->info->v4l_id; | |
2293 | if (!i) continue; | |
2294 | if (i <= ctl_id) continue; | |
2295 | if (cp2 && (cp2->info->v4l_id < i)) continue; | |
2296 | cp2 = cptr; | |
2297 | } | |
2298 | return cp2; | |
a0fd1cb1 | 2299 | return NULL; |
a761f431 MI |
2300 | } |
2301 | ||
2302 | ||
d855497e MI |
2303 | static const char *get_ctrl_typename(enum pvr2_ctl_type tp) |
2304 | { | |
2305 | switch (tp) { | |
2306 | case pvr2_ctl_int: return "integer"; | |
2307 | case pvr2_ctl_enum: return "enum"; | |
33213963 | 2308 | case pvr2_ctl_bool: return "boolean"; |
d855497e MI |
2309 | case pvr2_ctl_bitmask: return "bitmask"; |
2310 | } | |
2311 | return ""; | |
2312 | } | |
2313 | ||
2314 | ||
681c7399 MI |
2315 | /* Figure out if we need to commit control changes. If so, mark internal |
2316 | state flags to indicate this fact and return true. Otherwise do nothing | |
2317 | else and return false. */ | |
2318 | static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw) | |
d855497e | 2319 | { |
d855497e MI |
2320 | unsigned int idx; |
2321 | struct pvr2_ctrl *cptr; | |
2322 | int value; | |
2323 | int commit_flag = 0; | |
2324 | char buf[100]; | |
2325 | unsigned int bcnt,ccnt; | |
2326 | ||
c05c0462 | 2327 | for (idx = 0; idx < hdw->control_cnt; idx++) { |
d855497e | 2328 | cptr = hdw->controls + idx; |
5fa1247a | 2329 | if (!cptr->info->is_dirty) continue; |
d855497e | 2330 | if (!cptr->info->is_dirty(cptr)) continue; |
fe23a280 | 2331 | commit_flag = !0; |
d855497e | 2332 | |
fe23a280 | 2333 | if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue; |
d855497e MI |
2334 | bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ", |
2335 | cptr->info->name); | |
2336 | value = 0; | |
2337 | cptr->info->get_value(cptr,&value); | |
2338 | pvr2_ctrl_value_to_sym_internal(cptr,~0,value, | |
2339 | buf+bcnt, | |
2340 | sizeof(buf)-bcnt,&ccnt); | |
2341 | bcnt += ccnt; | |
2342 | bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>", | |
2343 | get_ctrl_typename(cptr->info->type)); | |
2344 | pvr2_trace(PVR2_TRACE_CTL, | |
2345 | "/*--TRACE_COMMIT--*/ %.*s", | |
2346 | bcnt,buf); | |
2347 | } | |
2348 | ||
2349 | if (!commit_flag) { | |
2350 | /* Nothing has changed */ | |
2351 | return 0; | |
2352 | } | |
2353 | ||
681c7399 MI |
2354 | hdw->state_pipeline_config = 0; |
2355 | trace_stbit("state_pipeline_config",hdw->state_pipeline_config); | |
2356 | pvr2_hdw_state_sched(hdw); | |
2357 | ||
2358 | return !0; | |
2359 | } | |
2360 | ||
2361 | ||
2362 | /* Perform all operations needed to commit all control changes. This must | |
2363 | be performed in synchronization with the pipeline state and is thus | |
2364 | expected to be called as part of the driver's worker thread. Return | |
2365 | true if commit successful, otherwise return false to indicate that | |
2366 | commit isn't possible at this time. */ | |
2367 | static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw) | |
2368 | { | |
2369 | unsigned int idx; | |
2370 | struct pvr2_ctrl *cptr; | |
2371 | int disruptive_change; | |
2372 | ||
d855497e MI |
2373 | /* When video standard changes, reset the hres and vres values - |
2374 | but if the user has pending changes there, then let the changes | |
2375 | take priority. */ | |
2376 | if (hdw->std_dirty) { | |
2377 | /* Rewrite the vertical resolution to be appropriate to the | |
2378 | video standard that has been selected. */ | |
2379 | int nvres; | |
2380 | if (hdw->std_mask_cur & V4L2_STD_525_60) { | |
2381 | nvres = 480; | |
2382 | } else { | |
2383 | nvres = 576; | |
2384 | } | |
2385 | if (nvres != hdw->res_ver_val) { | |
2386 | hdw->res_ver_val = nvres; | |
2387 | hdw->res_ver_dirty = !0; | |
2388 | } | |
d855497e MI |
2389 | } |
2390 | ||
62433e31 MI |
2391 | if (hdw->input_dirty && |
2392 | (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ? | |
2393 | PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) != | |
2394 | hdw->pathway_state)) { | |
2395 | /* Change of mode being asked for... */ | |
2396 | hdw->state_pathway_ok = 0; | |
e9db1ff2 | 2397 | trace_stbit("state_pathway_ok",hdw->state_pathway_ok); |
62433e31 MI |
2398 | } |
2399 | if (!hdw->state_pathway_ok) { | |
2400 | /* Can't commit anything until pathway is ok. */ | |
2401 | return 0; | |
2402 | } | |
681c7399 MI |
2403 | /* If any of the below has changed, then we can't do the update |
2404 | while the pipeline is running. Pipeline must be paused first | |
2405 | and decoder -> encoder connection be made quiescent before we | |
2406 | can proceed. */ | |
2407 | disruptive_change = | |
2408 | (hdw->std_dirty || | |
2409 | hdw->enc_unsafe_stale || | |
2410 | hdw->srate_dirty || | |
2411 | hdw->res_ver_dirty || | |
2412 | hdw->res_hor_dirty || | |
2413 | hdw->input_dirty || | |
2414 | (hdw->active_stream_type != hdw->desired_stream_type)); | |
2415 | if (disruptive_change && !hdw->state_pipeline_idle) { | |
2416 | /* Pipeline is not idle; we can't proceed. Arrange to | |
2417 | cause pipeline to stop so that we can try this again | |
2418 | later.... */ | |
2419 | hdw->state_pipeline_pause = !0; | |
2420 | return 0; | |
275b2e28 PK |
2421 | } |
2422 | ||
b30d2441 MI |
2423 | if (hdw->srate_dirty) { |
2424 | /* Write new sample rate into control structure since | |
2425 | * the master copy is stale. We must track srate | |
2426 | * separate from the mpeg control structure because | |
2427 | * other logic also uses this value. */ | |
2428 | struct v4l2_ext_controls cs; | |
2429 | struct v4l2_ext_control c1; | |
2430 | memset(&cs,0,sizeof(cs)); | |
2431 | memset(&c1,0,sizeof(c1)); | |
2432 | cs.controls = &c1; | |
2433 | cs.count = 1; | |
2434 | c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ; | |
2435 | c1.value = hdw->srate_val; | |
01f1e44f | 2436 | cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS); |
b30d2441 | 2437 | } |
c05c0462 | 2438 | |
d855497e MI |
2439 | /* Scan i2c core at this point - before we clear all the dirty |
2440 | bits. Various parts of the i2c core will notice dirty bits as | |
2441 | appropriate and arrange to broadcast or directly send updates to | |
2442 | the client drivers in order to keep everything in sync */ | |
2443 | pvr2_i2c_core_check_stale(hdw); | |
2444 | ||
c05c0462 | 2445 | for (idx = 0; idx < hdw->control_cnt; idx++) { |
d855497e MI |
2446 | cptr = hdw->controls + idx; |
2447 | if (!cptr->info->clear_dirty) continue; | |
2448 | cptr->info->clear_dirty(cptr); | |
2449 | } | |
2450 | ||
681c7399 MI |
2451 | if (hdw->active_stream_type != hdw->desired_stream_type) { |
2452 | /* Handle any side effects of stream config here */ | |
2453 | hdw->active_stream_type = hdw->desired_stream_type; | |
2454 | } | |
2455 | ||
d855497e MI |
2456 | /* Now execute i2c core update */ |
2457 | pvr2_i2c_core_sync(hdw); | |
2458 | ||
62433e31 MI |
2459 | if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) && |
2460 | hdw->state_encoder_run) { | |
2461 | /* If encoder isn't running or it can't be touched, then | |
2462 | this will get worked out later when we start the | |
2463 | encoder. */ | |
681c7399 MI |
2464 | if (pvr2_encoder_adjust(hdw) < 0) return !0; |
2465 | } | |
d855497e | 2466 | |
681c7399 MI |
2467 | hdw->state_pipeline_config = !0; |
2468 | trace_stbit("state_pipeline_config",hdw->state_pipeline_config); | |
2469 | return !0; | |
d855497e MI |
2470 | } |
2471 | ||
2472 | ||
2473 | int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw) | |
2474 | { | |
681c7399 MI |
2475 | int fl; |
2476 | LOCK_TAKE(hdw->big_lock); | |
2477 | fl = pvr2_hdw_commit_setup(hdw); | |
2478 | LOCK_GIVE(hdw->big_lock); | |
2479 | if (!fl) return 0; | |
2480 | return pvr2_hdw_wait(hdw,0); | |
2481 | } | |
2482 | ||
2483 | ||
2484 | static void pvr2_hdw_worker_i2c(struct work_struct *work) | |
2485 | { | |
2486 | struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync); | |
d855497e | 2487 | LOCK_TAKE(hdw->big_lock); do { |
681c7399 | 2488 | pvr2_i2c_core_sync(hdw); |
d855497e | 2489 | } while (0); LOCK_GIVE(hdw->big_lock); |
d855497e MI |
2490 | } |
2491 | ||
2492 | ||
681c7399 | 2493 | static void pvr2_hdw_worker_poll(struct work_struct *work) |
d855497e | 2494 | { |
681c7399 MI |
2495 | int fl = 0; |
2496 | struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll); | |
d855497e | 2497 | LOCK_TAKE(hdw->big_lock); do { |
681c7399 | 2498 | fl = pvr2_hdw_state_eval(hdw); |
d855497e | 2499 | } while (0); LOCK_GIVE(hdw->big_lock); |
681c7399 MI |
2500 | if (fl && hdw->state_func) { |
2501 | hdw->state_func(hdw->state_data); | |
2502 | } | |
d855497e MI |
2503 | } |
2504 | ||
2505 | ||
681c7399 | 2506 | static void pvr2_hdw_worker_init(struct work_struct *work) |
d855497e | 2507 | { |
681c7399 | 2508 | struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workinit); |
d855497e | 2509 | LOCK_TAKE(hdw->big_lock); do { |
681c7399 | 2510 | pvr2_hdw_setup(hdw); |
d855497e MI |
2511 | } while (0); LOCK_GIVE(hdw->big_lock); |
2512 | } | |
2513 | ||
2514 | ||
681c7399 | 2515 | static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state) |
d855497e | 2516 | { |
681c7399 MI |
2517 | return wait_event_interruptible( |
2518 | hdw->state_wait_data, | |
2519 | (hdw->state_stale == 0) && | |
2520 | (!state || (hdw->master_state != state))); | |
2521 | } | |
2522 | ||
2523 | ||
2524 | void pvr2_hdw_set_state_callback(struct pvr2_hdw *hdw, | |
2525 | void (*callback_func)(void *), | |
2526 | void *callback_data) | |
2527 | { | |
2528 | LOCK_TAKE(hdw->big_lock); do { | |
2529 | hdw->state_data = callback_data; | |
2530 | hdw->state_func = callback_func; | |
2531 | } while (0); LOCK_GIVE(hdw->big_lock); | |
d855497e MI |
2532 | } |
2533 | ||
681c7399 | 2534 | |
d855497e MI |
2535 | /* Return name for this driver instance */ |
2536 | const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw) | |
2537 | { | |
2538 | return hdw->name; | |
2539 | } | |
2540 | ||
2541 | ||
78a47101 MI |
2542 | const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw) |
2543 | { | |
2544 | return hdw->hdw_desc->description; | |
2545 | } | |
2546 | ||
2547 | ||
2548 | const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw) | |
2549 | { | |
2550 | return hdw->hdw_desc->shortname; | |
2551 | } | |
2552 | ||
2553 | ||
d855497e MI |
2554 | int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw) |
2555 | { | |
2556 | int result; | |
2557 | LOCK_TAKE(hdw->ctl_lock); do { | |
8d364363 | 2558 | hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED; |
d855497e MI |
2559 | result = pvr2_send_request(hdw, |
2560 | hdw->cmd_buffer,1, | |
2561 | hdw->cmd_buffer,1); | |
2562 | if (result < 0) break; | |
2563 | result = (hdw->cmd_buffer[0] != 0); | |
2564 | } while(0); LOCK_GIVE(hdw->ctl_lock); | |
2565 | return result; | |
2566 | } | |
2567 | ||
2568 | ||
18103c57 MI |
2569 | /* Execute poll of tuner status */ |
2570 | void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw) | |
d855497e | 2571 | { |
d855497e | 2572 | LOCK_TAKE(hdw->big_lock); do { |
18103c57 | 2573 | pvr2_i2c_core_status_poll(hdw); |
d855497e | 2574 | } while (0); LOCK_GIVE(hdw->big_lock); |
18103c57 MI |
2575 | } |
2576 | ||
2577 | ||
2578 | /* Return information about the tuner */ | |
2579 | int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp) | |
2580 | { | |
2581 | LOCK_TAKE(hdw->big_lock); do { | |
2582 | if (hdw->tuner_signal_stale) { | |
2583 | pvr2_i2c_core_status_poll(hdw); | |
2584 | } | |
2585 | memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner)); | |
2586 | } while (0); LOCK_GIVE(hdw->big_lock); | |
2587 | return 0; | |
d855497e MI |
2588 | } |
2589 | ||
2590 | ||
2591 | /* Get handle to video output stream */ | |
2592 | struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp) | |
2593 | { | |
2594 | return hp->vid_stream; | |
2595 | } | |
2596 | ||
2597 | ||
2598 | void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw) | |
2599 | { | |
4f1a3e5b | 2600 | int nr = pvr2_hdw_get_unit_number(hdw); |
d855497e MI |
2601 | LOCK_TAKE(hdw->big_lock); do { |
2602 | hdw->log_requested = !0; | |
4f1a3e5b | 2603 | printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr); |
d855497e MI |
2604 | pvr2_i2c_core_check_stale(hdw); |
2605 | hdw->log_requested = 0; | |
2606 | pvr2_i2c_core_sync(hdw); | |
b30d2441 | 2607 | pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:"); |
99eb44fe | 2608 | cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2"); |
681c7399 | 2609 | pvr2_hdw_state_log_state(hdw); |
4f1a3e5b | 2610 | printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr); |
d855497e MI |
2611 | } while (0); LOCK_GIVE(hdw->big_lock); |
2612 | } | |
2613 | ||
4db666cc MI |
2614 | |
2615 | /* Grab EEPROM contents, needed for direct method. */ | |
2616 | #define EEPROM_SIZE 8192 | |
2617 | #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__) | |
2618 | static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw) | |
2619 | { | |
2620 | struct i2c_msg msg[2]; | |
2621 | u8 *eeprom; | |
2622 | u8 iadd[2]; | |
2623 | u8 addr; | |
2624 | u16 eepromSize; | |
2625 | unsigned int offs; | |
2626 | int ret; | |
2627 | int mode16 = 0; | |
2628 | unsigned pcnt,tcnt; | |
2629 | eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL); | |
2630 | if (!eeprom) { | |
2631 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
2632 | "Failed to allocate memory" | |
2633 | " required to read eeprom"); | |
2634 | return NULL; | |
2635 | } | |
2636 | ||
2637 | trace_eeprom("Value for eeprom addr from controller was 0x%x", | |
2638 | hdw->eeprom_addr); | |
2639 | addr = hdw->eeprom_addr; | |
2640 | /* Seems that if the high bit is set, then the *real* eeprom | |
2641 | address is shifted right now bit position (noticed this in | |
2642 | newer PVR USB2 hardware) */ | |
2643 | if (addr & 0x80) addr >>= 1; | |
2644 | ||
2645 | /* FX2 documentation states that a 16bit-addressed eeprom is | |
2646 | expected if the I2C address is an odd number (yeah, this is | |
2647 | strange but it's what they do) */ | |
2648 | mode16 = (addr & 1); | |
2649 | eepromSize = (mode16 ? EEPROM_SIZE : 256); | |
2650 | trace_eeprom("Examining %d byte eeprom at location 0x%x" | |
2651 | " using %d bit addressing",eepromSize,addr, | |
2652 | mode16 ? 16 : 8); | |
2653 | ||
2654 | msg[0].addr = addr; | |
2655 | msg[0].flags = 0; | |
2656 | msg[0].len = mode16 ? 2 : 1; | |
2657 | msg[0].buf = iadd; | |
2658 | msg[1].addr = addr; | |
2659 | msg[1].flags = I2C_M_RD; | |
2660 | ||
2661 | /* We have to do the actual eeprom data fetch ourselves, because | |
2662 | (1) we're only fetching part of the eeprom, and (2) if we were | |
2663 | getting the whole thing our I2C driver can't grab it in one | |
2664 | pass - which is what tveeprom is otherwise going to attempt */ | |
2665 | memset(eeprom,0,EEPROM_SIZE); | |
2666 | for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) { | |
2667 | pcnt = 16; | |
2668 | if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt; | |
2669 | offs = tcnt + (eepromSize - EEPROM_SIZE); | |
2670 | if (mode16) { | |
2671 | iadd[0] = offs >> 8; | |
2672 | iadd[1] = offs; | |
2673 | } else { | |
2674 | iadd[0] = offs; | |
2675 | } | |
2676 | msg[1].len = pcnt; | |
2677 | msg[1].buf = eeprom+tcnt; | |
2678 | if ((ret = i2c_transfer(&hdw->i2c_adap, | |
2679 | msg,ARRAY_SIZE(msg))) != 2) { | |
2680 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
2681 | "eeprom fetch set offs err=%d",ret); | |
2682 | kfree(eeprom); | |
2683 | return NULL; | |
2684 | } | |
2685 | } | |
2686 | return eeprom; | |
2687 | } | |
2688 | ||
2689 | ||
2690 | void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw, | |
2691 | int prom_flag, | |
2692 | int enable_flag) | |
d855497e MI |
2693 | { |
2694 | int ret; | |
2695 | u16 address; | |
2696 | unsigned int pipe; | |
2697 | LOCK_TAKE(hdw->big_lock); do { | |
5fa1247a | 2698 | if ((hdw->fw_buffer == NULL) == !enable_flag) break; |
d855497e MI |
2699 | |
2700 | if (!enable_flag) { | |
2701 | pvr2_trace(PVR2_TRACE_FIRMWARE, | |
2702 | "Cleaning up after CPU firmware fetch"); | |
2703 | kfree(hdw->fw_buffer); | |
a0fd1cb1 | 2704 | hdw->fw_buffer = NULL; |
d855497e | 2705 | hdw->fw_size = 0; |
4db666cc MI |
2706 | if (hdw->fw_cpu_flag) { |
2707 | /* Now release the CPU. It will disconnect | |
2708 | and reconnect later. */ | |
2709 | pvr2_hdw_cpureset_assert(hdw,0); | |
2710 | } | |
d855497e MI |
2711 | break; |
2712 | } | |
2713 | ||
4db666cc MI |
2714 | hdw->fw_cpu_flag = (prom_flag == 0); |
2715 | if (hdw->fw_cpu_flag) { | |
2716 | pvr2_trace(PVR2_TRACE_FIRMWARE, | |
2717 | "Preparing to suck out CPU firmware"); | |
2718 | hdw->fw_size = 0x2000; | |
2719 | hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL); | |
2720 | if (!hdw->fw_buffer) { | |
2721 | hdw->fw_size = 0; | |
2722 | break; | |
2723 | } | |
d855497e | 2724 | |
4db666cc MI |
2725 | /* We have to hold the CPU during firmware upload. */ |
2726 | pvr2_hdw_cpureset_assert(hdw,1); | |
d855497e | 2727 | |
4db666cc MI |
2728 | /* download the firmware from address 0000-1fff in 2048 |
2729 | (=0x800) bytes chunk. */ | |
d855497e | 2730 | |
4db666cc MI |
2731 | pvr2_trace(PVR2_TRACE_FIRMWARE, |
2732 | "Grabbing CPU firmware"); | |
2733 | pipe = usb_rcvctrlpipe(hdw->usb_dev, 0); | |
2734 | for(address = 0; address < hdw->fw_size; | |
2735 | address += 0x800) { | |
2736 | ret = usb_control_msg(hdw->usb_dev,pipe, | |
2737 | 0xa0,0xc0, | |
2738 | address,0, | |
2739 | hdw->fw_buffer+address, | |
2740 | 0x800,HZ); | |
2741 | if (ret < 0) break; | |
2742 | } | |
d855497e | 2743 | |
4db666cc MI |
2744 | pvr2_trace(PVR2_TRACE_FIRMWARE, |
2745 | "Done grabbing CPU firmware"); | |
2746 | } else { | |
2747 | pvr2_trace(PVR2_TRACE_FIRMWARE, | |
2748 | "Sucking down EEPROM contents"); | |
2749 | hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw); | |
2750 | if (!hdw->fw_buffer) { | |
2751 | pvr2_trace(PVR2_TRACE_FIRMWARE, | |
2752 | "EEPROM content suck failed."); | |
2753 | break; | |
2754 | } | |
2755 | hdw->fw_size = EEPROM_SIZE; | |
2756 | pvr2_trace(PVR2_TRACE_FIRMWARE, | |
2757 | "Done sucking down EEPROM contents"); | |
2758 | } | |
d855497e MI |
2759 | |
2760 | } while (0); LOCK_GIVE(hdw->big_lock); | |
2761 | } | |
2762 | ||
2763 | ||
2764 | /* Return true if we're in a mode for retrieval CPU firmware */ | |
2765 | int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw) | |
2766 | { | |
5fa1247a | 2767 | return hdw->fw_buffer != NULL; |
d855497e MI |
2768 | } |
2769 | ||
2770 | ||
2771 | int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs, | |
2772 | char *buf,unsigned int cnt) | |
2773 | { | |
2774 | int ret = -EINVAL; | |
2775 | LOCK_TAKE(hdw->big_lock); do { | |
2776 | if (!buf) break; | |
2777 | if (!cnt) break; | |
2778 | ||
2779 | if (!hdw->fw_buffer) { | |
2780 | ret = -EIO; | |
2781 | break; | |
2782 | } | |
2783 | ||
2784 | if (offs >= hdw->fw_size) { | |
2785 | pvr2_trace(PVR2_TRACE_FIRMWARE, | |
2786 | "Read firmware data offs=%d EOF", | |
2787 | offs); | |
2788 | ret = 0; | |
2789 | break; | |
2790 | } | |
2791 | ||
2792 | if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs; | |
2793 | ||
2794 | memcpy(buf,hdw->fw_buffer+offs,cnt); | |
2795 | ||
2796 | pvr2_trace(PVR2_TRACE_FIRMWARE, | |
2797 | "Read firmware data offs=%d cnt=%d", | |
2798 | offs,cnt); | |
2799 | ret = cnt; | |
2800 | } while (0); LOCK_GIVE(hdw->big_lock); | |
2801 | ||
2802 | return ret; | |
2803 | } | |
2804 | ||
2805 | ||
fd5a75fe | 2806 | int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw, |
8079384e | 2807 | enum pvr2_v4l_type index) |
d855497e | 2808 | { |
fd5a75fe | 2809 | switch (index) { |
8079384e MI |
2810 | case pvr2_v4l_type_video: return hdw->v4l_minor_number_video; |
2811 | case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi; | |
2812 | case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio; | |
fd5a75fe MI |
2813 | default: return -1; |
2814 | } | |
d855497e MI |
2815 | } |
2816 | ||
2817 | ||
2fdf3d9c | 2818 | /* Store a v4l minor device number */ |
fd5a75fe | 2819 | void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw, |
8079384e | 2820 | enum pvr2_v4l_type index,int v) |
d855497e | 2821 | { |
fd5a75fe | 2822 | switch (index) { |
8079384e MI |
2823 | case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v; |
2824 | case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v; | |
2825 | case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v; | |
fd5a75fe MI |
2826 | default: break; |
2827 | } | |
d855497e MI |
2828 | } |
2829 | ||
2830 | ||
7d12e780 | 2831 | static void pvr2_ctl_write_complete(struct urb *urb) |
d855497e MI |
2832 | { |
2833 | struct pvr2_hdw *hdw = urb->context; | |
2834 | hdw->ctl_write_pend_flag = 0; | |
2835 | if (hdw->ctl_read_pend_flag) return; | |
2836 | complete(&hdw->ctl_done); | |
2837 | } | |
2838 | ||
2839 | ||
7d12e780 | 2840 | static void pvr2_ctl_read_complete(struct urb *urb) |
d855497e MI |
2841 | { |
2842 | struct pvr2_hdw *hdw = urb->context; | |
2843 | hdw->ctl_read_pend_flag = 0; | |
2844 | if (hdw->ctl_write_pend_flag) return; | |
2845 | complete(&hdw->ctl_done); | |
2846 | } | |
2847 | ||
2848 | ||
2849 | static void pvr2_ctl_timeout(unsigned long data) | |
2850 | { | |
2851 | struct pvr2_hdw *hdw = (struct pvr2_hdw *)data; | |
2852 | if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) { | |
2853 | hdw->ctl_timeout_flag = !0; | |
5e55d2ce | 2854 | if (hdw->ctl_write_pend_flag) |
d855497e | 2855 | usb_unlink_urb(hdw->ctl_write_urb); |
5e55d2ce | 2856 | if (hdw->ctl_read_pend_flag) |
d855497e | 2857 | usb_unlink_urb(hdw->ctl_read_urb); |
d855497e MI |
2858 | } |
2859 | } | |
2860 | ||
2861 | ||
e61b6fc5 MI |
2862 | /* Issue a command and get a response from the device. This extended |
2863 | version includes a probe flag (which if set means that device errors | |
2864 | should not be logged or treated as fatal) and a timeout in jiffies. | |
2865 | This can be used to non-lethally probe the health of endpoint 1. */ | |
07e337ee AB |
2866 | static int pvr2_send_request_ex(struct pvr2_hdw *hdw, |
2867 | unsigned int timeout,int probe_fl, | |
2868 | void *write_data,unsigned int write_len, | |
2869 | void *read_data,unsigned int read_len) | |
d855497e MI |
2870 | { |
2871 | unsigned int idx; | |
2872 | int status = 0; | |
2873 | struct timer_list timer; | |
2874 | if (!hdw->ctl_lock_held) { | |
2875 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
2876 | "Attempted to execute control transfer" | |
2877 | " without lock!!"); | |
2878 | return -EDEADLK; | |
2879 | } | |
681c7399 | 2880 | if (!hdw->flag_ok && !probe_fl) { |
d855497e MI |
2881 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, |
2882 | "Attempted to execute control transfer" | |
2883 | " when device not ok"); | |
2884 | return -EIO; | |
2885 | } | |
2886 | if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) { | |
2887 | if (!probe_fl) { | |
2888 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
2889 | "Attempted to execute control transfer" | |
2890 | " when USB is disconnected"); | |
2891 | } | |
2892 | return -ENOTTY; | |
2893 | } | |
2894 | ||
2895 | /* Ensure that we have sane parameters */ | |
2896 | if (!write_data) write_len = 0; | |
2897 | if (!read_data) read_len = 0; | |
2898 | if (write_len > PVR2_CTL_BUFFSIZE) { | |
2899 | pvr2_trace( | |
2900 | PVR2_TRACE_ERROR_LEGS, | |
2901 | "Attempted to execute %d byte" | |
2902 | " control-write transfer (limit=%d)", | |
2903 | write_len,PVR2_CTL_BUFFSIZE); | |
2904 | return -EINVAL; | |
2905 | } | |
2906 | if (read_len > PVR2_CTL_BUFFSIZE) { | |
2907 | pvr2_trace( | |
2908 | PVR2_TRACE_ERROR_LEGS, | |
2909 | "Attempted to execute %d byte" | |
2910 | " control-read transfer (limit=%d)", | |
2911 | write_len,PVR2_CTL_BUFFSIZE); | |
2912 | return -EINVAL; | |
2913 | } | |
2914 | if ((!write_len) && (!read_len)) { | |
2915 | pvr2_trace( | |
2916 | PVR2_TRACE_ERROR_LEGS, | |
2917 | "Attempted to execute null control transfer?"); | |
2918 | return -EINVAL; | |
2919 | } | |
2920 | ||
2921 | ||
2922 | hdw->cmd_debug_state = 1; | |
2923 | if (write_len) { | |
2924 | hdw->cmd_debug_code = ((unsigned char *)write_data)[0]; | |
2925 | } else { | |
2926 | hdw->cmd_debug_code = 0; | |
2927 | } | |
2928 | hdw->cmd_debug_write_len = write_len; | |
2929 | hdw->cmd_debug_read_len = read_len; | |
2930 | ||
2931 | /* Initialize common stuff */ | |
2932 | init_completion(&hdw->ctl_done); | |
2933 | hdw->ctl_timeout_flag = 0; | |
2934 | hdw->ctl_write_pend_flag = 0; | |
2935 | hdw->ctl_read_pend_flag = 0; | |
2936 | init_timer(&timer); | |
2937 | timer.expires = jiffies + timeout; | |
2938 | timer.data = (unsigned long)hdw; | |
2939 | timer.function = pvr2_ctl_timeout; | |
2940 | ||
2941 | if (write_len) { | |
2942 | hdw->cmd_debug_state = 2; | |
2943 | /* Transfer write data to internal buffer */ | |
2944 | for (idx = 0; idx < write_len; idx++) { | |
2945 | hdw->ctl_write_buffer[idx] = | |
2946 | ((unsigned char *)write_data)[idx]; | |
2947 | } | |
2948 | /* Initiate a write request */ | |
2949 | usb_fill_bulk_urb(hdw->ctl_write_urb, | |
2950 | hdw->usb_dev, | |
2951 | usb_sndbulkpipe(hdw->usb_dev, | |
2952 | PVR2_CTL_WRITE_ENDPOINT), | |
2953 | hdw->ctl_write_buffer, | |
2954 | write_len, | |
2955 | pvr2_ctl_write_complete, | |
2956 | hdw); | |
2957 | hdw->ctl_write_urb->actual_length = 0; | |
2958 | hdw->ctl_write_pend_flag = !0; | |
2959 | status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL); | |
2960 | if (status < 0) { | |
2961 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
2962 | "Failed to submit write-control" | |
2963 | " URB status=%d",status); | |
2964 | hdw->ctl_write_pend_flag = 0; | |
2965 | goto done; | |
2966 | } | |
2967 | } | |
2968 | ||
2969 | if (read_len) { | |
2970 | hdw->cmd_debug_state = 3; | |
2971 | memset(hdw->ctl_read_buffer,0x43,read_len); | |
2972 | /* Initiate a read request */ | |
2973 | usb_fill_bulk_urb(hdw->ctl_read_urb, | |
2974 | hdw->usb_dev, | |
2975 | usb_rcvbulkpipe(hdw->usb_dev, | |
2976 | PVR2_CTL_READ_ENDPOINT), | |
2977 | hdw->ctl_read_buffer, | |
2978 | read_len, | |
2979 | pvr2_ctl_read_complete, | |
2980 | hdw); | |
2981 | hdw->ctl_read_urb->actual_length = 0; | |
2982 | hdw->ctl_read_pend_flag = !0; | |
2983 | status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL); | |
2984 | if (status < 0) { | |
2985 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
2986 | "Failed to submit read-control" | |
2987 | " URB status=%d",status); | |
2988 | hdw->ctl_read_pend_flag = 0; | |
2989 | goto done; | |
2990 | } | |
2991 | } | |
2992 | ||
2993 | /* Start timer */ | |
2994 | add_timer(&timer); | |
2995 | ||
2996 | /* Now wait for all I/O to complete */ | |
2997 | hdw->cmd_debug_state = 4; | |
2998 | while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) { | |
2999 | wait_for_completion(&hdw->ctl_done); | |
3000 | } | |
3001 | hdw->cmd_debug_state = 5; | |
3002 | ||
3003 | /* Stop timer */ | |
3004 | del_timer_sync(&timer); | |
3005 | ||
3006 | hdw->cmd_debug_state = 6; | |
3007 | status = 0; | |
3008 | ||
3009 | if (hdw->ctl_timeout_flag) { | |
3010 | status = -ETIMEDOUT; | |
3011 | if (!probe_fl) { | |
3012 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
3013 | "Timed out control-write"); | |
3014 | } | |
3015 | goto done; | |
3016 | } | |
3017 | ||
3018 | if (write_len) { | |
3019 | /* Validate results of write request */ | |
3020 | if ((hdw->ctl_write_urb->status != 0) && | |
3021 | (hdw->ctl_write_urb->status != -ENOENT) && | |
3022 | (hdw->ctl_write_urb->status != -ESHUTDOWN) && | |
3023 | (hdw->ctl_write_urb->status != -ECONNRESET)) { | |
3024 | /* USB subsystem is reporting some kind of failure | |
3025 | on the write */ | |
3026 | status = hdw->ctl_write_urb->status; | |
3027 | if (!probe_fl) { | |
3028 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
3029 | "control-write URB failure," | |
3030 | " status=%d", | |
3031 | status); | |
3032 | } | |
3033 | goto done; | |
3034 | } | |
3035 | if (hdw->ctl_write_urb->actual_length < write_len) { | |
3036 | /* Failed to write enough data */ | |
3037 | status = -EIO; | |
3038 | if (!probe_fl) { | |
3039 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
3040 | "control-write URB short," | |
3041 | " expected=%d got=%d", | |
3042 | write_len, | |
3043 | hdw->ctl_write_urb->actual_length); | |
3044 | } | |
3045 | goto done; | |
3046 | } | |
3047 | } | |
3048 | if (read_len) { | |
3049 | /* Validate results of read request */ | |
3050 | if ((hdw->ctl_read_urb->status != 0) && | |
3051 | (hdw->ctl_read_urb->status != -ENOENT) && | |
3052 | (hdw->ctl_read_urb->status != -ESHUTDOWN) && | |
3053 | (hdw->ctl_read_urb->status != -ECONNRESET)) { | |
3054 | /* USB subsystem is reporting some kind of failure | |
3055 | on the read */ | |
3056 | status = hdw->ctl_read_urb->status; | |
3057 | if (!probe_fl) { | |
3058 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
3059 | "control-read URB failure," | |
3060 | " status=%d", | |
3061 | status); | |
3062 | } | |
3063 | goto done; | |
3064 | } | |
3065 | if (hdw->ctl_read_urb->actual_length < read_len) { | |
3066 | /* Failed to read enough data */ | |
3067 | status = -EIO; | |
3068 | if (!probe_fl) { | |
3069 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
3070 | "control-read URB short," | |
3071 | " expected=%d got=%d", | |
3072 | read_len, | |
3073 | hdw->ctl_read_urb->actual_length); | |
3074 | } | |
3075 | goto done; | |
3076 | } | |
3077 | /* Transfer retrieved data out from internal buffer */ | |
3078 | for (idx = 0; idx < read_len; idx++) { | |
3079 | ((unsigned char *)read_data)[idx] = | |
3080 | hdw->ctl_read_buffer[idx]; | |
3081 | } | |
3082 | } | |
3083 | ||
3084 | done: | |
3085 | ||
3086 | hdw->cmd_debug_state = 0; | |
3087 | if ((status < 0) && (!probe_fl)) { | |
681c7399 | 3088 | pvr2_hdw_render_useless(hdw); |
d855497e MI |
3089 | } |
3090 | return status; | |
3091 | } | |
3092 | ||
3093 | ||
3094 | int pvr2_send_request(struct pvr2_hdw *hdw, | |
3095 | void *write_data,unsigned int write_len, | |
3096 | void *read_data,unsigned int read_len) | |
3097 | { | |
3098 | return pvr2_send_request_ex(hdw,HZ*4,0, | |
3099 | write_data,write_len, | |
3100 | read_data,read_len); | |
3101 | } | |
3102 | ||
3103 | int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data) | |
3104 | { | |
3105 | int ret; | |
3106 | ||
3107 | LOCK_TAKE(hdw->ctl_lock); | |
3108 | ||
8d364363 | 3109 | hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */ |
d855497e MI |
3110 | PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data); |
3111 | hdw->cmd_buffer[5] = 0; | |
3112 | hdw->cmd_buffer[6] = (reg >> 8) & 0xff; | |
3113 | hdw->cmd_buffer[7] = reg & 0xff; | |
3114 | ||
3115 | ||
3116 | ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0); | |
3117 | ||
3118 | LOCK_GIVE(hdw->ctl_lock); | |
3119 | ||
3120 | return ret; | |
3121 | } | |
3122 | ||
3123 | ||
07e337ee | 3124 | static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data) |
d855497e MI |
3125 | { |
3126 | int ret = 0; | |
3127 | ||
3128 | LOCK_TAKE(hdw->ctl_lock); | |
3129 | ||
8d364363 | 3130 | hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */ |
d855497e MI |
3131 | hdw->cmd_buffer[1] = 0; |
3132 | hdw->cmd_buffer[2] = 0; | |
3133 | hdw->cmd_buffer[3] = 0; | |
3134 | hdw->cmd_buffer[4] = 0; | |
3135 | hdw->cmd_buffer[5] = 0; | |
3136 | hdw->cmd_buffer[6] = (reg >> 8) & 0xff; | |
3137 | hdw->cmd_buffer[7] = reg & 0xff; | |
3138 | ||
3139 | ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4); | |
3140 | *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0); | |
3141 | ||
3142 | LOCK_GIVE(hdw->ctl_lock); | |
3143 | ||
3144 | return ret; | |
3145 | } | |
3146 | ||
3147 | ||
681c7399 | 3148 | void pvr2_hdw_render_useless(struct pvr2_hdw *hdw) |
d855497e MI |
3149 | { |
3150 | if (!hdw->flag_ok) return; | |
681c7399 MI |
3151 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, |
3152 | "Device being rendered inoperable"); | |
d855497e | 3153 | if (hdw->vid_stream) { |
a0fd1cb1 | 3154 | pvr2_stream_setup(hdw->vid_stream,NULL,0,0); |
d855497e | 3155 | } |
681c7399 MI |
3156 | hdw->flag_ok = 0; |
3157 | trace_stbit("flag_ok",hdw->flag_ok); | |
3158 | pvr2_hdw_state_sched(hdw); | |
d855497e MI |
3159 | } |
3160 | ||
3161 | ||
3162 | void pvr2_hdw_device_reset(struct pvr2_hdw *hdw) | |
3163 | { | |
3164 | int ret; | |
3165 | pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset..."); | |
a0fd1cb1 | 3166 | ret = usb_lock_device_for_reset(hdw->usb_dev,NULL); |
d855497e MI |
3167 | if (ret == 1) { |
3168 | ret = usb_reset_device(hdw->usb_dev); | |
3169 | usb_unlock_device(hdw->usb_dev); | |
3170 | } else { | |
3171 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
3172 | "Failed to lock USB device ret=%d",ret); | |
3173 | } | |
3174 | if (init_pause_msec) { | |
3175 | pvr2_trace(PVR2_TRACE_INFO, | |
3176 | "Waiting %u msec for hardware to settle", | |
3177 | init_pause_msec); | |
3178 | msleep(init_pause_msec); | |
3179 | } | |
3180 | ||
3181 | } | |
3182 | ||
3183 | ||
3184 | void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val) | |
3185 | { | |
3186 | char da[1]; | |
3187 | unsigned int pipe; | |
3188 | int ret; | |
3189 | ||
3190 | if (!hdw->usb_dev) return; | |
3191 | ||
3192 | pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val); | |
3193 | ||
3194 | da[0] = val ? 0x01 : 0x00; | |
3195 | ||
3196 | /* Write the CPUCS register on the 8051. The lsb of the register | |
3197 | is the reset bit; a 1 asserts reset while a 0 clears it. */ | |
3198 | pipe = usb_sndctrlpipe(hdw->usb_dev, 0); | |
3199 | ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ); | |
3200 | if (ret < 0) { | |
3201 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
3202 | "cpureset_assert(%d) error=%d",val,ret); | |
3203 | pvr2_hdw_render_useless(hdw); | |
3204 | } | |
3205 | } | |
3206 | ||
3207 | ||
3208 | int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw) | |
3209 | { | |
3210 | int status; | |
3211 | LOCK_TAKE(hdw->ctl_lock); do { | |
3212 | pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset"); | |
8d364363 | 3213 | hdw->cmd_buffer[0] = FX2CMD_DEEP_RESET; |
a0fd1cb1 | 3214 | status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0); |
d855497e MI |
3215 | } while (0); LOCK_GIVE(hdw->ctl_lock); |
3216 | return status; | |
3217 | } | |
3218 | ||
3219 | ||
e1edb19a | 3220 | static int pvr2_hdw_cmd_power_ctrl(struct pvr2_hdw *hdw, int onoff) |
d855497e MI |
3221 | { |
3222 | int status; | |
3223 | LOCK_TAKE(hdw->ctl_lock); do { | |
e1edb19a MK |
3224 | if (onoff) { |
3225 | pvr2_trace(PVR2_TRACE_INIT, "Requesting powerup"); | |
3226 | hdw->cmd_buffer[0] = FX2CMD_POWER_ON; | |
3227 | } else { | |
3228 | pvr2_trace(PVR2_TRACE_INIT, "Requesting powerdown"); | |
3229 | hdw->cmd_buffer[0] = FX2CMD_POWER_OFF; | |
3230 | } | |
3231 | status = pvr2_send_request(hdw, hdw->cmd_buffer, 1, NULL, 0); | |
d855497e MI |
3232 | } while (0); LOCK_GIVE(hdw->ctl_lock); |
3233 | return status; | |
3234 | } | |
3235 | ||
e1edb19a MK |
3236 | int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw) |
3237 | { | |
3238 | return pvr2_hdw_cmd_power_ctrl(hdw, 1); | |
3239 | } | |
3240 | ||
3241 | int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw) | |
3242 | { | |
3243 | return pvr2_hdw_cmd_power_ctrl(hdw, 0); | |
3244 | } | |
3245 | ||
d855497e MI |
3246 | |
3247 | int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw) | |
3248 | { | |
3249 | if (!hdw->decoder_ctrl) { | |
3250 | pvr2_trace(PVR2_TRACE_INIT, | |
3251 | "Unable to reset decoder: nothing attached"); | |
3252 | return -ENOTTY; | |
3253 | } | |
3254 | ||
3255 | if (!hdw->decoder_ctrl->force_reset) { | |
3256 | pvr2_trace(PVR2_TRACE_INIT, | |
3257 | "Unable to reset decoder: not implemented"); | |
3258 | return -ENOTTY; | |
3259 | } | |
3260 | ||
3261 | pvr2_trace(PVR2_TRACE_INIT, | |
3262 | "Requesting decoder reset"); | |
3263 | hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt); | |
3264 | return 0; | |
3265 | } | |
3266 | ||
3267 | ||
62433e31 | 3268 | static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff) |
84147f3d MI |
3269 | { |
3270 | int status; | |
3271 | ||
3272 | LOCK_TAKE(hdw->ctl_lock); do { | |
62433e31 MI |
3273 | pvr2_trace(PVR2_TRACE_INIT, |
3274 | "Issuing fe demod wake command (%s)", | |
3275 | (onoff ? "on" : "off")); | |
84147f3d MI |
3276 | hdw->flag_ok = !0; |
3277 | hdw->cmd_buffer[0] = FX2CMD_HCW_DEMOD_RESETIN; | |
3278 | hdw->cmd_buffer[1] = onoff; | |
3279 | status = pvr2_send_request(hdw, hdw->cmd_buffer, 2, NULL, 0); | |
3280 | } while (0); LOCK_GIVE(hdw->ctl_lock); | |
3281 | ||
3282 | return status; | |
3283 | } | |
3284 | ||
84147f3d | 3285 | |
62433e31 | 3286 | static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff) |
84147f3d MI |
3287 | { |
3288 | int status; | |
3289 | ||
3290 | LOCK_TAKE(hdw->ctl_lock); do { | |
62433e31 MI |
3291 | pvr2_trace(PVR2_TRACE_INIT, |
3292 | "Issuing fe power command to CPLD (%s)", | |
3293 | (onoff ? "on" : "off")); | |
84147f3d MI |
3294 | hdw->flag_ok = !0; |
3295 | hdw->cmd_buffer[0] = | |
3296 | (onoff ? FX2CMD_ONAIR_DTV_POWER_ON : | |
3297 | FX2CMD_ONAIR_DTV_POWER_OFF); | |
3298 | status = pvr2_send_request(hdw, hdw->cmd_buffer, 1, NULL, 0); | |
3299 | } while (0); LOCK_GIVE(hdw->ctl_lock); | |
3300 | ||
3301 | return status; | |
3302 | } | |
3303 | ||
62433e31 MI |
3304 | |
3305 | static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw, | |
3306 | int onoff) | |
84147f3d MI |
3307 | { |
3308 | int status; | |
3309 | LOCK_TAKE(hdw->ctl_lock); do { | |
62433e31 MI |
3310 | pvr2_trace(PVR2_TRACE_INIT, |
3311 | "Issuing onair digital setup command (%s)", | |
3312 | (onoff ? "on" : "off")); | |
84147f3d MI |
3313 | hdw->cmd_buffer[0] = |
3314 | (onoff ? FX2CMD_ONAIR_DTV_STREAMING_ON : | |
3315 | FX2CMD_ONAIR_DTV_STREAMING_OFF); | |
3316 | status = pvr2_send_request(hdw, hdw->cmd_buffer, 1, NULL, 0); | |
3317 | } while (0); LOCK_GIVE(hdw->ctl_lock); | |
3318 | return status; | |
3319 | } | |
3320 | ||
62433e31 MI |
3321 | |
3322 | static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl) | |
3323 | { | |
3324 | int cmode; | |
3325 | /* Compare digital/analog desired setting with current setting. If | |
3326 | they don't match, fix it... */ | |
3327 | cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG); | |
3328 | if (cmode == hdw->pathway_state) { | |
3329 | /* They match; nothing to do */ | |
3330 | return; | |
3331 | } | |
3332 | ||
3333 | switch (hdw->hdw_desc->digital_control_scheme) { | |
3334 | case PVR2_DIGITAL_SCHEME_HAUPPAUGE: | |
3335 | pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl); | |
3336 | if (cmode == PVR2_PATHWAY_ANALOG) { | |
3337 | /* If moving to analog mode, also force the decoder | |
3338 | to reset. If no decoder is attached, then it's | |
3339 | ok to ignore this because if/when the decoder | |
3340 | attaches, it will reset itself at that time. */ | |
3341 | pvr2_hdw_cmd_decoder_reset(hdw); | |
3342 | } | |
3343 | break; | |
3344 | case PVR2_DIGITAL_SCHEME_ONAIR: | |
3345 | /* Supposedly we should always have the power on whether in | |
3346 | digital or analog mode. But for now do what appears to | |
3347 | work... */ | |
3348 | if (digitalFl) pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,!0); | |
3349 | pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,digitalFl); | |
3350 | if (!digitalFl) pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,0); | |
3351 | break; | |
3352 | default: break; | |
3353 | } | |
3354 | ||
1b9c18c5 | 3355 | pvr2_hdw_untrip_unlocked(hdw); |
62433e31 MI |
3356 | hdw->pathway_state = cmode; |
3357 | } | |
3358 | ||
3359 | ||
c55a97d7 MI |
3360 | /* Toggle LED */ |
3361 | int pvr2_led_ctrl(struct pvr2_hdw *hdw, int onoff) | |
3362 | { | |
3363 | /* change some GPIO data | |
3364 | * | |
3365 | * note: bit d7 of dir appears to control the LED, | |
3366 | * so we shut it off here. | |
3367 | * | |
3368 | * FIXME: is this device-specific? | |
3369 | */ | |
3370 | if (onoff) | |
3371 | pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481); | |
3372 | else | |
3373 | pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401); | |
3374 | ||
3375 | pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000); | |
3376 | ||
3377 | return 0; | |
3378 | } | |
3379 | ||
3380 | ||
e61b6fc5 | 3381 | /* Stop / start video stream transport */ |
07e337ee | 3382 | static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl) |
d855497e | 3383 | { |
62433e31 MI |
3384 | int status,cc; |
3385 | if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) && | |
3386 | hdw->hdw_desc->digital_control_scheme == | |
3387 | PVR2_DIGITAL_SCHEME_HAUPPAUGE) { | |
3388 | cc = (runFl ? | |
3389 | FX2CMD_HCW_DTV_STREAMING_ON : | |
3390 | FX2CMD_HCW_DTV_STREAMING_OFF); | |
3391 | } else { | |
3392 | cc = (runFl ? | |
3393 | FX2CMD_STREAMING_ON : | |
3394 | FX2CMD_STREAMING_OFF); | |
3395 | } | |
3396 | ||
d855497e | 3397 | LOCK_TAKE(hdw->ctl_lock); do { |
62433e31 | 3398 | hdw->cmd_buffer[0] = cc; |
a0fd1cb1 | 3399 | status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0); |
d855497e | 3400 | } while (0); LOCK_GIVE(hdw->ctl_lock); |
d855497e MI |
3401 | return status; |
3402 | } | |
3403 | ||
3404 | ||
62433e31 MI |
3405 | /* Evaluate whether or not state_pathway_ok can change */ |
3406 | static int state_eval_pathway_ok(struct pvr2_hdw *hdw) | |
3407 | { | |
3408 | if (hdw->state_pathway_ok) { | |
3409 | /* Nothing to do if pathway is already ok */ | |
3410 | return 0; | |
3411 | } | |
3412 | if (!hdw->state_pipeline_idle) { | |
3413 | /* Not allowed to change anything if pipeline is not idle */ | |
3414 | return 0; | |
3415 | } | |
3416 | pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV); | |
3417 | hdw->state_pathway_ok = !0; | |
e9db1ff2 | 3418 | trace_stbit("state_pathway_ok",hdw->state_pathway_ok); |
62433e31 MI |
3419 | return !0; |
3420 | } | |
3421 | ||
3422 | ||
681c7399 MI |
3423 | /* Evaluate whether or not state_encoder_ok can change */ |
3424 | static int state_eval_encoder_ok(struct pvr2_hdw *hdw) | |
3425 | { | |
3426 | if (hdw->state_encoder_ok) return 0; | |
3427 | if (hdw->flag_tripped) return 0; | |
3428 | if (hdw->state_encoder_run) return 0; | |
3429 | if (hdw->state_encoder_config) return 0; | |
3430 | if (hdw->state_decoder_run) return 0; | |
3431 | if (hdw->state_usbstream_run) return 0; | |
62433e31 | 3432 | if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) return 0; |
681c7399 MI |
3433 | if (pvr2_upload_firmware2(hdw) < 0) { |
3434 | hdw->flag_tripped = !0; | |
3435 | trace_stbit("flag_tripped",hdw->flag_tripped); | |
3436 | return !0; | |
3437 | } | |
3438 | hdw->state_encoder_ok = !0; | |
3439 | trace_stbit("state_encoder_ok",hdw->state_encoder_ok); | |
3440 | return !0; | |
3441 | } | |
3442 | ||
3443 | ||
3444 | /* Evaluate whether or not state_encoder_config can change */ | |
3445 | static int state_eval_encoder_config(struct pvr2_hdw *hdw) | |
3446 | { | |
3447 | if (hdw->state_encoder_config) { | |
3448 | if (hdw->state_encoder_ok) { | |
3449 | if (hdw->state_pipeline_req && | |
3450 | !hdw->state_pipeline_pause) return 0; | |
3451 | } | |
3452 | hdw->state_encoder_config = 0; | |
3453 | hdw->state_encoder_waitok = 0; | |
3454 | trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok); | |
3455 | /* paranoia - solve race if timer just completed */ | |
3456 | del_timer_sync(&hdw->encoder_wait_timer); | |
3457 | } else { | |
62433e31 MI |
3458 | if (!hdw->state_pathway_ok || |
3459 | (hdw->pathway_state != PVR2_PATHWAY_ANALOG) || | |
3460 | !hdw->state_encoder_ok || | |
681c7399 MI |
3461 | !hdw->state_pipeline_idle || |
3462 | hdw->state_pipeline_pause || | |
3463 | !hdw->state_pipeline_req || | |
3464 | !hdw->state_pipeline_config) { | |
3465 | /* We must reset the enforced wait interval if | |
3466 | anything has happened that might have disturbed | |
3467 | the encoder. This should be a rare case. */ | |
3468 | if (timer_pending(&hdw->encoder_wait_timer)) { | |
3469 | del_timer_sync(&hdw->encoder_wait_timer); | |
3470 | } | |
3471 | if (hdw->state_encoder_waitok) { | |
3472 | /* Must clear the state - therefore we did | |
3473 | something to a state bit and must also | |
3474 | return true. */ | |
3475 | hdw->state_encoder_waitok = 0; | |
3476 | trace_stbit("state_encoder_waitok", | |
3477 | hdw->state_encoder_waitok); | |
3478 | return !0; | |
3479 | } | |
3480 | return 0; | |
3481 | } | |
3482 | if (!hdw->state_encoder_waitok) { | |
3483 | if (!timer_pending(&hdw->encoder_wait_timer)) { | |
3484 | /* waitok flag wasn't set and timer isn't | |
3485 | running. Check flag once more to avoid | |
3486 | a race then start the timer. This is | |
3487 | the point when we measure out a minimal | |
3488 | quiet interval before doing something to | |
3489 | the encoder. */ | |
3490 | if (!hdw->state_encoder_waitok) { | |
3491 | hdw->encoder_wait_timer.expires = | |
3492 | jiffies + (HZ*50/1000); | |
3493 | add_timer(&hdw->encoder_wait_timer); | |
3494 | } | |
3495 | } | |
3496 | /* We can't continue until we know we have been | |
3497 | quiet for the interval measured by this | |
3498 | timer. */ | |
3499 | return 0; | |
3500 | } | |
3501 | pvr2_encoder_configure(hdw); | |
3502 | if (hdw->state_encoder_ok) hdw->state_encoder_config = !0; | |
3503 | } | |
3504 | trace_stbit("state_encoder_config",hdw->state_encoder_config); | |
3505 | return !0; | |
3506 | } | |
3507 | ||
3508 | ||
3509 | /* Evaluate whether or not state_encoder_run can change */ | |
3510 | static int state_eval_encoder_run(struct pvr2_hdw *hdw) | |
3511 | { | |
3512 | if (hdw->state_encoder_run) { | |
3513 | if (hdw->state_encoder_ok) { | |
62433e31 MI |
3514 | if (hdw->state_decoder_run && |
3515 | hdw->state_pathway_ok) return 0; | |
681c7399 MI |
3516 | if (pvr2_encoder_stop(hdw) < 0) return !0; |
3517 | } | |
3518 | hdw->state_encoder_run = 0; | |
3519 | } else { | |
3520 | if (!hdw->state_encoder_ok) return 0; | |
3521 | if (!hdw->state_decoder_run) return 0; | |
62433e31 MI |
3522 | if (!hdw->state_pathway_ok) return 0; |
3523 | if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) return 0; | |
681c7399 MI |
3524 | if (pvr2_encoder_start(hdw) < 0) return !0; |
3525 | hdw->state_encoder_run = !0; | |
3526 | } | |
3527 | trace_stbit("state_encoder_run",hdw->state_encoder_run); | |
3528 | return !0; | |
3529 | } | |
3530 | ||
3531 | ||
3532 | /* Timeout function for quiescent timer. */ | |
3533 | static void pvr2_hdw_quiescent_timeout(unsigned long data) | |
3534 | { | |
3535 | struct pvr2_hdw *hdw = (struct pvr2_hdw *)data; | |
3536 | hdw->state_decoder_quiescent = !0; | |
3537 | trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent); | |
3538 | hdw->state_stale = !0; | |
3539 | queue_work(hdw->workqueue,&hdw->workpoll); | |
3540 | } | |
3541 | ||
3542 | ||
3543 | /* Timeout function for encoder wait timer. */ | |
3544 | static void pvr2_hdw_encoder_wait_timeout(unsigned long data) | |
3545 | { | |
3546 | struct pvr2_hdw *hdw = (struct pvr2_hdw *)data; | |
3547 | hdw->state_encoder_waitok = !0; | |
3548 | trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok); | |
3549 | hdw->state_stale = !0; | |
3550 | queue_work(hdw->workqueue,&hdw->workpoll); | |
3551 | } | |
3552 | ||
3553 | ||
3554 | /* Evaluate whether or not state_decoder_run can change */ | |
3555 | static int state_eval_decoder_run(struct pvr2_hdw *hdw) | |
3556 | { | |
3557 | if (hdw->state_decoder_run) { | |
3558 | if (hdw->state_encoder_ok) { | |
3559 | if (hdw->state_pipeline_req && | |
62433e31 MI |
3560 | !hdw->state_pipeline_pause && |
3561 | hdw->state_pathway_ok) return 0; | |
681c7399 MI |
3562 | } |
3563 | if (!hdw->flag_decoder_missed) { | |
3564 | pvr2_decoder_enable(hdw,0); | |
3565 | } | |
3566 | hdw->state_decoder_quiescent = 0; | |
3567 | hdw->state_decoder_run = 0; | |
3568 | /* paranoia - solve race if timer just completed */ | |
3569 | del_timer_sync(&hdw->quiescent_timer); | |
3570 | } else { | |
3571 | if (!hdw->state_decoder_quiescent) { | |
3572 | if (!timer_pending(&hdw->quiescent_timer)) { | |
3573 | /* We don't do something about the | |
3574 | quiescent timer until right here because | |
3575 | we also want to catch cases where the | |
3576 | decoder was already not running (like | |
3577 | after initialization) as opposed to | |
3578 | knowing that we had just stopped it. | |
3579 | The second flag check is here to cover a | |
3580 | race - the timer could have run and set | |
3581 | this flag just after the previous check | |
3582 | but before we did the pending check. */ | |
3583 | if (!hdw->state_decoder_quiescent) { | |
3584 | hdw->quiescent_timer.expires = | |
3585 | jiffies + (HZ*50/1000); | |
3586 | add_timer(&hdw->quiescent_timer); | |
3587 | } | |
3588 | } | |
3589 | /* Don't allow decoder to start again until it has | |
3590 | been quiesced first. This little detail should | |
3591 | hopefully further stabilize the encoder. */ | |
3592 | return 0; | |
3593 | } | |
62433e31 MI |
3594 | if (!hdw->state_pathway_ok || |
3595 | (hdw->pathway_state != PVR2_PATHWAY_ANALOG) || | |
3596 | !hdw->state_pipeline_req || | |
681c7399 MI |
3597 | hdw->state_pipeline_pause || |
3598 | !hdw->state_pipeline_config || | |
3599 | !hdw->state_encoder_config || | |
3600 | !hdw->state_encoder_ok) return 0; | |
3601 | del_timer_sync(&hdw->quiescent_timer); | |
3602 | if (hdw->flag_decoder_missed) return 0; | |
3603 | if (pvr2_decoder_enable(hdw,!0) < 0) return 0; | |
3604 | hdw->state_decoder_quiescent = 0; | |
3605 | hdw->state_decoder_run = !0; | |
3606 | } | |
3607 | trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent); | |
3608 | trace_stbit("state_decoder_run",hdw->state_decoder_run); | |
3609 | return !0; | |
3610 | } | |
3611 | ||
3612 | ||
3613 | /* Evaluate whether or not state_usbstream_run can change */ | |
3614 | static int state_eval_usbstream_run(struct pvr2_hdw *hdw) | |
3615 | { | |
3616 | if (hdw->state_usbstream_run) { | |
62433e31 MI |
3617 | if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) { |
3618 | if (hdw->state_encoder_ok && | |
3619 | hdw->state_encoder_run && | |
3620 | hdw->state_pathway_ok) return 0; | |
3621 | } else { | |
3622 | if (hdw->state_pipeline_req && | |
3623 | !hdw->state_pipeline_pause && | |
3624 | hdw->state_pathway_ok) return 0; | |
681c7399 MI |
3625 | } |
3626 | pvr2_hdw_cmd_usbstream(hdw,0); | |
3627 | hdw->state_usbstream_run = 0; | |
3628 | } else { | |
62433e31 MI |
3629 | if (!hdw->state_pipeline_req || |
3630 | hdw->state_pipeline_pause || | |
3631 | !hdw->state_pathway_ok) return 0; | |
3632 | if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) { | |
3633 | if (!hdw->state_encoder_ok || | |
3634 | !hdw->state_encoder_run) return 0; | |
3635 | } | |
681c7399 MI |
3636 | if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0; |
3637 | hdw->state_usbstream_run = !0; | |
3638 | } | |
3639 | trace_stbit("state_usbstream_run",hdw->state_usbstream_run); | |
3640 | return !0; | |
3641 | } | |
3642 | ||
3643 | ||
3644 | /* Attempt to configure pipeline, if needed */ | |
3645 | static int state_eval_pipeline_config(struct pvr2_hdw *hdw) | |
3646 | { | |
3647 | if (hdw->state_pipeline_config || | |
3648 | hdw->state_pipeline_pause) return 0; | |
3649 | pvr2_hdw_commit_execute(hdw); | |
3650 | return !0; | |
3651 | } | |
3652 | ||
3653 | ||
3654 | /* Update pipeline idle and pipeline pause tracking states based on other | |
3655 | inputs. This must be called whenever the other relevant inputs have | |
3656 | changed. */ | |
3657 | static int state_update_pipeline_state(struct pvr2_hdw *hdw) | |
3658 | { | |
3659 | unsigned int st; | |
3660 | int updatedFl = 0; | |
3661 | /* Update pipeline state */ | |
3662 | st = !(hdw->state_encoder_run || | |
3663 | hdw->state_decoder_run || | |
3664 | hdw->state_usbstream_run || | |
3665 | (!hdw->state_decoder_quiescent)); | |
3666 | if (!st != !hdw->state_pipeline_idle) { | |
3667 | hdw->state_pipeline_idle = st; | |
3668 | updatedFl = !0; | |
3669 | } | |
3670 | if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) { | |
3671 | hdw->state_pipeline_pause = 0; | |
3672 | updatedFl = !0; | |
3673 | } | |
3674 | return updatedFl; | |
3675 | } | |
3676 | ||
3677 | ||
3678 | typedef int (*state_eval_func)(struct pvr2_hdw *); | |
3679 | ||
3680 | /* Set of functions to be run to evaluate various states in the driver. */ | |
3681 | const static state_eval_func eval_funcs[] = { | |
62433e31 | 3682 | state_eval_pathway_ok, |
681c7399 MI |
3683 | state_eval_pipeline_config, |
3684 | state_eval_encoder_ok, | |
3685 | state_eval_encoder_config, | |
3686 | state_eval_decoder_run, | |
3687 | state_eval_encoder_run, | |
3688 | state_eval_usbstream_run, | |
3689 | }; | |
3690 | ||
3691 | ||
3692 | /* Process various states and return true if we did anything interesting. */ | |
3693 | static int pvr2_hdw_state_update(struct pvr2_hdw *hdw) | |
3694 | { | |
3695 | unsigned int i; | |
3696 | int state_updated = 0; | |
3697 | int check_flag; | |
3698 | ||
3699 | if (!hdw->state_stale) return 0; | |
3700 | if ((hdw->fw1_state != FW1_STATE_OK) || | |
3701 | !hdw->flag_ok) { | |
3702 | hdw->state_stale = 0; | |
3703 | return !0; | |
3704 | } | |
3705 | /* This loop is the heart of the entire driver. It keeps trying to | |
3706 | evaluate various bits of driver state until nothing changes for | |
3707 | one full iteration. Each "bit of state" tracks some global | |
3708 | aspect of the driver, e.g. whether decoder should run, if | |
3709 | pipeline is configured, usb streaming is on, etc. We separately | |
3710 | evaluate each of those questions based on other driver state to | |
3711 | arrive at the correct running configuration. */ | |
3712 | do { | |
3713 | check_flag = 0; | |
3714 | state_update_pipeline_state(hdw); | |
3715 | /* Iterate over each bit of state */ | |
3716 | for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) { | |
3717 | if ((*eval_funcs[i])(hdw)) { | |
3718 | check_flag = !0; | |
3719 | state_updated = !0; | |
3720 | state_update_pipeline_state(hdw); | |
3721 | } | |
3722 | } | |
3723 | } while (check_flag && hdw->flag_ok); | |
3724 | hdw->state_stale = 0; | |
3725 | trace_stbit("state_stale",hdw->state_stale); | |
3726 | return state_updated; | |
3727 | } | |
3728 | ||
3729 | ||
62433e31 MI |
3730 | static const char *pvr2_pathway_state_name(int id) |
3731 | { | |
3732 | switch (id) { | |
3733 | case PVR2_PATHWAY_ANALOG: return "analog"; | |
3734 | case PVR2_PATHWAY_DIGITAL: return "digital"; | |
3735 | default: return "unknown"; | |
3736 | } | |
3737 | } | |
3738 | ||
3739 | ||
681c7399 MI |
3740 | static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which, |
3741 | char *buf,unsigned int acnt) | |
3742 | { | |
3743 | switch (which) { | |
3744 | case 0: | |
3745 | return scnprintf( | |
3746 | buf,acnt, | |
e9db1ff2 | 3747 | "driver:%s%s%s%s%s <mode=%s>", |
681c7399 MI |
3748 | (hdw->flag_ok ? " <ok>" : " <fail>"), |
3749 | (hdw->flag_init_ok ? " <init>" : " <uninitialized>"), | |
3750 | (hdw->flag_disconnected ? " <disconnected>" : | |
3751 | " <connected>"), | |
3752 | (hdw->flag_tripped ? " <tripped>" : ""), | |
62433e31 MI |
3753 | (hdw->flag_decoder_missed ? " <no decoder>" : ""), |
3754 | pvr2_pathway_state_name(hdw->pathway_state)); | |
3755 | ||
681c7399 MI |
3756 | case 1: |
3757 | return scnprintf( | |
3758 | buf,acnt, | |
3759 | "pipeline:%s%s%s%s", | |
3760 | (hdw->state_pipeline_idle ? " <idle>" : ""), | |
3761 | (hdw->state_pipeline_config ? | |
3762 | " <configok>" : " <stale>"), | |
3763 | (hdw->state_pipeline_req ? " <req>" : ""), | |
3764 | (hdw->state_pipeline_pause ? " <pause>" : "")); | |
3765 | case 2: | |
3766 | return scnprintf( | |
3767 | buf,acnt, | |
62433e31 | 3768 | "worker:%s%s%s%s%s%s%s", |
681c7399 MI |
3769 | (hdw->state_decoder_run ? |
3770 | " <decode:run>" : | |
3771 | (hdw->state_decoder_quiescent ? | |
3772 | "" : " <decode:stop>")), | |
3773 | (hdw->state_decoder_quiescent ? | |
3774 | " <decode:quiescent>" : ""), | |
3775 | (hdw->state_encoder_ok ? | |
3776 | "" : " <encode:init>"), | |
3777 | (hdw->state_encoder_run ? | |
3778 | " <encode:run>" : " <encode:stop>"), | |
3779 | (hdw->state_encoder_config ? | |
3780 | " <encode:configok>" : | |
3781 | (hdw->state_encoder_waitok ? | |
3782 | "" : " <encode:wait>")), | |
3783 | (hdw->state_usbstream_run ? | |
62433e31 MI |
3784 | " <usb:run>" : " <usb:stop>"), |
3785 | (hdw->state_pathway_ok ? | |
e9db1ff2 | 3786 | " <pathway:ok>" : "")); |
681c7399 MI |
3787 | break; |
3788 | case 3: | |
3789 | return scnprintf( | |
3790 | buf,acnt, | |
3791 | "state: %s", | |
3792 | pvr2_get_state_name(hdw->master_state)); | |
3793 | break; | |
3794 | default: break; | |
3795 | } | |
3796 | return 0; | |
3797 | } | |
3798 | ||
3799 | ||
3800 | unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw, | |
3801 | char *buf,unsigned int acnt) | |
3802 | { | |
3803 | unsigned int bcnt,ccnt,idx; | |
3804 | bcnt = 0; | |
3805 | LOCK_TAKE(hdw->big_lock); | |
3806 | for (idx = 0; ; idx++) { | |
3807 | ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt); | |
3808 | if (!ccnt) break; | |
3809 | bcnt += ccnt; acnt -= ccnt; buf += ccnt; | |
3810 | if (!acnt) break; | |
3811 | buf[0] = '\n'; ccnt = 1; | |
3812 | bcnt += ccnt; acnt -= ccnt; buf += ccnt; | |
3813 | } | |
3814 | LOCK_GIVE(hdw->big_lock); | |
3815 | return bcnt; | |
3816 | } | |
3817 | ||
3818 | ||
3819 | static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw) | |
3820 | { | |
3821 | char buf[128]; | |
3822 | unsigned int idx,ccnt; | |
3823 | ||
3824 | for (idx = 0; ; idx++) { | |
3825 | ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf)); | |
3826 | if (!ccnt) break; | |
3827 | printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf); | |
3828 | } | |
3829 | } | |
3830 | ||
3831 | ||
3832 | /* Evaluate and update the driver's current state, taking various actions | |
3833 | as appropriate for the update. */ | |
3834 | static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw) | |
3835 | { | |
3836 | unsigned int st; | |
3837 | int state_updated = 0; | |
3838 | int callback_flag = 0; | |
1b9c18c5 | 3839 | int analog_mode; |
681c7399 MI |
3840 | |
3841 | pvr2_trace(PVR2_TRACE_STBITS, | |
3842 | "Drive state check START"); | |
3843 | if (pvrusb2_debug & PVR2_TRACE_STBITS) { | |
3844 | pvr2_hdw_state_log_state(hdw); | |
3845 | } | |
3846 | ||
3847 | /* Process all state and get back over disposition */ | |
3848 | state_updated = pvr2_hdw_state_update(hdw); | |
3849 | ||
1b9c18c5 MI |
3850 | analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL); |
3851 | ||
681c7399 MI |
3852 | /* Update master state based upon all other states. */ |
3853 | if (!hdw->flag_ok) { | |
3854 | st = PVR2_STATE_DEAD; | |
3855 | } else if (hdw->fw1_state != FW1_STATE_OK) { | |
3856 | st = PVR2_STATE_COLD; | |
1b9c18c5 | 3857 | } else if (analog_mode && !hdw->state_encoder_ok) { |
681c7399 | 3858 | st = PVR2_STATE_WARM; |
1b9c18c5 MI |
3859 | } else if (hdw->flag_tripped || |
3860 | (analog_mode && hdw->flag_decoder_missed)) { | |
681c7399 | 3861 | st = PVR2_STATE_ERROR; |
62433e31 | 3862 | } else if (hdw->state_usbstream_run && |
1b9c18c5 | 3863 | (!analog_mode || |
62433e31 | 3864 | (hdw->state_encoder_run && hdw->state_decoder_run))) { |
681c7399 MI |
3865 | st = PVR2_STATE_RUN; |
3866 | } else { | |
3867 | st = PVR2_STATE_READY; | |
3868 | } | |
3869 | if (hdw->master_state != st) { | |
3870 | pvr2_trace(PVR2_TRACE_STATE, | |
3871 | "Device state change from %s to %s", | |
3872 | pvr2_get_state_name(hdw->master_state), | |
3873 | pvr2_get_state_name(st)); | |
3874 | hdw->master_state = st; | |
3875 | state_updated = !0; | |
3876 | callback_flag = !0; | |
3877 | } | |
3878 | if (state_updated) { | |
3879 | /* Trigger anyone waiting on any state changes here. */ | |
3880 | wake_up(&hdw->state_wait_data); | |
3881 | } | |
3882 | ||
3883 | if (pvrusb2_debug & PVR2_TRACE_STBITS) { | |
3884 | pvr2_hdw_state_log_state(hdw); | |
3885 | } | |
3886 | pvr2_trace(PVR2_TRACE_STBITS, | |
3887 | "Drive state check DONE callback=%d",callback_flag); | |
3888 | ||
3889 | return callback_flag; | |
3890 | } | |
3891 | ||
3892 | ||
3893 | /* Cause kernel thread to check / update driver state */ | |
3894 | static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw) | |
3895 | { | |
3896 | if (hdw->state_stale) return; | |
3897 | hdw->state_stale = !0; | |
3898 | trace_stbit("state_stale",hdw->state_stale); | |
3899 | queue_work(hdw->workqueue,&hdw->workpoll); | |
3900 | } | |
3901 | ||
3902 | ||
3903 | void pvr2_hdw_get_debug_info_unlocked(const struct pvr2_hdw *hdw, | |
3904 | struct pvr2_hdw_debug_info *ptr) | |
d855497e MI |
3905 | { |
3906 | ptr->big_lock_held = hdw->big_lock_held; | |
3907 | ptr->ctl_lock_held = hdw->ctl_lock_held; | |
d855497e MI |
3908 | ptr->flag_disconnected = hdw->flag_disconnected; |
3909 | ptr->flag_init_ok = hdw->flag_init_ok; | |
681c7399 MI |
3910 | ptr->flag_ok = hdw->flag_ok; |
3911 | ptr->fw1_state = hdw->fw1_state; | |
3912 | ptr->flag_decoder_missed = hdw->flag_decoder_missed; | |
3913 | ptr->flag_tripped = hdw->flag_tripped; | |
3914 | ptr->state_encoder_ok = hdw->state_encoder_ok; | |
3915 | ptr->state_encoder_run = hdw->state_encoder_run; | |
3916 | ptr->state_decoder_run = hdw->state_decoder_run; | |
3917 | ptr->state_usbstream_run = hdw->state_usbstream_run; | |
3918 | ptr->state_decoder_quiescent = hdw->state_decoder_quiescent; | |
3919 | ptr->state_pipeline_config = hdw->state_pipeline_config; | |
3920 | ptr->state_pipeline_req = hdw->state_pipeline_req; | |
3921 | ptr->state_pipeline_pause = hdw->state_pipeline_pause; | |
3922 | ptr->state_pipeline_idle = hdw->state_pipeline_idle; | |
d855497e MI |
3923 | ptr->cmd_debug_state = hdw->cmd_debug_state; |
3924 | ptr->cmd_code = hdw->cmd_debug_code; | |
3925 | ptr->cmd_debug_write_len = hdw->cmd_debug_write_len; | |
3926 | ptr->cmd_debug_read_len = hdw->cmd_debug_read_len; | |
3927 | ptr->cmd_debug_timeout = hdw->ctl_timeout_flag; | |
3928 | ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag; | |
3929 | ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag; | |
3930 | ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status; | |
3931 | ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status; | |
3932 | } | |
3933 | ||
3934 | ||
681c7399 MI |
3935 | void pvr2_hdw_get_debug_info_locked(struct pvr2_hdw *hdw, |
3936 | struct pvr2_hdw_debug_info *ptr) | |
3937 | { | |
3938 | LOCK_TAKE(hdw->ctl_lock); do { | |
3939 | pvr2_hdw_get_debug_info_unlocked(hdw,ptr); | |
3940 | } while(0); LOCK_GIVE(hdw->ctl_lock); | |
3941 | } | |
3942 | ||
3943 | ||
d855497e MI |
3944 | int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp) |
3945 | { | |
3946 | return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp); | |
3947 | } | |
3948 | ||
3949 | ||
3950 | int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp) | |
3951 | { | |
3952 | return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp); | |
3953 | } | |
3954 | ||
3955 | ||
3956 | int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp) | |
3957 | { | |
3958 | return pvr2_read_register(hdw,PVR2_GPIO_IN,dp); | |
3959 | } | |
3960 | ||
3961 | ||
3962 | int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val) | |
3963 | { | |
3964 | u32 cval,nval; | |
3965 | int ret; | |
3966 | if (~msk) { | |
3967 | ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval); | |
3968 | if (ret) return ret; | |
3969 | nval = (cval & ~msk) | (val & msk); | |
3970 | pvr2_trace(PVR2_TRACE_GPIO, | |
3971 | "GPIO direction changing 0x%x:0x%x" | |
3972 | " from 0x%x to 0x%x", | |
3973 | msk,val,cval,nval); | |
3974 | } else { | |
3975 | nval = val; | |
3976 | pvr2_trace(PVR2_TRACE_GPIO, | |
3977 | "GPIO direction changing to 0x%x",nval); | |
3978 | } | |
3979 | return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval); | |
3980 | } | |
3981 | ||
3982 | ||
3983 | int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val) | |
3984 | { | |
3985 | u32 cval,nval; | |
3986 | int ret; | |
3987 | if (~msk) { | |
3988 | ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval); | |
3989 | if (ret) return ret; | |
3990 | nval = (cval & ~msk) | (val & msk); | |
3991 | pvr2_trace(PVR2_TRACE_GPIO, | |
3992 | "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x", | |
3993 | msk,val,cval,nval); | |
3994 | } else { | |
3995 | nval = val; | |
3996 | pvr2_trace(PVR2_TRACE_GPIO, | |
3997 | "GPIO output changing to 0x%x",nval); | |
3998 | } | |
3999 | return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval); | |
4000 | } | |
4001 | ||
4002 | ||
7fb20fa3 MI |
4003 | unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw) |
4004 | { | |
4005 | return hdw->input_avail_mask; | |
4006 | } | |
4007 | ||
4008 | ||
e61b6fc5 | 4009 | /* Find I2C address of eeprom */ |
07e337ee | 4010 | static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw) |
d855497e MI |
4011 | { |
4012 | int result; | |
4013 | LOCK_TAKE(hdw->ctl_lock); do { | |
8d364363 | 4014 | hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR; |
d855497e MI |
4015 | result = pvr2_send_request(hdw, |
4016 | hdw->cmd_buffer,1, | |
4017 | hdw->cmd_buffer,1); | |
4018 | if (result < 0) break; | |
4019 | result = hdw->cmd_buffer[0]; | |
4020 | } while(0); LOCK_GIVE(hdw->ctl_lock); | |
4021 | return result; | |
4022 | } | |
4023 | ||
4024 | ||
32ffa9ae | 4025 | int pvr2_hdw_register_access(struct pvr2_hdw *hdw, |
f3d092b8 HV |
4026 | u32 match_type, u32 match_chip, u64 reg_id, |
4027 | int setFl,u64 *val_ptr) | |
32ffa9ae MI |
4028 | { |
4029 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
32ffa9ae MI |
4030 | struct pvr2_i2c_client *cp; |
4031 | struct v4l2_register req; | |
6d98816f MI |
4032 | int stat = 0; |
4033 | int okFl = 0; | |
32ffa9ae | 4034 | |
201f5c9c MI |
4035 | if (!capable(CAP_SYS_ADMIN)) return -EPERM; |
4036 | ||
f3d092b8 HV |
4037 | req.match_type = match_type; |
4038 | req.match_chip = match_chip; | |
32ffa9ae MI |
4039 | req.reg = reg_id; |
4040 | if (setFl) req.val = *val_ptr; | |
4041 | mutex_lock(&hdw->i2c_list_lock); do { | |
e77e2c2f | 4042 | list_for_each_entry(cp, &hdw->i2c_clients, list) { |
8481a750 MI |
4043 | if (!v4l2_chip_match_i2c_client( |
4044 | cp->client, | |
4045 | req.match_type, req.match_chip)) { | |
f3d092b8 HV |
4046 | continue; |
4047 | } | |
32ffa9ae | 4048 | stat = pvr2_i2c_client_cmd( |
52ebc763 TP |
4049 | cp,(setFl ? VIDIOC_DBG_S_REGISTER : |
4050 | VIDIOC_DBG_G_REGISTER),&req); | |
32ffa9ae | 4051 | if (!setFl) *val_ptr = req.val; |
6d98816f MI |
4052 | okFl = !0; |
4053 | break; | |
32ffa9ae MI |
4054 | } |
4055 | } while (0); mutex_unlock(&hdw->i2c_list_lock); | |
6d98816f MI |
4056 | if (okFl) { |
4057 | return stat; | |
4058 | } | |
32ffa9ae MI |
4059 | return -EINVAL; |
4060 | #else | |
4061 | return -ENOSYS; | |
4062 | #endif | |
4063 | } | |
4064 | ||
4065 | ||
d855497e MI |
4066 | /* |
4067 | Stuff for Emacs to see, in order to encourage consistent editing style: | |
4068 | *** Local Variables: *** | |
4069 | *** mode: c *** | |
4070 | *** fill-column: 75 *** | |
4071 | *** tab-width: 8 *** | |
4072 | *** c-basic-offset: 8 *** | |
4073 | *** End: *** | |
4074 | */ |