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V4L/DVB (11205): pvrusb2: Remove ancient IVTV specific ioctl functions
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
d855497e
MI		 3 *
4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21#include <linux/errno.h>
22#include <linux/string.h>
23#include <linux/slab.h>
24#include <linux/firmware.h>
d855497e 25#include <linux/videodev2.h>
32ffa9ae 26#include <media/v4l2-common.h>
75212a02 27#include <media/tuner.h>
d855497e
MI		 28#include "pvrusb2.h"
29#include "pvrusb2-std.h"
30#include "pvrusb2-util.h"
31#include "pvrusb2-hdw.h"
32#include "pvrusb2-i2c-core.h"
d855497e
MI		 33#include "pvrusb2-eeprom.h"
34#include "pvrusb2-hdw-internal.h"
35#include "pvrusb2-encoder.h"
36#include "pvrusb2-debug.h"
8d364363 37#include "pvrusb2-fx2-cmd.h"
5f6dae80 38#include "pvrusb2-wm8775.h"
6f956512 39#include "pvrusb2-video-v4l.h"
634ba268 40#include "pvrusb2-cx2584x-v4l.h"
76891d65 41#include "pvrusb2-audio.h"
d855497e 42
1bde0289
MI		 43#define TV_MIN_FREQ 55250000L
44#define TV_MAX_FREQ 850000000L
25d8527a 45
83ce57aa
MI		 46/* This defines a minimum interval that the decoder must remain quiet
47 before we are allowed to start it running. */
48#define TIME_MSEC_DECODER_WAIT 50
49
50/* This defines a minimum interval that the encoder must remain quiet
fa98e594
MI		 51 before we are allowed to configure it. I had this originally set to
52 50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
53 things work better when it's set to 100msec. */
54#define TIME_MSEC_ENCODER_WAIT 100
83ce57aa
MI		 55
56/* This defines the minimum interval that the encoder must successfully run
57 before we consider that the encoder has run at least once since its
58 firmware has been loaded. This measurement is in important for cases
59 where we can't do something until we know that the encoder has been run
60 at least once. */
61#define TIME_MSEC_ENCODER_OK 250
62
a0fd1cb1 63static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 64static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e 65
ff699e6b 66static int ctlchg;
ff699e6b 67static int procreload;
d855497e
MI		 68static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
69static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
70static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
ff699e6b 71static int init_pause_msec;
d855497e
MI		 72
73module_param(ctlchg, int, S_IRUGO|S_IWUSR);
74MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
75module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
76MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
d855497e
MI		 77module_param(procreload, int, S_IRUGO|S_IWUSR);
78MODULE_PARM_DESC(procreload,
79 "Attempt init failure recovery with firmware reload");
80module_param_array(tuner, int, NULL, 0444);
81MODULE_PARM_DESC(tuner,"specify installed tuner type");
82module_param_array(video_std, int, NULL, 0444);
83MODULE_PARM_DESC(video_std,"specify initial video standard");
84module_param_array(tolerance, int, NULL, 0444);
85MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
86
5a4f5da6
MK		 87/* US Broadcast channel 7 (175.25 MHz) */
88static int default_tv_freq = 175250000L;
89/* 104.3 MHz, a usable FM station for my area */
90static int default_radio_freq = 104300000L;
91
92module_param_named(tv_freq, default_tv_freq, int, 0444);
93MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
94module_param_named(radio_freq, default_radio_freq, int, 0444);
95MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
96
d855497e
MI		 97#define PVR2_CTL_WRITE_ENDPOINT 0x01
98#define PVR2_CTL_READ_ENDPOINT 0x81
99
100#define PVR2_GPIO_IN 0x9008
101#define PVR2_GPIO_OUT 0x900c
102#define PVR2_GPIO_DIR 0x9020
103
104#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
105
106#define PVR2_FIRMWARE_ENDPOINT 0x02
107
108/* size of a firmware chunk */
109#define FIRMWARE_CHUNK_SIZE 0x2000
110
edb9dcb8
MI		 111typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
112 struct v4l2_subdev *);
113
114static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
4ecbc28d 115 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
6f956512 116 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
76891d65 117 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
634ba268 118 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
edb9dcb8
MI		 119};
120
e9c64a78
MI		 121static const char *module_names[] = {
122 [PVR2_CLIENT_ID_MSP3400] = "msp3400",
123 [PVR2_CLIENT_ID_CX25840] = "cx25840",
124 [PVR2_CLIENT_ID_SAA7115] = "saa7115",
125 [PVR2_CLIENT_ID_TUNER] = "tuner",
851981a1 126 [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
5f6dae80 127 [PVR2_CLIENT_ID_WM8775] = "wm8775",
e9c64a78
MI		 128};
129
130
131static const unsigned char *module_i2c_addresses[] = {
132 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
1dfe6c77
MI		 133 [PVR2_CLIENT_ID_MSP3400] = "\x40",
134 [PVR2_CLIENT_ID_SAA7115] = "\x21",
ae111f76 135 [PVR2_CLIENT_ID_WM8775] = "\x1b",
0b467014 136 [PVR2_CLIENT_ID_CX25840] = "\x44",
23334a22 137 [PVR2_CLIENT_ID_CS53L32A] = "\x11",
e9c64a78
MI		 138};
139
140
b30d2441
MI		 141/* Define the list of additional controls we'll dynamically construct based
142 on query of the cx2341x module. */
143struct pvr2_mpeg_ids {
144 const char *strid;
145 int id;
146};
147static const struct pvr2_mpeg_ids mpeg_ids[] = {
148 {
149 .strid = "audio_layer",
150 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
151 },{
152 .strid = "audio_bitrate",
153 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
154 },{
155 /* Already using audio_mode elsewhere :-( */
156 .strid = "mpeg_audio_mode",
157 .id = V4L2_CID_MPEG_AUDIO_MODE,
158 },{
159 .strid = "mpeg_audio_mode_extension",
160 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
161 },{
162 .strid = "audio_emphasis",
163 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
164 },{
165 .strid = "audio_crc",
166 .id = V4L2_CID_MPEG_AUDIO_CRC,
167 },{
168 .strid = "video_aspect",
169 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
170 },{
171 .strid = "video_b_frames",
172 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
173 },{
174 .strid = "video_gop_size",
175 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
176 },{
177 .strid = "video_gop_closure",
178 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 179 },{
180 .strid = "video_bitrate_mode",
181 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
182 },{
183 .strid = "video_bitrate",
184 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
185 },{
186 .strid = "video_bitrate_peak",
187 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
188 },{
189 .strid = "video_temporal_decimation",
190 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
191 },{
192 .strid = "stream_type",
193 .id = V4L2_CID_MPEG_STREAM_TYPE,
194 },{
195 .strid = "video_spatial_filter_mode",
196 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
197 },{
198 .strid = "video_spatial_filter",
199 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
200 },{
201 .strid = "video_luma_spatial_filter_type",
202 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
203 },{
204 .strid = "video_chroma_spatial_filter_type",
205 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
206 },{
207 .strid = "video_temporal_filter_mode",
208 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
209 },{
210 .strid = "video_temporal_filter",
211 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
212 },{
213 .strid = "video_median_filter_type",
214 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
215 },{
216 .strid = "video_luma_median_filter_top",
217 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
218 },{
219 .strid = "video_luma_median_filter_bottom",
220 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
221 },{
222 .strid = "video_chroma_median_filter_top",
223 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
224 },{
225 .strid = "video_chroma_median_filter_bottom",
226 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
227 }
228};
eca8ebfc 229#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 230
434449f4 231
d855497e 232static const char *control_values_srate[] = {
434449f4
MI		 233 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
234 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
235 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 236};
237
238
d855497e 239
d855497e
MI		 240static const char *control_values_input[] = {
241 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
29bf5b1d 242 [PVR2_CVAL_INPUT_DTV] = "dtv",
d855497e
MI		 243 [PVR2_CVAL_INPUT_RADIO] = "radio",
244 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
245 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
246};
247
248
249static const char *control_values_audiomode[] = {
250 [V4L2_TUNER_MODE_MONO] = "Mono",
251 [V4L2_TUNER_MODE_STEREO] = "Stereo",
252 [V4L2_TUNER_MODE_LANG1] = "Lang1",
253 [V4L2_TUNER_MODE_LANG2] = "Lang2",
254 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
255};
256
257
258static const char *control_values_hsm[] = {
259 [PVR2_CVAL_HSM_FAIL] = "Fail",
260 [PVR2_CVAL_HSM_HIGH] = "High",
261 [PVR2_CVAL_HSM_FULL] = "Full",
262};
263
264
681c7399
MI		 265static const char *pvr2_state_names[] = {
266 [PVR2_STATE_NONE] = "none",
267 [PVR2_STATE_DEAD] = "dead",
268 [PVR2_STATE_COLD] = "cold",
269 [PVR2_STATE_WARM] = "warm",
270 [PVR2_STATE_ERROR] = "error",
271 [PVR2_STATE_READY] = "ready",
272 [PVR2_STATE_RUN] = "run",
d855497e
MI		 273};
274
681c7399 275
694dca2b 276struct pvr2_fx2cmd_descdef {
1c9d10d4
MI		 277 unsigned char id;
278 unsigned char *desc;
279};
280
694dca2b 281static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
1c9d10d4
MI		 282 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
283 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
31335b13 284 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
1c9d10d4
MI		 285 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
286 {FX2CMD_REG_WRITE, "write encoder register"},
287 {FX2CMD_REG_READ, "read encoder register"},
288 {FX2CMD_MEMSEL, "encoder memsel"},
289 {FX2CMD_I2C_WRITE, "i2c write"},
290 {FX2CMD_I2C_READ, "i2c read"},
291 {FX2CMD_GET_USB_SPEED, "get USB speed"},
292 {FX2CMD_STREAMING_ON, "stream on"},
293 {FX2CMD_STREAMING_OFF, "stream off"},
294 {FX2CMD_FWPOST1, "fwpost1"},
295 {FX2CMD_POWER_OFF, "power off"},
296 {FX2CMD_POWER_ON, "power on"},
297 {FX2CMD_DEEP_RESET, "deep reset"},
298 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
299 {FX2CMD_GET_IR_CODE, "get IR code"},
300 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
301 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
302 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
303 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
304 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
305 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
306 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
307};
308
309
1cb03b76 310static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
681c7399
MI		 311static void pvr2_hdw_state_sched(struct pvr2_hdw *);
312static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 313static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399 314static void pvr2_hdw_worker_poll(struct work_struct *work);
681c7399
MI		 315static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
316static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
317static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 318static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 319static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 320static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 321static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
322static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
681c7399
MI		 323static void pvr2_hdw_quiescent_timeout(unsigned long);
324static void pvr2_hdw_encoder_wait_timeout(unsigned long);
d913d630 325static void pvr2_hdw_encoder_run_timeout(unsigned long);
1c9d10d4 326static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
07e337ee
AB		 327static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
328 unsigned int timeout,int probe_fl,
329 void *write_data,unsigned int write_len,
330 void *read_data,unsigned int read_len);
432907f7 331static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
d855497e 332
681c7399
MI		 333
334static void trace_stbit(const char *name,int val)
335{
336 pvr2_trace(PVR2_TRACE_STBITS,
337 "State bit %s <-- %s",
338 name,(val ? "true" : "false"));
339}
340
d855497e
MI		 341static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
342{
343 struct pvr2_hdw *hdw = cptr->hdw;
344 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
345 *vp = hdw->freqTable[hdw->freqProgSlot-1];
346 } else {
347 *vp = 0;
348 }
349 return 0;
350}
351
352static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
353{
354 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 355 unsigned int slotId = hdw->freqProgSlot;
356 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
357 hdw->freqTable[slotId-1] = v;
358 /* Handle side effects correctly - if we're tuned to this
359 slot, then forgot the slot id relation since the stored
360 frequency has been changed. */
361 if (hdw->freqSelector) {
362 if (hdw->freqSlotRadio == slotId) {
363 hdw->freqSlotRadio = 0;
364 }
365 } else {
366 if (hdw->freqSlotTelevision == slotId) {
367 hdw->freqSlotTelevision = 0;
368 }
369 }
d855497e
MI		 370 }
371 return 0;
372}
373
374static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
375{
376 *vp = cptr->hdw->freqProgSlot;
377 return 0;
378}
379
380static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
381{
382 struct pvr2_hdw *hdw = cptr->hdw;
383 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
384 hdw->freqProgSlot = v;
385 }
386 return 0;
387}
388
389static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
390{
1bde0289
MI		 391 struct pvr2_hdw *hdw = cptr->hdw;
392 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 393 return 0;
394}
395
1bde0289 396static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 397{
398 unsigned freq = 0;
399 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 400 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
401 if (slotId > 0) {
402 freq = hdw->freqTable[slotId-1];
403 if (!freq) return 0;
404 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 405 }
1bde0289
MI		 406 if (hdw->freqSelector) {
407 hdw->freqSlotRadio = slotId;
408 } else {
409 hdw->freqSlotTelevision = slotId;
d855497e
MI		 410 }
411 return 0;
412}
413
414static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
415{
1bde0289 416 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 417 return 0;
418}
419
420static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
421{
422 return cptr->hdw->freqDirty != 0;
423}
424
425static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
426{
427 cptr->hdw->freqDirty = 0;
428}
429
430static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
431{
1bde0289 432 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 433 return 0;
434}
435
e784bfb9 436static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
437{
432907f7
MI		 438 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
439 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
440 if (stat != 0) {
432907f7 441 return stat;
e784bfb9 442 }
432907f7 443 *left = cap->bounds.left;
e784bfb9 444 return 0;
445}
446
447static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
448{
432907f7
MI		 449 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
450 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
451 if (stat != 0) {
432907f7
MI		 452 return stat;
453 }
454 *left = cap->bounds.left;
455 if (cap->bounds.width > cptr->hdw->cropw_val) {
432907f7 456 *left += cap->bounds.width - cptr->hdw->cropw_val;
e784bfb9 457 }
458 return 0;
459}
460
461static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
462{
432907f7
MI		 463 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
464 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
465 if (stat != 0) {
432907f7 466 return stat;
e784bfb9 467 }
432907f7 468 *top = cap->bounds.top;
e784bfb9 469 return 0;
470}
471
432907f7 472static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
3ad9fc37 473{
432907f7
MI		 474 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
475 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
476 if (stat != 0) {
432907f7
MI		 477 return stat;
478 }
479 *top = cap->bounds.top;
480 if (cap->bounds.height > cptr->hdw->croph_val) {
432907f7 481 *top += cap->bounds.height - cptr->hdw->croph_val;
3ad9fc37
MI		 482 }
483 return 0;
484}
485
432907f7
MI		 486static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
487{
488 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
489 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
490 if (stat != 0) {
432907f7
MI		 491 return stat;
492 }
493 *val = 0;
494 if (cap->bounds.width > cptr->hdw->cropl_val) {
432907f7
MI		 495 *val = cap->bounds.width - cptr->hdw->cropl_val;
496 }
497 return 0;
498}
499
500static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
501{
502 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
503 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
504 if (stat != 0) {
432907f7
MI		 505 return stat;
506 }
507 *val = 0;
508 if (cap->bounds.height > cptr->hdw->cropt_val) {
432907f7
MI		 509 *val = cap->bounds.height - cptr->hdw->cropt_val;
510 }
511 return 0;
512}
513
514static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
515{
516 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
517 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
518 if (stat != 0) {
432907f7
MI		 519 return stat;
520 }
521 *val = cap->bounds.left;
522 return 0;
523}
524
525static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
526{
527 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
528 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
529 if (stat != 0) {
432907f7
MI		 530 return stat;
531 }
532 *val = cap->bounds.top;
533 return 0;
534}
535
536static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
537{
538 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
539 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
540 if (stat != 0) {
432907f7
MI		 541 return stat;
542 }
543 *val = cap->bounds.width;
544 return 0;
545}
546
547static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
548{
549 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
550 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
551 if (stat != 0) {
432907f7
MI		 552 return stat;
553 }
554 *val = cap->bounds.height;
555 return 0;
556}
557
558static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
559{
560 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
561 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
562 if (stat != 0) {
432907f7
MI		 563 return stat;
564 }
565 *val = cap->defrect.left;
566 return 0;
567}
568
569static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
570{
571 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
572 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
573 if (stat != 0) {
432907f7
MI		 574 return stat;
575 }
576 *val = cap->defrect.top;
577 return 0;
578}
579
580static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
581{
582 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
583 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
584 if (stat != 0) {
432907f7
MI		 585 return stat;
586 }
587 *val = cap->defrect.width;
588 return 0;
589}
590
591static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
592{
593 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
594 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
595 if (stat != 0) {
432907f7
MI		 596 return stat;
597 }
598 *val = cap->defrect.height;
599 return 0;
600}
601
602static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
603{
604 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
605 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
606 if (stat != 0) {
432907f7
MI		 607 return stat;
608 }
609 *val = cap->pixelaspect.numerator;
610 return 0;
611}
612
613static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
614{
615 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
616 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
617 if (stat != 0) {
432907f7
MI		 618 return stat;
619 }
620 *val = cap->pixelaspect.denominator;
621 return 0;
622}
623
624static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
e784bfb9 625{
432907f7
MI		 626 /* Actual maximum depends on the video standard in effect. */
627 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
628 *vp = 480;
e784bfb9 629 } else {
432907f7 630 *vp = 576;
e784bfb9 631 }
632 return 0;
633}
634
3ad9fc37
MI		 635static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
636{
989eb154
MI		 637 /* Actual minimum depends on device digitizer type. */
638 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 639 *vp = 75;
640 } else {
641 *vp = 17;
642 }
643 return 0;
644}
645
1bde0289 646static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 647{
1bde0289
MI		 648 *vp = cptr->hdw->input_val;
649 return 0;
650}
651
29bf5b1d
MI		 652static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
653{
1cb03b76 654 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
29bf5b1d
MI		 655}
656
1bde0289
MI		 657static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
658{
1cb03b76 659 return pvr2_hdw_set_input(cptr->hdw,v);
1bde0289
MI		 660}
661
662static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
663{
664 return cptr->hdw->input_dirty != 0;
665}
666
667static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
668{
669 cptr->hdw->input_dirty = 0;
670}
671
5549f54f 672
25d8527a
PK		 673static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
674{
644afdb9
MI		 675 unsigned long fv;
676 struct pvr2_hdw *hdw = cptr->hdw;
677 if (hdw->tuner_signal_stale) {
a51f5000 678 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 679 }
680 fv = hdw->tuner_signal_info.rangehigh;
681 if (!fv) {
682 /* Safety fallback */
25d8527a 683 *vp = TV_MAX_FREQ;
644afdb9 684 return 0;
25d8527a 685 }
644afdb9
MI		 686 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
687 fv = (fv * 125) / 2;
688 } else {
689 fv = fv * 62500;
690 }
691 *vp = fv;
25d8527a
PK		 692 return 0;
693}
694
695static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
696{
644afdb9
MI		 697 unsigned long fv;
698 struct pvr2_hdw *hdw = cptr->hdw;
699 if (hdw->tuner_signal_stale) {
a51f5000 700 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 701 }
702 fv = hdw->tuner_signal_info.rangelow;
703 if (!fv) {
704 /* Safety fallback */
25d8527a 705 *vp = TV_MIN_FREQ;
644afdb9
MI		 706 return 0;
707 }
708 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
709 fv = (fv * 125) / 2;
710 } else {
711 fv = fv * 62500;
25d8527a 712 }
644afdb9 713 *vp = fv;
25d8527a
PK		 714 return 0;
715}
716
b30d2441
MI		 717static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
718{
719 return cptr->hdw->enc_stale != 0;
720}
721
722static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
723{
724 cptr->hdw->enc_stale = 0;
681c7399 725 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 726}
727
728static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
729{
730 int ret;
731 struct v4l2_ext_controls cs;
732 struct v4l2_ext_control c1;
733 memset(&cs,0,sizeof(cs));
734 memset(&c1,0,sizeof(c1));
735 cs.controls = &c1;
736 cs.count = 1;
737 c1.id = cptr->info->v4l_id;
01f1e44f 738 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 739 VIDIOC_G_EXT_CTRLS);
740 if (ret) return ret;
741 *vp = c1.value;
742 return 0;
743}
744
745static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
746{
747 int ret;
681c7399 748 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 749 struct v4l2_ext_controls cs;
750 struct v4l2_ext_control c1;
751 memset(&cs,0,sizeof(cs));
752 memset(&c1,0,sizeof(c1));
753 cs.controls = &c1;
754 cs.count = 1;
755 c1.id = cptr->info->v4l_id;
756 c1.value = v;
681c7399
MI		 757 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
758 hdw->state_encoder_run, &cs,
b30d2441 759 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 760 if (ret == -EBUSY) {
761 /* Oops. cx2341x is telling us it's not safe to change
762 this control while we're capturing. Make a note of this
763 fact so that the pipeline will be stopped the next time
764 controls are committed. Then go on ahead and store this
765 change anyway. */
766 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
767 0, &cs,
768 VIDIOC_S_EXT_CTRLS);
769 if (!ret) hdw->enc_unsafe_stale = !0;
770 }
b30d2441 771 if (ret) return ret;
681c7399 772 hdw->enc_stale = !0;
b30d2441
MI		 773 return 0;
774}
775
776static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
777{
778 struct v4l2_queryctrl qctrl;
779 struct pvr2_ctl_info *info;
780 qctrl.id = cptr->info->v4l_id;
781 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
782 /* Strip out the const so we can adjust a function pointer. It's
783 OK to do this here because we know this is a dynamically created
784 control, so the underlying storage for the info pointer is (a)
785 private to us, and (b) not in read-only storage. Either we do
786 this or we significantly complicate the underlying control
787 implementation. */
788 info = (struct pvr2_ctl_info *)(cptr->info);
789 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
790 if (info->set_value) {
a0fd1cb1 791 info->set_value = NULL;
b30d2441
MI		 792 }
793 } else {
794 if (!(info->set_value)) {
795 info->set_value = ctrl_cx2341x_set;
796 }
797 }
798 return qctrl.flags;
799}
800
d855497e
MI		 801static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
802{
681c7399
MI		 803 *vp = cptr->hdw->state_pipeline_req;
804 return 0;
805}
806
807static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
808{
809 *vp = cptr->hdw->master_state;
d855497e
MI		 810 return 0;
811}
812
813static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
814{
815 int result = pvr2_hdw_is_hsm(cptr->hdw);
816 *vp = PVR2_CVAL_HSM_FULL;
817 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
818 if (result) *vp = PVR2_CVAL_HSM_HIGH;
819 return 0;
820}
821
822static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
823{
824 *vp = cptr->hdw->std_mask_avail;
825 return 0;
826}
827
828static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
829{
830 struct pvr2_hdw *hdw = cptr->hdw;
831 v4l2_std_id ns;
832 ns = hdw->std_mask_avail;
833 ns = (ns & ~m) | (v & m);
834 if (ns == hdw->std_mask_avail) return 0;
835 hdw->std_mask_avail = ns;
836 pvr2_hdw_internal_set_std_avail(hdw);
837 pvr2_hdw_internal_find_stdenum(hdw);
838 return 0;
839}
840
841static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
842 char *bufPtr,unsigned int bufSize,
843 unsigned int *len)
844{
845 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
846 return 0;
847}
848
849static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
850 const char *bufPtr,unsigned int bufSize,
851 int *mskp,int *valp)
852{
853 int ret;
854 v4l2_std_id id;
855 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
856 if (ret < 0) return ret;
857 if (mskp) *mskp = id;
858 if (valp) *valp = id;
859 return 0;
860}
861
862static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
863{
864 *vp = cptr->hdw->std_mask_cur;
865 return 0;
866}
867
868static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
869{
870 struct pvr2_hdw *hdw = cptr->hdw;
871 v4l2_std_id ns;
872 ns = hdw->std_mask_cur;
873 ns = (ns & ~m) | (v & m);
874 if (ns == hdw->std_mask_cur) return 0;
875 hdw->std_mask_cur = ns;
876 hdw->std_dirty = !0;
877 pvr2_hdw_internal_find_stdenum(hdw);
878 return 0;
879}
880
881static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
882{
883 return cptr->hdw->std_dirty != 0;
884}
885
886static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
887{
888 cptr->hdw->std_dirty = 0;
889}
890
891static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
892{
18103c57 893 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 894 pvr2_hdw_status_poll(hdw);
18103c57
MI		 895 *vp = hdw->tuner_signal_info.signal;
896 return 0;
897}
898
899static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
900{
901 int val = 0;
902 unsigned int subchan;
903 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 904 pvr2_hdw_status_poll(hdw);
18103c57
MI		 905 subchan = hdw->tuner_signal_info.rxsubchans;
906 if (subchan & V4L2_TUNER_SUB_MONO) {
907 val |= (1 << V4L2_TUNER_MODE_MONO);
908 }
909 if (subchan & V4L2_TUNER_SUB_STEREO) {
910 val |= (1 << V4L2_TUNER_MODE_STEREO);
911 }
912 if (subchan & V4L2_TUNER_SUB_LANG1) {
913 val |= (1 << V4L2_TUNER_MODE_LANG1);
914 }
915 if (subchan & V4L2_TUNER_SUB_LANG2) {
916 val |= (1 << V4L2_TUNER_MODE_LANG2);
917 }
918 *vp = val;
d855497e
MI		 919 return 0;
920}
921
d855497e
MI		 922
923static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
924{
925 struct pvr2_hdw *hdw = cptr->hdw;
926 if (v < 0) return -EINVAL;
927 if (v > hdw->std_enum_cnt) return -EINVAL;
928 hdw->std_enum_cur = v;
929 if (!v) return 0;
930 v--;
931 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
932 hdw->std_mask_cur = hdw->std_defs[v].id;
933 hdw->std_dirty = !0;
934 return 0;
935}
936
937
938static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
939{
940 *vp = cptr->hdw->std_enum_cur;
941 return 0;
942}
943
944
945static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
946{
947 return cptr->hdw->std_dirty != 0;
948}
949
950
951static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
952{
953 cptr->hdw->std_dirty = 0;
954}
955
956
957#define DEFINT(vmin,vmax) \
958 .type = pvr2_ctl_int, \
959 .def.type_int.min_value = vmin, \
960 .def.type_int.max_value = vmax
961
962#define DEFENUM(tab) \
963 .type = pvr2_ctl_enum, \
27c7b710 964 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 965 .def.type_enum.value_names = tab
966
33213963
MI		 967#define DEFBOOL \
968 .type = pvr2_ctl_bool
969
d855497e
MI		 970#define DEFMASK(msk,tab) \
971 .type = pvr2_ctl_bitmask, \
972 .def.type_bitmask.valid_bits = msk, \
973 .def.type_bitmask.bit_names = tab
974
975#define DEFREF(vname) \
976 .set_value = ctrl_set_##vname, \
977 .get_value = ctrl_get_##vname, \
978 .is_dirty = ctrl_isdirty_##vname, \
979 .clear_dirty = ctrl_cleardirty_##vname
980
981
982#define VCREATE_FUNCS(vname) \
983static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
984{*vp = cptr->hdw->vname##_val; return 0;} \
985static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
986{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
987static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
988{return cptr->hdw->vname##_dirty != 0;} \
989static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
990{cptr->hdw->vname##_dirty = 0;}
991
992VCREATE_FUNCS(brightness)
993VCREATE_FUNCS(contrast)
994VCREATE_FUNCS(saturation)
995VCREATE_FUNCS(hue)
996VCREATE_FUNCS(volume)
997VCREATE_FUNCS(balance)
998VCREATE_FUNCS(bass)
999VCREATE_FUNCS(treble)
1000VCREATE_FUNCS(mute)
e784bfb9 1001VCREATE_FUNCS(cropl)
1002VCREATE_FUNCS(cropt)
1003VCREATE_FUNCS(cropw)
1004VCREATE_FUNCS(croph)
c05c0462
MI		 1005VCREATE_FUNCS(audiomode)
1006VCREATE_FUNCS(res_hor)
1007VCREATE_FUNCS(res_ver)
d855497e 1008VCREATE_FUNCS(srate)
d855497e 1009
d855497e
MI		 1010/* Table definition of all controls which can be manipulated */
1011static const struct pvr2_ctl_info control_defs[] = {
1012 {
1013 .v4l_id = V4L2_CID_BRIGHTNESS,
1014 .desc = "Brightness",
1015 .name = "brightness",
1016 .default_value = 128,
1017 DEFREF(brightness),
1018 DEFINT(0,255),
1019 },{
1020 .v4l_id = V4L2_CID_CONTRAST,
1021 .desc = "Contrast",
1022 .name = "contrast",
1023 .default_value = 68,
1024 DEFREF(contrast),
1025 DEFINT(0,127),
1026 },{
1027 .v4l_id = V4L2_CID_SATURATION,
1028 .desc = "Saturation",
1029 .name = "saturation",
1030 .default_value = 64,
1031 DEFREF(saturation),
1032 DEFINT(0,127),
1033 },{
1034 .v4l_id = V4L2_CID_HUE,
1035 .desc = "Hue",
1036 .name = "hue",
1037 .default_value = 0,
1038 DEFREF(hue),
1039 DEFINT(-128,127),
1040 },{
1041 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1042 .desc = "Volume",
1043 .name = "volume",
139eecf9 1044 .default_value = 62000,
d855497e
MI		 1045 DEFREF(volume),
1046 DEFINT(0,65535),
1047 },{
1048 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1049 .desc = "Balance",
1050 .name = "balance",
1051 .default_value = 0,
1052 DEFREF(balance),
1053 DEFINT(-32768,32767),
1054 },{
1055 .v4l_id = V4L2_CID_AUDIO_BASS,
1056 .desc = "Bass",
1057 .name = "bass",
1058 .default_value = 0,
1059 DEFREF(bass),
1060 DEFINT(-32768,32767),
1061 },{
1062 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1063 .desc = "Treble",
1064 .name = "treble",
1065 .default_value = 0,
1066 DEFREF(treble),
1067 DEFINT(-32768,32767),
1068 },{
1069 .v4l_id = V4L2_CID_AUDIO_MUTE,
1070 .desc = "Mute",
1071 .name = "mute",
1072 .default_value = 0,
1073 DEFREF(mute),
33213963 1074 DEFBOOL,
e784bfb9 1075 }, {
432907f7 1076 .desc = "Capture crop left margin",
e784bfb9 1077 .name = "crop_left",
1078 .internal_id = PVR2_CID_CROPL,
1079 .default_value = 0,
1080 DEFREF(cropl),
1081 DEFINT(-129, 340),
1082 .get_min_value = ctrl_cropl_min_get,
1083 .get_max_value = ctrl_cropl_max_get,
432907f7 1084 .get_def_value = ctrl_get_cropcapdl,
e784bfb9 1085 }, {
432907f7 1086 .desc = "Capture crop top margin",
e784bfb9 1087 .name = "crop_top",
1088 .internal_id = PVR2_CID_CROPT,
1089 .default_value = 0,
1090 DEFREF(cropt),
1091 DEFINT(-35, 544),
1092 .get_min_value = ctrl_cropt_min_get,
1093 .get_max_value = ctrl_cropt_max_get,
432907f7 1094 .get_def_value = ctrl_get_cropcapdt,
e784bfb9 1095 }, {
432907f7 1096 .desc = "Capture crop width",
e784bfb9 1097 .name = "crop_width",
1098 .internal_id = PVR2_CID_CROPW,
1099 .default_value = 720,
1100 DEFREF(cropw),
432907f7
MI		 1101 .get_max_value = ctrl_cropw_max_get,
1102 .get_def_value = ctrl_get_cropcapdw,
e784bfb9 1103 }, {
432907f7 1104 .desc = "Capture crop height",
e784bfb9 1105 .name = "crop_height",
1106 .internal_id = PVR2_CID_CROPH,
1107 .default_value = 480,
1108 DEFREF(croph),
432907f7
MI		 1109 .get_max_value = ctrl_croph_max_get,
1110 .get_def_value = ctrl_get_cropcapdh,
1111 }, {
1112 .desc = "Capture capability pixel aspect numerator",
1113 .name = "cropcap_pixel_numerator",
1114 .internal_id = PVR2_CID_CROPCAPPAN,
1115 .get_value = ctrl_get_cropcappan,
1116 }, {
1117 .desc = "Capture capability pixel aspect denominator",
1118 .name = "cropcap_pixel_denominator",
1119 .internal_id = PVR2_CID_CROPCAPPAD,
1120 .get_value = ctrl_get_cropcappad,
1121 }, {
1122 .desc = "Capture capability bounds top",
1123 .name = "cropcap_bounds_top",
1124 .internal_id = PVR2_CID_CROPCAPBT,
1125 .get_value = ctrl_get_cropcapbt,
1126 }, {
1127 .desc = "Capture capability bounds left",
1128 .name = "cropcap_bounds_left",
1129 .internal_id = PVR2_CID_CROPCAPBL,
1130 .get_value = ctrl_get_cropcapbl,
1131 }, {
1132 .desc = "Capture capability bounds width",
1133 .name = "cropcap_bounds_width",
1134 .internal_id = PVR2_CID_CROPCAPBW,
1135 .get_value = ctrl_get_cropcapbw,
1136 }, {
1137 .desc = "Capture capability bounds height",
1138 .name = "cropcap_bounds_height",
1139 .internal_id = PVR2_CID_CROPCAPBH,
1140 .get_value = ctrl_get_cropcapbh,
c05c0462
MI		 1141 },{
1142 .desc = "Video Source",
1143 .name = "input",
1144 .internal_id = PVR2_CID_INPUT,
1145 .default_value = PVR2_CVAL_INPUT_TV,
29bf5b1d 1146 .check_value = ctrl_check_input,
c05c0462
MI		 1147 DEFREF(input),
1148 DEFENUM(control_values_input),
1149 },{
1150 .desc = "Audio Mode",
1151 .name = "audio_mode",
1152 .internal_id = PVR2_CID_AUDIOMODE,
1153 .default_value = V4L2_TUNER_MODE_STEREO,
1154 DEFREF(audiomode),
1155 DEFENUM(control_values_audiomode),
1156 },{
1157 .desc = "Horizontal capture resolution",
1158 .name = "resolution_hor",
1159 .internal_id = PVR2_CID_HRES,
1160 .default_value = 720,
1161 DEFREF(res_hor),
3ad9fc37 1162 DEFINT(19,720),
c05c0462
MI		 1163 },{
1164 .desc = "Vertical capture resolution",
1165 .name = "resolution_ver",
1166 .internal_id = PVR2_CID_VRES,
1167 .default_value = 480,
1168 DEFREF(res_ver),
3ad9fc37
MI		 1169 DEFINT(17,576),
1170 /* Hook in check for video standard and adjust maximum
1171 depending on the standard. */
1172 .get_max_value = ctrl_vres_max_get,
1173 .get_min_value = ctrl_vres_min_get,
d855497e 1174 },{
b30d2441 1175 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 1176 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1177 .desc = "Audio Sampling Frequency",
d855497e 1178 .name = "srate",
d855497e
MI		 1179 DEFREF(srate),
1180 DEFENUM(control_values_srate),
d855497e
MI		 1181 },{
1182 .desc = "Tuner Frequency (Hz)",
1183 .name = "frequency",
1184 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 1185 .default_value = 0,
d855497e
MI		 1186 .set_value = ctrl_freq_set,
1187 .get_value = ctrl_freq_get,
1188 .is_dirty = ctrl_freq_is_dirty,
1189 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 1190 DEFINT(0,0),
25d8527a
PK		 1191 /* Hook in check for input value (tv/radio) and adjust
1192 max/min values accordingly */
1193 .get_max_value = ctrl_freq_max_get,
1194 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1195 },{
1196 .desc = "Channel",
1197 .name = "channel",
1198 .set_value = ctrl_channel_set,
1199 .get_value = ctrl_channel_get,
1200 DEFINT(0,FREQTABLE_SIZE),
1201 },{
1202 .desc = "Channel Program Frequency",
1203 .name = "freq_table_value",
1204 .set_value = ctrl_channelfreq_set,
1205 .get_value = ctrl_channelfreq_get,
644afdb9 1206 DEFINT(0,0),
1bde0289
MI		 1207 /* Hook in check for input value (tv/radio) and adjust
1208 max/min values accordingly */
1bde0289
MI		 1209 .get_max_value = ctrl_freq_max_get,
1210 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1211 },{
1212 .desc = "Channel Program ID",
1213 .name = "freq_table_channel",
1214 .set_value = ctrl_channelprog_set,
1215 .get_value = ctrl_channelprog_get,
1216 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 1217 },{
1218 .desc = "Streaming Enabled",
1219 .name = "streaming_enabled",
1220 .get_value = ctrl_streamingenabled_get,
33213963 1221 DEFBOOL,
d855497e
MI		 1222 },{
1223 .desc = "USB Speed",
1224 .name = "usb_speed",
1225 .get_value = ctrl_hsm_get,
1226 DEFENUM(control_values_hsm),
681c7399
MI		 1227 },{
1228 .desc = "Master State",
1229 .name = "master_state",
1230 .get_value = ctrl_masterstate_get,
1231 DEFENUM(pvr2_state_names),
d855497e
MI		 1232 },{
1233 .desc = "Signal Present",
1234 .name = "signal_present",
1235 .get_value = ctrl_signal_get,
18103c57
MI		 1236 DEFINT(0,65535),
1237 },{
1238 .desc = "Audio Modes Present",
1239 .name = "audio_modes_present",
1240 .get_value = ctrl_audio_modes_present_get,
1241 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1242 v4l. Nothing outside of this module cares about this,
1243 but I reuse it in order to also reuse the
1244 control_values_audiomode string table. */
1245 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1246 (1 << V4L2_TUNER_MODE_STEREO)|
1247 (1 << V4L2_TUNER_MODE_LANG1)|
1248 (1 << V4L2_TUNER_MODE_LANG2)),
1249 control_values_audiomode),
d855497e
MI		 1250 },{
1251 .desc = "Video Standards Available Mask",
1252 .name = "video_standard_mask_available",
1253 .internal_id = PVR2_CID_STDAVAIL,
1254 .skip_init = !0,
1255 .get_value = ctrl_stdavail_get,
1256 .set_value = ctrl_stdavail_set,
1257 .val_to_sym = ctrl_std_val_to_sym,
1258 .sym_to_val = ctrl_std_sym_to_val,
1259 .type = pvr2_ctl_bitmask,
1260 },{
1261 .desc = "Video Standards In Use Mask",
1262 .name = "video_standard_mask_active",
1263 .internal_id = PVR2_CID_STDCUR,
1264 .skip_init = !0,
1265 .get_value = ctrl_stdcur_get,
1266 .set_value = ctrl_stdcur_set,
1267 .is_dirty = ctrl_stdcur_is_dirty,
1268 .clear_dirty = ctrl_stdcur_clear_dirty,
1269 .val_to_sym = ctrl_std_val_to_sym,
1270 .sym_to_val = ctrl_std_sym_to_val,
1271 .type = pvr2_ctl_bitmask,
d855497e
MI		 1272 },{
1273 .desc = "Video Standard Name",
1274 .name = "video_standard",
1275 .internal_id = PVR2_CID_STDENUM,
1276 .skip_init = !0,
1277 .get_value = ctrl_stdenumcur_get,
1278 .set_value = ctrl_stdenumcur_set,
1279 .is_dirty = ctrl_stdenumcur_is_dirty,
1280 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1281 .type = pvr2_ctl_enum,
1282 }
1283};
1284
eca8ebfc 1285#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 1286
1287
1288const char *pvr2_config_get_name(enum pvr2_config cfg)
1289{
1290 switch (cfg) {
1291 case pvr2_config_empty: return "empty";
1292 case pvr2_config_mpeg: return "mpeg";
1293 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 1294 case pvr2_config_pcm: return "pcm";
1295 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 1296 }
1297 return "<unknown>";
1298}
1299
1300
1301struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1302{
1303 return hdw->usb_dev;
1304}
1305
1306
1307unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1308{
1309 return hdw->serial_number;
1310}
1311
31a18547
MI		 1312
1313const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1314{
1315 return hdw->bus_info;
1316}
1317
1318
13a88797
MI		 1319const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1320{
1321 return hdw->identifier;
1322}
1323
1324
1bde0289
MI		 1325unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1326{
1327 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1328}
1329
1330/* Set the currently tuned frequency and account for all possible
1331 driver-core side effects of this action. */
f55a8712 1332static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1bde0289 1333{
7c74e57e 1334 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 1335 if (hdw->freqSelector) {
1336 /* Swing over to radio frequency selection */
1337 hdw->freqSelector = 0;
1338 hdw->freqDirty = !0;
1339 }
1bde0289
MI		 1340 if (hdw->freqValRadio != val) {
1341 hdw->freqValRadio = val;
1342 hdw->freqSlotRadio = 0;
7c74e57e 1343 hdw->freqDirty = !0;
1bde0289 1344 }
7c74e57e 1345 } else {
1bde0289
MI		 1346 if (!(hdw->freqSelector)) {
1347 /* Swing over to television frequency selection */
1348 hdw->freqSelector = 1;
1349 hdw->freqDirty = !0;
1350 }
1bde0289
MI		 1351 if (hdw->freqValTelevision != val) {
1352 hdw->freqValTelevision = val;
1353 hdw->freqSlotTelevision = 0;
7c74e57e 1354 hdw->freqDirty = !0;
1bde0289 1355 }
1bde0289
MI		 1356 }
1357}
1358
d855497e
MI		 1359int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1360{
1361 return hdw->unit_number;
1362}
1363
1364
1365/* Attempt to locate one of the given set of files. Messages are logged
1366 appropriate to what has been found. The return value will be 0 or
1367 greater on success (it will be the index of the file name found) and
1368 fw_entry will be filled in. Otherwise a negative error is returned on
1369 failure. If the return value is -ENOENT then no viable firmware file
1370 could be located. */
1371static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1372 const struct firmware **fw_entry,
1373 const char *fwtypename,
1374 unsigned int fwcount,
1375 const char *fwnames[])
1376{
1377 unsigned int idx;
1378 int ret = -EINVAL;
1379 for (idx = 0; idx < fwcount; idx++) {
1380 ret = request_firmware(fw_entry,
1381 fwnames[idx],
1382 &hdw->usb_dev->dev);
1383 if (!ret) {
1384 trace_firmware("Located %s firmware: %s;"
1385 " uploading...",
1386 fwtypename,
1387 fwnames[idx]);
1388 return idx;
1389 }
1390 if (ret == -ENOENT) continue;
1391 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1392 "request_firmware fatal error with code=%d",ret);
1393 return ret;
1394 }
1395 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1396 "***WARNING***"
1397 " Device %s firmware"
1398 " seems to be missing.",
1399 fwtypename);
1400 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1401 "Did you install the pvrusb2 firmware files"
1402 " in their proper location?");
1403 if (fwcount == 1) {
1404 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1405 "request_firmware unable to locate %s file %s",
1406 fwtypename,fwnames[0]);
1407 } else {
1408 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1409 "request_firmware unable to locate"
1410 " one of the following %s files:",
1411 fwtypename);
1412 for (idx = 0; idx < fwcount; idx++) {
1413 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1414 "request_firmware: Failed to find %s",
1415 fwnames[idx]);
1416 }
1417 }
1418 return ret;
1419}
1420
1421
1422/*
1423 * pvr2_upload_firmware1().
1424 *
1425 * Send the 8051 firmware to the device. After the upload, arrange for
1426 * device to re-enumerate.
1427 *
1428 * NOTE : the pointer to the firmware data given by request_firmware()
1429 * is not suitable for an usb transaction.
1430 *
1431 */
07e337ee 1432static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1433{
a0fd1cb1 1434 const struct firmware *fw_entry = NULL;
d855497e
MI		 1435 void *fw_ptr;
1436 unsigned int pipe;
1437 int ret;
1438 u16 address;
1d643a37 1439
989eb154 1440 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1441 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1442 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1443 "Connected device type defines"
1444 " no firmware to upload; ignoring firmware");
1445 return -ENOTTY;
1d643a37
MI		 1446 }
1447
d855497e
MI		 1448 hdw->fw1_state = FW1_STATE_FAILED; // default result
1449
1450 trace_firmware("pvr2_upload_firmware1");
1451
1452 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1453 hdw->hdw_desc->fx2_firmware.cnt,
1454 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1455 if (ret < 0) {
1456 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1457 return ret;
1458 }
1459
1460 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1461 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1462
1463 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1464
1465 if (fw_entry->size != 0x2000){
1466 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1467 release_firmware(fw_entry);
1468 return -ENOMEM;
1469 }
1470
1471 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1472 if (fw_ptr == NULL){
1473 release_firmware(fw_entry);
1474 return -ENOMEM;
1475 }
1476
1477 /* We have to hold the CPU during firmware upload. */
1478 pvr2_hdw_cpureset_assert(hdw,1);
1479
1480 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1481 chunk. */
1482
1483 ret = 0;
1484 for(address = 0; address < fw_entry->size; address += 0x800) {
1485 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1486 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1487 0, fw_ptr, 0x800, HZ);
1488 }
1489
1490 trace_firmware("Upload done, releasing device's CPU");
1491
1492 /* Now release the CPU. It will disconnect and reconnect later. */
1493 pvr2_hdw_cpureset_assert(hdw,0);
1494
1495 kfree(fw_ptr);
1496 release_firmware(fw_entry);
1497
1498 trace_firmware("Upload done (%d bytes sent)",ret);
1499
1500 /* We should have written 8192 bytes */
1501 if (ret == 8192) {
1502 hdw->fw1_state = FW1_STATE_RELOAD;
1503 return 0;
1504 }
1505
1506 return -EIO;
1507}
1508
1509
1510/*
1511 * pvr2_upload_firmware2()
1512 *
1513 * This uploads encoder firmware on endpoint 2.
1514 *
1515 */
1516
1517int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1518{
a0fd1cb1 1519 const struct firmware *fw_entry = NULL;
d855497e 1520 void *fw_ptr;
90060d32 1521 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1522 int actual_length;
1523 int ret = 0;
1524 int fwidx;
1525 static const char *fw_files[] = {
1526 CX2341X_FIRM_ENC_FILENAME,
1527 };
1528
989eb154 1529 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1530 return 0;
1531 }
1532
d855497e
MI		 1533 trace_firmware("pvr2_upload_firmware2");
1534
1535 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1536 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1537 if (ret < 0) return ret;
1538 fwidx = ret;
1539 ret = 0;
b30d2441
MI		 1540 /* Since we're about to completely reinitialize the encoder,
1541 invalidate our cached copy of its configuration state. Next
1542 time we configure the encoder, then we'll fully configure it. */
1543 hdw->enc_cur_valid = 0;
d855497e 1544
d913d630
MI		 1545 /* Encoder is about to be reset so note that as far as we're
1546 concerned now, the encoder has never been run. */
1547 del_timer_sync(&hdw->encoder_run_timer);
1548 if (hdw->state_encoder_runok) {
1549 hdw->state_encoder_runok = 0;
1550 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1551 }
1552
d855497e
MI		 1553 /* First prepare firmware loading */
1554 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1555 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1556 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1557 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1558 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1559 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1560 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1561 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1562 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1563 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1564 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1565 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1566 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1567 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1568 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1569 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1c9d10d4
MI		 1570 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1571 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1572
1573 if (ret) {
1574 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1575 "firmware2 upload prep failed, ret=%d",ret);
1576 release_firmware(fw_entry);
21684ba9 1577 goto done;
d855497e
MI		 1578 }
1579
1580 /* Now send firmware */
1581
1582 fw_len = fw_entry->size;
1583
90060d32 1584 if (fw_len % sizeof(u32)) {
d855497e
MI		 1585 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1586 "size of %s firmware"
48dc30a1 1587 " must be a multiple of %zu bytes",
90060d32 1588 fw_files[fwidx],sizeof(u32));
d855497e 1589 release_firmware(fw_entry);
21684ba9
MI		 1590 ret = -EINVAL;
1591 goto done;
d855497e
MI		 1592 }
1593
1594 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1595 if (fw_ptr == NULL){
1596 release_firmware(fw_entry);
1597 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1598 "failed to allocate memory for firmware2 upload");
21684ba9
MI		 1599 ret = -ENOMEM;
1600 goto done;
d855497e
MI		 1601 }
1602
1603 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1604
90060d32
MI		 1605 fw_done = 0;
1606 for (fw_done = 0; fw_done < fw_len;) {
1607 bcnt = fw_len - fw_done;
1608 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1609 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1610 /* Usbsnoop log shows that we must swap bytes... */
5f33df14
MI		 1611 /* Some background info: The data being swapped here is a
1612 firmware image destined for the mpeg encoder chip that
1613 lives at the other end of a USB endpoint. The encoder
1614 chip always talks in 32 bit chunks and its storage is
1615 organized into 32 bit words. However from the file
1616 system to the encoder chip everything is purely a byte
1617 stream. The firmware file's contents are always 32 bit
1618 swapped from what the encoder expects. Thus the need
1619 always exists to swap the bytes regardless of the endian
1620 type of the host processor and therefore swab32() makes
1621 the most sense. */
90060d32 1622 for (icnt = 0; icnt < bcnt/4 ; icnt++)
513edce6 1623 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
90060d32
MI		 1624
1625 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1626 &actual_length, HZ);
90060d32
MI		 1627 ret |= (actual_length != bcnt);
1628 if (ret) break;
1629 fw_done += bcnt;
d855497e
MI		 1630 }
1631
1632 trace_firmware("upload of %s : %i / %i ",
1633 fw_files[fwidx],fw_done,fw_len);
1634
1635 kfree(fw_ptr);
1636 release_firmware(fw_entry);
1637
1638 if (ret) {
1639 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1640 "firmware2 upload transfer failure");
21684ba9 1641 goto done;
d855497e
MI		 1642 }
1643
1644 /* Finish upload */
1645
1646 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1647 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1c9d10d4 1648 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1649
1650 if (ret) {
1651 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1652 "firmware2 upload post-proc failure");
d855497e 1653 }
21684ba9
MI		 1654
1655 done:
1df59f0b
MI		 1656 if (hdw->hdw_desc->signal_routing_scheme ==
1657 PVR2_ROUTING_SCHEME_GOTVIEW) {
1658 /* Ensure that GPIO 11 is set to output for GOTVIEW
1659 hardware. */
1660 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1661 }
d855497e
MI		 1662 return ret;
1663}
1664
1665
681c7399
MI		 1666static const char *pvr2_get_state_name(unsigned int st)
1667{
1668 if (st < ARRAY_SIZE(pvr2_state_names)) {
1669 return pvr2_state_names[st];
d855497e 1670 }
681c7399 1671 return "???";
d855497e
MI		 1672}
1673
681c7399 1674static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1675{
af78e16b
MI		 1676 /* Even though we really only care about the video decoder chip at
1677 this point, we'll broadcast stream on/off to all sub-devices
1678 anyway, just in case somebody else wants to hear the
1679 command... */
e260508d
MI		 1680 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1681 (enablefl ? "on" : "off"));
af78e16b
MI		 1682 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1683 if (hdw->decoder_client_id) {
1684 /* We get here if the encoder has been noticed. Otherwise
1685 we'll issue a warning to the user (which should
1686 normally never happen). */
1687 return 0;
1688 }
1689 if (!hdw->flag_decoder_missed) {
1690 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1691 "WARNING: No decoder present");
1692 hdw->flag_decoder_missed = !0;
1693 trace_stbit("flag_decoder_missed",
1694 hdw->flag_decoder_missed);
1695 }
1696 return -EIO;
d855497e
MI		 1697}
1698
1699
681c7399 1700int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1701{
681c7399 1702 return hdw->master_state;
d855497e
MI		 1703}
1704
1705
681c7399 1706static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1707{
681c7399
MI		 1708 if (!hdw->flag_tripped) return 0;
1709 hdw->flag_tripped = 0;
1710 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1711 "Clearing driver error statuss");
1712 return !0;
d855497e
MI		 1713}
1714
1715
681c7399 1716int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1717{
681c7399 1718 int fl;
d855497e 1719 LOCK_TAKE(hdw->big_lock); do {
681c7399 1720 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1721 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1722 if (fl) pvr2_hdw_state_sched(hdw);
1723 return 0;
d855497e
MI		 1724}
1725
1726
d855497e
MI		 1727
1728
1729int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1730{
681c7399 1731 return hdw->state_pipeline_req != 0;
d855497e
MI		 1732}
1733
1734
1735int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1736{
681c7399 1737 int ret,st;
d855497e 1738 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1739 pvr2_hdw_untrip_unlocked(hdw);
1740 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1741 hdw->state_pipeline_req = enable_flag != 0;
1742 pvr2_trace(PVR2_TRACE_START_STOP,
1743 "/*--TRACE_STREAM--*/ %s",
1744 enable_flag ? "enable" : "disable");
1745 }
1746 pvr2_hdw_state_sched(hdw);
d855497e 1747 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1748 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1749 if (enable_flag) {
1750 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1751 if (st != PVR2_STATE_READY) return -EIO;
1752 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1753 }
1754 }
d855497e
MI		 1755 return 0;
1756}
1757
1758
1759int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1760{
681c7399 1761 int fl;
d855497e 1762 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1763 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1764 hdw->desired_stream_type = config;
1765 hdw->state_pipeline_config = 0;
1766 trace_stbit("state_pipeline_config",
1767 hdw->state_pipeline_config);
1768 pvr2_hdw_state_sched(hdw);
1769 }
d855497e 1770 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1771 if (fl) return 0;
1772 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1773}
1774
1775
1776static int get_default_tuner_type(struct pvr2_hdw *hdw)
1777{
1778 int unit_number = hdw->unit_number;
1779 int tp = -1;
1780 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1781 tp = tuner[unit_number];
1782 }
1783 if (tp < 0) return -EINVAL;
1784 hdw->tuner_type = tp;
aaf7884d 1785 hdw->tuner_updated = !0;
d855497e
MI		 1786 return 0;
1787}
1788
1789
1790static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1791{
1792 int unit_number = hdw->unit_number;
1793 int tp = 0;
1794 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1795 tp = video_std[unit_number];
6a540254 1796 if (tp) return tp;
d855497e 1797 }
6a540254 1798 return 0;
d855497e
MI		 1799}
1800
1801
1802static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1803{
1804 int unit_number = hdw->unit_number;
1805 int tp = 0;
1806 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1807 tp = tolerance[unit_number];
1808 }
1809 return tp;
1810}
1811
1812
1813static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1814{
1815 /* Try a harmless request to fetch the eeprom's address over
1816 endpoint 1. See what happens. Only the full FX2 image can
1817 respond to this. If this probe fails then likely the FX2
1818 firmware needs be loaded. */
1819 int result;
1820 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1821 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1822 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1823 hdw->cmd_buffer,1,
1824 hdw->cmd_buffer,1);
1825 if (result < 0) break;
1826 } while(0); LOCK_GIVE(hdw->ctl_lock);
1827 if (result) {
1828 pvr2_trace(PVR2_TRACE_INIT,
1829 "Probe of device endpoint 1 result status %d",
1830 result);
1831 } else {
1832 pvr2_trace(PVR2_TRACE_INIT,
1833 "Probe of device endpoint 1 succeeded");
1834 }
1835 return result == 0;
1836}
1837
9f66d4ea
MI		 1838struct pvr2_std_hack {
1839 v4l2_std_id pat; /* Pattern to match */
1840 v4l2_std_id msk; /* Which bits we care about */
1841 v4l2_std_id std; /* What additional standards or default to set */
1842};
1843
1844/* This data structure labels specific combinations of standards from
1845 tveeprom that we'll try to recognize. If we recognize one, then assume
1846 a specified default standard to use. This is here because tveeprom only
1847 tells us about available standards not the intended default standard (if
1848 any) for the device in question. We guess the default based on what has
1849 been reported as available. Note that this is only for guessing a
1850 default - which can always be overridden explicitly - and if the user
1851 has otherwise named a default then that default will always be used in
1852 place of this table. */
ebff0330 1853static const struct pvr2_std_hack std_eeprom_maps[] = {
9f66d4ea
MI		 1854 { /* PAL(B/G) */
1855 .pat = V4L2_STD_B|V4L2_STD_GH,
1856 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1857 },
1858 { /* NTSC(M) */
1859 .pat = V4L2_STD_MN,
1860 .std = V4L2_STD_NTSC_M,
1861 },
1862 { /* PAL(I) */
1863 .pat = V4L2_STD_PAL_I,
1864 .std = V4L2_STD_PAL_I,
1865 },
1866 { /* SECAM(L/L') */
1867 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1868 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1869 },
1870 { /* PAL(D/D1/K) */
1871 .pat = V4L2_STD_DK,
ea2562d9 1872 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
9f66d4ea
MI		 1873 },
1874};
1875
d855497e
MI		 1876static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1877{
1878 char buf[40];
1879 unsigned int bcnt;
3d290bdb 1880 v4l2_std_id std1,std2,std3;
d855497e
MI		 1881
1882 std1 = get_default_standard(hdw);
3d290bdb 1883 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
d855497e
MI		 1884
1885 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1886 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1887 "Supported video standard(s) reported available"
1888 " in hardware: %.*s",
d855497e
MI		 1889 bcnt,buf);
1890
1891 hdw->std_mask_avail = hdw->std_mask_eeprom;
1892
3d290bdb 1893 std2 = (std1|std3) & ~hdw->std_mask_avail;
d855497e
MI		 1894 if (std2) {
1895 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1896 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1897 "Expanding supported video standards"
1898 " to include: %.*s",
1899 bcnt,buf);
1900 hdw->std_mask_avail |= std2;
1901 }
1902
1903 pvr2_hdw_internal_set_std_avail(hdw);
1904
1905 if (std1) {
1906 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1907 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1908 "Initial video standard forced to %.*s",
1909 bcnt,buf);
1910 hdw->std_mask_cur = std1;
1911 hdw->std_dirty = !0;
1912 pvr2_hdw_internal_find_stdenum(hdw);
1913 return;
1914 }
3d290bdb
MI		 1915 if (std3) {
1916 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1917 pvr2_trace(PVR2_TRACE_STD,
1918 "Initial video standard"
1919 " (determined by device type): %.*s",bcnt,buf);
1920 hdw->std_mask_cur = std3;
1921 hdw->std_dirty = !0;
1922 pvr2_hdw_internal_find_stdenum(hdw);
1923 return;
1924 }
d855497e 1925
9f66d4ea
MI		 1926 {
1927 unsigned int idx;
1928 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1929 if (std_eeprom_maps[idx].msk ?
1930 ((std_eeprom_maps[idx].pat ^
1931 hdw->std_mask_eeprom) &
1932 std_eeprom_maps[idx].msk) :
1933 (std_eeprom_maps[idx].pat !=
1934 hdw->std_mask_eeprom)) continue;
1935 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1936 std_eeprom_maps[idx].std);
56585386 1937 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1938 "Initial video standard guessed as %.*s",
1939 bcnt,buf);
1940 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1941 hdw->std_dirty = !0;
1942 pvr2_hdw_internal_find_stdenum(hdw);
1943 return;
1944 }
1945 }
1946
d855497e
MI		 1947 if (hdw->std_enum_cnt > 1) {
1948 // Autoselect the first listed standard
1949 hdw->std_enum_cur = 1;
1950 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1951 hdw->std_dirty = !0;
56585386 1952 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1953 "Initial video standard auto-selected to %s",
1954 hdw->std_defs[hdw->std_enum_cur-1].name);
1955 return;
1956 }
1957
0885ba1d 1958 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1959 "Unable to select a viable initial video standard");
1960}
1961
1962
e9c64a78
MI		 1963static unsigned int pvr2_copy_i2c_addr_list(
1964 unsigned short *dst, const unsigned char *src,
1965 unsigned int dst_max)
1966{
3ab8d295 1967 unsigned int cnt = 0;
e9c64a78
MI		 1968 if (!src) return 0;
1969 while (src[cnt] && (cnt + 1) < dst_max) {
1970 dst[cnt] = src[cnt];
1971 cnt++;
1972 }
1973 dst[cnt] = I2C_CLIENT_END;
1974 return cnt;
1975}
1976
1977
1ab5e74f
MI		 1978static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1979 const struct pvr2_device_client_desc *cd)
e9c64a78
MI		 1980{
1981 const char *fname;
1982 unsigned char mid;
1983 struct v4l2_subdev *sd;
1984 unsigned int i2ccnt;
1985 const unsigned char *p;
1986 /* Arbitrary count - max # i2c addresses we will probe */
1987 unsigned short i2caddr[25];
1988
1989 mid = cd->module_id;
1990 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
1991 if (!fname) {
1992 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f 1993 "Module ID %u for device %s has no name",
e9c64a78
MI		 1994 mid,
1995 hdw->hdw_desc->description);
1ab5e74f 1996 return -EINVAL;
e9c64a78 1997 }
bd14d4f8
MI		 1998 pvr2_trace(PVR2_TRACE_INIT,
1999 "Module ID %u (%s) for device %s being loaded...",
2000 mid, fname,
2001 hdw->hdw_desc->description);
e9c64a78
MI		 2002
2003 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2004 ARRAY_SIZE(i2caddr));
2005 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2006 module_i2c_addresses[mid] : NULL) != NULL)) {
2007 /* Second chance: Try default i2c address list */
2008 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2009 ARRAY_SIZE(i2caddr));
bd14d4f8
MI		 2010 if (i2ccnt) {
2011 pvr2_trace(PVR2_TRACE_INIT,
2012 "Module ID %u:"
2013 " Using default i2c address list",
2014 mid);
2015 }
e9c64a78
MI		 2016 }
2017
2018 if (!i2ccnt) {
2019 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f
MI		 2020 "Module ID %u (%s) for device %s:"
2021 " No i2c addresses",
2022 mid, fname, hdw->hdw_desc->description);
2023 return -EINVAL;
e9c64a78
MI		 2024 }
2025
2026 /* Note how the 2nd and 3rd arguments are the same for both
2027 * v4l2_i2c_new_subdev() and v4l2_i2c_new_probed_subdev(). Why?
2028 * Well the 2nd argument is the module name to load, while the 3rd
2029 * argument is documented in the framework as being the "chipid" -
2030 * and every other place where I can find examples of this, the
2031 * "chipid" appears to just be the module name again. So here we
2032 * just do the same thing. */
2033 if (i2ccnt == 1) {
bd14d4f8
MI		 2034 pvr2_trace(PVR2_TRACE_INIT,
2035 "Module ID %u:"
2036 " Setting up with specified i2c address 0x%x",
2037 mid, i2caddr[0]);
e9c64a78
MI		 2038 sd = v4l2_i2c_new_subdev(&hdw->i2c_adap,
2039 fname, fname,
2040 i2caddr[0]);
2041 } else {
bd14d4f8
MI		 2042 pvr2_trace(PVR2_TRACE_INIT,
2043 "Module ID %u:"
2044 " Setting up with address probe list",
2045 mid);
e9c64a78
MI		 2046 sd = v4l2_i2c_new_probed_subdev(&hdw->i2c_adap,
2047 fname, fname,
2048 i2caddr);
2049 }
2050
446dfdc6
MI		 2051 if (!sd) {
2052 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f
MI		 2053 "Module ID %u (%s) for device %s failed to load",
2054 mid, fname, hdw->hdw_desc->description);
2055 return -EIO;
446dfdc6
MI		 2056 }
2057
2058 /* Tag this sub-device instance with the module ID we know about.
2059 In other places we'll use that tag to determine if the instance
2060 requires special handling. */
2061 sd->grp_id = mid;
2062
bd14d4f8 2063 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
a932f507 2064
e9c64a78 2065
00e5f736
MI		 2066 /* client-specific setup... */
2067 switch (mid) {
2068 case PVR2_CLIENT_ID_CX25840:
2069 hdw->decoder_client_id = mid;
2070 {
2071 /*
2072 Mike Isely <isely@pobox.com> 19-Nov-2006 - This
2073 bit of nuttiness for cx25840 causes that module
2074 to correctly set up its video scaling. This is
2075 really a problem in the cx25840 module itself,
2076 but we work around it here. The problem has not
2077 been seen in ivtv because there VBI is supported
2078 and set up. We don't do VBI here (at least not
2079 yet) and thus we never attempted to even set it
2080 up.
2081 */
2082 struct v4l2_format fmt;
bd14d4f8
MI		 2083 pvr2_trace(PVR2_TRACE_INIT,
2084 "Module ID %u:"
2085 " Executing cx25840 VBI hack",
2086 mid);
00e5f736
MI		 2087 memset(&fmt, 0, sizeof(fmt));
2088 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2089 v4l2_device_call_all(&hdw->v4l2_dev, mid,
2090 video, s_fmt, &fmt);
2091 }
2092 break;
2093 case PVR2_CLIENT_ID_SAA7115:
2094 hdw->decoder_client_id = mid;
2095 break;
2096 default: break;
2097 }
1ab5e74f
MI		 2098
2099 return 0;
e9c64a78
MI		 2100}
2101
2102
2103static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2104{
2105 unsigned int idx;
2106 const struct pvr2_string_table *cm;
2107 const struct pvr2_device_client_table *ct;
1ab5e74f 2108 int okFl = !0;
e9c64a78
MI		 2109
2110 cm = &hdw->hdw_desc->client_modules;
2111 for (idx = 0; idx < cm->cnt; idx++) {
2112 request_module(cm->lst[idx]);
2113 }
2114
2115 ct = &hdw->hdw_desc->client_table;
2116 for (idx = 0; idx < ct->cnt; idx++) {
bd14d4f8 2117 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
e9c64a78 2118 }
1ab5e74f 2119 if (!okFl) pvr2_hdw_render_useless(hdw);
e9c64a78
MI		 2120}
2121
2122
d855497e
MI		 2123static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2124{
2125 int ret;
2126 unsigned int idx;
2127 struct pvr2_ctrl *cptr;
2128 int reloadFl = 0;
989eb154 2129 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 2130 if (!reloadFl) {
2131 reloadFl =
2132 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2133 == 0);
2134 if (reloadFl) {
2135 pvr2_trace(PVR2_TRACE_INIT,
2136 "USB endpoint config looks strange"
2137 "; possibly firmware needs to be"
2138 " loaded");
2139 }
d855497e 2140 }
1d643a37
MI		 2141 if (!reloadFl) {
2142 reloadFl = !pvr2_hdw_check_firmware(hdw);
2143 if (reloadFl) {
2144 pvr2_trace(PVR2_TRACE_INIT,
2145 "Check for FX2 firmware failed"
2146 "; possibly firmware needs to be"
2147 " loaded");
2148 }
d855497e 2149 }
1d643a37
MI		 2150 if (reloadFl) {
2151 if (pvr2_upload_firmware1(hdw) != 0) {
2152 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2153 "Failure uploading firmware1");
2154 }
2155 return;
d855497e 2156 }
d855497e
MI		 2157 }
2158 hdw->fw1_state = FW1_STATE_OK;
2159
d855497e
MI		 2160 if (!pvr2_hdw_dev_ok(hdw)) return;
2161
27764726
MI		 2162 hdw->force_dirty = !0;
2163
989eb154 2164 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 2165 pvr2_hdw_cmd_powerup(hdw);
2166 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 2167 }
2168
31335b13
MI		 2169 /* Take the IR chip out of reset, if appropriate */
2170 if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
2171 pvr2_issue_simple_cmd(hdw,
2172 FX2CMD_HCW_ZILOG_RESET |
2173 (1 << 8) |
2174 ((0) << 16));
2175 }
2176
d855497e
MI		 2177 // This step MUST happen after the earlier powerup step.
2178 pvr2_i2c_core_init(hdw);
2179 if (!pvr2_hdw_dev_ok(hdw)) return;
2180
e9c64a78 2181 pvr2_hdw_load_modules(hdw);
1ab5e74f 2182 if (!pvr2_hdw_dev_ok(hdw)) return;
e9c64a78 2183
5c6cb4e2
MI		 2184 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, init, 0);
2185
c05c0462 2186 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 2187 cptr = hdw->controls + idx;
2188 if (cptr->info->skip_init) continue;
2189 if (!cptr->info->set_value) continue;
2190 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2191 }
2192
1bde0289
MI		 2193 /* Set up special default values for the television and radio
2194 frequencies here. It's not really important what these defaults
2195 are, but I set them to something usable in the Chicago area just
2196 to make driver testing a little easier. */
2197
5a4f5da6
MK		 2198 hdw->freqValTelevision = default_tv_freq;
2199 hdw->freqValRadio = default_radio_freq;
1bde0289 2200
d855497e
MI		 2201 // Do not use pvr2_reset_ctl_endpoints() here. It is not
2202 // thread-safe against the normal pvr2_send_request() mechanism.
2203 // (We should make it thread safe).
2204
aaf7884d
MI		 2205 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2206 ret = pvr2_hdw_get_eeprom_addr(hdw);
d855497e 2207 if (!pvr2_hdw_dev_ok(hdw)) return;
aaf7884d
MI		 2208 if (ret < 0) {
2209 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2210 "Unable to determine location of eeprom,"
2211 " skipping");
2212 } else {
2213 hdw->eeprom_addr = ret;
2214 pvr2_eeprom_analyze(hdw);
2215 if (!pvr2_hdw_dev_ok(hdw)) return;
2216 }
2217 } else {
2218 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2219 hdw->tuner_updated = !0;
2220 hdw->std_mask_eeprom = V4L2_STD_ALL;
d855497e
MI		 2221 }
2222
13a88797
MI		 2223 if (hdw->serial_number) {
2224 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2225 "sn-%lu", hdw->serial_number);
2226 } else if (hdw->unit_number >= 0) {
2227 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2228 "unit-%c",
2229 hdw->unit_number + 'a');
2230 } else {
2231 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2232 "unit-??");
2233 }
2234 hdw->identifier[idx] = 0;
2235
d855497e
MI		 2236 pvr2_hdw_setup_std(hdw);
2237
2238 if (!get_default_tuner_type(hdw)) {
2239 pvr2_trace(PVR2_TRACE_INIT,
2240 "pvr2_hdw_setup: Tuner type overridden to %d",
2241 hdw->tuner_type);
2242 }
2243
d855497e
MI		 2244
2245 if (!pvr2_hdw_dev_ok(hdw)) return;
2246
1df59f0b
MI		 2247 if (hdw->hdw_desc->signal_routing_scheme ==
2248 PVR2_ROUTING_SCHEME_GOTVIEW) {
2249 /* Ensure that GPIO 11 is set to output for GOTVIEW
2250 hardware. */
2251 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2252 }
2253
681c7399 2254 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 2255
2256 hdw->vid_stream = pvr2_stream_create();
2257 if (!pvr2_hdw_dev_ok(hdw)) return;
2258 pvr2_trace(PVR2_TRACE_INIT,
2259 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2260 if (hdw->vid_stream) {
2261 idx = get_default_error_tolerance(hdw);
2262 if (idx) {
2263 pvr2_trace(PVR2_TRACE_INIT,
2264 "pvr2_hdw_setup: video stream %p"
2265 " setting tolerance %u",
2266 hdw->vid_stream,idx);
2267 }
2268 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2269 PVR2_VID_ENDPOINT,idx);
2270 }
2271
2272 if (!pvr2_hdw_dev_ok(hdw)) return;
2273
d855497e 2274 hdw->flag_init_ok = !0;
681c7399
MI		 2275
2276 pvr2_hdw_state_sched(hdw);
d855497e
MI		 2277}
2278
2279
681c7399
MI		 2280/* Set up the structure and attempt to put the device into a usable state.
2281 This can be a time-consuming operation, which is why it is not done
2282 internally as part of the create() step. */
2283static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 2284{
2285 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 2286 do {
d855497e
MI		 2287 pvr2_hdw_setup_low(hdw);
2288 pvr2_trace(PVR2_TRACE_INIT,
2289 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 2290 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 2291 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 2292 if (hdw->flag_init_ok) {
d855497e
MI		 2293 pvr2_trace(
2294 PVR2_TRACE_INFO,
2295 "Device initialization"
2296 " completed successfully.");
2297 break;
2298 }
2299 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2300 pvr2_trace(
2301 PVR2_TRACE_INFO,
2302 "Device microcontroller firmware"
2303 " (re)loaded; it should now reset"
2304 " and reconnect.");
2305 break;
2306 }
2307 pvr2_trace(
2308 PVR2_TRACE_ERROR_LEGS,
2309 "Device initialization was not successful.");
2310 if (hdw->fw1_state == FW1_STATE_MISSING) {
2311 pvr2_trace(
2312 PVR2_TRACE_ERROR_LEGS,
2313 "Giving up since device"
2314 " microcontroller firmware"
2315 " appears to be missing.");
2316 break;
2317 }
2318 }
2319 if (procreload) {
2320 pvr2_trace(
2321 PVR2_TRACE_ERROR_LEGS,
2322 "Attempting pvrusb2 recovery by reloading"
2323 " primary firmware.");
2324 pvr2_trace(
2325 PVR2_TRACE_ERROR_LEGS,
2326 "If this works, device should disconnect"
2327 " and reconnect in a sane state.");
2328 hdw->fw1_state = FW1_STATE_UNKNOWN;
2329 pvr2_upload_firmware1(hdw);
2330 } else {
2331 pvr2_trace(
2332 PVR2_TRACE_ERROR_LEGS,
2333 "***WARNING*** pvrusb2 device hardware"
2334 " appears to be jammed"
2335 " and I can't clear it.");
2336 pvr2_trace(
2337 PVR2_TRACE_ERROR_LEGS,
2338 "You might need to power cycle"
2339 " the pvrusb2 device"
2340 " in order to recover.");
2341 }
681c7399 2342 } while (0);
d855497e 2343 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 2344}
2345
2346
c4a8828d
MI		 2347/* Perform second stage initialization. Set callback pointer first so that
2348 we can avoid a possible initialization race (if the kernel thread runs
2349 before the callback has been set). */
794b1607
MI		 2350int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2351 void (*callback_func)(void *),
2352 void *callback_data)
c4a8828d
MI		 2353{
2354 LOCK_TAKE(hdw->big_lock); do {
97f26ff6
MI		 2355 if (hdw->flag_disconnected) {
2356 /* Handle a race here: If we're already
2357 disconnected by this point, then give up. If we
2358 get past this then we'll remain connected for
2359 the duration of initialization since the entire
2360 initialization sequence is now protected by the
2361 big_lock. */
2362 break;
2363 }
c4a8828d
MI		 2364 hdw->state_data = callback_data;
2365 hdw->state_func = callback_func;
97f26ff6 2366 pvr2_hdw_setup(hdw);
c4a8828d 2367 } while (0); LOCK_GIVE(hdw->big_lock);
794b1607 2368 return hdw->flag_init_ok;
c4a8828d
MI		 2369}
2370
2371
2372/* Create, set up, and return a structure for interacting with the
2373 underlying hardware. */
d855497e
MI		 2374struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2375 const struct usb_device_id *devid)
2376{
7fb20fa3 2377 unsigned int idx,cnt1,cnt2,m;
fe15f136 2378 struct pvr2_hdw *hdw = NULL;
d855497e
MI		 2379 int valid_std_mask;
2380 struct pvr2_ctrl *cptr;
b72b7bf5 2381 struct usb_device *usb_dev;
989eb154 2382 const struct pvr2_device_desc *hdw_desc;
d855497e 2383 __u8 ifnum;
b30d2441
MI		 2384 struct v4l2_queryctrl qctrl;
2385 struct pvr2_ctl_info *ciptr;
d855497e 2386
b72b7bf5
MI		 2387 usb_dev = interface_to_usbdev(intf);
2388
d130fa8a 2389 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
d855497e 2390
fe15f136
MI		 2391 if (hdw_desc == NULL) {
2392 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2393 " No device description pointer,"
2394 " unable to continue.");
2395 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2396 " please contact Mike Isely <isely@pobox.com>"
2397 " to get it included in the driver\n");
2398 goto fail;
2399 }
2400
ca545f7c 2401 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 2402 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 2403 hdw,hdw_desc->description);
d855497e 2404 if (!hdw) goto fail;
681c7399
MI		 2405
2406 init_timer(&hdw->quiescent_timer);
2407 hdw->quiescent_timer.data = (unsigned long)hdw;
2408 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2409
2410 init_timer(&hdw->encoder_wait_timer);
2411 hdw->encoder_wait_timer.data = (unsigned long)hdw;
2412 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2413
d913d630
MI		 2414 init_timer(&hdw->encoder_run_timer);
2415 hdw->encoder_run_timer.data = (unsigned long)hdw;
2416 hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2417
681c7399
MI		 2418 hdw->master_state = PVR2_STATE_DEAD;
2419
2420 init_waitqueue_head(&hdw->state_wait_data);
2421
18103c57 2422 hdw->tuner_signal_stale = !0;
b30d2441 2423 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 2424
7fb20fa3
MI		 2425 /* Calculate which inputs are OK */
2426 m = 0;
2427 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
e8f5bacf
MI		 2428 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2429 m |= 1 << PVR2_CVAL_INPUT_DTV;
2430 }
7fb20fa3
MI		 2431 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2432 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2433 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2434 hdw->input_avail_mask = m;
1cb03b76 2435 hdw->input_allowed_mask = hdw->input_avail_mask;
7fb20fa3 2436
62433e31
MI		 2437 /* If not a hybrid device, pathway_state never changes. So
2438 initialize it here to what it should forever be. */
2439 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2440 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2441 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2442 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2443 }
2444
c05c0462 2445 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 2446 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 2447 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 2448 GFP_KERNEL);
2449 if (!hdw->controls) goto fail;
989eb154 2450 hdw->hdw_desc = hdw_desc;
c05c0462
MI		 2451 for (idx = 0; idx < hdw->control_cnt; idx++) {
2452 cptr = hdw->controls + idx;
2453 cptr->hdw = hdw;
2454 }
d855497e
MI		 2455 for (idx = 0; idx < 32; idx++) {
2456 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2457 }
c05c0462 2458 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 2459 cptr = hdw->controls + idx;
d855497e
MI		 2460 cptr->info = control_defs+idx;
2461 }
dbc40a0e
MI		 2462
2463 /* Ensure that default input choice is a valid one. */
2464 m = hdw->input_avail_mask;
2465 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2466 if (!((1 << idx) & m)) continue;
2467 hdw->input_val = idx;
2468 break;
2469 }
2470
b30d2441 2471 /* Define and configure additional controls from cx2341x module. */
ca545f7c 2472 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 2473 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2474 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 2475 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2476 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2477 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2478 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2479 ciptr->name = mpeg_ids[idx].strid;
2480 ciptr->v4l_id = mpeg_ids[idx].id;
2481 ciptr->skip_init = !0;
2482 ciptr->get_value = ctrl_cx2341x_get;
2483 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2484 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2485 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2486 qctrl.id = ciptr->v4l_id;
2487 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2488 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2489 ciptr->set_value = ctrl_cx2341x_set;
2490 }
2491 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2492 PVR2_CTLD_INFO_DESC_SIZE);
2493 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2494 ciptr->default_value = qctrl.default_value;
2495 switch (qctrl.type) {
2496 default:
2497 case V4L2_CTRL_TYPE_INTEGER:
2498 ciptr->type = pvr2_ctl_int;
2499 ciptr->def.type_int.min_value = qctrl.minimum;
2500 ciptr->def.type_int.max_value = qctrl.maximum;
2501 break;
2502 case V4L2_CTRL_TYPE_BOOLEAN:
2503 ciptr->type = pvr2_ctl_bool;
2504 break;
2505 case V4L2_CTRL_TYPE_MENU:
2506 ciptr->type = pvr2_ctl_enum;
2507 ciptr->def.type_enum.value_names =
e0e31cdb
HV		 2508 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2509 ciptr->v4l_id);
b30d2441
MI		 2510 for (cnt1 = 0;
2511 ciptr->def.type_enum.value_names[cnt1] != NULL;
2512 cnt1++) { }
2513 ciptr->def.type_enum.count = cnt1;
2514 break;
2515 }
2516 cptr->info = ciptr;
2517 }
d855497e
MI		 2518
2519 // Initialize video standard enum dynamic control
2520 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2521 if (cptr) {
2522 memcpy(&hdw->std_info_enum,cptr->info,
2523 sizeof(hdw->std_info_enum));
2524 cptr->info = &hdw->std_info_enum;
2525
2526 }
2527 // Initialize control data regarding video standard masks
2528 valid_std_mask = pvr2_std_get_usable();
2529 for (idx = 0; idx < 32; idx++) {
2530 if (!(valid_std_mask & (1 << idx))) continue;
2531 cnt1 = pvr2_std_id_to_str(
2532 hdw->std_mask_names[idx],
2533 sizeof(hdw->std_mask_names[idx])-1,
2534 1 << idx);
2535 hdw->std_mask_names[idx][cnt1] = 0;
2536 }
2537 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2538 if (cptr) {
2539 memcpy(&hdw->std_info_avail,cptr->info,
2540 sizeof(hdw->std_info_avail));
2541 cptr->info = &hdw->std_info_avail;
2542 hdw->std_info_avail.def.type_bitmask.bit_names =
2543 hdw->std_mask_ptrs;
2544 hdw->std_info_avail.def.type_bitmask.valid_bits =
2545 valid_std_mask;
2546 }
2547 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2548 if (cptr) {
2549 memcpy(&hdw->std_info_cur,cptr->info,
2550 sizeof(hdw->std_info_cur));
2551 cptr->info = &hdw->std_info_cur;
2552 hdw->std_info_cur.def.type_bitmask.bit_names =
2553 hdw->std_mask_ptrs;
2554 hdw->std_info_avail.def.type_bitmask.valid_bits =
2555 valid_std_mask;
2556 }
2557
432907f7 2558 hdw->cropcap_stale = !0;
d855497e
MI		 2559 hdw->eeprom_addr = -1;
2560 hdw->unit_number = -1;
8079384e
MI		 2561 hdw->v4l_minor_number_video = -1;
2562 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 2563 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 2564 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2565 if (!hdw->ctl_write_buffer) goto fail;
2566 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2567 if (!hdw->ctl_read_buffer) goto fail;
2568 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2569 if (!hdw->ctl_write_urb) goto fail;
2570 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2571 if (!hdw->ctl_read_urb) goto fail;
2572
b72b7bf5
MI		 2573 if (v4l2_device_register(&usb_dev->dev, &hdw->v4l2_dev) != 0) {
2574 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2575 "Error registering with v4l core, giving up");
2576 goto fail;
2577 }
8df0c87c 2578 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2579 for (idx = 0; idx < PVR_NUM; idx++) {
2580 if (unit_pointers[idx]) continue;
2581 hdw->unit_number = idx;
2582 unit_pointers[idx] = hdw;
2583 break;
2584 }
8df0c87c 2585 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 2586
2587 cnt1 = 0;
2588 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2589 cnt1 += cnt2;
2590 if (hdw->unit_number >= 0) {
2591 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2592 ('a' + hdw->unit_number));
2593 cnt1 += cnt2;
2594 }
2595 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2596 hdw->name[cnt1] = 0;
2597
681c7399
MI		 2598 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2599 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
681c7399 2600
d855497e
MI		 2601 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2602 hdw->unit_number,hdw->name);
2603
2604 hdw->tuner_type = -1;
2605 hdw->flag_ok = !0;
d855497e
MI		 2606
2607 hdw->usb_intf = intf;
b72b7bf5 2608 hdw->usb_dev = usb_dev;
d855497e 2609
87e3495c 2610 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
31a18547 2611
d855497e
MI		 2612 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2613 usb_set_interface(hdw->usb_dev,ifnum,0);
2614
2615 mutex_init(&hdw->ctl_lock_mutex);
2616 mutex_init(&hdw->big_lock_mutex);
2617
2618 return hdw;
2619 fail:
2620 if (hdw) {
681c7399 2621 del_timer_sync(&hdw->quiescent_timer);
d913d630 2622 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 2623 del_timer_sync(&hdw->encoder_wait_timer);
2624 if (hdw->workqueue) {
2625 flush_workqueue(hdw->workqueue);
2626 destroy_workqueue(hdw->workqueue);
2627 hdw->workqueue = NULL;
2628 }
5e55d2ce
MK		 2629 usb_free_urb(hdw->ctl_read_urb);
2630 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2631 kfree(hdw->ctl_read_buffer);
2632 kfree(hdw->ctl_write_buffer);
2633 kfree(hdw->controls);
2634 kfree(hdw->mpeg_ctrl_info);
681c7399
MI		 2635 kfree(hdw->std_defs);
2636 kfree(hdw->std_enum_names);
d855497e
MI		 2637 kfree(hdw);
2638 }
a0fd1cb1 2639 return NULL;
d855497e
MI		 2640}
2641
2642
2643/* Remove _all_ associations between this driver and the underlying USB
2644 layer. */
07e337ee 2645static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2646{
2647 if (hdw->flag_disconnected) return;
2648 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2649 if (hdw->ctl_read_urb) {
2650 usb_kill_urb(hdw->ctl_read_urb);
2651 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2652 hdw->ctl_read_urb = NULL;
d855497e
MI		 2653 }
2654 if (hdw->ctl_write_urb) {
2655 usb_kill_urb(hdw->ctl_write_urb);
2656 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2657 hdw->ctl_write_urb = NULL;
d855497e
MI		 2658 }
2659 if (hdw->ctl_read_buffer) {
2660 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2661 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2662 }
2663 if (hdw->ctl_write_buffer) {
2664 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2665 hdw->ctl_write_buffer = NULL;
d855497e 2666 }
d855497e 2667 hdw->flag_disconnected = !0;
b72b7bf5
MI		 2668 /* If we don't do this, then there will be a dangling struct device
2669 reference to our disappearing device persisting inside the V4L
2670 core... */
2671 if (hdw->v4l2_dev.dev) {
2672 dev_set_drvdata(hdw->v4l2_dev.dev, NULL);
2673 hdw->v4l2_dev.dev = NULL;
2674 }
a0fd1cb1
MI		 2675 hdw->usb_dev = NULL;
2676 hdw->usb_intf = NULL;
681c7399 2677 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2678}
2679
2680
2681/* Destroy hardware interaction structure */
2682void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2683{
401c27ce 2684 if (!hdw) return;
d855497e 2685 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2686 if (hdw->workqueue) {
2687 flush_workqueue(hdw->workqueue);
2688 destroy_workqueue(hdw->workqueue);
2689 hdw->workqueue = NULL;
2690 }
8f59100a 2691 del_timer_sync(&hdw->quiescent_timer);
d913d630 2692 del_timer_sync(&hdw->encoder_run_timer);
8f59100a 2693 del_timer_sync(&hdw->encoder_wait_timer);
d855497e
MI		 2694 if (hdw->fw_buffer) {
2695 kfree(hdw->fw_buffer);
a0fd1cb1 2696 hdw->fw_buffer = NULL;
d855497e
MI		 2697 }
2698 if (hdw->vid_stream) {
2699 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2700 hdw->vid_stream = NULL;
d855497e 2701 }
d855497e 2702 pvr2_i2c_core_done(hdw);
b72b7bf5 2703 v4l2_device_unregister(&hdw->v4l2_dev);
d855497e 2704 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2705 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2706 if ((hdw->unit_number >= 0) &&
2707 (hdw->unit_number < PVR_NUM) &&
2708 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2709 unit_pointers[hdw->unit_number] = NULL;
d855497e 2710 }
8df0c87c 2711 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2712 kfree(hdw->controls);
2713 kfree(hdw->mpeg_ctrl_info);
2714 kfree(hdw->std_defs);
2715 kfree(hdw->std_enum_names);
d855497e
MI		 2716 kfree(hdw);
2717}
2718
2719
d855497e
MI		 2720int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2721{
2722 return (hdw && hdw->flag_ok);
2723}
2724
2725
2726/* Called when hardware has been unplugged */
2727void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2728{
2729 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2730 LOCK_TAKE(hdw->big_lock);
2731 LOCK_TAKE(hdw->ctl_lock);
2732 pvr2_hdw_remove_usb_stuff(hdw);
2733 LOCK_GIVE(hdw->ctl_lock);
2734 LOCK_GIVE(hdw->big_lock);
2735}
2736
2737
2738// Attempt to autoselect an appropriate value for std_enum_cur given
2739// whatever is currently in std_mask_cur
07e337ee 2740static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2741{
2742 unsigned int idx;
2743 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2744 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2745 hdw->std_enum_cur = idx;
2746 return;
2747 }
2748 }
2749 hdw->std_enum_cur = 0;
2750}
2751
2752
2753// Calculate correct set of enumerated standards based on currently known
2754// set of available standards bits.
07e337ee 2755static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2756{
2757 struct v4l2_standard *newstd;
2758 unsigned int std_cnt;
2759 unsigned int idx;
2760
2761 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2762
2763 if (hdw->std_defs) {
2764 kfree(hdw->std_defs);
a0fd1cb1 2765 hdw->std_defs = NULL;
d855497e
MI		 2766 }
2767 hdw->std_enum_cnt = 0;
2768 if (hdw->std_enum_names) {
2769 kfree(hdw->std_enum_names);
a0fd1cb1 2770 hdw->std_enum_names = NULL;
d855497e
MI		 2771 }
2772
2773 if (!std_cnt) {
2774 pvr2_trace(
2775 PVR2_TRACE_ERROR_LEGS,
2776 "WARNING: Failed to identify any viable standards");
2777 }
2778 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2779 hdw->std_enum_names[0] = "none";
2780 for (idx = 0; idx < std_cnt; idx++) {
2781 hdw->std_enum_names[idx+1] =
2782 newstd[idx].name;
2783 }
2784 // Set up the dynamic control for this standard
2785 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2786 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2787 hdw->std_defs = newstd;
2788 hdw->std_enum_cnt = std_cnt+1;
2789 hdw->std_enum_cur = 0;
2790 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2791}
2792
2793
2794int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2795 struct v4l2_standard *std,
2796 unsigned int idx)
2797{
2798 int ret = -EINVAL;
2799 if (!idx) return ret;
2800 LOCK_TAKE(hdw->big_lock); do {
2801 if (idx >= hdw->std_enum_cnt) break;
2802 idx--;
2803 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2804 ret = 0;
2805 } while (0); LOCK_GIVE(hdw->big_lock);
2806 return ret;
2807}
2808
2809
2810/* Get the number of defined controls */
2811unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2812{
c05c0462 2813 return hdw->control_cnt;
d855497e
MI		 2814}
2815
2816
2817/* Retrieve a control handle given its index (0..count-1) */
2818struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2819 unsigned int idx)
2820{
a0fd1cb1 2821 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2822 return hdw->controls + idx;
2823}
2824
2825
2826/* Retrieve a control handle given its index (0..count-1) */
2827struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2828 unsigned int ctl_id)
2829{
2830 struct pvr2_ctrl *cptr;
2831 unsigned int idx;
2832 int i;
2833
2834 /* This could be made a lot more efficient, but for now... */
c05c0462 2835 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2836 cptr = hdw->controls + idx;
2837 i = cptr->info->internal_id;
2838 if (i && (i == ctl_id)) return cptr;
2839 }
a0fd1cb1 2840 return NULL;
d855497e
MI		 2841}
2842
2843
a761f431 2844/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2845struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2846{
2847 struct pvr2_ctrl *cptr;
2848 unsigned int idx;
2849 int i;
2850
2851 /* This could be made a lot more efficient, but for now... */
c05c0462 2852 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2853 cptr = hdw->controls + idx;
2854 i = cptr->info->v4l_id;
2855 if (i && (i == ctl_id)) return cptr;
2856 }
a0fd1cb1 2857 return NULL;
d855497e
MI		 2858}
2859
2860
a761f431
MI		 2861/* Given a V4L ID for its immediate predecessor, retrieve the control
2862 structure associated with it. */
2863struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2864 unsigned int ctl_id)
2865{
2866 struct pvr2_ctrl *cptr,*cp2;
2867 unsigned int idx;
2868 int i;
2869
2870 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2871 cp2 = NULL;
a761f431
MI		 2872 for (idx = 0; idx < hdw->control_cnt; idx++) {
2873 cptr = hdw->controls + idx;
2874 i = cptr->info->v4l_id;
2875 if (!i) continue;
2876 if (i <= ctl_id) continue;
2877 if (cp2 && (cp2->info->v4l_id < i)) continue;
2878 cp2 = cptr;
2879 }
2880 return cp2;
a0fd1cb1 2881 return NULL;
a761f431
MI		 2882}
2883
2884
d855497e
MI		 2885static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2886{
2887 switch (tp) {
2888 case pvr2_ctl_int: return "integer";
2889 case pvr2_ctl_enum: return "enum";
33213963 2890 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2891 case pvr2_ctl_bitmask: return "bitmask";
2892 }
2893 return "";
2894}
2895
2896
2641df36
MI		 2897static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2898 const char *name, int val)
2899{
2900 struct v4l2_control ctrl;
2901 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2902 memset(&ctrl, 0, sizeof(ctrl));
2903 ctrl.id = id;
2904 ctrl.value = val;
2905 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2906}
2907
2908#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
27764726 2909 if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \
2641df36
MI		 2910 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2911 }
2912
5ceaad14 2913/* Execute whatever commands are required to update the state of all the
2641df36 2914 sub-devices so that they match our current control values. */
5ceaad14
MI		 2915static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2916{
edb9dcb8
MI		 2917 struct v4l2_subdev *sd;
2918 unsigned int id;
2919 pvr2_subdev_update_func fp;
2920
75212a02
MI		 2921 pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2922
27764726 2923 if (hdw->tuner_updated || hdw->force_dirty) {
75212a02
MI		 2924 struct tuner_setup setup;
2925 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2926 hdw->tuner_type);
2927 if (((int)(hdw->tuner_type)) >= 0) {
2928 setup.addr = ADDR_UNSET;
2929 setup.type = hdw->tuner_type;
2930 setup.mode_mask = T_RADIO | T_ANALOG_TV;
2931 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2932 tuner, s_type_addr, &setup);
2933 }
2934 }
2935
27764726 2936 if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
b481880b 2937 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2641df36
MI		 2938 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2939 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2940 tuner, s_radio);
2941 } else {
2942 v4l2_std_id vs;
2943 vs = hdw->std_mask_cur;
2944 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2945 tuner, s_std, vs);
2946 }
2947 hdw->tuner_signal_stale = !0;
2948 hdw->cropcap_stale = !0;
2949 }
2950
2951 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2952 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2953 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2954 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2955 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2956 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2957 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2958 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2959 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2960
27764726 2961 if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2641df36
MI		 2962 struct v4l2_tuner vt;
2963 memset(&vt, 0, sizeof(vt));
2964 vt.audmode = hdw->audiomode_val;
2965 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2966 }
2967
27764726 2968 if (hdw->freqDirty || hdw->force_dirty) {
2641df36
MI		 2969 unsigned long fv;
2970 struct v4l2_frequency freq;
2971 fv = pvr2_hdw_get_cur_freq(hdw);
2972 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2973 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2974 memset(&freq, 0, sizeof(freq));
2975 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2976 /* ((fv * 1000) / 62500) */
2977 freq.frequency = (fv * 2) / 125;
2978 } else {
2979 freq.frequency = fv / 62500;
2980 }
2981 /* tuner-core currently doesn't seem to care about this, but
2982 let's set it anyway for completeness. */
2983 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2984 freq.type = V4L2_TUNER_RADIO;
2985 } else {
2986 freq.type = V4L2_TUNER_ANALOG_TV;
2987 }
2988 freq.tuner = 0;
2989 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2990 s_frequency, &freq);
2991 }
2992
27764726 2993 if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
2641df36
MI		 2994 struct v4l2_format fmt;
2995 memset(&fmt, 0, sizeof(fmt));
2996 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2997 fmt.fmt.pix.width = hdw->res_hor_val;
2998 fmt.fmt.pix.height = hdw->res_ver_val;
7dfdf1ee 2999 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
2641df36
MI		 3000 fmt.fmt.pix.width, fmt.fmt.pix.height);
3001 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
3002 }
3003
27764726 3004 if (hdw->srate_dirty || hdw->force_dirty) {
01c59df8
MI		 3005 u32 val;
3006 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3007 hdw->srate_val);
3008 switch (hdw->srate_val) {
3009 default:
3010 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3011 val = 48000;
3012 break;
3013 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3014 val = 44100;
3015 break;
3016 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3017 val = 32000;
3018 break;
3019 }
3020 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3021 audio, s_clock_freq, val);
3022 }
3023
2641df36
MI		 3024 /* Unable to set crop parameters; there is apparently no equivalent
3025 for VIDIOC_S_CROP */
3026
edb9dcb8
MI		 3027 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3028 id = sd->grp_id;
3029 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3030 fp = pvr2_module_update_functions[id];
3031 if (!fp) continue;
3032 (*fp)(hdw, sd);
3033 }
2641df36 3034
27764726 3035 if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
2641df36
MI		 3036 pvr2_hdw_status_poll(hdw);
3037 }
5ceaad14
MI		 3038}
3039
3040
681c7399
MI		 3041/* Figure out if we need to commit control changes. If so, mark internal
3042 state flags to indicate this fact and return true. Otherwise do nothing
3043 else and return false. */
3044static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 3045{
d855497e
MI		 3046 unsigned int idx;
3047 struct pvr2_ctrl *cptr;
3048 int value;
27764726 3049 int commit_flag = hdw->force_dirty;
d855497e
MI		 3050 char buf[100];
3051 unsigned int bcnt,ccnt;
3052
c05c0462 3053 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e 3054 cptr = hdw->controls + idx;
5fa1247a 3055 if (!cptr->info->is_dirty) continue;
d855497e 3056 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 3057 commit_flag = !0;
d855497e 3058
fe23a280 3059 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 3060 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3061 cptr->info->name);
3062 value = 0;
3063 cptr->info->get_value(cptr,&value);
3064 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3065 buf+bcnt,
3066 sizeof(buf)-bcnt,&ccnt);
3067 bcnt += ccnt;
3068 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3069 get_ctrl_typename(cptr->info->type));
3070 pvr2_trace(PVR2_TRACE_CTL,
3071 "/*--TRACE_COMMIT--*/ %.*s",
3072 bcnt,buf);
3073 }
3074
3075 if (!commit_flag) {
3076 /* Nothing has changed */
3077 return 0;
3078 }
3079
681c7399
MI		 3080 hdw->state_pipeline_config = 0;
3081 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3082 pvr2_hdw_state_sched(hdw);
3083
3084 return !0;
3085}
3086
3087
3088/* Perform all operations needed to commit all control changes. This must
3089 be performed in synchronization with the pipeline state and is thus
3090 expected to be called as part of the driver's worker thread. Return
3091 true if commit successful, otherwise return false to indicate that
3092 commit isn't possible at this time. */
3093static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3094{
3095 unsigned int idx;
3096 struct pvr2_ctrl *cptr;
3097 int disruptive_change;
3098
ab062fe3
MI		 3099 /* Handle some required side effects when the video standard is
3100 changed.... */
d855497e 3101 if (hdw->std_dirty) {
d855497e 3102 int nvres;
00528d9c 3103 int gop_size;
d855497e
MI		 3104 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3105 nvres = 480;
00528d9c 3106 gop_size = 15;
d855497e
MI		 3107 } else {
3108 nvres = 576;
00528d9c 3109 gop_size = 12;
d855497e 3110 }
00528d9c
MI		 3111 /* Rewrite the vertical resolution to be appropriate to the
3112 video standard that has been selected. */
d855497e
MI		 3113 if (nvres != hdw->res_ver_val) {
3114 hdw->res_ver_val = nvres;
3115 hdw->res_ver_dirty = !0;
3116 }
00528d9c
MI		 3117 /* Rewrite the GOP size to be appropriate to the video
3118 standard that has been selected. */
3119 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3120 struct v4l2_ext_controls cs;
3121 struct v4l2_ext_control c1;
3122 memset(&cs, 0, sizeof(cs));
3123 memset(&c1, 0, sizeof(c1));
3124 cs.controls = &c1;
3125 cs.count = 1;
3126 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3127 c1.value = gop_size;
3128 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3129 VIDIOC_S_EXT_CTRLS);
3130 }
d855497e
MI		 3131 }
3132
38d9a2cf 3133 if (hdw->input_dirty && hdw->state_pathway_ok &&
62433e31
MI		 3134 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3135 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3136 hdw->pathway_state)) {
3137 /* Change of mode being asked for... */
3138 hdw->state_pathway_ok = 0;
e9db1ff2 3139 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 3140 }
3141 if (!hdw->state_pathway_ok) {
3142 /* Can't commit anything until pathway is ok. */
3143 return 0;
3144 }
e784bfb9 3145 /* The broadcast decoder can only scale down, so if
3146 * res_*_dirty && crop window < output format ==> enlarge crop.
3147 *
3148 * The mpeg encoder receives fields of res_hor_val dots and
3149 * res_ver_val halflines. Limits: hor<=720, ver<=576.
3150 */
3151 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3152 hdw->cropw_val = hdw->res_hor_val;
3153 hdw->cropw_dirty = !0;
3154 } else if (hdw->cropw_dirty) {
3155 hdw->res_hor_dirty = !0; /* must rescale */
3156 hdw->res_hor_val = min(720, hdw->cropw_val);
3157 }
3158 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3159 hdw->croph_val = hdw->res_ver_val;
3160 hdw->croph_dirty = !0;
3161 } else if (hdw->croph_dirty) {
3162 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3163 hdw->res_ver_dirty = !0;
3164 hdw->res_ver_val = min(nvres, hdw->croph_val);
3165 }
3166
681c7399
MI		 3167 /* If any of the below has changed, then we can't do the update
3168 while the pipeline is running. Pipeline must be paused first
3169 and decoder -> encoder connection be made quiescent before we
3170 can proceed. */
3171 disruptive_change =
3172 (hdw->std_dirty ||
3173 hdw->enc_unsafe_stale ||
3174 hdw->srate_dirty ||
3175 hdw->res_ver_dirty ||
3176 hdw->res_hor_dirty ||
755879c6
MI		 3177 hdw->cropw_dirty ||
3178 hdw->croph_dirty ||
681c7399
MI		 3179 hdw->input_dirty ||
3180 (hdw->active_stream_type != hdw->desired_stream_type));
3181 if (disruptive_change && !hdw->state_pipeline_idle) {
3182 /* Pipeline is not idle; we can't proceed. Arrange to
3183 cause pipeline to stop so that we can try this again
3184 later.... */
3185 hdw->state_pipeline_pause = !0;
3186 return 0;
275b2e28
PK		 3187 }
3188
b30d2441
MI		 3189 if (hdw->srate_dirty) {
3190 /* Write new sample rate into control structure since
3191 * the master copy is stale. We must track srate
3192 * separate from the mpeg control structure because
3193 * other logic also uses this value. */
3194 struct v4l2_ext_controls cs;
3195 struct v4l2_ext_control c1;
3196 memset(&cs,0,sizeof(cs));
3197 memset(&c1,0,sizeof(c1));
3198 cs.controls = &c1;
3199 cs.count = 1;
3200 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3201 c1.value = hdw->srate_val;
01f1e44f 3202 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 3203 }
c05c0462 3204
681c7399
MI		 3205 if (hdw->active_stream_type != hdw->desired_stream_type) {
3206 /* Handle any side effects of stream config here */
3207 hdw->active_stream_type = hdw->desired_stream_type;
3208 }
3209
1df59f0b
MI		 3210 if (hdw->hdw_desc->signal_routing_scheme ==
3211 PVR2_ROUTING_SCHEME_GOTVIEW) {
3212 u32 b;
3213 /* Handle GOTVIEW audio switching */
3214 pvr2_hdw_gpio_get_out(hdw,&b);
3215 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3216 /* Set GPIO 11 */
3217 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3218 } else {
3219 /* Clear GPIO 11 */
3220 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3221 }
3222 }
3223
e68a619a
MI		 3224 /* Check and update state for all sub-devices. */
3225 pvr2_subdev_update(hdw);
3226
75212a02 3227 hdw->tuner_updated = 0;
27764726 3228 hdw->force_dirty = 0;
5ceaad14
MI		 3229 for (idx = 0; idx < hdw->control_cnt; idx++) {
3230 cptr = hdw->controls + idx;
3231 if (!cptr->info->clear_dirty) continue;
3232 cptr->info->clear_dirty(cptr);
3233 }
3234
62433e31
MI		 3235 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3236 hdw->state_encoder_run) {
3237 /* If encoder isn't running or it can't be touched, then
3238 this will get worked out later when we start the
3239 encoder. */
681c7399
MI		 3240 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3241 }
d855497e 3242
681c7399 3243 hdw->state_pipeline_config = !0;
432907f7
MI		 3244 /* Hardware state may have changed in a way to cause the cropping
3245 capabilities to have changed. So mark it stale, which will
3246 cause a later re-fetch. */
681c7399
MI		 3247 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3248 return !0;
d855497e
MI		 3249}
3250
3251
3252int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3253{
681c7399
MI		 3254 int fl;
3255 LOCK_TAKE(hdw->big_lock);
3256 fl = pvr2_hdw_commit_setup(hdw);
3257 LOCK_GIVE(hdw->big_lock);
3258 if (!fl) return 0;
3259 return pvr2_hdw_wait(hdw,0);
3260}
3261
3262
681c7399 3263static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 3264{
681c7399
MI		 3265 int fl = 0;
3266 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 3267 LOCK_TAKE(hdw->big_lock); do {
681c7399 3268 fl = pvr2_hdw_state_eval(hdw);
d855497e 3269 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 3270 if (fl && hdw->state_func) {
3271 hdw->state_func(hdw->state_data);
3272 }
d855497e
MI		 3273}
3274
3275
681c7399 3276static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 3277{
681c7399
MI		 3278 return wait_event_interruptible(
3279 hdw->state_wait_data,
3280 (hdw->state_stale == 0) &&
3281 (!state || (hdw->master_state != state)));
3282}
3283
3284
d855497e
MI		 3285/* Return name for this driver instance */
3286const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3287{
3288 return hdw->name;
3289}
3290
3291
78a47101
MI		 3292const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3293{
3294 return hdw->hdw_desc->description;
3295}
3296
3297
3298const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3299{
3300 return hdw->hdw_desc->shortname;
3301}
3302
3303
d855497e
MI		 3304int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3305{
3306 int result;
3307 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3308 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 3309 result = pvr2_send_request(hdw,
3310 hdw->cmd_buffer,1,
3311 hdw->cmd_buffer,1);
3312 if (result < 0) break;
3313 result = (hdw->cmd_buffer[0] != 0);
3314 } while(0); LOCK_GIVE(hdw->ctl_lock);
3315 return result;
3316}
3317
3318
18103c57
MI		 3319/* Execute poll of tuner status */
3320void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 3321{
d855497e 3322 LOCK_TAKE(hdw->big_lock); do {
a51f5000 3323 pvr2_hdw_status_poll(hdw);
d855497e 3324 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 3325}
3326
3327
432907f7
MI		 3328static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3329{
3330 if (!hdw->cropcap_stale) {
432907f7
MI		 3331 return 0;
3332 }
a51f5000 3333 pvr2_hdw_status_poll(hdw);
432907f7 3334 if (hdw->cropcap_stale) {
432907f7
MI		 3335 return -EIO;
3336 }
3337 return 0;
3338}
3339
3340
3341/* Return information about cropping capabilities */
3342int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3343{
3344 int stat = 0;
3345 LOCK_TAKE(hdw->big_lock);
3346 stat = pvr2_hdw_check_cropcap(hdw);
3347 if (!stat) {
432907f7
MI		 3348 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3349 }
3350 LOCK_GIVE(hdw->big_lock);
3351 return stat;
3352}
3353
3354
18103c57
MI		 3355/* Return information about the tuner */
3356int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3357{
3358 LOCK_TAKE(hdw->big_lock); do {
3359 if (hdw->tuner_signal_stale) {
a51f5000 3360 pvr2_hdw_status_poll(hdw);
18103c57
MI		 3361 }
3362 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3363 } while (0); LOCK_GIVE(hdw->big_lock);
3364 return 0;
d855497e
MI		 3365}
3366
3367
3368/* Get handle to video output stream */
3369struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3370{
3371 return hp->vid_stream;
3372}
3373
3374
3375void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3376{
4f1a3e5b 3377 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e 3378 LOCK_TAKE(hdw->big_lock); do {
4f1a3e5b 3379 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
ed3261a8 3380 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
b30d2441 3381 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 3382 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 3383 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 3384 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 3385 } while (0); LOCK_GIVE(hdw->big_lock);
3386}
3387
4db666cc
MI		 3388
3389/* Grab EEPROM contents, needed for direct method. */
3390#define EEPROM_SIZE 8192
3391#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3392static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3393{
3394 struct i2c_msg msg[2];
3395 u8 *eeprom;
3396 u8 iadd[2];
3397 u8 addr;
3398 u16 eepromSize;
3399 unsigned int offs;
3400 int ret;
3401 int mode16 = 0;
3402 unsigned pcnt,tcnt;
3403 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3404 if (!eeprom) {
3405 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3406 "Failed to allocate memory"
3407 " required to read eeprom");
3408 return NULL;
3409 }
3410
3411 trace_eeprom("Value for eeprom addr from controller was 0x%x",
3412 hdw->eeprom_addr);
3413 addr = hdw->eeprom_addr;
3414 /* Seems that if the high bit is set, then the *real* eeprom
3415 address is shifted right now bit position (noticed this in
3416 newer PVR USB2 hardware) */
3417 if (addr & 0x80) addr >>= 1;
3418
3419 /* FX2 documentation states that a 16bit-addressed eeprom is
3420 expected if the I2C address is an odd number (yeah, this is
3421 strange but it's what they do) */
3422 mode16 = (addr & 1);
3423 eepromSize = (mode16 ? EEPROM_SIZE : 256);
3424 trace_eeprom("Examining %d byte eeprom at location 0x%x"
3425 " using %d bit addressing",eepromSize,addr,
3426 mode16 ? 16 : 8);
3427
3428 msg[0].addr = addr;
3429 msg[0].flags = 0;
3430 msg[0].len = mode16 ? 2 : 1;
3431 msg[0].buf = iadd;
3432 msg[1].addr = addr;
3433 msg[1].flags = I2C_M_RD;
3434
3435 /* We have to do the actual eeprom data fetch ourselves, because
3436 (1) we're only fetching part of the eeprom, and (2) if we were
3437 getting the whole thing our I2C driver can't grab it in one
3438 pass - which is what tveeprom is otherwise going to attempt */
3439 memset(eeprom,0,EEPROM_SIZE);
3440 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3441 pcnt = 16;
3442 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3443 offs = tcnt + (eepromSize - EEPROM_SIZE);
3444 if (mode16) {
3445 iadd[0] = offs >> 8;
3446 iadd[1] = offs;
3447 } else {
3448 iadd[0] = offs;
3449 }
3450 msg[1].len = pcnt;
3451 msg[1].buf = eeprom+tcnt;
3452 if ((ret = i2c_transfer(&hdw->i2c_adap,
3453 msg,ARRAY_SIZE(msg))) != 2) {
3454 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3455 "eeprom fetch set offs err=%d",ret);
3456 kfree(eeprom);
3457 return NULL;
3458 }
3459 }
3460 return eeprom;
3461}
3462
3463
3464void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3465 int prom_flag,
3466 int enable_flag)
d855497e
MI		 3467{
3468 int ret;
3469 u16 address;
3470 unsigned int pipe;
3471 LOCK_TAKE(hdw->big_lock); do {
5fa1247a 3472 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
d855497e
MI		 3473
3474 if (!enable_flag) {
3475 pvr2_trace(PVR2_TRACE_FIRMWARE,
3476 "Cleaning up after CPU firmware fetch");
3477 kfree(hdw->fw_buffer);
a0fd1cb1 3478 hdw->fw_buffer = NULL;
d855497e 3479 hdw->fw_size = 0;
4db666cc
MI		 3480 if (hdw->fw_cpu_flag) {
3481 /* Now release the CPU. It will disconnect
3482 and reconnect later. */
3483 pvr2_hdw_cpureset_assert(hdw,0);
3484 }
d855497e
MI		 3485 break;
3486 }
3487
4db666cc
MI		 3488 hdw->fw_cpu_flag = (prom_flag == 0);
3489 if (hdw->fw_cpu_flag) {
3490 pvr2_trace(PVR2_TRACE_FIRMWARE,
3491 "Preparing to suck out CPU firmware");
3492 hdw->fw_size = 0x2000;
3493 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3494 if (!hdw->fw_buffer) {
3495 hdw->fw_size = 0;
3496 break;
3497 }
d855497e 3498
4db666cc
MI		 3499 /* We have to hold the CPU during firmware upload. */
3500 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 3501
4db666cc
MI		 3502 /* download the firmware from address 0000-1fff in 2048
3503 (=0x800) bytes chunk. */
d855497e 3504
4db666cc
MI		 3505 pvr2_trace(PVR2_TRACE_FIRMWARE,
3506 "Grabbing CPU firmware");
3507 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3508 for(address = 0; address < hdw->fw_size;
3509 address += 0x800) {
3510 ret = usb_control_msg(hdw->usb_dev,pipe,
3511 0xa0,0xc0,
3512 address,0,
3513 hdw->fw_buffer+address,
3514 0x800,HZ);
3515 if (ret < 0) break;
3516 }
d855497e 3517
4db666cc
MI		 3518 pvr2_trace(PVR2_TRACE_FIRMWARE,
3519 "Done grabbing CPU firmware");
3520 } else {
3521 pvr2_trace(PVR2_TRACE_FIRMWARE,
3522 "Sucking down EEPROM contents");
3523 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3524 if (!hdw->fw_buffer) {
3525 pvr2_trace(PVR2_TRACE_FIRMWARE,
3526 "EEPROM content suck failed.");
3527 break;
3528 }
3529 hdw->fw_size = EEPROM_SIZE;
3530 pvr2_trace(PVR2_TRACE_FIRMWARE,
3531 "Done sucking down EEPROM contents");
3532 }
d855497e
MI		 3533
3534 } while (0); LOCK_GIVE(hdw->big_lock);
3535}
3536
3537
3538/* Return true if we're in a mode for retrieval CPU firmware */
3539int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3540{
5fa1247a 3541 return hdw->fw_buffer != NULL;
d855497e
MI		 3542}
3543
3544
3545int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3546 char *buf,unsigned int cnt)
3547{
3548 int ret = -EINVAL;
3549 LOCK_TAKE(hdw->big_lock); do {
3550 if (!buf) break;
3551 if (!cnt) break;
3552
3553 if (!hdw->fw_buffer) {
3554 ret = -EIO;
3555 break;
3556 }
3557
3558 if (offs >= hdw->fw_size) {
3559 pvr2_trace(PVR2_TRACE_FIRMWARE,
3560 "Read firmware data offs=%d EOF",
3561 offs);
3562 ret = 0;
3563 break;
3564 }
3565
3566 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3567
3568 memcpy(buf,hdw->fw_buffer+offs,cnt);
3569
3570 pvr2_trace(PVR2_TRACE_FIRMWARE,
3571 "Read firmware data offs=%d cnt=%d",
3572 offs,cnt);
3573 ret = cnt;
3574 } while (0); LOCK_GIVE(hdw->big_lock);
3575
3576 return ret;
3577}
3578
3579
fd5a75fe 3580int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 3581 enum pvr2_v4l_type index)
d855497e 3582{
fd5a75fe 3583 switch (index) {
8079384e
MI		 3584 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3585 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3586 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 3587 default: return -1;
3588 }
d855497e
MI		 3589}
3590
3591
2fdf3d9c 3592/* Store a v4l minor device number */
fd5a75fe 3593void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 3594 enum pvr2_v4l_type index,int v)
d855497e 3595{
fd5a75fe 3596 switch (index) {
8079384e
MI		 3597 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3598 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3599 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 3600 default: break;
3601 }
d855497e
MI		 3602}
3603
3604
7d12e780 3605static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 3606{
3607 struct pvr2_hdw *hdw = urb->context;
3608 hdw->ctl_write_pend_flag = 0;
3609 if (hdw->ctl_read_pend_flag) return;
3610 complete(&hdw->ctl_done);
3611}
3612
3613
7d12e780 3614static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 3615{
3616 struct pvr2_hdw *hdw = urb->context;
3617 hdw->ctl_read_pend_flag = 0;
3618 if (hdw->ctl_write_pend_flag) return;
3619 complete(&hdw->ctl_done);
3620}
3621
3622
3623static void pvr2_ctl_timeout(unsigned long data)
3624{
3625 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3626 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3627 hdw->ctl_timeout_flag = !0;
5e55d2ce 3628 if (hdw->ctl_write_pend_flag)
d855497e 3629 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 3630 if (hdw->ctl_read_pend_flag)
d855497e 3631 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 3632 }
3633}
3634
3635
e61b6fc5
MI		 3636/* Issue a command and get a response from the device. This extended
3637 version includes a probe flag (which if set means that device errors
3638 should not be logged or treated as fatal) and a timeout in jiffies.
3639 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 3640static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3641 unsigned int timeout,int probe_fl,
3642 void *write_data,unsigned int write_len,
3643 void *read_data,unsigned int read_len)
d855497e
MI		 3644{
3645 unsigned int idx;
3646 int status = 0;
3647 struct timer_list timer;
3648 if (!hdw->ctl_lock_held) {
3649 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3650 "Attempted to execute control transfer"
3651 " without lock!!");
3652 return -EDEADLK;
3653 }
681c7399 3654 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 3655 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3656 "Attempted to execute control transfer"
3657 " when device not ok");
3658 return -EIO;
3659 }
3660 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3661 if (!probe_fl) {
3662 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3663 "Attempted to execute control transfer"
3664 " when USB is disconnected");
3665 }
3666 return -ENOTTY;
3667 }
3668
3669 /* Ensure that we have sane parameters */
3670 if (!write_data) write_len = 0;
3671 if (!read_data) read_len = 0;
3672 if (write_len > PVR2_CTL_BUFFSIZE) {
3673 pvr2_trace(
3674 PVR2_TRACE_ERROR_LEGS,
3675 "Attempted to execute %d byte"
3676 " control-write transfer (limit=%d)",
3677 write_len,PVR2_CTL_BUFFSIZE);
3678 return -EINVAL;
3679 }
3680 if (read_len > PVR2_CTL_BUFFSIZE) {
3681 pvr2_trace(
3682 PVR2_TRACE_ERROR_LEGS,
3683 "Attempted to execute %d byte"
3684 " control-read transfer (limit=%d)",
3685 write_len,PVR2_CTL_BUFFSIZE);
3686 return -EINVAL;
3687 }
3688 if ((!write_len) && (!read_len)) {
3689 pvr2_trace(
3690 PVR2_TRACE_ERROR_LEGS,
3691 "Attempted to execute null control transfer?");
3692 return -EINVAL;
3693 }
3694
3695
3696 hdw->cmd_debug_state = 1;
3697 if (write_len) {
3698 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3699 } else {
3700 hdw->cmd_debug_code = 0;
3701 }
3702 hdw->cmd_debug_write_len = write_len;
3703 hdw->cmd_debug_read_len = read_len;
3704
3705 /* Initialize common stuff */
3706 init_completion(&hdw->ctl_done);
3707 hdw->ctl_timeout_flag = 0;
3708 hdw->ctl_write_pend_flag = 0;
3709 hdw->ctl_read_pend_flag = 0;
3710 init_timer(&timer);
3711 timer.expires = jiffies + timeout;
3712 timer.data = (unsigned long)hdw;
3713 timer.function = pvr2_ctl_timeout;
3714
3715 if (write_len) {
3716 hdw->cmd_debug_state = 2;
3717 /* Transfer write data to internal buffer */
3718 for (idx = 0; idx < write_len; idx++) {
3719 hdw->ctl_write_buffer[idx] =
3720 ((unsigned char *)write_data)[idx];
3721 }
3722 /* Initiate a write request */
3723 usb_fill_bulk_urb(hdw->ctl_write_urb,
3724 hdw->usb_dev,
3725 usb_sndbulkpipe(hdw->usb_dev,
3726 PVR2_CTL_WRITE_ENDPOINT),
3727 hdw->ctl_write_buffer,
3728 write_len,
3729 pvr2_ctl_write_complete,
3730 hdw);
3731 hdw->ctl_write_urb->actual_length = 0;
3732 hdw->ctl_write_pend_flag = !0;
3733 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3734 if (status < 0) {
3735 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3736 "Failed to submit write-control"
3737 " URB status=%d",status);
3738 hdw->ctl_write_pend_flag = 0;
3739 goto done;
3740 }
3741 }
3742
3743 if (read_len) {
3744 hdw->cmd_debug_state = 3;
3745 memset(hdw->ctl_read_buffer,0x43,read_len);
3746 /* Initiate a read request */
3747 usb_fill_bulk_urb(hdw->ctl_read_urb,
3748 hdw->usb_dev,
3749 usb_rcvbulkpipe(hdw->usb_dev,
3750 PVR2_CTL_READ_ENDPOINT),
3751 hdw->ctl_read_buffer,
3752 read_len,
3753 pvr2_ctl_read_complete,
3754 hdw);
3755 hdw->ctl_read_urb->actual_length = 0;
3756 hdw->ctl_read_pend_flag = !0;
3757 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3758 if (status < 0) {
3759 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3760 "Failed to submit read-control"
3761 " URB status=%d",status);
3762 hdw->ctl_read_pend_flag = 0;
3763 goto done;
3764 }
3765 }
3766
3767 /* Start timer */
3768 add_timer(&timer);
3769
3770 /* Now wait for all I/O to complete */
3771 hdw->cmd_debug_state = 4;
3772 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3773 wait_for_completion(&hdw->ctl_done);
3774 }
3775 hdw->cmd_debug_state = 5;
3776
3777 /* Stop timer */
3778 del_timer_sync(&timer);
3779
3780 hdw->cmd_debug_state = 6;
3781 status = 0;
3782
3783 if (hdw->ctl_timeout_flag) {
3784 status = -ETIMEDOUT;
3785 if (!probe_fl) {
3786 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3787 "Timed out control-write");
3788 }
3789 goto done;
3790 }
3791
3792 if (write_len) {
3793 /* Validate results of write request */
3794 if ((hdw->ctl_write_urb->status != 0) &&
3795 (hdw->ctl_write_urb->status != -ENOENT) &&
3796 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3797 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3798 /* USB subsystem is reporting some kind of failure
3799 on the write */
3800 status = hdw->ctl_write_urb->status;
3801 if (!probe_fl) {
3802 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3803 "control-write URB failure,"
3804 " status=%d",
3805 status);
3806 }
3807 goto done;
3808 }
3809 if (hdw->ctl_write_urb->actual_length < write_len) {
3810 /* Failed to write enough data */
3811 status = -EIO;
3812 if (!probe_fl) {
3813 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3814 "control-write URB short,"
3815 " expected=%d got=%d",
3816 write_len,
3817 hdw->ctl_write_urb->actual_length);
3818 }
3819 goto done;
3820 }
3821 }
3822 if (read_len) {
3823 /* Validate results of read request */
3824 if ((hdw->ctl_read_urb->status != 0) &&
3825 (hdw->ctl_read_urb->status != -ENOENT) &&
3826 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3827 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3828 /* USB subsystem is reporting some kind of failure
3829 on the read */
3830 status = hdw->ctl_read_urb->status;
3831 if (!probe_fl) {
3832 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3833 "control-read URB failure,"
3834 " status=%d",
3835 status);
3836 }
3837 goto done;
3838 }
3839 if (hdw->ctl_read_urb->actual_length < read_len) {
3840 /* Failed to read enough data */
3841 status = -EIO;
3842 if (!probe_fl) {
3843 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3844 "control-read URB short,"
3845 " expected=%d got=%d",
3846 read_len,
3847 hdw->ctl_read_urb->actual_length);
3848 }
3849 goto done;
3850 }
3851 /* Transfer retrieved data out from internal buffer */
3852 for (idx = 0; idx < read_len; idx++) {
3853 ((unsigned char *)read_data)[idx] =
3854 hdw->ctl_read_buffer[idx];
3855 }
3856 }
3857
3858 done:
3859
3860 hdw->cmd_debug_state = 0;
3861 if ((status < 0) && (!probe_fl)) {
681c7399 3862 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3863 }
3864 return status;
3865}
3866
3867
3868int pvr2_send_request(struct pvr2_hdw *hdw,
3869 void *write_data,unsigned int write_len,
3870 void *read_data,unsigned int read_len)
3871{
3872 return pvr2_send_request_ex(hdw,HZ*4,0,
3873 write_data,write_len,
3874 read_data,read_len);
3875}
3876
1c9d10d4
MI		 3877
3878static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3879{
3880 int ret;
3881 unsigned int cnt = 1;
3882 unsigned int args = 0;
3883 LOCK_TAKE(hdw->ctl_lock);
3884 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3885 args = (cmdcode >> 8) & 0xffu;
3886 args = (args > 2) ? 2 : args;
3887 if (args) {
3888 cnt += args;
3889 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3890 if (args > 1) {
3891 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3892 }
3893 }
3894 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3895 unsigned int idx;
3896 unsigned int ccnt,bcnt;
3897 char tbuf[50];
3898 cmdcode &= 0xffu;
3899 bcnt = 0;
3900 ccnt = scnprintf(tbuf+bcnt,
3901 sizeof(tbuf)-bcnt,
3902 "Sending FX2 command 0x%x",cmdcode);
3903 bcnt += ccnt;
3904 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3905 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3906 ccnt = scnprintf(tbuf+bcnt,
3907 sizeof(tbuf)-bcnt,
3908 " \"%s\"",
3909 pvr2_fx2cmd_desc[idx].desc);
3910 bcnt += ccnt;
3911 break;
3912 }
3913 }
3914 if (args) {
3915 ccnt = scnprintf(tbuf+bcnt,
3916 sizeof(tbuf)-bcnt,
3917 " (%u",hdw->cmd_buffer[1]);
3918 bcnt += ccnt;
3919 if (args > 1) {
3920 ccnt = scnprintf(tbuf+bcnt,
3921 sizeof(tbuf)-bcnt,
3922 ",%u",hdw->cmd_buffer[2]);
3923 bcnt += ccnt;
3924 }
3925 ccnt = scnprintf(tbuf+bcnt,
3926 sizeof(tbuf)-bcnt,
3927 ")");
3928 bcnt += ccnt;
3929 }
3930 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3931 }
3932 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3933 LOCK_GIVE(hdw->ctl_lock);
3934 return ret;
3935}
3936
3937
d855497e
MI		 3938int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3939{
3940 int ret;
3941
3942 LOCK_TAKE(hdw->ctl_lock);
3943
8d364363 3944 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 3945 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3946 hdw->cmd_buffer[5] = 0;
3947 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3948 hdw->cmd_buffer[7] = reg & 0xff;
3949
3950
3951 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3952
3953 LOCK_GIVE(hdw->ctl_lock);
3954
3955 return ret;
3956}
3957
3958
07e337ee 3959static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 3960{
3961 int ret = 0;
3962
3963 LOCK_TAKE(hdw->ctl_lock);
3964
8d364363 3965 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 3966 hdw->cmd_buffer[1] = 0;
3967 hdw->cmd_buffer[2] = 0;
3968 hdw->cmd_buffer[3] = 0;
3969 hdw->cmd_buffer[4] = 0;
3970 hdw->cmd_buffer[5] = 0;
3971 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3972 hdw->cmd_buffer[7] = reg & 0xff;
3973
3974 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3975 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3976
3977 LOCK_GIVE(hdw->ctl_lock);
3978
3979 return ret;
3980}
3981
3982
681c7399 3983void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 3984{
3985 if (!hdw->flag_ok) return;
681c7399
MI		 3986 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3987 "Device being rendered inoperable");
d855497e 3988 if (hdw->vid_stream) {
a0fd1cb1 3989 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 3990 }
681c7399
MI		 3991 hdw->flag_ok = 0;
3992 trace_stbit("flag_ok",hdw->flag_ok);
3993 pvr2_hdw_state_sched(hdw);
d855497e
MI		 3994}
3995
3996
3997void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3998{
3999 int ret;
4000 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 4001 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
011b15df 4002 if (ret == 0) {
d855497e
MI		 4003 ret = usb_reset_device(hdw->usb_dev);
4004 usb_unlock_device(hdw->usb_dev);
4005 } else {
4006 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4007 "Failed to lock USB device ret=%d",ret);
4008 }
4009 if (init_pause_msec) {
4010 pvr2_trace(PVR2_TRACE_INFO,
4011 "Waiting %u msec for hardware to settle",
4012 init_pause_msec);
4013 msleep(init_pause_msec);
4014 }
4015
4016}
4017
4018
4019void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4020{
4021 char da[1];
4022 unsigned int pipe;
4023 int ret;
4024
4025 if (!hdw->usb_dev) return;
4026
4027 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4028
4029 da[0] = val ? 0x01 : 0x00;
4030
4031 /* Write the CPUCS register on the 8051. The lsb of the register
4032 is the reset bit; a 1 asserts reset while a 0 clears it. */
4033 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4034 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4035 if (ret < 0) {
4036 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4037 "cpureset_assert(%d) error=%d",val,ret);
4038 pvr2_hdw_render_useless(hdw);
4039 }
4040}
4041
4042
4043int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4044{
1c9d10d4 4045 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
d855497e
MI		 4046}
4047
4048
e1edb19a
MK		 4049int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4050{
1c9d10d4 4051 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
e1edb19a
MK		 4052}
4053
1c9d10d4 4054
e1edb19a
MK		 4055int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4056{
1c9d10d4 4057 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
e1edb19a
MK		 4058}
4059
d855497e
MI		 4060
4061int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4062{
af78e16b
MI		 4063 pvr2_trace(PVR2_TRACE_INIT,
4064 "Requesting decoder reset");
af78e16b
MI		 4065 if (hdw->decoder_client_id) {
4066 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4067 core, reset, 0);
4068 return 0;
d855497e 4069 }
d855497e 4070 pvr2_trace(PVR2_TRACE_INIT,
af78e16b
MI		 4071 "Unable to reset decoder: nothing attached");
4072 return -ENOTTY;
d855497e
MI		 4073}
4074
4075
62433e31 4076static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
84147f3d 4077{
1c9d10d4
MI		 4078 hdw->flag_ok = !0;
4079 return pvr2_issue_simple_cmd(hdw,
4080 FX2CMD_HCW_DEMOD_RESETIN |
4081 (1 << 8) |
4082 ((onoff ? 1 : 0) << 16));
84147f3d
MI		 4083}
4084
84147f3d 4085
62433e31 4086static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
84147f3d 4087{
1c9d10d4
MI		 4088 hdw->flag_ok = !0;
4089 return pvr2_issue_simple_cmd(hdw,(onoff ?
4090 FX2CMD_ONAIR_DTV_POWER_ON :
4091 FX2CMD_ONAIR_DTV_POWER_OFF));
84147f3d
MI		 4092}
4093
62433e31
MI		 4094
4095static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4096 int onoff)
84147f3d 4097{
1c9d10d4
MI		 4098 return pvr2_issue_simple_cmd(hdw,(onoff ?
4099 FX2CMD_ONAIR_DTV_STREAMING_ON :
4100 FX2CMD_ONAIR_DTV_STREAMING_OFF));
84147f3d
MI		 4101}
4102
62433e31
MI		 4103
4104static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4105{
4106 int cmode;
4107 /* Compare digital/analog desired setting with current setting. If
4108 they don't match, fix it... */
4109 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4110 if (cmode == hdw->pathway_state) {
4111 /* They match; nothing to do */
4112 return;
4113 }
4114
4115 switch (hdw->hdw_desc->digital_control_scheme) {
4116 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4117 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4118 if (cmode == PVR2_PATHWAY_ANALOG) {
4119 /* If moving to analog mode, also force the decoder
4120 to reset. If no decoder is attached, then it's
4121 ok to ignore this because if/when the decoder
4122 attaches, it will reset itself at that time. */
4123 pvr2_hdw_cmd_decoder_reset(hdw);
4124 }
4125 break;
4126 case PVR2_DIGITAL_SCHEME_ONAIR:
4127 /* Supposedly we should always have the power on whether in
4128 digital or analog mode. But for now do what appears to
4129 work... */
bb0c2fe0 4130 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
62433e31
MI		 4131 break;
4132 default: break;
4133 }
4134
1b9c18c5 4135 pvr2_hdw_untrip_unlocked(hdw);
62433e31
MI		 4136 hdw->pathway_state = cmode;
4137}
4138
4139
e9b59f6e 4140static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
c55a97d7
MI		 4141{
4142 /* change some GPIO data
4143 *
4144 * note: bit d7 of dir appears to control the LED,
4145 * so we shut it off here.
4146 *
c55a97d7 4147 */
40381cb0 4148 if (onoff) {
c55a97d7 4149 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
40381cb0 4150 } else {
c55a97d7 4151 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
40381cb0 4152 }
c55a97d7 4153 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
40381cb0 4154}
c55a97d7 4155
40381cb0
MI		 4156
4157typedef void (*led_method_func)(struct pvr2_hdw *,int);
4158
4159static led_method_func led_methods[] = {
4160 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4161};
4162
4163
4164/* Toggle LED */
4165static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4166{
4167 unsigned int scheme_id;
4168 led_method_func fp;
4169
4170 if ((!onoff) == (!hdw->led_on)) return;
4171
4172 hdw->led_on = onoff != 0;
4173
4174 scheme_id = hdw->hdw_desc->led_scheme;
4175 if (scheme_id < ARRAY_SIZE(led_methods)) {
4176 fp = led_methods[scheme_id];
4177 } else {
4178 fp = NULL;
4179 }
4180
4181 if (fp) (*fp)(hdw,onoff);
c55a97d7
MI		 4182}
4183
4184
e61b6fc5 4185/* Stop / start video stream transport */
07e337ee 4186static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e 4187{
bb0c2fe0
MI		 4188 int ret;
4189
4190 /* If we're in analog mode, then just issue the usual analog
4191 command. */
4192 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4193 return pvr2_issue_simple_cmd(hdw,
4194 (runFl ?
4195 FX2CMD_STREAMING_ON :
4196 FX2CMD_STREAMING_OFF));
4197 /*Note: Not reached */
4198 }
4199
4200 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4201 /* Whoops, we don't know what mode we're in... */
4202 return -EINVAL;
4203 }
4204
4205 /* To get here we have to be in digital mode. The mechanism here
4206 is unfortunately different for different vendors. So we switch
4207 on the device's digital scheme attribute in order to figure out
4208 what to do. */
4209 switch (hdw->hdw_desc->digital_control_scheme) {
4210 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4211 return pvr2_issue_simple_cmd(hdw,
4212 (runFl ?
4213 FX2CMD_HCW_DTV_STREAMING_ON :
4214 FX2CMD_HCW_DTV_STREAMING_OFF));
4215 case PVR2_DIGITAL_SCHEME_ONAIR:
4216 ret = pvr2_issue_simple_cmd(hdw,
4217 (runFl ?
4218 FX2CMD_STREAMING_ON :
4219 FX2CMD_STREAMING_OFF));
4220 if (ret) return ret;
4221 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4222 default:
4223 return -EINVAL;
62433e31 4224 }
d855497e
MI		 4225}
4226
4227
62433e31
MI		 4228/* Evaluate whether or not state_pathway_ok can change */
4229static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4230{
4231 if (hdw->state_pathway_ok) {
4232 /* Nothing to do if pathway is already ok */
4233 return 0;
4234 }
4235 if (!hdw->state_pipeline_idle) {
4236 /* Not allowed to change anything if pipeline is not idle */
4237 return 0;
4238 }
4239 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4240 hdw->state_pathway_ok = !0;
e9db1ff2 4241 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 4242 return !0;
4243}
4244
4245
681c7399
MI		 4246/* Evaluate whether or not state_encoder_ok can change */
4247static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4248{
4249 if (hdw->state_encoder_ok) return 0;
4250 if (hdw->flag_tripped) return 0;
4251 if (hdw->state_encoder_run) return 0;
4252 if (hdw->state_encoder_config) return 0;
4253 if (hdw->state_decoder_run) return 0;
4254 if (hdw->state_usbstream_run) return 0;
72998b71
MI		 4255 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4256 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4257 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4258 return 0;
4259 }
4260
681c7399
MI		 4261 if (pvr2_upload_firmware2(hdw) < 0) {
4262 hdw->flag_tripped = !0;
4263 trace_stbit("flag_tripped",hdw->flag_tripped);
4264 return !0;
4265 }
4266 hdw->state_encoder_ok = !0;
4267 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4268 return !0;
4269}
4270
4271
4272/* Evaluate whether or not state_encoder_config can change */
4273static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4274{
4275 if (hdw->state_encoder_config) {
4276 if (hdw->state_encoder_ok) {
4277 if (hdw->state_pipeline_req &&
4278 !hdw->state_pipeline_pause) return 0;
4279 }
4280 hdw->state_encoder_config = 0;
4281 hdw->state_encoder_waitok = 0;
4282 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4283 /* paranoia - solve race if timer just completed */
4284 del_timer_sync(&hdw->encoder_wait_timer);
4285 } else {
62433e31
MI		 4286 if (!hdw->state_pathway_ok ||
4287 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4288 !hdw->state_encoder_ok ||
681c7399
MI		 4289 !hdw->state_pipeline_idle ||
4290 hdw->state_pipeline_pause ||
4291 !hdw->state_pipeline_req ||
4292 !hdw->state_pipeline_config) {
4293 /* We must reset the enforced wait interval if
4294 anything has happened that might have disturbed
4295 the encoder. This should be a rare case. */
4296 if (timer_pending(&hdw->encoder_wait_timer)) {
4297 del_timer_sync(&hdw->encoder_wait_timer);
4298 }
4299 if (hdw->state_encoder_waitok) {
4300 /* Must clear the state - therefore we did
4301 something to a state bit and must also
4302 return true. */
4303 hdw->state_encoder_waitok = 0;
4304 trace_stbit("state_encoder_waitok",
4305 hdw->state_encoder_waitok);
4306 return !0;
4307 }
4308 return 0;
4309 }
4310 if (!hdw->state_encoder_waitok) {
4311 if (!timer_pending(&hdw->encoder_wait_timer)) {
4312 /* waitok flag wasn't set and timer isn't
4313 running. Check flag once more to avoid
4314 a race then start the timer. This is
4315 the point when we measure out a minimal
4316 quiet interval before doing something to
4317 the encoder. */
4318 if (!hdw->state_encoder_waitok) {
4319 hdw->encoder_wait_timer.expires =
83ce57aa
MI		 4320 jiffies +
4321 (HZ * TIME_MSEC_ENCODER_WAIT
4322 / 1000);
681c7399
MI		 4323 add_timer(&hdw->encoder_wait_timer);
4324 }
4325 }
4326 /* We can't continue until we know we have been
4327 quiet for the interval measured by this
4328 timer. */
4329 return 0;
4330 }
4331 pvr2_encoder_configure(hdw);
4332 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4333 }
4334 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4335 return !0;
4336}
4337
4338
d913d630
MI		 4339/* Return true if the encoder should not be running. */
4340static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4341{
4342 if (!hdw->state_encoder_ok) {
4343 /* Encoder isn't healthy at the moment, so stop it. */
4344 return !0;
4345 }
4346 if (!hdw->state_pathway_ok) {
4347 /* Mode is not understood at the moment (i.e. it wants to
4348 change), so encoder must be stopped. */
4349 return !0;
4350 }
4351
4352 switch (hdw->pathway_state) {
4353 case PVR2_PATHWAY_ANALOG:
4354 if (!hdw->state_decoder_run) {
4355 /* We're in analog mode and the decoder is not
4356 running; thus the encoder should be stopped as
4357 well. */
4358 return !0;
4359 }
4360 break;
4361 case PVR2_PATHWAY_DIGITAL:
4362 if (hdw->state_encoder_runok) {
4363 /* This is a funny case. We're in digital mode so
4364 really the encoder should be stopped. However
4365 if it really is running, only kill it after
4366 runok has been set. This gives a chance for the
4367 onair quirk to function (encoder must run
4368 briefly first, at least once, before onair
4369 digital streaming can work). */
4370 return !0;
4371 }
4372 break;
4373 default:
4374 /* Unknown mode; so encoder should be stopped. */
4375 return !0;
4376 }
4377
4378 /* If we get here, we haven't found a reason to stop the
4379 encoder. */
4380 return 0;
4381}
4382
4383
4384/* Return true if the encoder should be running. */
4385static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4386{
4387 if (!hdw->state_encoder_ok) {
4388 /* Don't run the encoder if it isn't healthy... */
4389 return 0;
4390 }
4391 if (!hdw->state_pathway_ok) {
4392 /* Don't run the encoder if we don't (yet) know what mode
4393 we need to be in... */
4394 return 0;
4395 }
4396
4397 switch (hdw->pathway_state) {
4398 case PVR2_PATHWAY_ANALOG:
4399 if (hdw->state_decoder_run) {
4400 /* In analog mode, if the decoder is running, then
4401 run the encoder. */
4402 return !0;
4403 }
4404 break;
4405 case PVR2_PATHWAY_DIGITAL:
4406 if ((hdw->hdw_desc->digital_control_scheme ==
4407 PVR2_DIGITAL_SCHEME_ONAIR) &&
4408 !hdw->state_encoder_runok) {
4409 /* This is a quirk. OnAir hardware won't stream
4410 digital until the encoder has been run at least
4411 once, for a minimal period of time (empiricially
4412 measured to be 1/4 second). So if we're on
4413 OnAir hardware and the encoder has never been
4414 run at all, then start the encoder. Normal
4415 state machine logic in the driver will
4416 automatically handle the remaining bits. */
4417 return !0;
4418 }
4419 break;
4420 default:
4421 /* For completeness (unknown mode; encoder won't run ever) */
4422 break;
4423 }
4424 /* If we get here, then we haven't found any reason to run the
4425 encoder, so don't run it. */
4426 return 0;
4427}
4428
4429
681c7399
MI		 4430/* Evaluate whether or not state_encoder_run can change */
4431static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4432{
4433 if (hdw->state_encoder_run) {
d913d630 4434 if (!state_check_disable_encoder_run(hdw)) return 0;
681c7399 4435 if (hdw->state_encoder_ok) {
d913d630 4436 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 4437 if (pvr2_encoder_stop(hdw) < 0) return !0;
4438 }
4439 hdw->state_encoder_run = 0;
4440 } else {
d913d630 4441 if (!state_check_enable_encoder_run(hdw)) return 0;
681c7399
MI		 4442 if (pvr2_encoder_start(hdw) < 0) return !0;
4443 hdw->state_encoder_run = !0;
d913d630
MI		 4444 if (!hdw->state_encoder_runok) {
4445 hdw->encoder_run_timer.expires =
83ce57aa 4446 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
d913d630
MI		 4447 add_timer(&hdw->encoder_run_timer);
4448 }
681c7399
MI		 4449 }
4450 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4451 return !0;
4452}
4453
4454
4455/* Timeout function for quiescent timer. */
4456static void pvr2_hdw_quiescent_timeout(unsigned long data)
4457{
4458 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4459 hdw->state_decoder_quiescent = !0;
4460 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4461 hdw->state_stale = !0;
4462 queue_work(hdw->workqueue,&hdw->workpoll);
4463}
4464
4465
4466/* Timeout function for encoder wait timer. */
4467static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4468{
4469 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4470 hdw->state_encoder_waitok = !0;
4471 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4472 hdw->state_stale = !0;
4473 queue_work(hdw->workqueue,&hdw->workpoll);
4474}
4475
4476
d913d630
MI		 4477/* Timeout function for encoder run timer. */
4478static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4479{
4480 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4481 if (!hdw->state_encoder_runok) {
4482 hdw->state_encoder_runok = !0;
4483 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4484 hdw->state_stale = !0;
4485 queue_work(hdw->workqueue,&hdw->workpoll);
4486 }
4487}
4488
4489
681c7399
MI		 4490/* Evaluate whether or not state_decoder_run can change */
4491static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4492{
4493 if (hdw->state_decoder_run) {
4494 if (hdw->state_encoder_ok) {
4495 if (hdw->state_pipeline_req &&
62433e31
MI		 4496 !hdw->state_pipeline_pause &&
4497 hdw->state_pathway_ok) return 0;
681c7399
MI		 4498 }
4499 if (!hdw->flag_decoder_missed) {
4500 pvr2_decoder_enable(hdw,0);
4501 }
4502 hdw->state_decoder_quiescent = 0;
4503 hdw->state_decoder_run = 0;
4504 /* paranoia - solve race if timer just completed */
4505 del_timer_sync(&hdw->quiescent_timer);
4506 } else {
4507 if (!hdw->state_decoder_quiescent) {
4508 if (!timer_pending(&hdw->quiescent_timer)) {
4509 /* We don't do something about the
4510 quiescent timer until right here because
4511 we also want to catch cases where the
4512 decoder was already not running (like
4513 after initialization) as opposed to
4514 knowing that we had just stopped it.
4515 The second flag check is here to cover a
4516 race - the timer could have run and set
4517 this flag just after the previous check
4518 but before we did the pending check. */
4519 if (!hdw->state_decoder_quiescent) {
4520 hdw->quiescent_timer.expires =
83ce57aa
MI		 4521 jiffies +
4522 (HZ * TIME_MSEC_DECODER_WAIT
4523 / 1000);
681c7399
MI		 4524 add_timer(&hdw->quiescent_timer);
4525 }
4526 }
4527 /* Don't allow decoder to start again until it has
4528 been quiesced first. This little detail should
4529 hopefully further stabilize the encoder. */
4530 return 0;
4531 }
62433e31
MI		 4532 if (!hdw->state_pathway_ok ||
4533 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4534 !hdw->state_pipeline_req ||
681c7399
MI		 4535 hdw->state_pipeline_pause ||
4536 !hdw->state_pipeline_config ||
4537 !hdw->state_encoder_config ||
4538 !hdw->state_encoder_ok) return 0;
4539 del_timer_sync(&hdw->quiescent_timer);
4540 if (hdw->flag_decoder_missed) return 0;
4541 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4542 hdw->state_decoder_quiescent = 0;
4543 hdw->state_decoder_run = !0;
4544 }
4545 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4546 trace_stbit("state_decoder_run",hdw->state_decoder_run);
4547 return !0;
4548}
4549
4550
4551/* Evaluate whether or not state_usbstream_run can change */
4552static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4553{
4554 if (hdw->state_usbstream_run) {
72998b71 4555 int fl = !0;
62433e31 4556 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
72998b71
MI		 4557 fl = (hdw->state_encoder_ok &&
4558 hdw->state_encoder_run);
4559 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4560 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4561 fl = hdw->state_encoder_ok;
4562 }
4563 if (fl &&
4564 hdw->state_pipeline_req &&
4565 !hdw->state_pipeline_pause &&
4566 hdw->state_pathway_ok) {
4567 return 0;
681c7399
MI		 4568 }
4569 pvr2_hdw_cmd_usbstream(hdw,0);
4570 hdw->state_usbstream_run = 0;
4571 } else {
62433e31
MI		 4572 if (!hdw->state_pipeline_req ||
4573 hdw->state_pipeline_pause ||
4574 !hdw->state_pathway_ok) return 0;
4575 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4576 if (!hdw->state_encoder_ok ||
4577 !hdw->state_encoder_run) return 0;
72998b71
MI		 4578 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4579 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4580 if (!hdw->state_encoder_ok) return 0;
d913d630
MI		 4581 if (hdw->state_encoder_run) return 0;
4582 if (hdw->hdw_desc->digital_control_scheme ==
4583 PVR2_DIGITAL_SCHEME_ONAIR) {
4584 /* OnAir digital receivers won't stream
4585 unless the analog encoder has run first.
4586 Why? I have no idea. But don't even
4587 try until we know the analog side is
4588 known to have run. */
4589 if (!hdw->state_encoder_runok) return 0;
4590 }
62433e31 4591 }
681c7399
MI		 4592 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4593 hdw->state_usbstream_run = !0;
4594 }
4595 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4596 return !0;
4597}
4598
4599
4600/* Attempt to configure pipeline, if needed */
4601static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4602{
4603 if (hdw->state_pipeline_config ||
4604 hdw->state_pipeline_pause) return 0;
4605 pvr2_hdw_commit_execute(hdw);
4606 return !0;
4607}
4608
4609
4610/* Update pipeline idle and pipeline pause tracking states based on other
4611 inputs. This must be called whenever the other relevant inputs have
4612 changed. */
4613static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4614{
4615 unsigned int st;
4616 int updatedFl = 0;
4617 /* Update pipeline state */
4618 st = !(hdw->state_encoder_run ||
4619 hdw->state_decoder_run ||
4620 hdw->state_usbstream_run ||
4621 (!hdw->state_decoder_quiescent));
4622 if (!st != !hdw->state_pipeline_idle) {
4623 hdw->state_pipeline_idle = st;
4624 updatedFl = !0;
4625 }
4626 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4627 hdw->state_pipeline_pause = 0;
4628 updatedFl = !0;
4629 }
4630 return updatedFl;
4631}
4632
4633
4634typedef int (*state_eval_func)(struct pvr2_hdw *);
4635
4636/* Set of functions to be run to evaluate various states in the driver. */
ebff0330 4637static const state_eval_func eval_funcs[] = {
62433e31 4638 state_eval_pathway_ok,
681c7399
MI		 4639 state_eval_pipeline_config,
4640 state_eval_encoder_ok,
4641 state_eval_encoder_config,
4642 state_eval_decoder_run,
4643 state_eval_encoder_run,
4644 state_eval_usbstream_run,
4645};
4646
4647
4648/* Process various states and return true if we did anything interesting. */
4649static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4650{
4651 unsigned int i;
4652 int state_updated = 0;
4653 int check_flag;
4654
4655 if (!hdw->state_stale) return 0;
4656 if ((hdw->fw1_state != FW1_STATE_OK) ||
4657 !hdw->flag_ok) {
4658 hdw->state_stale = 0;
4659 return !0;
4660 }
4661 /* This loop is the heart of the entire driver. It keeps trying to
4662 evaluate various bits of driver state until nothing changes for
4663 one full iteration. Each "bit of state" tracks some global
4664 aspect of the driver, e.g. whether decoder should run, if
4665 pipeline is configured, usb streaming is on, etc. We separately
4666 evaluate each of those questions based on other driver state to
4667 arrive at the correct running configuration. */
4668 do {
4669 check_flag = 0;
4670 state_update_pipeline_state(hdw);
4671 /* Iterate over each bit of state */
4672 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4673 if ((*eval_funcs[i])(hdw)) {
4674 check_flag = !0;
4675 state_updated = !0;
4676 state_update_pipeline_state(hdw);
4677 }
4678 }
4679 } while (check_flag && hdw->flag_ok);
4680 hdw->state_stale = 0;
4681 trace_stbit("state_stale",hdw->state_stale);
4682 return state_updated;
4683}
4684
4685
1cb03b76
MI		 4686static unsigned int print_input_mask(unsigned int msk,
4687 char *buf,unsigned int acnt)
4688{
4689 unsigned int idx,ccnt;
4690 unsigned int tcnt = 0;
4691 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4692 if (!((1 << idx) & msk)) continue;
4693 ccnt = scnprintf(buf+tcnt,
4694 acnt-tcnt,
4695 "%s%s",
4696 (tcnt ? ", " : ""),
4697 control_values_input[idx]);
4698 tcnt += ccnt;
4699 }
4700 return tcnt;
4701}
4702
4703
62433e31
MI		 4704static const char *pvr2_pathway_state_name(int id)
4705{
4706 switch (id) {
4707 case PVR2_PATHWAY_ANALOG: return "analog";
4708 case PVR2_PATHWAY_DIGITAL: return "digital";
4709 default: return "unknown";
4710 }
4711}
4712
4713
681c7399
MI		 4714static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4715 char *buf,unsigned int acnt)
4716{
4717 switch (which) {
4718 case 0:
4719 return scnprintf(
4720 buf,acnt,
e9db1ff2 4721 "driver:%s%s%s%s%s <mode=%s>",
681c7399
MI		 4722 (hdw->flag_ok ? " <ok>" : " <fail>"),
4723 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4724 (hdw->flag_disconnected ? " <disconnected>" :
4725 " <connected>"),
4726 (hdw->flag_tripped ? " <tripped>" : ""),
62433e31
MI		 4727 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4728 pvr2_pathway_state_name(hdw->pathway_state));
4729
681c7399
MI		 4730 case 1:
4731 return scnprintf(
4732 buf,acnt,
4733 "pipeline:%s%s%s%s",
4734 (hdw->state_pipeline_idle ? " <idle>" : ""),
4735 (hdw->state_pipeline_config ?
4736 " <configok>" : " <stale>"),
4737 (hdw->state_pipeline_req ? " <req>" : ""),
4738 (hdw->state_pipeline_pause ? " <pause>" : ""));
4739 case 2:
4740 return scnprintf(
4741 buf,acnt,
62433e31 4742 "worker:%s%s%s%s%s%s%s",
681c7399
MI		 4743 (hdw->state_decoder_run ?
4744 " <decode:run>" :
4745 (hdw->state_decoder_quiescent ?
4746 "" : " <decode:stop>")),
4747 (hdw->state_decoder_quiescent ?
4748 " <decode:quiescent>" : ""),
4749 (hdw->state_encoder_ok ?
4750 "" : " <encode:init>"),
4751 (hdw->state_encoder_run ?
d913d630
MI		 4752 (hdw->state_encoder_runok ?
4753 " <encode:run>" :
4754 " <encode:firstrun>") :
4755 (hdw->state_encoder_runok ?
4756 " <encode:stop>" :
4757 " <encode:virgin>")),
681c7399
MI		 4758 (hdw->state_encoder_config ?
4759 " <encode:configok>" :
4760 (hdw->state_encoder_waitok ?
b9a37d91 4761 "" : " <encode:waitok>")),
681c7399 4762 (hdw->state_usbstream_run ?
62433e31
MI		 4763 " <usb:run>" : " <usb:stop>"),
4764 (hdw->state_pathway_ok ?
e9db1ff2 4765 " <pathway:ok>" : ""));
681c7399
MI		 4766 case 3:
4767 return scnprintf(
4768 buf,acnt,
4769 "state: %s",
4770 pvr2_get_state_name(hdw->master_state));
ad0992e9 4771 case 4: {
1cb03b76
MI		 4772 unsigned int tcnt = 0;
4773 unsigned int ccnt;
4774
4775 ccnt = scnprintf(buf,
4776 acnt,
4777 "Hardware supported inputs: ");
4778 tcnt += ccnt;
4779 tcnt += print_input_mask(hdw->input_avail_mask,
4780 buf+tcnt,
4781 acnt-tcnt);
4782 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4783 ccnt = scnprintf(buf+tcnt,
4784 acnt-tcnt,
4785 "; allowed inputs: ");
4786 tcnt += ccnt;
4787 tcnt += print_input_mask(hdw->input_allowed_mask,
4788 buf+tcnt,
4789 acnt-tcnt);
4790 }
4791 return tcnt;
4792 }
4793 case 5: {
ad0992e9
MI		 4794 struct pvr2_stream_stats stats;
4795 if (!hdw->vid_stream) break;
4796 pvr2_stream_get_stats(hdw->vid_stream,
4797 &stats,
4798 0);
4799 return scnprintf(
4800 buf,acnt,
4801 "Bytes streamed=%u"
4802 " URBs: queued=%u idle=%u ready=%u"
4803 " processed=%u failed=%u",
4804 stats.bytes_processed,
4805 stats.buffers_in_queue,
4806 stats.buffers_in_idle,
4807 stats.buffers_in_ready,
4808 stats.buffers_processed,
4809 stats.buffers_failed);
4810 }
2eb563b7
MI		 4811 default: break;
4812 }
4813 return 0;
4814}
4815
4816
4817/* Generate report containing info about attached sub-devices and attached
4818 i2c clients, including an indication of which attached i2c clients are
4819 actually sub-devices. */
4820static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4821 char *buf, unsigned int acnt)
4822{
4823 struct v4l2_subdev *sd;
4824 unsigned int tcnt = 0;
4825 unsigned int ccnt;
4826 struct i2c_client *client;
4827 struct list_head *item;
4828 void *cd;
4829 const char *p;
4830 unsigned int id;
4831
4832 ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers:");
4833 tcnt += ccnt;
4834 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4835 id = sd->grp_id;
4836 p = NULL;
4837 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4838 if (p) {
4839 ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s", p);
4840 tcnt += ccnt;
4841 } else {
4842 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4843 " (unknown id=%u)", id);
4844 tcnt += ccnt;
4845 }
4846 }
4847 ccnt = scnprintf(buf + tcnt, acnt - tcnt, "\n");
4848 tcnt += ccnt;
4849
4850 ccnt = scnprintf(buf + tcnt, acnt - tcnt, "I2C clients:\n");
4851 tcnt += ccnt;
4852
4853 mutex_lock(&hdw->i2c_adap.clist_lock);
4854 list_for_each(item, &hdw->i2c_adap.clients) {
4855 client = list_entry(item, struct i2c_client, list);
4856 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4857 " %s: i2c=%02x", client->name, client->addr);
858f910e 4858 tcnt += ccnt;
2eb563b7 4859 cd = i2c_get_clientdata(client);
858f910e 4860 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
2eb563b7
MI		 4861 if (cd == sd) {
4862 id = sd->grp_id;
4863 p = NULL;
4864 if (id < ARRAY_SIZE(module_names)) {
4865 p = module_names[id];
4866 }
4867 if (p) {
4868 ccnt = scnprintf(buf + tcnt,
4869 acnt - tcnt,
4870 " subdev=%s", p);
4871 tcnt += ccnt;
4872 } else {
4873 ccnt = scnprintf(buf + tcnt,
4874 acnt - tcnt,
4875 " subdev= id %u)",
4876 id);
4877 tcnt += ccnt;
4878 }
4879 break;
5f757ddd 4880 }
858f910e 4881 }
2eb563b7
MI		 4882 ccnt = scnprintf(buf + tcnt, acnt - tcnt, "\n");
4883 tcnt += ccnt;
681c7399 4884 }
2eb563b7
MI		 4885 mutex_unlock(&hdw->i2c_adap.clist_lock);
4886 return tcnt;
681c7399
MI		 4887}
4888
4889
4890unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4891 char *buf,unsigned int acnt)
4892{
4893 unsigned int bcnt,ccnt,idx;
4894 bcnt = 0;
4895 LOCK_TAKE(hdw->big_lock);
4896 for (idx = 0; ; idx++) {
4897 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4898 if (!ccnt) break;
4899 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4900 if (!acnt) break;
4901 buf[0] = '\n'; ccnt = 1;
4902 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4903 }
2eb563b7
MI		 4904 ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4905 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
681c7399
MI		 4906 LOCK_GIVE(hdw->big_lock);
4907 return bcnt;
4908}
4909
4910
4911static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4912{
2eb563b7
MI		 4913 char buf[256];
4914 unsigned int idx, ccnt;
4915 unsigned int lcnt, ucnt;
681c7399
MI		 4916
4917 for (idx = 0; ; idx++) {
4918 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4919 if (!ccnt) break;
4920 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4921 }
2eb563b7
MI		 4922 ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
4923 ucnt = 0;
4924 while (ucnt < ccnt) {
4925 lcnt = 0;
4926 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4927 lcnt++;
4928 }
4929 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4930 ucnt += lcnt + 1;
4931 }
681c7399
MI		 4932}
4933
4934
4935/* Evaluate and update the driver's current state, taking various actions
4936 as appropriate for the update. */
4937static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4938{
4939 unsigned int st;
4940 int state_updated = 0;
4941 int callback_flag = 0;
1b9c18c5 4942 int analog_mode;
681c7399
MI		 4943
4944 pvr2_trace(PVR2_TRACE_STBITS,
4945 "Drive state check START");
4946 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4947 pvr2_hdw_state_log_state(hdw);
4948 }
4949
4950 /* Process all state and get back over disposition */
4951 state_updated = pvr2_hdw_state_update(hdw);
4952
1b9c18c5
MI		 4953 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4954
681c7399
MI		 4955 /* Update master state based upon all other states. */
4956 if (!hdw->flag_ok) {
4957 st = PVR2_STATE_DEAD;
4958 } else if (hdw->fw1_state != FW1_STATE_OK) {
4959 st = PVR2_STATE_COLD;
72998b71
MI		 4960 } else if ((analog_mode ||
4961 hdw->hdw_desc->flag_digital_requires_cx23416) &&
4962 !hdw->state_encoder_ok) {
681c7399 4963 st = PVR2_STATE_WARM;
1b9c18c5
MI		 4964 } else if (hdw->flag_tripped ||
4965 (analog_mode && hdw->flag_decoder_missed)) {
681c7399 4966 st = PVR2_STATE_ERROR;
62433e31 4967 } else if (hdw->state_usbstream_run &&
1b9c18c5 4968 (!analog_mode ||
62433e31 4969 (hdw->state_encoder_run && hdw->state_decoder_run))) {
681c7399
MI		 4970 st = PVR2_STATE_RUN;
4971 } else {
4972 st = PVR2_STATE_READY;
4973 }
4974 if (hdw->master_state != st) {
4975 pvr2_trace(PVR2_TRACE_STATE,
4976 "Device state change from %s to %s",
4977 pvr2_get_state_name(hdw->master_state),
4978 pvr2_get_state_name(st));
40381cb0 4979 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
681c7399
MI		 4980 hdw->master_state = st;
4981 state_updated = !0;
4982 callback_flag = !0;
4983 }
4984 if (state_updated) {
4985 /* Trigger anyone waiting on any state changes here. */
4986 wake_up(&hdw->state_wait_data);
4987 }
4988
4989 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4990 pvr2_hdw_state_log_state(hdw);
4991 }
4992 pvr2_trace(PVR2_TRACE_STBITS,
4993 "Drive state check DONE callback=%d",callback_flag);
4994
4995 return callback_flag;
4996}
4997
4998
4999/* Cause kernel thread to check / update driver state */
5000static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
5001{
5002 if (hdw->state_stale) return;
5003 hdw->state_stale = !0;
5004 trace_stbit("state_stale",hdw->state_stale);
5005 queue_work(hdw->workqueue,&hdw->workpoll);
5006}
5007
5008
d855497e
MI		 5009int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
5010{
5011 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5012}
5013
5014
5015int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5016{
5017 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5018}
5019
5020
5021int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5022{
5023 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5024}
5025
5026
5027int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5028{
5029 u32 cval,nval;
5030 int ret;
5031 if (~msk) {
5032 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5033 if (ret) return ret;
5034 nval = (cval & ~msk) | (val & msk);
5035 pvr2_trace(PVR2_TRACE_GPIO,
5036 "GPIO direction changing 0x%x:0x%x"
5037 " from 0x%x to 0x%x",
5038 msk,val,cval,nval);
5039 } else {
5040 nval = val;
5041 pvr2_trace(PVR2_TRACE_GPIO,
5042 "GPIO direction changing to 0x%x",nval);
5043 }
5044 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5045}
5046
5047
5048int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5049{
5050 u32 cval,nval;
5051 int ret;
5052 if (~msk) {
5053 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5054 if (ret) return ret;
5055 nval = (cval & ~msk) | (val & msk);
5056 pvr2_trace(PVR2_TRACE_GPIO,
5057 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5058 msk,val,cval,nval);
5059 } else {
5060 nval = val;
5061 pvr2_trace(PVR2_TRACE_GPIO,
5062 "GPIO output changing to 0x%x",nval);
5063 }
5064 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5065}
5066
5067
a51f5000
MI		 5068void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5069{
40f07111
MI		 5070 struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5071 memset(vtp, 0, sizeof(*vtp));
2641df36 5072 hdw->tuner_signal_stale = 0;
40f07111
MI		 5073 /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5074 using v4l2-subdev - therefore we can't support that AT ALL right
5075 now. (Of course, no sub-drivers seem to implement it either.
5076 But now it's a a chicken and egg problem...) */
5077 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5078 &hdw->tuner_signal_info);
2641df36 5079 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
40f07111
MI		 5080 " type=%u strength=%u audio=0x%x cap=0x%x"
5081 " low=%u hi=%u",
5082 vtp->type,
5083 vtp->signal, vtp->rxsubchans, vtp->capability,
5084 vtp->rangelow, vtp->rangehigh);
2641df36
MI		 5085
5086 /* We have to do this to avoid getting into constant polling if
5087 there's nobody to answer a poll of cropcap info. */
5088 hdw->cropcap_stale = 0;
a51f5000
MI		 5089}
5090
5091
7fb20fa3
MI		 5092unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5093{
5094 return hdw->input_avail_mask;
5095}
5096
5097
1cb03b76
MI		 5098unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5099{
5100 return hdw->input_allowed_mask;
5101}
5102
5103
5104static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5105{
5106 if (hdw->input_val != v) {
5107 hdw->input_val = v;
5108 hdw->input_dirty = !0;
5109 }
5110
5111 /* Handle side effects - if we switch to a mode that needs the RF
5112 tuner, then select the right frequency choice as well and mark
5113 it dirty. */
5114 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5115 hdw->freqSelector = 0;
5116 hdw->freqDirty = !0;
5117 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5118 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5119 hdw->freqSelector = 1;
5120 hdw->freqDirty = !0;
5121 }
5122 return 0;
5123}
5124
5125
5126int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5127 unsigned int change_mask,
5128 unsigned int change_val)
5129{
5130 int ret = 0;
5131 unsigned int nv,m,idx;
5132 LOCK_TAKE(hdw->big_lock);
5133 do {
5134 nv = hdw->input_allowed_mask & ~change_mask;
5135 nv |= (change_val & change_mask);
5136 nv &= hdw->input_avail_mask;
5137 if (!nv) {
5138 /* No legal modes left; return error instead. */
5139 ret = -EPERM;
5140 break;
5141 }
5142 hdw->input_allowed_mask = nv;
5143 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5144 /* Current mode is still in the allowed mask, so
5145 we're done. */
5146 break;
5147 }
5148 /* Select and switch to a mode that is still in the allowed
5149 mask */
5150 if (!hdw->input_allowed_mask) {
5151 /* Nothing legal; give up */
5152 break;
5153 }
5154 m = hdw->input_allowed_mask;
5155 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5156 if (!((1 << idx) & m)) continue;
5157 pvr2_hdw_set_input(hdw,idx);
5158 break;
5159 }
5160 } while (0);
5161 LOCK_GIVE(hdw->big_lock);
5162 return ret;
5163}
5164
5165
e61b6fc5 5166/* Find I2C address of eeprom */
07e337ee 5167static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 5168{
5169 int result;
5170 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 5171 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 5172 result = pvr2_send_request(hdw,
5173 hdw->cmd_buffer,1,
5174 hdw->cmd_buffer,1);
5175 if (result < 0) break;
5176 result = hdw->cmd_buffer[0];
5177 } while(0); LOCK_GIVE(hdw->ctl_lock);
5178 return result;
5179}
5180
5181
32ffa9ae 5182int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
aecde8b5
HV		 5183 struct v4l2_dbg_match *match, u64 reg_id,
5184 int setFl, u64 *val_ptr)
32ffa9ae
MI		 5185{
5186#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 5187 struct v4l2_dbg_register req;
6d98816f
MI		 5188 int stat = 0;
5189 int okFl = 0;
32ffa9ae 5190
201f5c9c
MI		 5191 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5192
aecde8b5 5193 req.match = *match;
32ffa9ae
MI		 5194 req.reg = reg_id;
5195 if (setFl) req.val = *val_ptr;
d8f5b9ba
MI		 5196 /* It would be nice to know if a sub-device answered the request */
5197 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5198 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 5199 if (okFl) {
5200 return stat;
5201 }
32ffa9ae
MI		 5202 return -EINVAL;
5203#else
5204 return -ENOSYS;
5205#endif
5206}
5207
5208
d855497e
MI		 5209/*
5210 Stuff for Emacs to see, in order to encourage consistent editing style:
5211 *** Local Variables: ***
5212 *** mode: c ***
5213 *** fill-column: 75 ***
5214 *** tab-width: 8 ***
5215 *** c-basic-offset: 8 ***
5216 *** End: ***
5217 */
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