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V4L/DVB (11175): pvrusb2: Implement sub-device specific update framework
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
d855497e
MI		 3 *
4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21#include <linux/errno.h>
22#include <linux/string.h>
23#include <linux/slab.h>
24#include <linux/firmware.h>
d855497e 25#include <linux/videodev2.h>
32ffa9ae 26#include <media/v4l2-common.h>
d855497e
MI		 27#include "pvrusb2.h"
28#include "pvrusb2-std.h"
29#include "pvrusb2-util.h"
30#include "pvrusb2-hdw.h"
31#include "pvrusb2-i2c-core.h"
59af3367 32#include "pvrusb2-i2c-track.h"
d855497e
MI		 33#include "pvrusb2-tuner.h"
34#include "pvrusb2-eeprom.h"
35#include "pvrusb2-hdw-internal.h"
36#include "pvrusb2-encoder.h"
37#include "pvrusb2-debug.h"
8d364363 38#include "pvrusb2-fx2-cmd.h"
d855497e 39
1bde0289
MI		 40#define TV_MIN_FREQ 55250000L
41#define TV_MAX_FREQ 850000000L
25d8527a 42
83ce57aa
MI		 43/* This defines a minimum interval that the decoder must remain quiet
44 before we are allowed to start it running. */
45#define TIME_MSEC_DECODER_WAIT 50
46
47/* This defines a minimum interval that the encoder must remain quiet
fa98e594
MI		 48 before we are allowed to configure it. I had this originally set to
49 50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
50 things work better when it's set to 100msec. */
51#define TIME_MSEC_ENCODER_WAIT 100
83ce57aa
MI		 52
53/* This defines the minimum interval that the encoder must successfully run
54 before we consider that the encoder has run at least once since its
55 firmware has been loaded. This measurement is in important for cases
56 where we can't do something until we know that the encoder has been run
57 at least once. */
58#define TIME_MSEC_ENCODER_OK 250
59
a0fd1cb1 60static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 61static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e 62
ff699e6b 63static int ctlchg;
ff699e6b 64static int procreload;
d855497e
MI		 65static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
66static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
67static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
ff699e6b 68static int init_pause_msec;
d855497e
MI		 69
70module_param(ctlchg, int, S_IRUGO|S_IWUSR);
71MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
72module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
73MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
d855497e
MI		 74module_param(procreload, int, S_IRUGO|S_IWUSR);
75MODULE_PARM_DESC(procreload,
76 "Attempt init failure recovery with firmware reload");
77module_param_array(tuner, int, NULL, 0444);
78MODULE_PARM_DESC(tuner,"specify installed tuner type");
79module_param_array(video_std, int, NULL, 0444);
80MODULE_PARM_DESC(video_std,"specify initial video standard");
81module_param_array(tolerance, int, NULL, 0444);
82MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
83
5a4f5da6
MK		 84/* US Broadcast channel 7 (175.25 MHz) */
85static int default_tv_freq = 175250000L;
86/* 104.3 MHz, a usable FM station for my area */
87static int default_radio_freq = 104300000L;
88
89module_param_named(tv_freq, default_tv_freq, int, 0444);
90MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
91module_param_named(radio_freq, default_radio_freq, int, 0444);
92MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
93
d855497e
MI		 94#define PVR2_CTL_WRITE_ENDPOINT 0x01
95#define PVR2_CTL_READ_ENDPOINT 0x81
96
97#define PVR2_GPIO_IN 0x9008
98#define PVR2_GPIO_OUT 0x900c
99#define PVR2_GPIO_DIR 0x9020
100
101#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
102
103#define PVR2_FIRMWARE_ENDPOINT 0x02
104
105/* size of a firmware chunk */
106#define FIRMWARE_CHUNK_SIZE 0x2000
107
edb9dcb8
MI		 108typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
109 struct v4l2_subdev *);
110
111static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
112 /* ????? */
113};
114
e9c64a78
MI		 115static const char *module_names[] = {
116 [PVR2_CLIENT_ID_MSP3400] = "msp3400",
117 [PVR2_CLIENT_ID_CX25840] = "cx25840",
118 [PVR2_CLIENT_ID_SAA7115] = "saa7115",
119 [PVR2_CLIENT_ID_TUNER] = "tuner",
120 [PVR2_CLIENT_ID_CS53132A] = "cs53132a",
121};
122
123
124static const unsigned char *module_i2c_addresses[] = {
125 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
126};
127
128
b30d2441
MI		 129/* Define the list of additional controls we'll dynamically construct based
130 on query of the cx2341x module. */
131struct pvr2_mpeg_ids {
132 const char *strid;
133 int id;
134};
135static const struct pvr2_mpeg_ids mpeg_ids[] = {
136 {
137 .strid = "audio_layer",
138 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
139 },{
140 .strid = "audio_bitrate",
141 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
142 },{
143 /* Already using audio_mode elsewhere :-( */
144 .strid = "mpeg_audio_mode",
145 .id = V4L2_CID_MPEG_AUDIO_MODE,
146 },{
147 .strid = "mpeg_audio_mode_extension",
148 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
149 },{
150 .strid = "audio_emphasis",
151 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
152 },{
153 .strid = "audio_crc",
154 .id = V4L2_CID_MPEG_AUDIO_CRC,
155 },{
156 .strid = "video_aspect",
157 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
158 },{
159 .strid = "video_b_frames",
160 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
161 },{
162 .strid = "video_gop_size",
163 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
164 },{
165 .strid = "video_gop_closure",
166 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 167 },{
168 .strid = "video_bitrate_mode",
169 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
170 },{
171 .strid = "video_bitrate",
172 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
173 },{
174 .strid = "video_bitrate_peak",
175 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
176 },{
177 .strid = "video_temporal_decimation",
178 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
179 },{
180 .strid = "stream_type",
181 .id = V4L2_CID_MPEG_STREAM_TYPE,
182 },{
183 .strid = "video_spatial_filter_mode",
184 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
185 },{
186 .strid = "video_spatial_filter",
187 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
188 },{
189 .strid = "video_luma_spatial_filter_type",
190 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
191 },{
192 .strid = "video_chroma_spatial_filter_type",
193 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
194 },{
195 .strid = "video_temporal_filter_mode",
196 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
197 },{
198 .strid = "video_temporal_filter",
199 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
200 },{
201 .strid = "video_median_filter_type",
202 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
203 },{
204 .strid = "video_luma_median_filter_top",
205 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
206 },{
207 .strid = "video_luma_median_filter_bottom",
208 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
209 },{
210 .strid = "video_chroma_median_filter_top",
211 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
212 },{
213 .strid = "video_chroma_median_filter_bottom",
214 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
215 }
216};
eca8ebfc 217#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 218
434449f4 219
d855497e 220static const char *control_values_srate[] = {
434449f4
MI		 221 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
222 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
223 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 224};
225
226
d855497e 227
d855497e
MI		 228static const char *control_values_input[] = {
229 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
29bf5b1d 230 [PVR2_CVAL_INPUT_DTV] = "dtv",
d855497e
MI		 231 [PVR2_CVAL_INPUT_RADIO] = "radio",
232 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
233 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
234};
235
236
237static const char *control_values_audiomode[] = {
238 [V4L2_TUNER_MODE_MONO] = "Mono",
239 [V4L2_TUNER_MODE_STEREO] = "Stereo",
240 [V4L2_TUNER_MODE_LANG1] = "Lang1",
241 [V4L2_TUNER_MODE_LANG2] = "Lang2",
242 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
243};
244
245
246static const char *control_values_hsm[] = {
247 [PVR2_CVAL_HSM_FAIL] = "Fail",
248 [PVR2_CVAL_HSM_HIGH] = "High",
249 [PVR2_CVAL_HSM_FULL] = "Full",
250};
251
252
681c7399
MI		 253static const char *pvr2_state_names[] = {
254 [PVR2_STATE_NONE] = "none",
255 [PVR2_STATE_DEAD] = "dead",
256 [PVR2_STATE_COLD] = "cold",
257 [PVR2_STATE_WARM] = "warm",
258 [PVR2_STATE_ERROR] = "error",
259 [PVR2_STATE_READY] = "ready",
260 [PVR2_STATE_RUN] = "run",
d855497e
MI		 261};
262
681c7399 263
694dca2b 264struct pvr2_fx2cmd_descdef {
1c9d10d4
MI		 265 unsigned char id;
266 unsigned char *desc;
267};
268
694dca2b 269static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
1c9d10d4
MI		 270 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
271 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
31335b13 272 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
1c9d10d4
MI		 273 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
274 {FX2CMD_REG_WRITE, "write encoder register"},
275 {FX2CMD_REG_READ, "read encoder register"},
276 {FX2CMD_MEMSEL, "encoder memsel"},
277 {FX2CMD_I2C_WRITE, "i2c write"},
278 {FX2CMD_I2C_READ, "i2c read"},
279 {FX2CMD_GET_USB_SPEED, "get USB speed"},
280 {FX2CMD_STREAMING_ON, "stream on"},
281 {FX2CMD_STREAMING_OFF, "stream off"},
282 {FX2CMD_FWPOST1, "fwpost1"},
283 {FX2CMD_POWER_OFF, "power off"},
284 {FX2CMD_POWER_ON, "power on"},
285 {FX2CMD_DEEP_RESET, "deep reset"},
286 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
287 {FX2CMD_GET_IR_CODE, "get IR code"},
288 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
289 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
290 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
291 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
292 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
293 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
294 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
295};
296
297
1cb03b76 298static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
681c7399
MI		 299static void pvr2_hdw_state_sched(struct pvr2_hdw *);
300static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 301static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399
MI		 302static void pvr2_hdw_worker_i2c(struct work_struct *work);
303static void pvr2_hdw_worker_poll(struct work_struct *work);
681c7399
MI		 304static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
305static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
306static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 307static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 308static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 309static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 310static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
311static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
681c7399
MI		 312static void pvr2_hdw_quiescent_timeout(unsigned long);
313static void pvr2_hdw_encoder_wait_timeout(unsigned long);
d913d630 314static void pvr2_hdw_encoder_run_timeout(unsigned long);
1c9d10d4 315static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
07e337ee
AB		 316static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
317 unsigned int timeout,int probe_fl,
318 void *write_data,unsigned int write_len,
319 void *read_data,unsigned int read_len);
432907f7 320static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
d855497e 321
681c7399
MI		 322
323static void trace_stbit(const char *name,int val)
324{
325 pvr2_trace(PVR2_TRACE_STBITS,
326 "State bit %s <-- %s",
327 name,(val ? "true" : "false"));
328}
329
d855497e
MI		 330static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
331{
332 struct pvr2_hdw *hdw = cptr->hdw;
333 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
334 *vp = hdw->freqTable[hdw->freqProgSlot-1];
335 } else {
336 *vp = 0;
337 }
338 return 0;
339}
340
341static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
342{
343 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 344 unsigned int slotId = hdw->freqProgSlot;
345 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
346 hdw->freqTable[slotId-1] = v;
347 /* Handle side effects correctly - if we're tuned to this
348 slot, then forgot the slot id relation since the stored
349 frequency has been changed. */
350 if (hdw->freqSelector) {
351 if (hdw->freqSlotRadio == slotId) {
352 hdw->freqSlotRadio = 0;
353 }
354 } else {
355 if (hdw->freqSlotTelevision == slotId) {
356 hdw->freqSlotTelevision = 0;
357 }
358 }
d855497e
MI		 359 }
360 return 0;
361}
362
363static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
364{
365 *vp = cptr->hdw->freqProgSlot;
366 return 0;
367}
368
369static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
370{
371 struct pvr2_hdw *hdw = cptr->hdw;
372 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
373 hdw->freqProgSlot = v;
374 }
375 return 0;
376}
377
378static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
379{
1bde0289
MI		 380 struct pvr2_hdw *hdw = cptr->hdw;
381 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 382 return 0;
383}
384
1bde0289 385static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 386{
387 unsigned freq = 0;
388 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 389 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
390 if (slotId > 0) {
391 freq = hdw->freqTable[slotId-1];
392 if (!freq) return 0;
393 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 394 }
1bde0289
MI		 395 if (hdw->freqSelector) {
396 hdw->freqSlotRadio = slotId;
397 } else {
398 hdw->freqSlotTelevision = slotId;
d855497e
MI		 399 }
400 return 0;
401}
402
403static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
404{
1bde0289 405 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 406 return 0;
407}
408
409static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
410{
411 return cptr->hdw->freqDirty != 0;
412}
413
414static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
415{
416 cptr->hdw->freqDirty = 0;
417}
418
419static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
420{
1bde0289 421 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 422 return 0;
423}
424
e784bfb9 425static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
426{
432907f7
MI		 427 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
428 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
429 if (stat != 0) {
432907f7 430 return stat;
e784bfb9 431 }
432907f7 432 *left = cap->bounds.left;
e784bfb9 433 return 0;
434}
435
436static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
437{
432907f7
MI		 438 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
439 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
440 if (stat != 0) {
432907f7
MI		 441 return stat;
442 }
443 *left = cap->bounds.left;
444 if (cap->bounds.width > cptr->hdw->cropw_val) {
432907f7 445 *left += cap->bounds.width - cptr->hdw->cropw_val;
e784bfb9 446 }
447 return 0;
448}
449
450static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
451{
432907f7
MI		 452 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
453 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
454 if (stat != 0) {
432907f7 455 return stat;
e784bfb9 456 }
432907f7 457 *top = cap->bounds.top;
e784bfb9 458 return 0;
459}
460
432907f7 461static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
3ad9fc37 462{
432907f7
MI		 463 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
464 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
465 if (stat != 0) {
432907f7
MI		 466 return stat;
467 }
468 *top = cap->bounds.top;
469 if (cap->bounds.height > cptr->hdw->croph_val) {
432907f7 470 *top += cap->bounds.height - cptr->hdw->croph_val;
3ad9fc37
MI		 471 }
472 return 0;
473}
474
432907f7
MI		 475static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
476{
477 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
478 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
479 if (stat != 0) {
432907f7
MI		 480 return stat;
481 }
482 *val = 0;
483 if (cap->bounds.width > cptr->hdw->cropl_val) {
432907f7
MI		 484 *val = cap->bounds.width - cptr->hdw->cropl_val;
485 }
486 return 0;
487}
488
489static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
490{
491 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
492 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
493 if (stat != 0) {
432907f7
MI		 494 return stat;
495 }
496 *val = 0;
497 if (cap->bounds.height > cptr->hdw->cropt_val) {
432907f7
MI		 498 *val = cap->bounds.height - cptr->hdw->cropt_val;
499 }
500 return 0;
501}
502
503static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
504{
505 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
506 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
507 if (stat != 0) {
432907f7
MI		 508 return stat;
509 }
510 *val = cap->bounds.left;
511 return 0;
512}
513
514static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
515{
516 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
517 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
518 if (stat != 0) {
432907f7
MI		 519 return stat;
520 }
521 *val = cap->bounds.top;
522 return 0;
523}
524
525static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
526{
527 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
528 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
529 if (stat != 0) {
432907f7
MI		 530 return stat;
531 }
532 *val = cap->bounds.width;
533 return 0;
534}
535
536static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
537{
538 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
539 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
540 if (stat != 0) {
432907f7
MI		 541 return stat;
542 }
543 *val = cap->bounds.height;
544 return 0;
545}
546
547static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
548{
549 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
550 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
551 if (stat != 0) {
432907f7
MI		 552 return stat;
553 }
554 *val = cap->defrect.left;
555 return 0;
556}
557
558static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
559{
560 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
561 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
562 if (stat != 0) {
432907f7
MI		 563 return stat;
564 }
565 *val = cap->defrect.top;
566 return 0;
567}
568
569static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
570{
571 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
572 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
573 if (stat != 0) {
432907f7
MI		 574 return stat;
575 }
576 *val = cap->defrect.width;
577 return 0;
578}
579
580static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
581{
582 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
583 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
584 if (stat != 0) {
432907f7
MI		 585 return stat;
586 }
587 *val = cap->defrect.height;
588 return 0;
589}
590
591static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
592{
593 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
594 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
595 if (stat != 0) {
432907f7
MI		 596 return stat;
597 }
598 *val = cap->pixelaspect.numerator;
599 return 0;
600}
601
602static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
603{
604 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
605 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
606 if (stat != 0) {
432907f7
MI		 607 return stat;
608 }
609 *val = cap->pixelaspect.denominator;
610 return 0;
611}
612
613static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
e784bfb9 614{
432907f7
MI		 615 /* Actual maximum depends on the video standard in effect. */
616 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
617 *vp = 480;
e784bfb9 618 } else {
432907f7 619 *vp = 576;
e784bfb9 620 }
621 return 0;
622}
623
3ad9fc37
MI		 624static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
625{
989eb154
MI		 626 /* Actual minimum depends on device digitizer type. */
627 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 628 *vp = 75;
629 } else {
630 *vp = 17;
631 }
632 return 0;
633}
634
1bde0289 635static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 636{
1bde0289
MI		 637 *vp = cptr->hdw->input_val;
638 return 0;
639}
640
29bf5b1d
MI		 641static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
642{
1cb03b76 643 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
29bf5b1d
MI		 644}
645
1bde0289
MI		 646static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
647{
1cb03b76 648 return pvr2_hdw_set_input(cptr->hdw,v);
1bde0289
MI		 649}
650
651static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
652{
653 return cptr->hdw->input_dirty != 0;
654}
655
656static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
657{
658 cptr->hdw->input_dirty = 0;
659}
660
5549f54f 661
25d8527a
PK		 662static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
663{
644afdb9
MI		 664 unsigned long fv;
665 struct pvr2_hdw *hdw = cptr->hdw;
666 if (hdw->tuner_signal_stale) {
a51f5000 667 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 668 }
669 fv = hdw->tuner_signal_info.rangehigh;
670 if (!fv) {
671 /* Safety fallback */
25d8527a 672 *vp = TV_MAX_FREQ;
644afdb9 673 return 0;
25d8527a 674 }
644afdb9
MI		 675 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
676 fv = (fv * 125) / 2;
677 } else {
678 fv = fv * 62500;
679 }
680 *vp = fv;
25d8527a
PK		 681 return 0;
682}
683
684static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
685{
644afdb9
MI		 686 unsigned long fv;
687 struct pvr2_hdw *hdw = cptr->hdw;
688 if (hdw->tuner_signal_stale) {
a51f5000 689 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 690 }
691 fv = hdw->tuner_signal_info.rangelow;
692 if (!fv) {
693 /* Safety fallback */
25d8527a 694 *vp = TV_MIN_FREQ;
644afdb9
MI		 695 return 0;
696 }
697 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
698 fv = (fv * 125) / 2;
699 } else {
700 fv = fv * 62500;
25d8527a 701 }
644afdb9 702 *vp = fv;
25d8527a
PK		 703 return 0;
704}
705
b30d2441
MI		 706static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
707{
708 return cptr->hdw->enc_stale != 0;
709}
710
711static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
712{
713 cptr->hdw->enc_stale = 0;
681c7399 714 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 715}
716
717static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
718{
719 int ret;
720 struct v4l2_ext_controls cs;
721 struct v4l2_ext_control c1;
722 memset(&cs,0,sizeof(cs));
723 memset(&c1,0,sizeof(c1));
724 cs.controls = &c1;
725 cs.count = 1;
726 c1.id = cptr->info->v4l_id;
01f1e44f 727 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 728 VIDIOC_G_EXT_CTRLS);
729 if (ret) return ret;
730 *vp = c1.value;
731 return 0;
732}
733
734static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
735{
736 int ret;
681c7399 737 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 738 struct v4l2_ext_controls cs;
739 struct v4l2_ext_control c1;
740 memset(&cs,0,sizeof(cs));
741 memset(&c1,0,sizeof(c1));
742 cs.controls = &c1;
743 cs.count = 1;
744 c1.id = cptr->info->v4l_id;
745 c1.value = v;
681c7399
MI		 746 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
747 hdw->state_encoder_run, &cs,
b30d2441 748 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 749 if (ret == -EBUSY) {
750 /* Oops. cx2341x is telling us it's not safe to change
751 this control while we're capturing. Make a note of this
752 fact so that the pipeline will be stopped the next time
753 controls are committed. Then go on ahead and store this
754 change anyway. */
755 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
756 0, &cs,
757 VIDIOC_S_EXT_CTRLS);
758 if (!ret) hdw->enc_unsafe_stale = !0;
759 }
b30d2441 760 if (ret) return ret;
681c7399 761 hdw->enc_stale = !0;
b30d2441
MI		 762 return 0;
763}
764
765static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
766{
767 struct v4l2_queryctrl qctrl;
768 struct pvr2_ctl_info *info;
769 qctrl.id = cptr->info->v4l_id;
770 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
771 /* Strip out the const so we can adjust a function pointer. It's
772 OK to do this here because we know this is a dynamically created
773 control, so the underlying storage for the info pointer is (a)
774 private to us, and (b) not in read-only storage. Either we do
775 this or we significantly complicate the underlying control
776 implementation. */
777 info = (struct pvr2_ctl_info *)(cptr->info);
778 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
779 if (info->set_value) {
a0fd1cb1 780 info->set_value = NULL;
b30d2441
MI		 781 }
782 } else {
783 if (!(info->set_value)) {
784 info->set_value = ctrl_cx2341x_set;
785 }
786 }
787 return qctrl.flags;
788}
789
d855497e
MI		 790static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
791{
681c7399
MI		 792 *vp = cptr->hdw->state_pipeline_req;
793 return 0;
794}
795
796static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
797{
798 *vp = cptr->hdw->master_state;
d855497e
MI		 799 return 0;
800}
801
802static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
803{
804 int result = pvr2_hdw_is_hsm(cptr->hdw);
805 *vp = PVR2_CVAL_HSM_FULL;
806 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
807 if (result) *vp = PVR2_CVAL_HSM_HIGH;
808 return 0;
809}
810
811static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
812{
813 *vp = cptr->hdw->std_mask_avail;
814 return 0;
815}
816
817static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
818{
819 struct pvr2_hdw *hdw = cptr->hdw;
820 v4l2_std_id ns;
821 ns = hdw->std_mask_avail;
822 ns = (ns & ~m) | (v & m);
823 if (ns == hdw->std_mask_avail) return 0;
824 hdw->std_mask_avail = ns;
825 pvr2_hdw_internal_set_std_avail(hdw);
826 pvr2_hdw_internal_find_stdenum(hdw);
827 return 0;
828}
829
830static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
831 char *bufPtr,unsigned int bufSize,
832 unsigned int *len)
833{
834 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
835 return 0;
836}
837
838static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
839 const char *bufPtr,unsigned int bufSize,
840 int *mskp,int *valp)
841{
842 int ret;
843 v4l2_std_id id;
844 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
845 if (ret < 0) return ret;
846 if (mskp) *mskp = id;
847 if (valp) *valp = id;
848 return 0;
849}
850
851static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
852{
853 *vp = cptr->hdw->std_mask_cur;
854 return 0;
855}
856
857static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
858{
859 struct pvr2_hdw *hdw = cptr->hdw;
860 v4l2_std_id ns;
861 ns = hdw->std_mask_cur;
862 ns = (ns & ~m) | (v & m);
863 if (ns == hdw->std_mask_cur) return 0;
864 hdw->std_mask_cur = ns;
865 hdw->std_dirty = !0;
866 pvr2_hdw_internal_find_stdenum(hdw);
867 return 0;
868}
869
870static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
871{
872 return cptr->hdw->std_dirty != 0;
873}
874
875static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
876{
877 cptr->hdw->std_dirty = 0;
878}
879
880static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
881{
18103c57 882 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 883 pvr2_hdw_status_poll(hdw);
18103c57
MI		 884 *vp = hdw->tuner_signal_info.signal;
885 return 0;
886}
887
888static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
889{
890 int val = 0;
891 unsigned int subchan;
892 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 893 pvr2_hdw_status_poll(hdw);
18103c57
MI		 894 subchan = hdw->tuner_signal_info.rxsubchans;
895 if (subchan & V4L2_TUNER_SUB_MONO) {
896 val |= (1 << V4L2_TUNER_MODE_MONO);
897 }
898 if (subchan & V4L2_TUNER_SUB_STEREO) {
899 val |= (1 << V4L2_TUNER_MODE_STEREO);
900 }
901 if (subchan & V4L2_TUNER_SUB_LANG1) {
902 val |= (1 << V4L2_TUNER_MODE_LANG1);
903 }
904 if (subchan & V4L2_TUNER_SUB_LANG2) {
905 val |= (1 << V4L2_TUNER_MODE_LANG2);
906 }
907 *vp = val;
d855497e
MI		 908 return 0;
909}
910
d855497e
MI		 911
912static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
913{
914 struct pvr2_hdw *hdw = cptr->hdw;
915 if (v < 0) return -EINVAL;
916 if (v > hdw->std_enum_cnt) return -EINVAL;
917 hdw->std_enum_cur = v;
918 if (!v) return 0;
919 v--;
920 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
921 hdw->std_mask_cur = hdw->std_defs[v].id;
922 hdw->std_dirty = !0;
923 return 0;
924}
925
926
927static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
928{
929 *vp = cptr->hdw->std_enum_cur;
930 return 0;
931}
932
933
934static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
935{
936 return cptr->hdw->std_dirty != 0;
937}
938
939
940static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
941{
942 cptr->hdw->std_dirty = 0;
943}
944
945
946#define DEFINT(vmin,vmax) \
947 .type = pvr2_ctl_int, \
948 .def.type_int.min_value = vmin, \
949 .def.type_int.max_value = vmax
950
951#define DEFENUM(tab) \
952 .type = pvr2_ctl_enum, \
27c7b710 953 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 954 .def.type_enum.value_names = tab
955
33213963
MI		 956#define DEFBOOL \
957 .type = pvr2_ctl_bool
958
d855497e
MI		 959#define DEFMASK(msk,tab) \
960 .type = pvr2_ctl_bitmask, \
961 .def.type_bitmask.valid_bits = msk, \
962 .def.type_bitmask.bit_names = tab
963
964#define DEFREF(vname) \
965 .set_value = ctrl_set_##vname, \
966 .get_value = ctrl_get_##vname, \
967 .is_dirty = ctrl_isdirty_##vname, \
968 .clear_dirty = ctrl_cleardirty_##vname
969
970
971#define VCREATE_FUNCS(vname) \
972static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
973{*vp = cptr->hdw->vname##_val; return 0;} \
974static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
975{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
976static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
977{return cptr->hdw->vname##_dirty != 0;} \
978static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
979{cptr->hdw->vname##_dirty = 0;}
980
981VCREATE_FUNCS(brightness)
982VCREATE_FUNCS(contrast)
983VCREATE_FUNCS(saturation)
984VCREATE_FUNCS(hue)
985VCREATE_FUNCS(volume)
986VCREATE_FUNCS(balance)
987VCREATE_FUNCS(bass)
988VCREATE_FUNCS(treble)
989VCREATE_FUNCS(mute)
e784bfb9 990VCREATE_FUNCS(cropl)
991VCREATE_FUNCS(cropt)
992VCREATE_FUNCS(cropw)
993VCREATE_FUNCS(croph)
c05c0462
MI		 994VCREATE_FUNCS(audiomode)
995VCREATE_FUNCS(res_hor)
996VCREATE_FUNCS(res_ver)
d855497e 997VCREATE_FUNCS(srate)
d855497e 998
d855497e
MI		 999/* Table definition of all controls which can be manipulated */
1000static const struct pvr2_ctl_info control_defs[] = {
1001 {
1002 .v4l_id = V4L2_CID_BRIGHTNESS,
1003 .desc = "Brightness",
1004 .name = "brightness",
1005 .default_value = 128,
1006 DEFREF(brightness),
1007 DEFINT(0,255),
1008 },{
1009 .v4l_id = V4L2_CID_CONTRAST,
1010 .desc = "Contrast",
1011 .name = "contrast",
1012 .default_value = 68,
1013 DEFREF(contrast),
1014 DEFINT(0,127),
1015 },{
1016 .v4l_id = V4L2_CID_SATURATION,
1017 .desc = "Saturation",
1018 .name = "saturation",
1019 .default_value = 64,
1020 DEFREF(saturation),
1021 DEFINT(0,127),
1022 },{
1023 .v4l_id = V4L2_CID_HUE,
1024 .desc = "Hue",
1025 .name = "hue",
1026 .default_value = 0,
1027 DEFREF(hue),
1028 DEFINT(-128,127),
1029 },{
1030 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1031 .desc = "Volume",
1032 .name = "volume",
139eecf9 1033 .default_value = 62000,
d855497e
MI		 1034 DEFREF(volume),
1035 DEFINT(0,65535),
1036 },{
1037 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1038 .desc = "Balance",
1039 .name = "balance",
1040 .default_value = 0,
1041 DEFREF(balance),
1042 DEFINT(-32768,32767),
1043 },{
1044 .v4l_id = V4L2_CID_AUDIO_BASS,
1045 .desc = "Bass",
1046 .name = "bass",
1047 .default_value = 0,
1048 DEFREF(bass),
1049 DEFINT(-32768,32767),
1050 },{
1051 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1052 .desc = "Treble",
1053 .name = "treble",
1054 .default_value = 0,
1055 DEFREF(treble),
1056 DEFINT(-32768,32767),
1057 },{
1058 .v4l_id = V4L2_CID_AUDIO_MUTE,
1059 .desc = "Mute",
1060 .name = "mute",
1061 .default_value = 0,
1062 DEFREF(mute),
33213963 1063 DEFBOOL,
e784bfb9 1064 }, {
432907f7 1065 .desc = "Capture crop left margin",
e784bfb9 1066 .name = "crop_left",
1067 .internal_id = PVR2_CID_CROPL,
1068 .default_value = 0,
1069 DEFREF(cropl),
1070 DEFINT(-129, 340),
1071 .get_min_value = ctrl_cropl_min_get,
1072 .get_max_value = ctrl_cropl_max_get,
432907f7 1073 .get_def_value = ctrl_get_cropcapdl,
e784bfb9 1074 }, {
432907f7 1075 .desc = "Capture crop top margin",
e784bfb9 1076 .name = "crop_top",
1077 .internal_id = PVR2_CID_CROPT,
1078 .default_value = 0,
1079 DEFREF(cropt),
1080 DEFINT(-35, 544),
1081 .get_min_value = ctrl_cropt_min_get,
1082 .get_max_value = ctrl_cropt_max_get,
432907f7 1083 .get_def_value = ctrl_get_cropcapdt,
e784bfb9 1084 }, {
432907f7 1085 .desc = "Capture crop width",
e784bfb9 1086 .name = "crop_width",
1087 .internal_id = PVR2_CID_CROPW,
1088 .default_value = 720,
1089 DEFREF(cropw),
432907f7
MI		 1090 .get_max_value = ctrl_cropw_max_get,
1091 .get_def_value = ctrl_get_cropcapdw,
e784bfb9 1092 }, {
432907f7 1093 .desc = "Capture crop height",
e784bfb9 1094 .name = "crop_height",
1095 .internal_id = PVR2_CID_CROPH,
1096 .default_value = 480,
1097 DEFREF(croph),
432907f7
MI		 1098 .get_max_value = ctrl_croph_max_get,
1099 .get_def_value = ctrl_get_cropcapdh,
1100 }, {
1101 .desc = "Capture capability pixel aspect numerator",
1102 .name = "cropcap_pixel_numerator",
1103 .internal_id = PVR2_CID_CROPCAPPAN,
1104 .get_value = ctrl_get_cropcappan,
1105 }, {
1106 .desc = "Capture capability pixel aspect denominator",
1107 .name = "cropcap_pixel_denominator",
1108 .internal_id = PVR2_CID_CROPCAPPAD,
1109 .get_value = ctrl_get_cropcappad,
1110 }, {
1111 .desc = "Capture capability bounds top",
1112 .name = "cropcap_bounds_top",
1113 .internal_id = PVR2_CID_CROPCAPBT,
1114 .get_value = ctrl_get_cropcapbt,
1115 }, {
1116 .desc = "Capture capability bounds left",
1117 .name = "cropcap_bounds_left",
1118 .internal_id = PVR2_CID_CROPCAPBL,
1119 .get_value = ctrl_get_cropcapbl,
1120 }, {
1121 .desc = "Capture capability bounds width",
1122 .name = "cropcap_bounds_width",
1123 .internal_id = PVR2_CID_CROPCAPBW,
1124 .get_value = ctrl_get_cropcapbw,
1125 }, {
1126 .desc = "Capture capability bounds height",
1127 .name = "cropcap_bounds_height",
1128 .internal_id = PVR2_CID_CROPCAPBH,
1129 .get_value = ctrl_get_cropcapbh,
c05c0462
MI		 1130 },{
1131 .desc = "Video Source",
1132 .name = "input",
1133 .internal_id = PVR2_CID_INPUT,
1134 .default_value = PVR2_CVAL_INPUT_TV,
29bf5b1d 1135 .check_value = ctrl_check_input,
c05c0462
MI		 1136 DEFREF(input),
1137 DEFENUM(control_values_input),
1138 },{
1139 .desc = "Audio Mode",
1140 .name = "audio_mode",
1141 .internal_id = PVR2_CID_AUDIOMODE,
1142 .default_value = V4L2_TUNER_MODE_STEREO,
1143 DEFREF(audiomode),
1144 DEFENUM(control_values_audiomode),
1145 },{
1146 .desc = "Horizontal capture resolution",
1147 .name = "resolution_hor",
1148 .internal_id = PVR2_CID_HRES,
1149 .default_value = 720,
1150 DEFREF(res_hor),
3ad9fc37 1151 DEFINT(19,720),
c05c0462
MI		 1152 },{
1153 .desc = "Vertical capture resolution",
1154 .name = "resolution_ver",
1155 .internal_id = PVR2_CID_VRES,
1156 .default_value = 480,
1157 DEFREF(res_ver),
3ad9fc37
MI		 1158 DEFINT(17,576),
1159 /* Hook in check for video standard and adjust maximum
1160 depending on the standard. */
1161 .get_max_value = ctrl_vres_max_get,
1162 .get_min_value = ctrl_vres_min_get,
d855497e 1163 },{
b30d2441 1164 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 1165 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1166 .desc = "Audio Sampling Frequency",
d855497e 1167 .name = "srate",
d855497e
MI		 1168 DEFREF(srate),
1169 DEFENUM(control_values_srate),
d855497e
MI		 1170 },{
1171 .desc = "Tuner Frequency (Hz)",
1172 .name = "frequency",
1173 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 1174 .default_value = 0,
d855497e
MI		 1175 .set_value = ctrl_freq_set,
1176 .get_value = ctrl_freq_get,
1177 .is_dirty = ctrl_freq_is_dirty,
1178 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 1179 DEFINT(0,0),
25d8527a
PK		 1180 /* Hook in check for input value (tv/radio) and adjust
1181 max/min values accordingly */
1182 .get_max_value = ctrl_freq_max_get,
1183 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1184 },{
1185 .desc = "Channel",
1186 .name = "channel",
1187 .set_value = ctrl_channel_set,
1188 .get_value = ctrl_channel_get,
1189 DEFINT(0,FREQTABLE_SIZE),
1190 },{
1191 .desc = "Channel Program Frequency",
1192 .name = "freq_table_value",
1193 .set_value = ctrl_channelfreq_set,
1194 .get_value = ctrl_channelfreq_get,
644afdb9 1195 DEFINT(0,0),
1bde0289
MI		 1196 /* Hook in check for input value (tv/radio) and adjust
1197 max/min values accordingly */
1bde0289
MI		 1198 .get_max_value = ctrl_freq_max_get,
1199 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1200 },{
1201 .desc = "Channel Program ID",
1202 .name = "freq_table_channel",
1203 .set_value = ctrl_channelprog_set,
1204 .get_value = ctrl_channelprog_get,
1205 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 1206 },{
1207 .desc = "Streaming Enabled",
1208 .name = "streaming_enabled",
1209 .get_value = ctrl_streamingenabled_get,
33213963 1210 DEFBOOL,
d855497e
MI		 1211 },{
1212 .desc = "USB Speed",
1213 .name = "usb_speed",
1214 .get_value = ctrl_hsm_get,
1215 DEFENUM(control_values_hsm),
681c7399
MI		 1216 },{
1217 .desc = "Master State",
1218 .name = "master_state",
1219 .get_value = ctrl_masterstate_get,
1220 DEFENUM(pvr2_state_names),
d855497e
MI		 1221 },{
1222 .desc = "Signal Present",
1223 .name = "signal_present",
1224 .get_value = ctrl_signal_get,
18103c57
MI		 1225 DEFINT(0,65535),
1226 },{
1227 .desc = "Audio Modes Present",
1228 .name = "audio_modes_present",
1229 .get_value = ctrl_audio_modes_present_get,
1230 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1231 v4l. Nothing outside of this module cares about this,
1232 but I reuse it in order to also reuse the
1233 control_values_audiomode string table. */
1234 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1235 (1 << V4L2_TUNER_MODE_STEREO)|
1236 (1 << V4L2_TUNER_MODE_LANG1)|
1237 (1 << V4L2_TUNER_MODE_LANG2)),
1238 control_values_audiomode),
d855497e
MI		 1239 },{
1240 .desc = "Video Standards Available Mask",
1241 .name = "video_standard_mask_available",
1242 .internal_id = PVR2_CID_STDAVAIL,
1243 .skip_init = !0,
1244 .get_value = ctrl_stdavail_get,
1245 .set_value = ctrl_stdavail_set,
1246 .val_to_sym = ctrl_std_val_to_sym,
1247 .sym_to_val = ctrl_std_sym_to_val,
1248 .type = pvr2_ctl_bitmask,
1249 },{
1250 .desc = "Video Standards In Use Mask",
1251 .name = "video_standard_mask_active",
1252 .internal_id = PVR2_CID_STDCUR,
1253 .skip_init = !0,
1254 .get_value = ctrl_stdcur_get,
1255 .set_value = ctrl_stdcur_set,
1256 .is_dirty = ctrl_stdcur_is_dirty,
1257 .clear_dirty = ctrl_stdcur_clear_dirty,
1258 .val_to_sym = ctrl_std_val_to_sym,
1259 .sym_to_val = ctrl_std_sym_to_val,
1260 .type = pvr2_ctl_bitmask,
d855497e
MI		 1261 },{
1262 .desc = "Video Standard Name",
1263 .name = "video_standard",
1264 .internal_id = PVR2_CID_STDENUM,
1265 .skip_init = !0,
1266 .get_value = ctrl_stdenumcur_get,
1267 .set_value = ctrl_stdenumcur_set,
1268 .is_dirty = ctrl_stdenumcur_is_dirty,
1269 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1270 .type = pvr2_ctl_enum,
1271 }
1272};
1273
eca8ebfc 1274#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 1275
1276
1277const char *pvr2_config_get_name(enum pvr2_config cfg)
1278{
1279 switch (cfg) {
1280 case pvr2_config_empty: return "empty";
1281 case pvr2_config_mpeg: return "mpeg";
1282 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 1283 case pvr2_config_pcm: return "pcm";
1284 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 1285 }
1286 return "<unknown>";
1287}
1288
1289
1290struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1291{
1292 return hdw->usb_dev;
1293}
1294
1295
1296unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1297{
1298 return hdw->serial_number;
1299}
1300
31a18547
MI		 1301
1302const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1303{
1304 return hdw->bus_info;
1305}
1306
1307
13a88797
MI		 1308const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1309{
1310 return hdw->identifier;
1311}
1312
1313
1bde0289
MI		 1314unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1315{
1316 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1317}
1318
1319/* Set the currently tuned frequency and account for all possible
1320 driver-core side effects of this action. */
f55a8712 1321static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1bde0289 1322{
7c74e57e 1323 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 1324 if (hdw->freqSelector) {
1325 /* Swing over to radio frequency selection */
1326 hdw->freqSelector = 0;
1327 hdw->freqDirty = !0;
1328 }
1bde0289
MI		 1329 if (hdw->freqValRadio != val) {
1330 hdw->freqValRadio = val;
1331 hdw->freqSlotRadio = 0;
7c74e57e 1332 hdw->freqDirty = !0;
1bde0289 1333 }
7c74e57e 1334 } else {
1bde0289
MI		 1335 if (!(hdw->freqSelector)) {
1336 /* Swing over to television frequency selection */
1337 hdw->freqSelector = 1;
1338 hdw->freqDirty = !0;
1339 }
1bde0289
MI		 1340 if (hdw->freqValTelevision != val) {
1341 hdw->freqValTelevision = val;
1342 hdw->freqSlotTelevision = 0;
7c74e57e 1343 hdw->freqDirty = !0;
1bde0289 1344 }
1bde0289
MI		 1345 }
1346}
1347
d855497e
MI		 1348int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1349{
1350 return hdw->unit_number;
1351}
1352
1353
1354/* Attempt to locate one of the given set of files. Messages are logged
1355 appropriate to what has been found. The return value will be 0 or
1356 greater on success (it will be the index of the file name found) and
1357 fw_entry will be filled in. Otherwise a negative error is returned on
1358 failure. If the return value is -ENOENT then no viable firmware file
1359 could be located. */
1360static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1361 const struct firmware **fw_entry,
1362 const char *fwtypename,
1363 unsigned int fwcount,
1364 const char *fwnames[])
1365{
1366 unsigned int idx;
1367 int ret = -EINVAL;
1368 for (idx = 0; idx < fwcount; idx++) {
1369 ret = request_firmware(fw_entry,
1370 fwnames[idx],
1371 &hdw->usb_dev->dev);
1372 if (!ret) {
1373 trace_firmware("Located %s firmware: %s;"
1374 " uploading...",
1375 fwtypename,
1376 fwnames[idx]);
1377 return idx;
1378 }
1379 if (ret == -ENOENT) continue;
1380 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1381 "request_firmware fatal error with code=%d",ret);
1382 return ret;
1383 }
1384 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1385 "***WARNING***"
1386 " Device %s firmware"
1387 " seems to be missing.",
1388 fwtypename);
1389 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1390 "Did you install the pvrusb2 firmware files"
1391 " in their proper location?");
1392 if (fwcount == 1) {
1393 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1394 "request_firmware unable to locate %s file %s",
1395 fwtypename,fwnames[0]);
1396 } else {
1397 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1398 "request_firmware unable to locate"
1399 " one of the following %s files:",
1400 fwtypename);
1401 for (idx = 0; idx < fwcount; idx++) {
1402 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1403 "request_firmware: Failed to find %s",
1404 fwnames[idx]);
1405 }
1406 }
1407 return ret;
1408}
1409
1410
1411/*
1412 * pvr2_upload_firmware1().
1413 *
1414 * Send the 8051 firmware to the device. After the upload, arrange for
1415 * device to re-enumerate.
1416 *
1417 * NOTE : the pointer to the firmware data given by request_firmware()
1418 * is not suitable for an usb transaction.
1419 *
1420 */
07e337ee 1421static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1422{
a0fd1cb1 1423 const struct firmware *fw_entry = NULL;
d855497e
MI		 1424 void *fw_ptr;
1425 unsigned int pipe;
1426 int ret;
1427 u16 address;
1d643a37 1428
989eb154 1429 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1430 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1431 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1432 "Connected device type defines"
1433 " no firmware to upload; ignoring firmware");
1434 return -ENOTTY;
1d643a37
MI		 1435 }
1436
d855497e
MI		 1437 hdw->fw1_state = FW1_STATE_FAILED; // default result
1438
1439 trace_firmware("pvr2_upload_firmware1");
1440
1441 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1442 hdw->hdw_desc->fx2_firmware.cnt,
1443 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1444 if (ret < 0) {
1445 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1446 return ret;
1447 }
1448
1449 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1450 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1451
1452 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1453
1454 if (fw_entry->size != 0x2000){
1455 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1456 release_firmware(fw_entry);
1457 return -ENOMEM;
1458 }
1459
1460 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1461 if (fw_ptr == NULL){
1462 release_firmware(fw_entry);
1463 return -ENOMEM;
1464 }
1465
1466 /* We have to hold the CPU during firmware upload. */
1467 pvr2_hdw_cpureset_assert(hdw,1);
1468
1469 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1470 chunk. */
1471
1472 ret = 0;
1473 for(address = 0; address < fw_entry->size; address += 0x800) {
1474 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1475 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1476 0, fw_ptr, 0x800, HZ);
1477 }
1478
1479 trace_firmware("Upload done, releasing device's CPU");
1480
1481 /* Now release the CPU. It will disconnect and reconnect later. */
1482 pvr2_hdw_cpureset_assert(hdw,0);
1483
1484 kfree(fw_ptr);
1485 release_firmware(fw_entry);
1486
1487 trace_firmware("Upload done (%d bytes sent)",ret);
1488
1489 /* We should have written 8192 bytes */
1490 if (ret == 8192) {
1491 hdw->fw1_state = FW1_STATE_RELOAD;
1492 return 0;
1493 }
1494
1495 return -EIO;
1496}
1497
1498
1499/*
1500 * pvr2_upload_firmware2()
1501 *
1502 * This uploads encoder firmware on endpoint 2.
1503 *
1504 */
1505
1506int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1507{
a0fd1cb1 1508 const struct firmware *fw_entry = NULL;
d855497e 1509 void *fw_ptr;
90060d32 1510 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1511 int actual_length;
1512 int ret = 0;
1513 int fwidx;
1514 static const char *fw_files[] = {
1515 CX2341X_FIRM_ENC_FILENAME,
1516 };
1517
989eb154 1518 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1519 return 0;
1520 }
1521
d855497e
MI		 1522 trace_firmware("pvr2_upload_firmware2");
1523
1524 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1525 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1526 if (ret < 0) return ret;
1527 fwidx = ret;
1528 ret = 0;
b30d2441
MI		 1529 /* Since we're about to completely reinitialize the encoder,
1530 invalidate our cached copy of its configuration state. Next
1531 time we configure the encoder, then we'll fully configure it. */
1532 hdw->enc_cur_valid = 0;
d855497e 1533
d913d630
MI		 1534 /* Encoder is about to be reset so note that as far as we're
1535 concerned now, the encoder has never been run. */
1536 del_timer_sync(&hdw->encoder_run_timer);
1537 if (hdw->state_encoder_runok) {
1538 hdw->state_encoder_runok = 0;
1539 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1540 }
1541
d855497e
MI		 1542 /* First prepare firmware loading */
1543 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1544 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1545 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1546 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1547 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1548 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1549 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1550 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1551 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1552 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1553 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1554 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1555 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1556 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1557 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1558 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1c9d10d4
MI		 1559 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1560 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1561
1562 if (ret) {
1563 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1564 "firmware2 upload prep failed, ret=%d",ret);
1565 release_firmware(fw_entry);
21684ba9 1566 goto done;
d855497e
MI		 1567 }
1568
1569 /* Now send firmware */
1570
1571 fw_len = fw_entry->size;
1572
90060d32 1573 if (fw_len % sizeof(u32)) {
d855497e
MI		 1574 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1575 "size of %s firmware"
48dc30a1 1576 " must be a multiple of %zu bytes",
90060d32 1577 fw_files[fwidx],sizeof(u32));
d855497e 1578 release_firmware(fw_entry);
21684ba9
MI		 1579 ret = -EINVAL;
1580 goto done;
d855497e
MI		 1581 }
1582
1583 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1584 if (fw_ptr == NULL){
1585 release_firmware(fw_entry);
1586 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1587 "failed to allocate memory for firmware2 upload");
21684ba9
MI		 1588 ret = -ENOMEM;
1589 goto done;
d855497e
MI		 1590 }
1591
1592 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1593
90060d32
MI		 1594 fw_done = 0;
1595 for (fw_done = 0; fw_done < fw_len;) {
1596 bcnt = fw_len - fw_done;
1597 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1598 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1599 /* Usbsnoop log shows that we must swap bytes... */
5f33df14
MI		 1600 /* Some background info: The data being swapped here is a
1601 firmware image destined for the mpeg encoder chip that
1602 lives at the other end of a USB endpoint. The encoder
1603 chip always talks in 32 bit chunks and its storage is
1604 organized into 32 bit words. However from the file
1605 system to the encoder chip everything is purely a byte
1606 stream. The firmware file's contents are always 32 bit
1607 swapped from what the encoder expects. Thus the need
1608 always exists to swap the bytes regardless of the endian
1609 type of the host processor and therefore swab32() makes
1610 the most sense. */
90060d32 1611 for (icnt = 0; icnt < bcnt/4 ; icnt++)
513edce6 1612 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
90060d32
MI		 1613
1614 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1615 &actual_length, HZ);
90060d32
MI		 1616 ret |= (actual_length != bcnt);
1617 if (ret) break;
1618 fw_done += bcnt;
d855497e
MI		 1619 }
1620
1621 trace_firmware("upload of %s : %i / %i ",
1622 fw_files[fwidx],fw_done,fw_len);
1623
1624 kfree(fw_ptr);
1625 release_firmware(fw_entry);
1626
1627 if (ret) {
1628 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1629 "firmware2 upload transfer failure");
21684ba9 1630 goto done;
d855497e
MI		 1631 }
1632
1633 /* Finish upload */
1634
1635 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1636 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1c9d10d4 1637 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1638
1639 if (ret) {
1640 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1641 "firmware2 upload post-proc failure");
d855497e 1642 }
21684ba9
MI		 1643
1644 done:
1df59f0b
MI		 1645 if (hdw->hdw_desc->signal_routing_scheme ==
1646 PVR2_ROUTING_SCHEME_GOTVIEW) {
1647 /* Ensure that GPIO 11 is set to output for GOTVIEW
1648 hardware. */
1649 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1650 }
d855497e
MI		 1651 return ret;
1652}
1653
1654
681c7399
MI		 1655static const char *pvr2_get_state_name(unsigned int st)
1656{
1657 if (st < ARRAY_SIZE(pvr2_state_names)) {
1658 return pvr2_state_names[st];
d855497e 1659 }
681c7399 1660 return "???";
d855497e
MI		 1661}
1662
681c7399 1663static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1664{
af78e16b
MI		 1665 if (hdw->decoder_ctrl) {
1666 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt, enablefl);
1667 return 0;
681c7399 1668 }
af78e16b
MI		 1669 /* Even though we really only care about the video decoder chip at
1670 this point, we'll broadcast stream on/off to all sub-devices
1671 anyway, just in case somebody else wants to hear the
1672 command... */
1673 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1674 if (hdw->decoder_client_id) {
1675 /* We get here if the encoder has been noticed. Otherwise
1676 we'll issue a warning to the user (which should
1677 normally never happen). */
1678 return 0;
1679 }
1680 if (!hdw->flag_decoder_missed) {
1681 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1682 "WARNING: No decoder present");
1683 hdw->flag_decoder_missed = !0;
1684 trace_stbit("flag_decoder_missed",
1685 hdw->flag_decoder_missed);
1686 }
1687 return -EIO;
d855497e
MI		 1688}
1689
1690
681c7399 1691void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
d855497e 1692{
681c7399
MI		 1693 if (hdw->decoder_ctrl == ptr) return;
1694 hdw->decoder_ctrl = ptr;
1695 if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1696 hdw->flag_decoder_missed = 0;
1697 trace_stbit("flag_decoder_missed",
1698 hdw->flag_decoder_missed);
1699 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1700 "Decoder has appeared");
1701 pvr2_hdw_state_sched(hdw);
1702 }
d855497e
MI		 1703}
1704
1705
681c7399 1706int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1707{
681c7399 1708 return hdw->master_state;
d855497e
MI		 1709}
1710
1711
681c7399 1712static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1713{
681c7399
MI		 1714 if (!hdw->flag_tripped) return 0;
1715 hdw->flag_tripped = 0;
1716 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1717 "Clearing driver error statuss");
1718 return !0;
d855497e
MI		 1719}
1720
1721
681c7399 1722int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1723{
681c7399 1724 int fl;
d855497e 1725 LOCK_TAKE(hdw->big_lock); do {
681c7399 1726 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1727 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1728 if (fl) pvr2_hdw_state_sched(hdw);
1729 return 0;
d855497e
MI		 1730}
1731
1732
d855497e
MI		 1733
1734
1735int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1736{
681c7399 1737 return hdw->state_pipeline_req != 0;
d855497e
MI		 1738}
1739
1740
1741int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1742{
681c7399 1743 int ret,st;
d855497e 1744 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1745 pvr2_hdw_untrip_unlocked(hdw);
1746 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1747 hdw->state_pipeline_req = enable_flag != 0;
1748 pvr2_trace(PVR2_TRACE_START_STOP,
1749 "/*--TRACE_STREAM--*/ %s",
1750 enable_flag ? "enable" : "disable");
1751 }
1752 pvr2_hdw_state_sched(hdw);
d855497e 1753 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1754 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1755 if (enable_flag) {
1756 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1757 if (st != PVR2_STATE_READY) return -EIO;
1758 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1759 }
1760 }
d855497e
MI		 1761 return 0;
1762}
1763
1764
1765int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1766{
681c7399 1767 int fl;
d855497e 1768 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1769 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1770 hdw->desired_stream_type = config;
1771 hdw->state_pipeline_config = 0;
1772 trace_stbit("state_pipeline_config",
1773 hdw->state_pipeline_config);
1774 pvr2_hdw_state_sched(hdw);
1775 }
d855497e 1776 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1777 if (fl) return 0;
1778 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1779}
1780
1781
1782static int get_default_tuner_type(struct pvr2_hdw *hdw)
1783{
1784 int unit_number = hdw->unit_number;
1785 int tp = -1;
1786 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1787 tp = tuner[unit_number];
1788 }
1789 if (tp < 0) return -EINVAL;
1790 hdw->tuner_type = tp;
aaf7884d 1791 hdw->tuner_updated = !0;
d855497e
MI		 1792 return 0;
1793}
1794
1795
1796static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1797{
1798 int unit_number = hdw->unit_number;
1799 int tp = 0;
1800 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1801 tp = video_std[unit_number];
6a540254 1802 if (tp) return tp;
d855497e 1803 }
6a540254 1804 return 0;
d855497e
MI		 1805}
1806
1807
1808static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1809{
1810 int unit_number = hdw->unit_number;
1811 int tp = 0;
1812 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1813 tp = tolerance[unit_number];
1814 }
1815 return tp;
1816}
1817
1818
1819static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1820{
1821 /* Try a harmless request to fetch the eeprom's address over
1822 endpoint 1. See what happens. Only the full FX2 image can
1823 respond to this. If this probe fails then likely the FX2
1824 firmware needs be loaded. */
1825 int result;
1826 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1827 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1828 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1829 hdw->cmd_buffer,1,
1830 hdw->cmd_buffer,1);
1831 if (result < 0) break;
1832 } while(0); LOCK_GIVE(hdw->ctl_lock);
1833 if (result) {
1834 pvr2_trace(PVR2_TRACE_INIT,
1835 "Probe of device endpoint 1 result status %d",
1836 result);
1837 } else {
1838 pvr2_trace(PVR2_TRACE_INIT,
1839 "Probe of device endpoint 1 succeeded");
1840 }
1841 return result == 0;
1842}
1843
9f66d4ea
MI		 1844struct pvr2_std_hack {
1845 v4l2_std_id pat; /* Pattern to match */
1846 v4l2_std_id msk; /* Which bits we care about */
1847 v4l2_std_id std; /* What additional standards or default to set */
1848};
1849
1850/* This data structure labels specific combinations of standards from
1851 tveeprom that we'll try to recognize. If we recognize one, then assume
1852 a specified default standard to use. This is here because tveeprom only
1853 tells us about available standards not the intended default standard (if
1854 any) for the device in question. We guess the default based on what has
1855 been reported as available. Note that this is only for guessing a
1856 default - which can always be overridden explicitly - and if the user
1857 has otherwise named a default then that default will always be used in
1858 place of this table. */
ebff0330 1859static const struct pvr2_std_hack std_eeprom_maps[] = {
9f66d4ea
MI		 1860 { /* PAL(B/G) */
1861 .pat = V4L2_STD_B|V4L2_STD_GH,
1862 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1863 },
1864 { /* NTSC(M) */
1865 .pat = V4L2_STD_MN,
1866 .std = V4L2_STD_NTSC_M,
1867 },
1868 { /* PAL(I) */
1869 .pat = V4L2_STD_PAL_I,
1870 .std = V4L2_STD_PAL_I,
1871 },
1872 { /* SECAM(L/L') */
1873 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1874 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1875 },
1876 { /* PAL(D/D1/K) */
1877 .pat = V4L2_STD_DK,
ea2562d9 1878 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
9f66d4ea
MI		 1879 },
1880};
1881
d855497e
MI		 1882static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1883{
1884 char buf[40];
1885 unsigned int bcnt;
3d290bdb 1886 v4l2_std_id std1,std2,std3;
d855497e
MI		 1887
1888 std1 = get_default_standard(hdw);
3d290bdb 1889 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
d855497e
MI		 1890
1891 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1892 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1893 "Supported video standard(s) reported available"
1894 " in hardware: %.*s",
d855497e
MI		 1895 bcnt,buf);
1896
1897 hdw->std_mask_avail = hdw->std_mask_eeprom;
1898
3d290bdb 1899 std2 = (std1|std3) & ~hdw->std_mask_avail;
d855497e
MI		 1900 if (std2) {
1901 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1902 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1903 "Expanding supported video standards"
1904 " to include: %.*s",
1905 bcnt,buf);
1906 hdw->std_mask_avail |= std2;
1907 }
1908
1909 pvr2_hdw_internal_set_std_avail(hdw);
1910
1911 if (std1) {
1912 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1913 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1914 "Initial video standard forced to %.*s",
1915 bcnt,buf);
1916 hdw->std_mask_cur = std1;
1917 hdw->std_dirty = !0;
1918 pvr2_hdw_internal_find_stdenum(hdw);
1919 return;
1920 }
3d290bdb
MI		 1921 if (std3) {
1922 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1923 pvr2_trace(PVR2_TRACE_STD,
1924 "Initial video standard"
1925 " (determined by device type): %.*s",bcnt,buf);
1926 hdw->std_mask_cur = std3;
1927 hdw->std_dirty = !0;
1928 pvr2_hdw_internal_find_stdenum(hdw);
1929 return;
1930 }
d855497e 1931
9f66d4ea
MI		 1932 {
1933 unsigned int idx;
1934 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1935 if (std_eeprom_maps[idx].msk ?
1936 ((std_eeprom_maps[idx].pat ^
1937 hdw->std_mask_eeprom) &
1938 std_eeprom_maps[idx].msk) :
1939 (std_eeprom_maps[idx].pat !=
1940 hdw->std_mask_eeprom)) continue;
1941 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1942 std_eeprom_maps[idx].std);
56585386 1943 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1944 "Initial video standard guessed as %.*s",
1945 bcnt,buf);
1946 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1947 hdw->std_dirty = !0;
1948 pvr2_hdw_internal_find_stdenum(hdw);
1949 return;
1950 }
1951 }
1952
d855497e
MI		 1953 if (hdw->std_enum_cnt > 1) {
1954 // Autoselect the first listed standard
1955 hdw->std_enum_cur = 1;
1956 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1957 hdw->std_dirty = !0;
56585386 1958 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1959 "Initial video standard auto-selected to %s",
1960 hdw->std_defs[hdw->std_enum_cur-1].name);
1961 return;
1962 }
1963
0885ba1d 1964 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1965 "Unable to select a viable initial video standard");
1966}
1967
1968
e9c64a78
MI		 1969static unsigned int pvr2_copy_i2c_addr_list(
1970 unsigned short *dst, const unsigned char *src,
1971 unsigned int dst_max)
1972{
1973 unsigned int cnt;
1974 if (!src) return 0;
1975 while (src[cnt] && (cnt + 1) < dst_max) {
1976 dst[cnt] = src[cnt];
1977 cnt++;
1978 }
1979 dst[cnt] = I2C_CLIENT_END;
1980 return cnt;
1981}
1982
1983
1ab5e74f
MI		 1984static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1985 const struct pvr2_device_client_desc *cd)
e9c64a78
MI		 1986{
1987 const char *fname;
1988 unsigned char mid;
1989 struct v4l2_subdev *sd;
1990 unsigned int i2ccnt;
1991 const unsigned char *p;
1992 /* Arbitrary count - max # i2c addresses we will probe */
1993 unsigned short i2caddr[25];
1994
1995 mid = cd->module_id;
1996 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
1997 if (!fname) {
1998 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f 1999 "Module ID %u for device %s has no name",
e9c64a78
MI		 2000 mid,
2001 hdw->hdw_desc->description);
1ab5e74f 2002 return -EINVAL;
e9c64a78
MI		 2003 }
2004
2005 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2006 ARRAY_SIZE(i2caddr));
2007 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2008 module_i2c_addresses[mid] : NULL) != NULL)) {
2009 /* Second chance: Try default i2c address list */
2010 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2011 ARRAY_SIZE(i2caddr));
2012 }
2013
2014 if (!i2ccnt) {
2015 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f
MI		 2016 "Module ID %u (%s) for device %s:"
2017 " No i2c addresses",
2018 mid, fname, hdw->hdw_desc->description);
2019 return -EINVAL;
e9c64a78
MI		 2020 }
2021
2022 /* Note how the 2nd and 3rd arguments are the same for both
2023 * v4l2_i2c_new_subdev() and v4l2_i2c_new_probed_subdev(). Why?
2024 * Well the 2nd argument is the module name to load, while the 3rd
2025 * argument is documented in the framework as being the "chipid" -
2026 * and every other place where I can find examples of this, the
2027 * "chipid" appears to just be the module name again. So here we
2028 * just do the same thing. */
2029 if (i2ccnt == 1) {
2030 sd = v4l2_i2c_new_subdev(&hdw->i2c_adap,
2031 fname, fname,
2032 i2caddr[0]);
2033 } else {
2034 sd = v4l2_i2c_new_probed_subdev(&hdw->i2c_adap,
2035 fname, fname,
2036 i2caddr);
2037 }
2038
446dfdc6
MI		 2039 if (!sd) {
2040 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f
MI		 2041 "Module ID %u (%s) for device %s failed to load",
2042 mid, fname, hdw->hdw_desc->description);
2043 return -EIO;
446dfdc6
MI		 2044 }
2045
2046 /* Tag this sub-device instance with the module ID we know about.
2047 In other places we'll use that tag to determine if the instance
2048 requires special handling. */
2049 sd->grp_id = mid;
2050
a932f507
MI		 2051 /* If we have both old and new i2c layers enabled, make sure that
2052 old layer isn't also tracking this module. This is a debugging
2053 aid, in normal situations there's no reason for both mechanisms
2054 to be enabled. */
2055 pvr2_i2c_untrack_subdev(hdw, sd);
446dfdc6 2056 pvr2_trace(PVR2_TRACE_INIT, "Attached sub-driver %s", fname);
a932f507 2057
e9c64a78 2058
00e5f736
MI		 2059 /* client-specific setup... */
2060 switch (mid) {
2061 case PVR2_CLIENT_ID_CX25840:
2062 hdw->decoder_client_id = mid;
2063 {
2064 /*
2065 Mike Isely <isely@pobox.com> 19-Nov-2006 - This
2066 bit of nuttiness for cx25840 causes that module
2067 to correctly set up its video scaling. This is
2068 really a problem in the cx25840 module itself,
2069 but we work around it here. The problem has not
2070 been seen in ivtv because there VBI is supported
2071 and set up. We don't do VBI here (at least not
2072 yet) and thus we never attempted to even set it
2073 up.
2074 */
2075 struct v4l2_format fmt;
2076 memset(&fmt, 0, sizeof(fmt));
2077 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2078 v4l2_device_call_all(&hdw->v4l2_dev, mid,
2079 video, s_fmt, &fmt);
2080 }
2081 break;
2082 case PVR2_CLIENT_ID_SAA7115:
2083 hdw->decoder_client_id = mid;
2084 break;
2085 default: break;
2086 }
1ab5e74f
MI		 2087
2088 return 0;
e9c64a78
MI		 2089}
2090
2091
2092static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2093{
2094 unsigned int idx;
2095 const struct pvr2_string_table *cm;
2096 const struct pvr2_device_client_table *ct;
1ab5e74f 2097 int okFl = !0;
e9c64a78
MI		 2098
2099 cm = &hdw->hdw_desc->client_modules;
2100 for (idx = 0; idx < cm->cnt; idx++) {
2101 request_module(cm->lst[idx]);
2102 }
2103
2104 ct = &hdw->hdw_desc->client_table;
2105 for (idx = 0; idx < ct->cnt; idx++) {
1ab5e74f 2106 if (!pvr2_hdw_load_subdev(hdw, &ct->lst[idx])) okFl = 0;
e9c64a78 2107 }
1ab5e74f 2108 if (!okFl) pvr2_hdw_render_useless(hdw);
e9c64a78
MI		 2109}
2110
2111
d855497e
MI		 2112static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2113{
2114 int ret;
2115 unsigned int idx;
2116 struct pvr2_ctrl *cptr;
2117 int reloadFl = 0;
989eb154 2118 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 2119 if (!reloadFl) {
2120 reloadFl =
2121 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2122 == 0);
2123 if (reloadFl) {
2124 pvr2_trace(PVR2_TRACE_INIT,
2125 "USB endpoint config looks strange"
2126 "; possibly firmware needs to be"
2127 " loaded");
2128 }
d855497e 2129 }
1d643a37
MI		 2130 if (!reloadFl) {
2131 reloadFl = !pvr2_hdw_check_firmware(hdw);
2132 if (reloadFl) {
2133 pvr2_trace(PVR2_TRACE_INIT,
2134 "Check for FX2 firmware failed"
2135 "; possibly firmware needs to be"
2136 " loaded");
2137 }
d855497e 2138 }
1d643a37
MI		 2139 if (reloadFl) {
2140 if (pvr2_upload_firmware1(hdw) != 0) {
2141 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2142 "Failure uploading firmware1");
2143 }
2144 return;
d855497e 2145 }
d855497e
MI		 2146 }
2147 hdw->fw1_state = FW1_STATE_OK;
2148
d855497e
MI		 2149 if (!pvr2_hdw_dev_ok(hdw)) return;
2150
989eb154 2151 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 2152 pvr2_hdw_cmd_powerup(hdw);
2153 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 2154 }
2155
31335b13
MI		 2156 /* Take the IR chip out of reset, if appropriate */
2157 if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
2158 pvr2_issue_simple_cmd(hdw,
2159 FX2CMD_HCW_ZILOG_RESET |
2160 (1 << 8) |
2161 ((0) << 16));
2162 }
2163
d855497e 2164 // This step MUST happen after the earlier powerup step.
59af3367 2165 pvr2_i2c_track_init(hdw);
d855497e
MI		 2166 pvr2_i2c_core_init(hdw);
2167 if (!pvr2_hdw_dev_ok(hdw)) return;
2168
e9c64a78 2169 pvr2_hdw_load_modules(hdw);
1ab5e74f 2170 if (!pvr2_hdw_dev_ok(hdw)) return;
e9c64a78 2171
c05c0462 2172 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 2173 cptr = hdw->controls + idx;
2174 if (cptr->info->skip_init) continue;
2175 if (!cptr->info->set_value) continue;
2176 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2177 }
2178
1bde0289
MI		 2179 /* Set up special default values for the television and radio
2180 frequencies here. It's not really important what these defaults
2181 are, but I set them to something usable in the Chicago area just
2182 to make driver testing a little easier. */
2183
5a4f5da6
MK		 2184 hdw->freqValTelevision = default_tv_freq;
2185 hdw->freqValRadio = default_radio_freq;
1bde0289 2186
d855497e
MI		 2187 // Do not use pvr2_reset_ctl_endpoints() here. It is not
2188 // thread-safe against the normal pvr2_send_request() mechanism.
2189 // (We should make it thread safe).
2190
aaf7884d
MI		 2191 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2192 ret = pvr2_hdw_get_eeprom_addr(hdw);
d855497e 2193 if (!pvr2_hdw_dev_ok(hdw)) return;
aaf7884d
MI		 2194 if (ret < 0) {
2195 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2196 "Unable to determine location of eeprom,"
2197 " skipping");
2198 } else {
2199 hdw->eeprom_addr = ret;
2200 pvr2_eeprom_analyze(hdw);
2201 if (!pvr2_hdw_dev_ok(hdw)) return;
2202 }
2203 } else {
2204 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2205 hdw->tuner_updated = !0;
2206 hdw->std_mask_eeprom = V4L2_STD_ALL;
d855497e
MI		 2207 }
2208
13a88797
MI		 2209 if (hdw->serial_number) {
2210 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2211 "sn-%lu", hdw->serial_number);
2212 } else if (hdw->unit_number >= 0) {
2213 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2214 "unit-%c",
2215 hdw->unit_number + 'a');
2216 } else {
2217 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2218 "unit-??");
2219 }
2220 hdw->identifier[idx] = 0;
2221
d855497e
MI		 2222 pvr2_hdw_setup_std(hdw);
2223
2224 if (!get_default_tuner_type(hdw)) {
2225 pvr2_trace(PVR2_TRACE_INIT,
2226 "pvr2_hdw_setup: Tuner type overridden to %d",
2227 hdw->tuner_type);
2228 }
2229
d855497e
MI		 2230 pvr2_i2c_core_check_stale(hdw);
2231 hdw->tuner_updated = 0;
2232
2233 if (!pvr2_hdw_dev_ok(hdw)) return;
2234
1df59f0b
MI		 2235 if (hdw->hdw_desc->signal_routing_scheme ==
2236 PVR2_ROUTING_SCHEME_GOTVIEW) {
2237 /* Ensure that GPIO 11 is set to output for GOTVIEW
2238 hardware. */
2239 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2240 }
2241
681c7399 2242 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 2243
2244 hdw->vid_stream = pvr2_stream_create();
2245 if (!pvr2_hdw_dev_ok(hdw)) return;
2246 pvr2_trace(PVR2_TRACE_INIT,
2247 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2248 if (hdw->vid_stream) {
2249 idx = get_default_error_tolerance(hdw);
2250 if (idx) {
2251 pvr2_trace(PVR2_TRACE_INIT,
2252 "pvr2_hdw_setup: video stream %p"
2253 " setting tolerance %u",
2254 hdw->vid_stream,idx);
2255 }
2256 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2257 PVR2_VID_ENDPOINT,idx);
2258 }
2259
2260 if (!pvr2_hdw_dev_ok(hdw)) return;
2261
d855497e 2262 hdw->flag_init_ok = !0;
681c7399
MI		 2263
2264 pvr2_hdw_state_sched(hdw);
d855497e
MI		 2265}
2266
2267
681c7399
MI		 2268/* Set up the structure and attempt to put the device into a usable state.
2269 This can be a time-consuming operation, which is why it is not done
2270 internally as part of the create() step. */
2271static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 2272{
2273 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 2274 do {
d855497e
MI		 2275 pvr2_hdw_setup_low(hdw);
2276 pvr2_trace(PVR2_TRACE_INIT,
2277 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 2278 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 2279 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 2280 if (hdw->flag_init_ok) {
d855497e
MI		 2281 pvr2_trace(
2282 PVR2_TRACE_INFO,
2283 "Device initialization"
2284 " completed successfully.");
2285 break;
2286 }
2287 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2288 pvr2_trace(
2289 PVR2_TRACE_INFO,
2290 "Device microcontroller firmware"
2291 " (re)loaded; it should now reset"
2292 " and reconnect.");
2293 break;
2294 }
2295 pvr2_trace(
2296 PVR2_TRACE_ERROR_LEGS,
2297 "Device initialization was not successful.");
2298 if (hdw->fw1_state == FW1_STATE_MISSING) {
2299 pvr2_trace(
2300 PVR2_TRACE_ERROR_LEGS,
2301 "Giving up since device"
2302 " microcontroller firmware"
2303 " appears to be missing.");
2304 break;
2305 }
2306 }
2307 if (procreload) {
2308 pvr2_trace(
2309 PVR2_TRACE_ERROR_LEGS,
2310 "Attempting pvrusb2 recovery by reloading"
2311 " primary firmware.");
2312 pvr2_trace(
2313 PVR2_TRACE_ERROR_LEGS,
2314 "If this works, device should disconnect"
2315 " and reconnect in a sane state.");
2316 hdw->fw1_state = FW1_STATE_UNKNOWN;
2317 pvr2_upload_firmware1(hdw);
2318 } else {
2319 pvr2_trace(
2320 PVR2_TRACE_ERROR_LEGS,
2321 "***WARNING*** pvrusb2 device hardware"
2322 " appears to be jammed"
2323 " and I can't clear it.");
2324 pvr2_trace(
2325 PVR2_TRACE_ERROR_LEGS,
2326 "You might need to power cycle"
2327 " the pvrusb2 device"
2328 " in order to recover.");
2329 }
681c7399 2330 } while (0);
d855497e 2331 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 2332}
2333
2334
c4a8828d
MI		 2335/* Perform second stage initialization. Set callback pointer first so that
2336 we can avoid a possible initialization race (if the kernel thread runs
2337 before the callback has been set). */
794b1607
MI		 2338int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2339 void (*callback_func)(void *),
2340 void *callback_data)
c4a8828d
MI		 2341{
2342 LOCK_TAKE(hdw->big_lock); do {
97f26ff6
MI		 2343 if (hdw->flag_disconnected) {
2344 /* Handle a race here: If we're already
2345 disconnected by this point, then give up. If we
2346 get past this then we'll remain connected for
2347 the duration of initialization since the entire
2348 initialization sequence is now protected by the
2349 big_lock. */
2350 break;
2351 }
c4a8828d
MI		 2352 hdw->state_data = callback_data;
2353 hdw->state_func = callback_func;
97f26ff6 2354 pvr2_hdw_setup(hdw);
c4a8828d 2355 } while (0); LOCK_GIVE(hdw->big_lock);
794b1607 2356 return hdw->flag_init_ok;
c4a8828d
MI		 2357}
2358
2359
2360/* Create, set up, and return a structure for interacting with the
2361 underlying hardware. */
d855497e
MI		 2362struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2363 const struct usb_device_id *devid)
2364{
7fb20fa3 2365 unsigned int idx,cnt1,cnt2,m;
fe15f136 2366 struct pvr2_hdw *hdw = NULL;
d855497e
MI		 2367 int valid_std_mask;
2368 struct pvr2_ctrl *cptr;
b72b7bf5 2369 struct usb_device *usb_dev;
989eb154 2370 const struct pvr2_device_desc *hdw_desc;
d855497e 2371 __u8 ifnum;
b30d2441
MI		 2372 struct v4l2_queryctrl qctrl;
2373 struct pvr2_ctl_info *ciptr;
d855497e 2374
b72b7bf5
MI		 2375 usb_dev = interface_to_usbdev(intf);
2376
d130fa8a 2377 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
d855497e 2378
fe15f136
MI		 2379 if (hdw_desc == NULL) {
2380 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2381 " No device description pointer,"
2382 " unable to continue.");
2383 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2384 " please contact Mike Isely <isely@pobox.com>"
2385 " to get it included in the driver\n");
2386 goto fail;
2387 }
2388
ca545f7c 2389 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 2390 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 2391 hdw,hdw_desc->description);
d855497e 2392 if (!hdw) goto fail;
681c7399
MI		 2393
2394 init_timer(&hdw->quiescent_timer);
2395 hdw->quiescent_timer.data = (unsigned long)hdw;
2396 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2397
2398 init_timer(&hdw->encoder_wait_timer);
2399 hdw->encoder_wait_timer.data = (unsigned long)hdw;
2400 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2401
d913d630
MI		 2402 init_timer(&hdw->encoder_run_timer);
2403 hdw->encoder_run_timer.data = (unsigned long)hdw;
2404 hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2405
681c7399
MI		 2406 hdw->master_state = PVR2_STATE_DEAD;
2407
2408 init_waitqueue_head(&hdw->state_wait_data);
2409
18103c57 2410 hdw->tuner_signal_stale = !0;
b30d2441 2411 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 2412
7fb20fa3
MI		 2413 /* Calculate which inputs are OK */
2414 m = 0;
2415 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
e8f5bacf
MI		 2416 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2417 m |= 1 << PVR2_CVAL_INPUT_DTV;
2418 }
7fb20fa3
MI		 2419 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2420 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2421 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2422 hdw->input_avail_mask = m;
1cb03b76 2423 hdw->input_allowed_mask = hdw->input_avail_mask;
7fb20fa3 2424
62433e31
MI		 2425 /* If not a hybrid device, pathway_state never changes. So
2426 initialize it here to what it should forever be. */
2427 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2428 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2429 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2430 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2431 }
2432
c05c0462 2433 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 2434 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 2435 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 2436 GFP_KERNEL);
2437 if (!hdw->controls) goto fail;
989eb154 2438 hdw->hdw_desc = hdw_desc;
c05c0462
MI		 2439 for (idx = 0; idx < hdw->control_cnt; idx++) {
2440 cptr = hdw->controls + idx;
2441 cptr->hdw = hdw;
2442 }
d855497e
MI		 2443 for (idx = 0; idx < 32; idx++) {
2444 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2445 }
c05c0462 2446 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 2447 cptr = hdw->controls + idx;
d855497e
MI		 2448 cptr->info = control_defs+idx;
2449 }
dbc40a0e
MI		 2450
2451 /* Ensure that default input choice is a valid one. */
2452 m = hdw->input_avail_mask;
2453 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2454 if (!((1 << idx) & m)) continue;
2455 hdw->input_val = idx;
2456 break;
2457 }
2458
b30d2441 2459 /* Define and configure additional controls from cx2341x module. */
ca545f7c 2460 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 2461 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2462 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 2463 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2464 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2465 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2466 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2467 ciptr->name = mpeg_ids[idx].strid;
2468 ciptr->v4l_id = mpeg_ids[idx].id;
2469 ciptr->skip_init = !0;
2470 ciptr->get_value = ctrl_cx2341x_get;
2471 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2472 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2473 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2474 qctrl.id = ciptr->v4l_id;
2475 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2476 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2477 ciptr->set_value = ctrl_cx2341x_set;
2478 }
2479 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2480 PVR2_CTLD_INFO_DESC_SIZE);
2481 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2482 ciptr->default_value = qctrl.default_value;
2483 switch (qctrl.type) {
2484 default:
2485 case V4L2_CTRL_TYPE_INTEGER:
2486 ciptr->type = pvr2_ctl_int;
2487 ciptr->def.type_int.min_value = qctrl.minimum;
2488 ciptr->def.type_int.max_value = qctrl.maximum;
2489 break;
2490 case V4L2_CTRL_TYPE_BOOLEAN:
2491 ciptr->type = pvr2_ctl_bool;
2492 break;
2493 case V4L2_CTRL_TYPE_MENU:
2494 ciptr->type = pvr2_ctl_enum;
2495 ciptr->def.type_enum.value_names =
e0e31cdb
HV		 2496 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2497 ciptr->v4l_id);
b30d2441
MI		 2498 for (cnt1 = 0;
2499 ciptr->def.type_enum.value_names[cnt1] != NULL;
2500 cnt1++) { }
2501 ciptr->def.type_enum.count = cnt1;
2502 break;
2503 }
2504 cptr->info = ciptr;
2505 }
d855497e
MI		 2506
2507 // Initialize video standard enum dynamic control
2508 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2509 if (cptr) {
2510 memcpy(&hdw->std_info_enum,cptr->info,
2511 sizeof(hdw->std_info_enum));
2512 cptr->info = &hdw->std_info_enum;
2513
2514 }
2515 // Initialize control data regarding video standard masks
2516 valid_std_mask = pvr2_std_get_usable();
2517 for (idx = 0; idx < 32; idx++) {
2518 if (!(valid_std_mask & (1 << idx))) continue;
2519 cnt1 = pvr2_std_id_to_str(
2520 hdw->std_mask_names[idx],
2521 sizeof(hdw->std_mask_names[idx])-1,
2522 1 << idx);
2523 hdw->std_mask_names[idx][cnt1] = 0;
2524 }
2525 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2526 if (cptr) {
2527 memcpy(&hdw->std_info_avail,cptr->info,
2528 sizeof(hdw->std_info_avail));
2529 cptr->info = &hdw->std_info_avail;
2530 hdw->std_info_avail.def.type_bitmask.bit_names =
2531 hdw->std_mask_ptrs;
2532 hdw->std_info_avail.def.type_bitmask.valid_bits =
2533 valid_std_mask;
2534 }
2535 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2536 if (cptr) {
2537 memcpy(&hdw->std_info_cur,cptr->info,
2538 sizeof(hdw->std_info_cur));
2539 cptr->info = &hdw->std_info_cur;
2540 hdw->std_info_cur.def.type_bitmask.bit_names =
2541 hdw->std_mask_ptrs;
2542 hdw->std_info_avail.def.type_bitmask.valid_bits =
2543 valid_std_mask;
2544 }
2545
432907f7 2546 hdw->cropcap_stale = !0;
d855497e
MI		 2547 hdw->eeprom_addr = -1;
2548 hdw->unit_number = -1;
8079384e
MI		 2549 hdw->v4l_minor_number_video = -1;
2550 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 2551 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 2552 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2553 if (!hdw->ctl_write_buffer) goto fail;
2554 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2555 if (!hdw->ctl_read_buffer) goto fail;
2556 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2557 if (!hdw->ctl_write_urb) goto fail;
2558 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2559 if (!hdw->ctl_read_urb) goto fail;
2560
b72b7bf5
MI		 2561 if (v4l2_device_register(&usb_dev->dev, &hdw->v4l2_dev) != 0) {
2562 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2563 "Error registering with v4l core, giving up");
2564 goto fail;
2565 }
8df0c87c 2566 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2567 for (idx = 0; idx < PVR_NUM; idx++) {
2568 if (unit_pointers[idx]) continue;
2569 hdw->unit_number = idx;
2570 unit_pointers[idx] = hdw;
2571 break;
2572 }
8df0c87c 2573 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 2574
2575 cnt1 = 0;
2576 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2577 cnt1 += cnt2;
2578 if (hdw->unit_number >= 0) {
2579 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2580 ('a' + hdw->unit_number));
2581 cnt1 += cnt2;
2582 }
2583 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2584 hdw->name[cnt1] = 0;
2585
681c7399
MI		 2586 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2587 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2588 INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
681c7399 2589
d855497e
MI		 2590 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2591 hdw->unit_number,hdw->name);
2592
2593 hdw->tuner_type = -1;
2594 hdw->flag_ok = !0;
d855497e
MI		 2595
2596 hdw->usb_intf = intf;
b72b7bf5 2597 hdw->usb_dev = usb_dev;
d855497e 2598
87e3495c 2599 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
31a18547 2600
d855497e
MI		 2601 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2602 usb_set_interface(hdw->usb_dev,ifnum,0);
2603
2604 mutex_init(&hdw->ctl_lock_mutex);
2605 mutex_init(&hdw->big_lock_mutex);
2606
2607 return hdw;
2608 fail:
2609 if (hdw) {
681c7399 2610 del_timer_sync(&hdw->quiescent_timer);
d913d630 2611 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 2612 del_timer_sync(&hdw->encoder_wait_timer);
2613 if (hdw->workqueue) {
2614 flush_workqueue(hdw->workqueue);
2615 destroy_workqueue(hdw->workqueue);
2616 hdw->workqueue = NULL;
2617 }
5e55d2ce
MK		 2618 usb_free_urb(hdw->ctl_read_urb);
2619 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2620 kfree(hdw->ctl_read_buffer);
2621 kfree(hdw->ctl_write_buffer);
2622 kfree(hdw->controls);
2623 kfree(hdw->mpeg_ctrl_info);
681c7399
MI		 2624 kfree(hdw->std_defs);
2625 kfree(hdw->std_enum_names);
d855497e
MI		 2626 kfree(hdw);
2627 }
a0fd1cb1 2628 return NULL;
d855497e
MI		 2629}
2630
2631
2632/* Remove _all_ associations between this driver and the underlying USB
2633 layer. */
07e337ee 2634static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2635{
2636 if (hdw->flag_disconnected) return;
2637 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2638 if (hdw->ctl_read_urb) {
2639 usb_kill_urb(hdw->ctl_read_urb);
2640 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2641 hdw->ctl_read_urb = NULL;
d855497e
MI		 2642 }
2643 if (hdw->ctl_write_urb) {
2644 usb_kill_urb(hdw->ctl_write_urb);
2645 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2646 hdw->ctl_write_urb = NULL;
d855497e
MI		 2647 }
2648 if (hdw->ctl_read_buffer) {
2649 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2650 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2651 }
2652 if (hdw->ctl_write_buffer) {
2653 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2654 hdw->ctl_write_buffer = NULL;
d855497e 2655 }
d855497e 2656 hdw->flag_disconnected = !0;
b72b7bf5
MI		 2657 /* If we don't do this, then there will be a dangling struct device
2658 reference to our disappearing device persisting inside the V4L
2659 core... */
2660 if (hdw->v4l2_dev.dev) {
2661 dev_set_drvdata(hdw->v4l2_dev.dev, NULL);
2662 hdw->v4l2_dev.dev = NULL;
2663 }
a0fd1cb1
MI		 2664 hdw->usb_dev = NULL;
2665 hdw->usb_intf = NULL;
681c7399 2666 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2667}
2668
2669
2670/* Destroy hardware interaction structure */
2671void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2672{
401c27ce 2673 if (!hdw) return;
d855497e 2674 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2675 if (hdw->workqueue) {
2676 flush_workqueue(hdw->workqueue);
2677 destroy_workqueue(hdw->workqueue);
2678 hdw->workqueue = NULL;
2679 }
8f59100a 2680 del_timer_sync(&hdw->quiescent_timer);
d913d630 2681 del_timer_sync(&hdw->encoder_run_timer);
8f59100a 2682 del_timer_sync(&hdw->encoder_wait_timer);
d855497e
MI		 2683 if (hdw->fw_buffer) {
2684 kfree(hdw->fw_buffer);
a0fd1cb1 2685 hdw->fw_buffer = NULL;
d855497e
MI		 2686 }
2687 if (hdw->vid_stream) {
2688 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2689 hdw->vid_stream = NULL;
d855497e 2690 }
d855497e
MI		 2691 if (hdw->decoder_ctrl) {
2692 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2693 }
2694 pvr2_i2c_core_done(hdw);
59af3367 2695 pvr2_i2c_track_done(hdw);
b72b7bf5 2696 v4l2_device_unregister(&hdw->v4l2_dev);
d855497e 2697 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2698 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2699 if ((hdw->unit_number >= 0) &&
2700 (hdw->unit_number < PVR_NUM) &&
2701 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2702 unit_pointers[hdw->unit_number] = NULL;
d855497e 2703 }
8df0c87c 2704 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2705 kfree(hdw->controls);
2706 kfree(hdw->mpeg_ctrl_info);
2707 kfree(hdw->std_defs);
2708 kfree(hdw->std_enum_names);
d855497e
MI		 2709 kfree(hdw);
2710}
2711
2712
d855497e
MI		 2713int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2714{
2715 return (hdw && hdw->flag_ok);
2716}
2717
2718
2719/* Called when hardware has been unplugged */
2720void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2721{
2722 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2723 LOCK_TAKE(hdw->big_lock);
2724 LOCK_TAKE(hdw->ctl_lock);
2725 pvr2_hdw_remove_usb_stuff(hdw);
2726 LOCK_GIVE(hdw->ctl_lock);
2727 LOCK_GIVE(hdw->big_lock);
2728}
2729
2730
2731// Attempt to autoselect an appropriate value for std_enum_cur given
2732// whatever is currently in std_mask_cur
07e337ee 2733static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2734{
2735 unsigned int idx;
2736 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2737 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2738 hdw->std_enum_cur = idx;
2739 return;
2740 }
2741 }
2742 hdw->std_enum_cur = 0;
2743}
2744
2745
2746// Calculate correct set of enumerated standards based on currently known
2747// set of available standards bits.
07e337ee 2748static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2749{
2750 struct v4l2_standard *newstd;
2751 unsigned int std_cnt;
2752 unsigned int idx;
2753
2754 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2755
2756 if (hdw->std_defs) {
2757 kfree(hdw->std_defs);
a0fd1cb1 2758 hdw->std_defs = NULL;
d855497e
MI		 2759 }
2760 hdw->std_enum_cnt = 0;
2761 if (hdw->std_enum_names) {
2762 kfree(hdw->std_enum_names);
a0fd1cb1 2763 hdw->std_enum_names = NULL;
d855497e
MI		 2764 }
2765
2766 if (!std_cnt) {
2767 pvr2_trace(
2768 PVR2_TRACE_ERROR_LEGS,
2769 "WARNING: Failed to identify any viable standards");
2770 }
2771 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2772 hdw->std_enum_names[0] = "none";
2773 for (idx = 0; idx < std_cnt; idx++) {
2774 hdw->std_enum_names[idx+1] =
2775 newstd[idx].name;
2776 }
2777 // Set up the dynamic control for this standard
2778 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2779 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2780 hdw->std_defs = newstd;
2781 hdw->std_enum_cnt = std_cnt+1;
2782 hdw->std_enum_cur = 0;
2783 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2784}
2785
2786
2787int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2788 struct v4l2_standard *std,
2789 unsigned int idx)
2790{
2791 int ret = -EINVAL;
2792 if (!idx) return ret;
2793 LOCK_TAKE(hdw->big_lock); do {
2794 if (idx >= hdw->std_enum_cnt) break;
2795 idx--;
2796 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2797 ret = 0;
2798 } while (0); LOCK_GIVE(hdw->big_lock);
2799 return ret;
2800}
2801
2802
2803/* Get the number of defined controls */
2804unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2805{
c05c0462 2806 return hdw->control_cnt;
d855497e
MI		 2807}
2808
2809
2810/* Retrieve a control handle given its index (0..count-1) */
2811struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2812 unsigned int idx)
2813{
a0fd1cb1 2814 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2815 return hdw->controls + idx;
2816}
2817
2818
2819/* Retrieve a control handle given its index (0..count-1) */
2820struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2821 unsigned int ctl_id)
2822{
2823 struct pvr2_ctrl *cptr;
2824 unsigned int idx;
2825 int i;
2826
2827 /* This could be made a lot more efficient, but for now... */
c05c0462 2828 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2829 cptr = hdw->controls + idx;
2830 i = cptr->info->internal_id;
2831 if (i && (i == ctl_id)) return cptr;
2832 }
a0fd1cb1 2833 return NULL;
d855497e
MI		 2834}
2835
2836
a761f431 2837/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2838struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2839{
2840 struct pvr2_ctrl *cptr;
2841 unsigned int idx;
2842 int i;
2843
2844 /* This could be made a lot more efficient, but for now... */
c05c0462 2845 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2846 cptr = hdw->controls + idx;
2847 i = cptr->info->v4l_id;
2848 if (i && (i == ctl_id)) return cptr;
2849 }
a0fd1cb1 2850 return NULL;
d855497e
MI		 2851}
2852
2853
a761f431
MI		 2854/* Given a V4L ID for its immediate predecessor, retrieve the control
2855 structure associated with it. */
2856struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2857 unsigned int ctl_id)
2858{
2859 struct pvr2_ctrl *cptr,*cp2;
2860 unsigned int idx;
2861 int i;
2862
2863 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2864 cp2 = NULL;
a761f431
MI		 2865 for (idx = 0; idx < hdw->control_cnt; idx++) {
2866 cptr = hdw->controls + idx;
2867 i = cptr->info->v4l_id;
2868 if (!i) continue;
2869 if (i <= ctl_id) continue;
2870 if (cp2 && (cp2->info->v4l_id < i)) continue;
2871 cp2 = cptr;
2872 }
2873 return cp2;
a0fd1cb1 2874 return NULL;
a761f431
MI		 2875}
2876
2877
d855497e
MI		 2878static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2879{
2880 switch (tp) {
2881 case pvr2_ctl_int: return "integer";
2882 case pvr2_ctl_enum: return "enum";
33213963 2883 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2884 case pvr2_ctl_bitmask: return "bitmask";
2885 }
2886 return "";
2887}
2888
2889
2641df36
MI		 2890static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2891 const char *name, int val)
2892{
2893 struct v4l2_control ctrl;
2894 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2895 memset(&ctrl, 0, sizeof(ctrl));
2896 ctrl.id = id;
2897 ctrl.value = val;
2898 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2899}
2900
2901#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2902 if ((hdw)->lab##_dirty) { \
2903 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2904 }
2905
5ceaad14 2906/* Execute whatever commands are required to update the state of all the
2641df36 2907 sub-devices so that they match our current control values. */
5ceaad14
MI		 2908static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2909{
edb9dcb8
MI		 2910 struct v4l2_subdev *sd;
2911 unsigned int id;
2912 pvr2_subdev_update_func fp;
2913
2641df36
MI		 2914 if (hdw->input_dirty || hdw->std_dirty) {
2915 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_standard");
2916 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2917 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2918 tuner, s_radio);
2919 } else {
2920 v4l2_std_id vs;
2921 vs = hdw->std_mask_cur;
2922 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2923 tuner, s_std, vs);
2924 }
2925 hdw->tuner_signal_stale = !0;
2926 hdw->cropcap_stale = !0;
2927 }
2928
2929 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2930 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2931 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2932 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2933 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2934 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2935 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2936 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2937 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2938
2939 if (hdw->input_dirty || hdw->audiomode_dirty) {
2940 struct v4l2_tuner vt;
2941 memset(&vt, 0, sizeof(vt));
2942 vt.audmode = hdw->audiomode_val;
2943 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2944 }
2945
2946 if (hdw->freqDirty) {
2947 unsigned long fv;
2948 struct v4l2_frequency freq;
2949 fv = pvr2_hdw_get_cur_freq(hdw);
2950 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2951 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2952 memset(&freq, 0, sizeof(freq));
2953 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2954 /* ((fv * 1000) / 62500) */
2955 freq.frequency = (fv * 2) / 125;
2956 } else {
2957 freq.frequency = fv / 62500;
2958 }
2959 /* tuner-core currently doesn't seem to care about this, but
2960 let's set it anyway for completeness. */
2961 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2962 freq.type = V4L2_TUNER_RADIO;
2963 } else {
2964 freq.type = V4L2_TUNER_ANALOG_TV;
2965 }
2966 freq.tuner = 0;
2967 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2968 s_frequency, &freq);
2969 }
2970
2971 if (hdw->res_hor_dirty || hdw->res_ver_dirty) {
2972 struct v4l2_format fmt;
2973 memset(&fmt, 0, sizeof(fmt));
2974 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2975 fmt.fmt.pix.width = hdw->res_hor_val;
2976 fmt.fmt.pix.height = hdw->res_ver_val;
2977 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_size(%dx%d)",
2978 fmt.fmt.pix.width, fmt.fmt.pix.height);
2979 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
2980 }
2981
2982 /* Unable to set crop parameters; there is apparently no equivalent
2983 for VIDIOC_S_CROP */
2984
edb9dcb8
MI		 2985 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
2986 id = sd->grp_id;
2987 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
2988 fp = pvr2_module_update_functions[id];
2989 if (!fp) continue;
2990 (*fp)(hdw, sd);
2991 }
2641df36
MI		 2992
2993 if (hdw->tuner_signal_stale && hdw->cropcap_stale) {
2994 pvr2_hdw_status_poll(hdw);
2995 }
5ceaad14
MI		 2996}
2997
2998
681c7399
MI		 2999/* Figure out if we need to commit control changes. If so, mark internal
3000 state flags to indicate this fact and return true. Otherwise do nothing
3001 else and return false. */
3002static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 3003{
d855497e
MI		 3004 unsigned int idx;
3005 struct pvr2_ctrl *cptr;
3006 int value;
3007 int commit_flag = 0;
3008 char buf[100];
3009 unsigned int bcnt,ccnt;
3010
c05c0462 3011 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e 3012 cptr = hdw->controls + idx;
5fa1247a 3013 if (!cptr->info->is_dirty) continue;
d855497e 3014 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 3015 commit_flag = !0;
d855497e 3016
fe23a280 3017 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 3018 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3019 cptr->info->name);
3020 value = 0;
3021 cptr->info->get_value(cptr,&value);
3022 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3023 buf+bcnt,
3024 sizeof(buf)-bcnt,&ccnt);
3025 bcnt += ccnt;
3026 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3027 get_ctrl_typename(cptr->info->type));
3028 pvr2_trace(PVR2_TRACE_CTL,
3029 "/*--TRACE_COMMIT--*/ %.*s",
3030 bcnt,buf);
3031 }
3032
3033 if (!commit_flag) {
3034 /* Nothing has changed */
3035 return 0;
3036 }
3037
681c7399
MI		 3038 hdw->state_pipeline_config = 0;
3039 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3040 pvr2_hdw_state_sched(hdw);
3041
3042 return !0;
3043}
3044
3045
3046/* Perform all operations needed to commit all control changes. This must
3047 be performed in synchronization with the pipeline state and is thus
3048 expected to be called as part of the driver's worker thread. Return
3049 true if commit successful, otherwise return false to indicate that
3050 commit isn't possible at this time. */
3051static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3052{
3053 unsigned int idx;
3054 struct pvr2_ctrl *cptr;
3055 int disruptive_change;
3056
ab062fe3
MI		 3057 /* Handle some required side effects when the video standard is
3058 changed.... */
d855497e 3059 if (hdw->std_dirty) {
d855497e 3060 int nvres;
00528d9c 3061 int gop_size;
d855497e
MI		 3062 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3063 nvres = 480;
00528d9c 3064 gop_size = 15;
d855497e
MI		 3065 } else {
3066 nvres = 576;
00528d9c 3067 gop_size = 12;
d855497e 3068 }
00528d9c
MI		 3069 /* Rewrite the vertical resolution to be appropriate to the
3070 video standard that has been selected. */
d855497e
MI		 3071 if (nvres != hdw->res_ver_val) {
3072 hdw->res_ver_val = nvres;
3073 hdw->res_ver_dirty = !0;
3074 }
00528d9c
MI		 3075 /* Rewrite the GOP size to be appropriate to the video
3076 standard that has been selected. */
3077 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3078 struct v4l2_ext_controls cs;
3079 struct v4l2_ext_control c1;
3080 memset(&cs, 0, sizeof(cs));
3081 memset(&c1, 0, sizeof(c1));
3082 cs.controls = &c1;
3083 cs.count = 1;
3084 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3085 c1.value = gop_size;
3086 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3087 VIDIOC_S_EXT_CTRLS);
3088 }
d855497e
MI		 3089 }
3090
38d9a2cf 3091 if (hdw->input_dirty && hdw->state_pathway_ok &&
62433e31
MI		 3092 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3093 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3094 hdw->pathway_state)) {
3095 /* Change of mode being asked for... */
3096 hdw->state_pathway_ok = 0;
e9db1ff2 3097 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 3098 }
3099 if (!hdw->state_pathway_ok) {
3100 /* Can't commit anything until pathway is ok. */
3101 return 0;
3102 }
e784bfb9 3103 /* The broadcast decoder can only scale down, so if
3104 * res_*_dirty && crop window < output format ==> enlarge crop.
3105 *
3106 * The mpeg encoder receives fields of res_hor_val dots and
3107 * res_ver_val halflines. Limits: hor<=720, ver<=576.
3108 */
3109 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3110 hdw->cropw_val = hdw->res_hor_val;
3111 hdw->cropw_dirty = !0;
3112 } else if (hdw->cropw_dirty) {
3113 hdw->res_hor_dirty = !0; /* must rescale */
3114 hdw->res_hor_val = min(720, hdw->cropw_val);
3115 }
3116 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3117 hdw->croph_val = hdw->res_ver_val;
3118 hdw->croph_dirty = !0;
3119 } else if (hdw->croph_dirty) {
3120 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3121 hdw->res_ver_dirty = !0;
3122 hdw->res_ver_val = min(nvres, hdw->croph_val);
3123 }
3124
681c7399
MI		 3125 /* If any of the below has changed, then we can't do the update
3126 while the pipeline is running. Pipeline must be paused first
3127 and decoder -> encoder connection be made quiescent before we
3128 can proceed. */
3129 disruptive_change =
3130 (hdw->std_dirty ||
3131 hdw->enc_unsafe_stale ||
3132 hdw->srate_dirty ||
3133 hdw->res_ver_dirty ||
3134 hdw->res_hor_dirty ||
755879c6
MI		 3135 hdw->cropw_dirty ||
3136 hdw->croph_dirty ||
681c7399
MI		 3137 hdw->input_dirty ||
3138 (hdw->active_stream_type != hdw->desired_stream_type));
3139 if (disruptive_change && !hdw->state_pipeline_idle) {
3140 /* Pipeline is not idle; we can't proceed. Arrange to
3141 cause pipeline to stop so that we can try this again
3142 later.... */
3143 hdw->state_pipeline_pause = !0;
3144 return 0;
275b2e28
PK		 3145 }
3146
b30d2441
MI		 3147 if (hdw->srate_dirty) {
3148 /* Write new sample rate into control structure since
3149 * the master copy is stale. We must track srate
3150 * separate from the mpeg control structure because
3151 * other logic also uses this value. */
3152 struct v4l2_ext_controls cs;
3153 struct v4l2_ext_control c1;
3154 memset(&cs,0,sizeof(cs));
3155 memset(&c1,0,sizeof(c1));
3156 cs.controls = &c1;
3157 cs.count = 1;
3158 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3159 c1.value = hdw->srate_val;
01f1e44f 3160 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 3161 }
c05c0462 3162
d855497e
MI		 3163 /* Scan i2c core at this point - before we clear all the dirty
3164 bits. Various parts of the i2c core will notice dirty bits as
3165 appropriate and arrange to broadcast or directly send updates to
3166 the client drivers in order to keep everything in sync */
3167 pvr2_i2c_core_check_stale(hdw);
3168
681c7399
MI		 3169 if (hdw->active_stream_type != hdw->desired_stream_type) {
3170 /* Handle any side effects of stream config here */
3171 hdw->active_stream_type = hdw->desired_stream_type;
3172 }
3173
1df59f0b
MI		 3174 if (hdw->hdw_desc->signal_routing_scheme ==
3175 PVR2_ROUTING_SCHEME_GOTVIEW) {
3176 u32 b;
3177 /* Handle GOTVIEW audio switching */
3178 pvr2_hdw_gpio_get_out(hdw,&b);
3179 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3180 /* Set GPIO 11 */
3181 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3182 } else {
3183 /* Clear GPIO 11 */
3184 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3185 }
3186 }
3187
5ceaad14
MI		 3188 for (idx = 0; idx < hdw->control_cnt; idx++) {
3189 cptr = hdw->controls + idx;
3190 if (!cptr->info->clear_dirty) continue;
3191 cptr->info->clear_dirty(cptr);
3192 }
3193
3194 /* Check and update state for all sub-devices. */
3195 pvr2_subdev_update(hdw);
3196
d855497e
MI		 3197 /* Now execute i2c core update */
3198 pvr2_i2c_core_sync(hdw);
3199
62433e31
MI		 3200 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3201 hdw->state_encoder_run) {
3202 /* If encoder isn't running or it can't be touched, then
3203 this will get worked out later when we start the
3204 encoder. */
681c7399
MI		 3205 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3206 }
d855497e 3207
681c7399 3208 hdw->state_pipeline_config = !0;
432907f7
MI		 3209 /* Hardware state may have changed in a way to cause the cropping
3210 capabilities to have changed. So mark it stale, which will
3211 cause a later re-fetch. */
681c7399
MI		 3212 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3213 return !0;
d855497e
MI		 3214}
3215
3216
3217int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3218{
681c7399
MI		 3219 int fl;
3220 LOCK_TAKE(hdw->big_lock);
3221 fl = pvr2_hdw_commit_setup(hdw);
3222 LOCK_GIVE(hdw->big_lock);
3223 if (!fl) return 0;
3224 return pvr2_hdw_wait(hdw,0);
3225}
3226
3227
3228static void pvr2_hdw_worker_i2c(struct work_struct *work)
3229{
3230 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
d855497e 3231 LOCK_TAKE(hdw->big_lock); do {
681c7399 3232 pvr2_i2c_core_sync(hdw);
d855497e 3233 } while (0); LOCK_GIVE(hdw->big_lock);
d855497e
MI		 3234}
3235
3236
681c7399 3237static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 3238{
681c7399
MI		 3239 int fl = 0;
3240 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 3241 LOCK_TAKE(hdw->big_lock); do {
681c7399 3242 fl = pvr2_hdw_state_eval(hdw);
d855497e 3243 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 3244 if (fl && hdw->state_func) {
3245 hdw->state_func(hdw->state_data);
3246 }
d855497e
MI		 3247}
3248
3249
681c7399 3250static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 3251{
681c7399
MI		 3252 return wait_event_interruptible(
3253 hdw->state_wait_data,
3254 (hdw->state_stale == 0) &&
3255 (!state || (hdw->master_state != state)));
3256}
3257
3258
d855497e
MI		 3259/* Return name for this driver instance */
3260const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3261{
3262 return hdw->name;
3263}
3264
3265
78a47101
MI		 3266const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3267{
3268 return hdw->hdw_desc->description;
3269}
3270
3271
3272const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3273{
3274 return hdw->hdw_desc->shortname;
3275}
3276
3277
d855497e
MI		 3278int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3279{
3280 int result;
3281 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3282 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 3283 result = pvr2_send_request(hdw,
3284 hdw->cmd_buffer,1,
3285 hdw->cmd_buffer,1);
3286 if (result < 0) break;
3287 result = (hdw->cmd_buffer[0] != 0);
3288 } while(0); LOCK_GIVE(hdw->ctl_lock);
3289 return result;
3290}
3291
3292
18103c57
MI		 3293/* Execute poll of tuner status */
3294void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 3295{
d855497e 3296 LOCK_TAKE(hdw->big_lock); do {
a51f5000 3297 pvr2_hdw_status_poll(hdw);
d855497e 3298 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 3299}
3300
3301
432907f7
MI		 3302static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3303{
3304 if (!hdw->cropcap_stale) {
432907f7
MI		 3305 return 0;
3306 }
a51f5000 3307 pvr2_hdw_status_poll(hdw);
432907f7 3308 if (hdw->cropcap_stale) {
432907f7
MI		 3309 return -EIO;
3310 }
3311 return 0;
3312}
3313
3314
3315/* Return information about cropping capabilities */
3316int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3317{
3318 int stat = 0;
3319 LOCK_TAKE(hdw->big_lock);
3320 stat = pvr2_hdw_check_cropcap(hdw);
3321 if (!stat) {
432907f7
MI		 3322 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3323 }
3324 LOCK_GIVE(hdw->big_lock);
3325 return stat;
3326}
3327
3328
18103c57
MI		 3329/* Return information about the tuner */
3330int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3331{
3332 LOCK_TAKE(hdw->big_lock); do {
3333 if (hdw->tuner_signal_stale) {
a51f5000 3334 pvr2_hdw_status_poll(hdw);
18103c57
MI		 3335 }
3336 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3337 } while (0); LOCK_GIVE(hdw->big_lock);
3338 return 0;
d855497e
MI		 3339}
3340
3341
3342/* Get handle to video output stream */
3343struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3344{
3345 return hp->vid_stream;
3346}
3347
3348
3349void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3350{
4f1a3e5b 3351 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e 3352 LOCK_TAKE(hdw->big_lock); do {
4f1a3e5b 3353 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
5ceaad14 3354 hdw->log_requested = !0;
d855497e 3355 pvr2_i2c_core_check_stale(hdw);
d855497e 3356 pvr2_i2c_core_sync(hdw);
a51f5000 3357 hdw->log_requested = 0;
ed3261a8 3358 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
b30d2441 3359 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 3360 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 3361 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 3362 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 3363 } while (0); LOCK_GIVE(hdw->big_lock);
3364}
3365
4db666cc
MI		 3366
3367/* Grab EEPROM contents, needed for direct method. */
3368#define EEPROM_SIZE 8192
3369#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3370static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3371{
3372 struct i2c_msg msg[2];
3373 u8 *eeprom;
3374 u8 iadd[2];
3375 u8 addr;
3376 u16 eepromSize;
3377 unsigned int offs;
3378 int ret;
3379 int mode16 = 0;
3380 unsigned pcnt,tcnt;
3381 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3382 if (!eeprom) {
3383 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3384 "Failed to allocate memory"
3385 " required to read eeprom");
3386 return NULL;
3387 }
3388
3389 trace_eeprom("Value for eeprom addr from controller was 0x%x",
3390 hdw->eeprom_addr);
3391 addr = hdw->eeprom_addr;
3392 /* Seems that if the high bit is set, then the *real* eeprom
3393 address is shifted right now bit position (noticed this in
3394 newer PVR USB2 hardware) */
3395 if (addr & 0x80) addr >>= 1;
3396
3397 /* FX2 documentation states that a 16bit-addressed eeprom is
3398 expected if the I2C address is an odd number (yeah, this is
3399 strange but it's what they do) */
3400 mode16 = (addr & 1);
3401 eepromSize = (mode16 ? EEPROM_SIZE : 256);
3402 trace_eeprom("Examining %d byte eeprom at location 0x%x"
3403 " using %d bit addressing",eepromSize,addr,
3404 mode16 ? 16 : 8);
3405
3406 msg[0].addr = addr;
3407 msg[0].flags = 0;
3408 msg[0].len = mode16 ? 2 : 1;
3409 msg[0].buf = iadd;
3410 msg[1].addr = addr;
3411 msg[1].flags = I2C_M_RD;
3412
3413 /* We have to do the actual eeprom data fetch ourselves, because
3414 (1) we're only fetching part of the eeprom, and (2) if we were
3415 getting the whole thing our I2C driver can't grab it in one
3416 pass - which is what tveeprom is otherwise going to attempt */
3417 memset(eeprom,0,EEPROM_SIZE);
3418 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3419 pcnt = 16;
3420 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3421 offs = tcnt + (eepromSize - EEPROM_SIZE);
3422 if (mode16) {
3423 iadd[0] = offs >> 8;
3424 iadd[1] = offs;
3425 } else {
3426 iadd[0] = offs;
3427 }
3428 msg[1].len = pcnt;
3429 msg[1].buf = eeprom+tcnt;
3430 if ((ret = i2c_transfer(&hdw->i2c_adap,
3431 msg,ARRAY_SIZE(msg))) != 2) {
3432 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3433 "eeprom fetch set offs err=%d",ret);
3434 kfree(eeprom);
3435 return NULL;
3436 }
3437 }
3438 return eeprom;
3439}
3440
3441
3442void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3443 int prom_flag,
3444 int enable_flag)
d855497e
MI		 3445{
3446 int ret;
3447 u16 address;
3448 unsigned int pipe;
3449 LOCK_TAKE(hdw->big_lock); do {
5fa1247a 3450 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
d855497e
MI		 3451
3452 if (!enable_flag) {
3453 pvr2_trace(PVR2_TRACE_FIRMWARE,
3454 "Cleaning up after CPU firmware fetch");
3455 kfree(hdw->fw_buffer);
a0fd1cb1 3456 hdw->fw_buffer = NULL;
d855497e 3457 hdw->fw_size = 0;
4db666cc
MI		 3458 if (hdw->fw_cpu_flag) {
3459 /* Now release the CPU. It will disconnect
3460 and reconnect later. */
3461 pvr2_hdw_cpureset_assert(hdw,0);
3462 }
d855497e
MI		 3463 break;
3464 }
3465
4db666cc
MI		 3466 hdw->fw_cpu_flag = (prom_flag == 0);
3467 if (hdw->fw_cpu_flag) {
3468 pvr2_trace(PVR2_TRACE_FIRMWARE,
3469 "Preparing to suck out CPU firmware");
3470 hdw->fw_size = 0x2000;
3471 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3472 if (!hdw->fw_buffer) {
3473 hdw->fw_size = 0;
3474 break;
3475 }
d855497e 3476
4db666cc
MI		 3477 /* We have to hold the CPU during firmware upload. */
3478 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 3479
4db666cc
MI		 3480 /* download the firmware from address 0000-1fff in 2048
3481 (=0x800) bytes chunk. */
d855497e 3482
4db666cc
MI		 3483 pvr2_trace(PVR2_TRACE_FIRMWARE,
3484 "Grabbing CPU firmware");
3485 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3486 for(address = 0; address < hdw->fw_size;
3487 address += 0x800) {
3488 ret = usb_control_msg(hdw->usb_dev,pipe,
3489 0xa0,0xc0,
3490 address,0,
3491 hdw->fw_buffer+address,
3492 0x800,HZ);
3493 if (ret < 0) break;
3494 }
d855497e 3495
4db666cc
MI		 3496 pvr2_trace(PVR2_TRACE_FIRMWARE,
3497 "Done grabbing CPU firmware");
3498 } else {
3499 pvr2_trace(PVR2_TRACE_FIRMWARE,
3500 "Sucking down EEPROM contents");
3501 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3502 if (!hdw->fw_buffer) {
3503 pvr2_trace(PVR2_TRACE_FIRMWARE,
3504 "EEPROM content suck failed.");
3505 break;
3506 }
3507 hdw->fw_size = EEPROM_SIZE;
3508 pvr2_trace(PVR2_TRACE_FIRMWARE,
3509 "Done sucking down EEPROM contents");
3510 }
d855497e
MI		 3511
3512 } while (0); LOCK_GIVE(hdw->big_lock);
3513}
3514
3515
3516/* Return true if we're in a mode for retrieval CPU firmware */
3517int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3518{
5fa1247a 3519 return hdw->fw_buffer != NULL;
d855497e
MI		 3520}
3521
3522
3523int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3524 char *buf,unsigned int cnt)
3525{
3526 int ret = -EINVAL;
3527 LOCK_TAKE(hdw->big_lock); do {
3528 if (!buf) break;
3529 if (!cnt) break;
3530
3531 if (!hdw->fw_buffer) {
3532 ret = -EIO;
3533 break;
3534 }
3535
3536 if (offs >= hdw->fw_size) {
3537 pvr2_trace(PVR2_TRACE_FIRMWARE,
3538 "Read firmware data offs=%d EOF",
3539 offs);
3540 ret = 0;
3541 break;
3542 }
3543
3544 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3545
3546 memcpy(buf,hdw->fw_buffer+offs,cnt);
3547
3548 pvr2_trace(PVR2_TRACE_FIRMWARE,
3549 "Read firmware data offs=%d cnt=%d",
3550 offs,cnt);
3551 ret = cnt;
3552 } while (0); LOCK_GIVE(hdw->big_lock);
3553
3554 return ret;
3555}
3556
3557
fd5a75fe 3558int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 3559 enum pvr2_v4l_type index)
d855497e 3560{
fd5a75fe 3561 switch (index) {
8079384e
MI		 3562 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3563 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3564 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 3565 default: return -1;
3566 }
d855497e
MI		 3567}
3568
3569
2fdf3d9c 3570/* Store a v4l minor device number */
fd5a75fe 3571void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 3572 enum pvr2_v4l_type index,int v)
d855497e 3573{
fd5a75fe 3574 switch (index) {
8079384e
MI		 3575 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3576 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3577 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 3578 default: break;
3579 }
d855497e
MI		 3580}
3581
3582
7d12e780 3583static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 3584{
3585 struct pvr2_hdw *hdw = urb->context;
3586 hdw->ctl_write_pend_flag = 0;
3587 if (hdw->ctl_read_pend_flag) return;
3588 complete(&hdw->ctl_done);
3589}
3590
3591
7d12e780 3592static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 3593{
3594 struct pvr2_hdw *hdw = urb->context;
3595 hdw->ctl_read_pend_flag = 0;
3596 if (hdw->ctl_write_pend_flag) return;
3597 complete(&hdw->ctl_done);
3598}
3599
3600
3601static void pvr2_ctl_timeout(unsigned long data)
3602{
3603 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3604 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3605 hdw->ctl_timeout_flag = !0;
5e55d2ce 3606 if (hdw->ctl_write_pend_flag)
d855497e 3607 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 3608 if (hdw->ctl_read_pend_flag)
d855497e 3609 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 3610 }
3611}
3612
3613
e61b6fc5
MI		 3614/* Issue a command and get a response from the device. This extended
3615 version includes a probe flag (which if set means that device errors
3616 should not be logged or treated as fatal) and a timeout in jiffies.
3617 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 3618static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3619 unsigned int timeout,int probe_fl,
3620 void *write_data,unsigned int write_len,
3621 void *read_data,unsigned int read_len)
d855497e
MI		 3622{
3623 unsigned int idx;
3624 int status = 0;
3625 struct timer_list timer;
3626 if (!hdw->ctl_lock_held) {
3627 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3628 "Attempted to execute control transfer"
3629 " without lock!!");
3630 return -EDEADLK;
3631 }
681c7399 3632 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 3633 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3634 "Attempted to execute control transfer"
3635 " when device not ok");
3636 return -EIO;
3637 }
3638 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3639 if (!probe_fl) {
3640 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3641 "Attempted to execute control transfer"
3642 " when USB is disconnected");
3643 }
3644 return -ENOTTY;
3645 }
3646
3647 /* Ensure that we have sane parameters */
3648 if (!write_data) write_len = 0;
3649 if (!read_data) read_len = 0;
3650 if (write_len > PVR2_CTL_BUFFSIZE) {
3651 pvr2_trace(
3652 PVR2_TRACE_ERROR_LEGS,
3653 "Attempted to execute %d byte"
3654 " control-write transfer (limit=%d)",
3655 write_len,PVR2_CTL_BUFFSIZE);
3656 return -EINVAL;
3657 }
3658 if (read_len > PVR2_CTL_BUFFSIZE) {
3659 pvr2_trace(
3660 PVR2_TRACE_ERROR_LEGS,
3661 "Attempted to execute %d byte"
3662 " control-read transfer (limit=%d)",
3663 write_len,PVR2_CTL_BUFFSIZE);
3664 return -EINVAL;
3665 }
3666 if ((!write_len) && (!read_len)) {
3667 pvr2_trace(
3668 PVR2_TRACE_ERROR_LEGS,
3669 "Attempted to execute null control transfer?");
3670 return -EINVAL;
3671 }
3672
3673
3674 hdw->cmd_debug_state = 1;
3675 if (write_len) {
3676 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3677 } else {
3678 hdw->cmd_debug_code = 0;
3679 }
3680 hdw->cmd_debug_write_len = write_len;
3681 hdw->cmd_debug_read_len = read_len;
3682
3683 /* Initialize common stuff */
3684 init_completion(&hdw->ctl_done);
3685 hdw->ctl_timeout_flag = 0;
3686 hdw->ctl_write_pend_flag = 0;
3687 hdw->ctl_read_pend_flag = 0;
3688 init_timer(&timer);
3689 timer.expires = jiffies + timeout;
3690 timer.data = (unsigned long)hdw;
3691 timer.function = pvr2_ctl_timeout;
3692
3693 if (write_len) {
3694 hdw->cmd_debug_state = 2;
3695 /* Transfer write data to internal buffer */
3696 for (idx = 0; idx < write_len; idx++) {
3697 hdw->ctl_write_buffer[idx] =
3698 ((unsigned char *)write_data)[idx];
3699 }
3700 /* Initiate a write request */
3701 usb_fill_bulk_urb(hdw->ctl_write_urb,
3702 hdw->usb_dev,
3703 usb_sndbulkpipe(hdw->usb_dev,
3704 PVR2_CTL_WRITE_ENDPOINT),
3705 hdw->ctl_write_buffer,
3706 write_len,
3707 pvr2_ctl_write_complete,
3708 hdw);
3709 hdw->ctl_write_urb->actual_length = 0;
3710 hdw->ctl_write_pend_flag = !0;
3711 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3712 if (status < 0) {
3713 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3714 "Failed to submit write-control"
3715 " URB status=%d",status);
3716 hdw->ctl_write_pend_flag = 0;
3717 goto done;
3718 }
3719 }
3720
3721 if (read_len) {
3722 hdw->cmd_debug_state = 3;
3723 memset(hdw->ctl_read_buffer,0x43,read_len);
3724 /* Initiate a read request */
3725 usb_fill_bulk_urb(hdw->ctl_read_urb,
3726 hdw->usb_dev,
3727 usb_rcvbulkpipe(hdw->usb_dev,
3728 PVR2_CTL_READ_ENDPOINT),
3729 hdw->ctl_read_buffer,
3730 read_len,
3731 pvr2_ctl_read_complete,
3732 hdw);
3733 hdw->ctl_read_urb->actual_length = 0;
3734 hdw->ctl_read_pend_flag = !0;
3735 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3736 if (status < 0) {
3737 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3738 "Failed to submit read-control"
3739 " URB status=%d",status);
3740 hdw->ctl_read_pend_flag = 0;
3741 goto done;
3742 }
3743 }
3744
3745 /* Start timer */
3746 add_timer(&timer);
3747
3748 /* Now wait for all I/O to complete */
3749 hdw->cmd_debug_state = 4;
3750 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3751 wait_for_completion(&hdw->ctl_done);
3752 }
3753 hdw->cmd_debug_state = 5;
3754
3755 /* Stop timer */
3756 del_timer_sync(&timer);
3757
3758 hdw->cmd_debug_state = 6;
3759 status = 0;
3760
3761 if (hdw->ctl_timeout_flag) {
3762 status = -ETIMEDOUT;
3763 if (!probe_fl) {
3764 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3765 "Timed out control-write");
3766 }
3767 goto done;
3768 }
3769
3770 if (write_len) {
3771 /* Validate results of write request */
3772 if ((hdw->ctl_write_urb->status != 0) &&
3773 (hdw->ctl_write_urb->status != -ENOENT) &&
3774 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3775 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3776 /* USB subsystem is reporting some kind of failure
3777 on the write */
3778 status = hdw->ctl_write_urb->status;
3779 if (!probe_fl) {
3780 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3781 "control-write URB failure,"
3782 " status=%d",
3783 status);
3784 }
3785 goto done;
3786 }
3787 if (hdw->ctl_write_urb->actual_length < write_len) {
3788 /* Failed to write enough data */
3789 status = -EIO;
3790 if (!probe_fl) {
3791 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3792 "control-write URB short,"
3793 " expected=%d got=%d",
3794 write_len,
3795 hdw->ctl_write_urb->actual_length);
3796 }
3797 goto done;
3798 }
3799 }
3800 if (read_len) {
3801 /* Validate results of read request */
3802 if ((hdw->ctl_read_urb->status != 0) &&
3803 (hdw->ctl_read_urb->status != -ENOENT) &&
3804 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3805 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3806 /* USB subsystem is reporting some kind of failure
3807 on the read */
3808 status = hdw->ctl_read_urb->status;
3809 if (!probe_fl) {
3810 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3811 "control-read URB failure,"
3812 " status=%d",
3813 status);
3814 }
3815 goto done;
3816 }
3817 if (hdw->ctl_read_urb->actual_length < read_len) {
3818 /* Failed to read enough data */
3819 status = -EIO;
3820 if (!probe_fl) {
3821 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3822 "control-read URB short,"
3823 " expected=%d got=%d",
3824 read_len,
3825 hdw->ctl_read_urb->actual_length);
3826 }
3827 goto done;
3828 }
3829 /* Transfer retrieved data out from internal buffer */
3830 for (idx = 0; idx < read_len; idx++) {
3831 ((unsigned char *)read_data)[idx] =
3832 hdw->ctl_read_buffer[idx];
3833 }
3834 }
3835
3836 done:
3837
3838 hdw->cmd_debug_state = 0;
3839 if ((status < 0) && (!probe_fl)) {
681c7399 3840 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3841 }
3842 return status;
3843}
3844
3845
3846int pvr2_send_request(struct pvr2_hdw *hdw,
3847 void *write_data,unsigned int write_len,
3848 void *read_data,unsigned int read_len)
3849{
3850 return pvr2_send_request_ex(hdw,HZ*4,0,
3851 write_data,write_len,
3852 read_data,read_len);
3853}
3854
1c9d10d4
MI		 3855
3856static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3857{
3858 int ret;
3859 unsigned int cnt = 1;
3860 unsigned int args = 0;
3861 LOCK_TAKE(hdw->ctl_lock);
3862 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3863 args = (cmdcode >> 8) & 0xffu;
3864 args = (args > 2) ? 2 : args;
3865 if (args) {
3866 cnt += args;
3867 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3868 if (args > 1) {
3869 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3870 }
3871 }
3872 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3873 unsigned int idx;
3874 unsigned int ccnt,bcnt;
3875 char tbuf[50];
3876 cmdcode &= 0xffu;
3877 bcnt = 0;
3878 ccnt = scnprintf(tbuf+bcnt,
3879 sizeof(tbuf)-bcnt,
3880 "Sending FX2 command 0x%x",cmdcode);
3881 bcnt += ccnt;
3882 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3883 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3884 ccnt = scnprintf(tbuf+bcnt,
3885 sizeof(tbuf)-bcnt,
3886 " \"%s\"",
3887 pvr2_fx2cmd_desc[idx].desc);
3888 bcnt += ccnt;
3889 break;
3890 }
3891 }
3892 if (args) {
3893 ccnt = scnprintf(tbuf+bcnt,
3894 sizeof(tbuf)-bcnt,
3895 " (%u",hdw->cmd_buffer[1]);
3896 bcnt += ccnt;
3897 if (args > 1) {
3898 ccnt = scnprintf(tbuf+bcnt,
3899 sizeof(tbuf)-bcnt,
3900 ",%u",hdw->cmd_buffer[2]);
3901 bcnt += ccnt;
3902 }
3903 ccnt = scnprintf(tbuf+bcnt,
3904 sizeof(tbuf)-bcnt,
3905 ")");
3906 bcnt += ccnt;
3907 }
3908 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3909 }
3910 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3911 LOCK_GIVE(hdw->ctl_lock);
3912 return ret;
3913}
3914
3915
d855497e
MI		 3916int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3917{
3918 int ret;
3919
3920 LOCK_TAKE(hdw->ctl_lock);
3921
8d364363 3922 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 3923 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3924 hdw->cmd_buffer[5] = 0;
3925 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3926 hdw->cmd_buffer[7] = reg & 0xff;
3927
3928
3929 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3930
3931 LOCK_GIVE(hdw->ctl_lock);
3932
3933 return ret;
3934}
3935
3936
07e337ee 3937static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 3938{
3939 int ret = 0;
3940
3941 LOCK_TAKE(hdw->ctl_lock);
3942
8d364363 3943 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 3944 hdw->cmd_buffer[1] = 0;
3945 hdw->cmd_buffer[2] = 0;
3946 hdw->cmd_buffer[3] = 0;
3947 hdw->cmd_buffer[4] = 0;
3948 hdw->cmd_buffer[5] = 0;
3949 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3950 hdw->cmd_buffer[7] = reg & 0xff;
3951
3952 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3953 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3954
3955 LOCK_GIVE(hdw->ctl_lock);
3956
3957 return ret;
3958}
3959
3960
681c7399 3961void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 3962{
3963 if (!hdw->flag_ok) return;
681c7399
MI		 3964 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3965 "Device being rendered inoperable");
d855497e 3966 if (hdw->vid_stream) {
a0fd1cb1 3967 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 3968 }
681c7399
MI		 3969 hdw->flag_ok = 0;
3970 trace_stbit("flag_ok",hdw->flag_ok);
3971 pvr2_hdw_state_sched(hdw);
d855497e
MI		 3972}
3973
3974
3975void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3976{
3977 int ret;
3978 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 3979 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
011b15df 3980 if (ret == 0) {
d855497e
MI		 3981 ret = usb_reset_device(hdw->usb_dev);
3982 usb_unlock_device(hdw->usb_dev);
3983 } else {
3984 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3985 "Failed to lock USB device ret=%d",ret);
3986 }
3987 if (init_pause_msec) {
3988 pvr2_trace(PVR2_TRACE_INFO,
3989 "Waiting %u msec for hardware to settle",
3990 init_pause_msec);
3991 msleep(init_pause_msec);
3992 }
3993
3994}
3995
3996
3997void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3998{
3999 char da[1];
4000 unsigned int pipe;
4001 int ret;
4002
4003 if (!hdw->usb_dev) return;
4004
4005 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4006
4007 da[0] = val ? 0x01 : 0x00;
4008
4009 /* Write the CPUCS register on the 8051. The lsb of the register
4010 is the reset bit; a 1 asserts reset while a 0 clears it. */
4011 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4012 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4013 if (ret < 0) {
4014 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4015 "cpureset_assert(%d) error=%d",val,ret);
4016 pvr2_hdw_render_useless(hdw);
4017 }
4018}
4019
4020
4021int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4022{
1c9d10d4 4023 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
d855497e
MI		 4024}
4025
4026
e1edb19a
MK		 4027int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4028{
1c9d10d4 4029 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
e1edb19a
MK		 4030}
4031
1c9d10d4 4032
e1edb19a
MK		 4033int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4034{
1c9d10d4 4035 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
e1edb19a
MK		 4036}
4037
d855497e
MI		 4038
4039int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4040{
af78e16b
MI		 4041 pvr2_trace(PVR2_TRACE_INIT,
4042 "Requesting decoder reset");
4043 if (hdw->decoder_ctrl) {
4044 if (!hdw->decoder_ctrl->force_reset) {
4045 pvr2_trace(PVR2_TRACE_INIT,
4046 "Unable to reset decoder: not implemented");
4047 return -ENOTTY;
4048 }
4049 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
4050 return 0;
4051 } else {
d855497e 4052 }
af78e16b
MI		 4053 if (hdw->decoder_client_id) {
4054 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4055 core, reset, 0);
4056 return 0;
d855497e 4057 }
d855497e 4058 pvr2_trace(PVR2_TRACE_INIT,
af78e16b
MI		 4059 "Unable to reset decoder: nothing attached");
4060 return -ENOTTY;
d855497e
MI		 4061}
4062
4063
62433e31 4064static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
84147f3d 4065{
1c9d10d4
MI		 4066 hdw->flag_ok = !0;
4067 return pvr2_issue_simple_cmd(hdw,
4068 FX2CMD_HCW_DEMOD_RESETIN |
4069 (1 << 8) |
4070 ((onoff ? 1 : 0) << 16));
84147f3d
MI		 4071}
4072
84147f3d 4073
62433e31 4074static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
84147f3d 4075{
1c9d10d4
MI		 4076 hdw->flag_ok = !0;
4077 return pvr2_issue_simple_cmd(hdw,(onoff ?
4078 FX2CMD_ONAIR_DTV_POWER_ON :
4079 FX2CMD_ONAIR_DTV_POWER_OFF));
84147f3d
MI		 4080}
4081
62433e31
MI		 4082
4083static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4084 int onoff)
84147f3d 4085{
1c9d10d4
MI		 4086 return pvr2_issue_simple_cmd(hdw,(onoff ?
4087 FX2CMD_ONAIR_DTV_STREAMING_ON :
4088 FX2CMD_ONAIR_DTV_STREAMING_OFF));
84147f3d
MI		 4089}
4090
62433e31
MI		 4091
4092static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4093{
4094 int cmode;
4095 /* Compare digital/analog desired setting with current setting. If
4096 they don't match, fix it... */
4097 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4098 if (cmode == hdw->pathway_state) {
4099 /* They match; nothing to do */
4100 return;
4101 }
4102
4103 switch (hdw->hdw_desc->digital_control_scheme) {
4104 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4105 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4106 if (cmode == PVR2_PATHWAY_ANALOG) {
4107 /* If moving to analog mode, also force the decoder
4108 to reset. If no decoder is attached, then it's
4109 ok to ignore this because if/when the decoder
4110 attaches, it will reset itself at that time. */
4111 pvr2_hdw_cmd_decoder_reset(hdw);
4112 }
4113 break;
4114 case PVR2_DIGITAL_SCHEME_ONAIR:
4115 /* Supposedly we should always have the power on whether in
4116 digital or analog mode. But for now do what appears to
4117 work... */
bb0c2fe0 4118 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
62433e31
MI		 4119 break;
4120 default: break;
4121 }
4122
1b9c18c5 4123 pvr2_hdw_untrip_unlocked(hdw);
62433e31
MI		 4124 hdw->pathway_state = cmode;
4125}
4126
4127
e9b59f6e 4128static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
c55a97d7
MI		 4129{
4130 /* change some GPIO data
4131 *
4132 * note: bit d7 of dir appears to control the LED,
4133 * so we shut it off here.
4134 *
c55a97d7 4135 */
40381cb0 4136 if (onoff) {
c55a97d7 4137 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
40381cb0 4138 } else {
c55a97d7 4139 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
40381cb0 4140 }
c55a97d7 4141 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
40381cb0 4142}
c55a97d7 4143
40381cb0
MI		 4144
4145typedef void (*led_method_func)(struct pvr2_hdw *,int);
4146
4147static led_method_func led_methods[] = {
4148 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4149};
4150
4151
4152/* Toggle LED */
4153static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4154{
4155 unsigned int scheme_id;
4156 led_method_func fp;
4157
4158 if ((!onoff) == (!hdw->led_on)) return;
4159
4160 hdw->led_on = onoff != 0;
4161
4162 scheme_id = hdw->hdw_desc->led_scheme;
4163 if (scheme_id < ARRAY_SIZE(led_methods)) {
4164 fp = led_methods[scheme_id];
4165 } else {
4166 fp = NULL;
4167 }
4168
4169 if (fp) (*fp)(hdw,onoff);
c55a97d7
MI		 4170}
4171
4172
e61b6fc5 4173/* Stop / start video stream transport */
07e337ee 4174static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e 4175{
bb0c2fe0
MI		 4176 int ret;
4177
4178 /* If we're in analog mode, then just issue the usual analog
4179 command. */
4180 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4181 return pvr2_issue_simple_cmd(hdw,
4182 (runFl ?
4183 FX2CMD_STREAMING_ON :
4184 FX2CMD_STREAMING_OFF));
4185 /*Note: Not reached */
4186 }
4187
4188 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4189 /* Whoops, we don't know what mode we're in... */
4190 return -EINVAL;
4191 }
4192
4193 /* To get here we have to be in digital mode. The mechanism here
4194 is unfortunately different for different vendors. So we switch
4195 on the device's digital scheme attribute in order to figure out
4196 what to do. */
4197 switch (hdw->hdw_desc->digital_control_scheme) {
4198 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4199 return pvr2_issue_simple_cmd(hdw,
4200 (runFl ?
4201 FX2CMD_HCW_DTV_STREAMING_ON :
4202 FX2CMD_HCW_DTV_STREAMING_OFF));
4203 case PVR2_DIGITAL_SCHEME_ONAIR:
4204 ret = pvr2_issue_simple_cmd(hdw,
4205 (runFl ?
4206 FX2CMD_STREAMING_ON :
4207 FX2CMD_STREAMING_OFF));
4208 if (ret) return ret;
4209 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4210 default:
4211 return -EINVAL;
62433e31 4212 }
d855497e
MI		 4213}
4214
4215
62433e31
MI		 4216/* Evaluate whether or not state_pathway_ok can change */
4217static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4218{
4219 if (hdw->state_pathway_ok) {
4220 /* Nothing to do if pathway is already ok */
4221 return 0;
4222 }
4223 if (!hdw->state_pipeline_idle) {
4224 /* Not allowed to change anything if pipeline is not idle */
4225 return 0;
4226 }
4227 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4228 hdw->state_pathway_ok = !0;
e9db1ff2 4229 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 4230 return !0;
4231}
4232
4233
681c7399
MI		 4234/* Evaluate whether or not state_encoder_ok can change */
4235static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4236{
4237 if (hdw->state_encoder_ok) return 0;
4238 if (hdw->flag_tripped) return 0;
4239 if (hdw->state_encoder_run) return 0;
4240 if (hdw->state_encoder_config) return 0;
4241 if (hdw->state_decoder_run) return 0;
4242 if (hdw->state_usbstream_run) return 0;
72998b71
MI		 4243 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4244 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4245 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4246 return 0;
4247 }
4248
681c7399
MI		 4249 if (pvr2_upload_firmware2(hdw) < 0) {
4250 hdw->flag_tripped = !0;
4251 trace_stbit("flag_tripped",hdw->flag_tripped);
4252 return !0;
4253 }
4254 hdw->state_encoder_ok = !0;
4255 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4256 return !0;
4257}
4258
4259
4260/* Evaluate whether or not state_encoder_config can change */
4261static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4262{
4263 if (hdw->state_encoder_config) {
4264 if (hdw->state_encoder_ok) {
4265 if (hdw->state_pipeline_req &&
4266 !hdw->state_pipeline_pause) return 0;
4267 }
4268 hdw->state_encoder_config = 0;
4269 hdw->state_encoder_waitok = 0;
4270 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4271 /* paranoia - solve race if timer just completed */
4272 del_timer_sync(&hdw->encoder_wait_timer);
4273 } else {
62433e31
MI		 4274 if (!hdw->state_pathway_ok ||
4275 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4276 !hdw->state_encoder_ok ||
681c7399
MI		 4277 !hdw->state_pipeline_idle ||
4278 hdw->state_pipeline_pause ||
4279 !hdw->state_pipeline_req ||
4280 !hdw->state_pipeline_config) {
4281 /* We must reset the enforced wait interval if
4282 anything has happened that might have disturbed
4283 the encoder. This should be a rare case. */
4284 if (timer_pending(&hdw->encoder_wait_timer)) {
4285 del_timer_sync(&hdw->encoder_wait_timer);
4286 }
4287 if (hdw->state_encoder_waitok) {
4288 /* Must clear the state - therefore we did
4289 something to a state bit and must also
4290 return true. */
4291 hdw->state_encoder_waitok = 0;
4292 trace_stbit("state_encoder_waitok",
4293 hdw->state_encoder_waitok);
4294 return !0;
4295 }
4296 return 0;
4297 }
4298 if (!hdw->state_encoder_waitok) {
4299 if (!timer_pending(&hdw->encoder_wait_timer)) {
4300 /* waitok flag wasn't set and timer isn't
4301 running. Check flag once more to avoid
4302 a race then start the timer. This is
4303 the point when we measure out a minimal
4304 quiet interval before doing something to
4305 the encoder. */
4306 if (!hdw->state_encoder_waitok) {
4307 hdw->encoder_wait_timer.expires =
83ce57aa
MI		 4308 jiffies +
4309 (HZ * TIME_MSEC_ENCODER_WAIT
4310 / 1000);
681c7399
MI		 4311 add_timer(&hdw->encoder_wait_timer);
4312 }
4313 }
4314 /* We can't continue until we know we have been
4315 quiet for the interval measured by this
4316 timer. */
4317 return 0;
4318 }
4319 pvr2_encoder_configure(hdw);
4320 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4321 }
4322 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4323 return !0;
4324}
4325
4326
d913d630
MI		 4327/* Return true if the encoder should not be running. */
4328static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4329{
4330 if (!hdw->state_encoder_ok) {
4331 /* Encoder isn't healthy at the moment, so stop it. */
4332 return !0;
4333 }
4334 if (!hdw->state_pathway_ok) {
4335 /* Mode is not understood at the moment (i.e. it wants to
4336 change), so encoder must be stopped. */
4337 return !0;
4338 }
4339
4340 switch (hdw->pathway_state) {
4341 case PVR2_PATHWAY_ANALOG:
4342 if (!hdw->state_decoder_run) {
4343 /* We're in analog mode and the decoder is not
4344 running; thus the encoder should be stopped as
4345 well. */
4346 return !0;
4347 }
4348 break;
4349 case PVR2_PATHWAY_DIGITAL:
4350 if (hdw->state_encoder_runok) {
4351 /* This is a funny case. We're in digital mode so
4352 really the encoder should be stopped. However
4353 if it really is running, only kill it after
4354 runok has been set. This gives a chance for the
4355 onair quirk to function (encoder must run
4356 briefly first, at least once, before onair
4357 digital streaming can work). */
4358 return !0;
4359 }
4360 break;
4361 default:
4362 /* Unknown mode; so encoder should be stopped. */
4363 return !0;
4364 }
4365
4366 /* If we get here, we haven't found a reason to stop the
4367 encoder. */
4368 return 0;
4369}
4370
4371
4372/* Return true if the encoder should be running. */
4373static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4374{
4375 if (!hdw->state_encoder_ok) {
4376 /* Don't run the encoder if it isn't healthy... */
4377 return 0;
4378 }
4379 if (!hdw->state_pathway_ok) {
4380 /* Don't run the encoder if we don't (yet) know what mode
4381 we need to be in... */
4382 return 0;
4383 }
4384
4385 switch (hdw->pathway_state) {
4386 case PVR2_PATHWAY_ANALOG:
4387 if (hdw->state_decoder_run) {
4388 /* In analog mode, if the decoder is running, then
4389 run the encoder. */
4390 return !0;
4391 }
4392 break;
4393 case PVR2_PATHWAY_DIGITAL:
4394 if ((hdw->hdw_desc->digital_control_scheme ==
4395 PVR2_DIGITAL_SCHEME_ONAIR) &&
4396 !hdw->state_encoder_runok) {
4397 /* This is a quirk. OnAir hardware won't stream
4398 digital until the encoder has been run at least
4399 once, for a minimal period of time (empiricially
4400 measured to be 1/4 second). So if we're on
4401 OnAir hardware and the encoder has never been
4402 run at all, then start the encoder. Normal
4403 state machine logic in the driver will
4404 automatically handle the remaining bits. */
4405 return !0;
4406 }
4407 break;
4408 default:
4409 /* For completeness (unknown mode; encoder won't run ever) */
4410 break;
4411 }
4412 /* If we get here, then we haven't found any reason to run the
4413 encoder, so don't run it. */
4414 return 0;
4415}
4416
4417
681c7399
MI		 4418/* Evaluate whether or not state_encoder_run can change */
4419static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4420{
4421 if (hdw->state_encoder_run) {
d913d630 4422 if (!state_check_disable_encoder_run(hdw)) return 0;
681c7399 4423 if (hdw->state_encoder_ok) {
d913d630 4424 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 4425 if (pvr2_encoder_stop(hdw) < 0) return !0;
4426 }
4427 hdw->state_encoder_run = 0;
4428 } else {
d913d630 4429 if (!state_check_enable_encoder_run(hdw)) return 0;
681c7399
MI		 4430 if (pvr2_encoder_start(hdw) < 0) return !0;
4431 hdw->state_encoder_run = !0;
d913d630
MI		 4432 if (!hdw->state_encoder_runok) {
4433 hdw->encoder_run_timer.expires =
83ce57aa 4434 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
d913d630
MI		 4435 add_timer(&hdw->encoder_run_timer);
4436 }
681c7399
MI		 4437 }
4438 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4439 return !0;
4440}
4441
4442
4443/* Timeout function for quiescent timer. */
4444static void pvr2_hdw_quiescent_timeout(unsigned long data)
4445{
4446 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4447 hdw->state_decoder_quiescent = !0;
4448 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4449 hdw->state_stale = !0;
4450 queue_work(hdw->workqueue,&hdw->workpoll);
4451}
4452
4453
4454/* Timeout function for encoder wait timer. */
4455static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4456{
4457 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4458 hdw->state_encoder_waitok = !0;
4459 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4460 hdw->state_stale = !0;
4461 queue_work(hdw->workqueue,&hdw->workpoll);
4462}
4463
4464
d913d630
MI		 4465/* Timeout function for encoder run timer. */
4466static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4467{
4468 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4469 if (!hdw->state_encoder_runok) {
4470 hdw->state_encoder_runok = !0;
4471 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4472 hdw->state_stale = !0;
4473 queue_work(hdw->workqueue,&hdw->workpoll);
4474 }
4475}
4476
4477
681c7399
MI		 4478/* Evaluate whether or not state_decoder_run can change */
4479static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4480{
4481 if (hdw->state_decoder_run) {
4482 if (hdw->state_encoder_ok) {
4483 if (hdw->state_pipeline_req &&
62433e31
MI		 4484 !hdw->state_pipeline_pause &&
4485 hdw->state_pathway_ok) return 0;
681c7399
MI		 4486 }
4487 if (!hdw->flag_decoder_missed) {
4488 pvr2_decoder_enable(hdw,0);
4489 }
4490 hdw->state_decoder_quiescent = 0;
4491 hdw->state_decoder_run = 0;
4492 /* paranoia - solve race if timer just completed */
4493 del_timer_sync(&hdw->quiescent_timer);
4494 } else {
4495 if (!hdw->state_decoder_quiescent) {
4496 if (!timer_pending(&hdw->quiescent_timer)) {
4497 /* We don't do something about the
4498 quiescent timer until right here because
4499 we also want to catch cases where the
4500 decoder was already not running (like
4501 after initialization) as opposed to
4502 knowing that we had just stopped it.
4503 The second flag check is here to cover a
4504 race - the timer could have run and set
4505 this flag just after the previous check
4506 but before we did the pending check. */
4507 if (!hdw->state_decoder_quiescent) {
4508 hdw->quiescent_timer.expires =
83ce57aa
MI		 4509 jiffies +
4510 (HZ * TIME_MSEC_DECODER_WAIT
4511 / 1000);
681c7399
MI		 4512 add_timer(&hdw->quiescent_timer);
4513 }
4514 }
4515 /* Don't allow decoder to start again until it has
4516 been quiesced first. This little detail should
4517 hopefully further stabilize the encoder. */
4518 return 0;
4519 }
62433e31
MI		 4520 if (!hdw->state_pathway_ok ||
4521 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4522 !hdw->state_pipeline_req ||
681c7399
MI		 4523 hdw->state_pipeline_pause ||
4524 !hdw->state_pipeline_config ||
4525 !hdw->state_encoder_config ||
4526 !hdw->state_encoder_ok) return 0;
4527 del_timer_sync(&hdw->quiescent_timer);
4528 if (hdw->flag_decoder_missed) return 0;
4529 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4530 hdw->state_decoder_quiescent = 0;
4531 hdw->state_decoder_run = !0;
4532 }
4533 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4534 trace_stbit("state_decoder_run",hdw->state_decoder_run);
4535 return !0;
4536}
4537
4538
4539/* Evaluate whether or not state_usbstream_run can change */
4540static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4541{
4542 if (hdw->state_usbstream_run) {
72998b71 4543 int fl = !0;
62433e31 4544 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
72998b71
MI		 4545 fl = (hdw->state_encoder_ok &&
4546 hdw->state_encoder_run);
4547 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4548 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4549 fl = hdw->state_encoder_ok;
4550 }
4551 if (fl &&
4552 hdw->state_pipeline_req &&
4553 !hdw->state_pipeline_pause &&
4554 hdw->state_pathway_ok) {
4555 return 0;
681c7399
MI		 4556 }
4557 pvr2_hdw_cmd_usbstream(hdw,0);
4558 hdw->state_usbstream_run = 0;
4559 } else {
62433e31
MI		 4560 if (!hdw->state_pipeline_req ||
4561 hdw->state_pipeline_pause ||
4562 !hdw->state_pathway_ok) return 0;
4563 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4564 if (!hdw->state_encoder_ok ||
4565 !hdw->state_encoder_run) return 0;
72998b71
MI		 4566 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4567 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4568 if (!hdw->state_encoder_ok) return 0;
d913d630
MI		 4569 if (hdw->state_encoder_run) return 0;
4570 if (hdw->hdw_desc->digital_control_scheme ==
4571 PVR2_DIGITAL_SCHEME_ONAIR) {
4572 /* OnAir digital receivers won't stream
4573 unless the analog encoder has run first.
4574 Why? I have no idea. But don't even
4575 try until we know the analog side is
4576 known to have run. */
4577 if (!hdw->state_encoder_runok) return 0;
4578 }
62433e31 4579 }
681c7399
MI		 4580 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4581 hdw->state_usbstream_run = !0;
4582 }
4583 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4584 return !0;
4585}
4586
4587
4588/* Attempt to configure pipeline, if needed */
4589static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4590{
4591 if (hdw->state_pipeline_config ||
4592 hdw->state_pipeline_pause) return 0;
4593 pvr2_hdw_commit_execute(hdw);
4594 return !0;
4595}
4596
4597
4598/* Update pipeline idle and pipeline pause tracking states based on other
4599 inputs. This must be called whenever the other relevant inputs have
4600 changed. */
4601static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4602{
4603 unsigned int st;
4604 int updatedFl = 0;
4605 /* Update pipeline state */
4606 st = !(hdw->state_encoder_run ||
4607 hdw->state_decoder_run ||
4608 hdw->state_usbstream_run ||
4609 (!hdw->state_decoder_quiescent));
4610 if (!st != !hdw->state_pipeline_idle) {
4611 hdw->state_pipeline_idle = st;
4612 updatedFl = !0;
4613 }
4614 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4615 hdw->state_pipeline_pause = 0;
4616 updatedFl = !0;
4617 }
4618 return updatedFl;
4619}
4620
4621
4622typedef int (*state_eval_func)(struct pvr2_hdw *);
4623
4624/* Set of functions to be run to evaluate various states in the driver. */
ebff0330 4625static const state_eval_func eval_funcs[] = {
62433e31 4626 state_eval_pathway_ok,
681c7399
MI		 4627 state_eval_pipeline_config,
4628 state_eval_encoder_ok,
4629 state_eval_encoder_config,
4630 state_eval_decoder_run,
4631 state_eval_encoder_run,
4632 state_eval_usbstream_run,
4633};
4634
4635
4636/* Process various states and return true if we did anything interesting. */
4637static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4638{
4639 unsigned int i;
4640 int state_updated = 0;
4641 int check_flag;
4642
4643 if (!hdw->state_stale) return 0;
4644 if ((hdw->fw1_state != FW1_STATE_OK) ||
4645 !hdw->flag_ok) {
4646 hdw->state_stale = 0;
4647 return !0;
4648 }
4649 /* This loop is the heart of the entire driver. It keeps trying to
4650 evaluate various bits of driver state until nothing changes for
4651 one full iteration. Each "bit of state" tracks some global
4652 aspect of the driver, e.g. whether decoder should run, if
4653 pipeline is configured, usb streaming is on, etc. We separately
4654 evaluate each of those questions based on other driver state to
4655 arrive at the correct running configuration. */
4656 do {
4657 check_flag = 0;
4658 state_update_pipeline_state(hdw);
4659 /* Iterate over each bit of state */
4660 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4661 if ((*eval_funcs[i])(hdw)) {
4662 check_flag = !0;
4663 state_updated = !0;
4664 state_update_pipeline_state(hdw);
4665 }
4666 }
4667 } while (check_flag && hdw->flag_ok);
4668 hdw->state_stale = 0;
4669 trace_stbit("state_stale",hdw->state_stale);
4670 return state_updated;
4671}
4672
4673
1cb03b76
MI		 4674static unsigned int print_input_mask(unsigned int msk,
4675 char *buf,unsigned int acnt)
4676{
4677 unsigned int idx,ccnt;
4678 unsigned int tcnt = 0;
4679 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4680 if (!((1 << idx) & msk)) continue;
4681 ccnt = scnprintf(buf+tcnt,
4682 acnt-tcnt,
4683 "%s%s",
4684 (tcnt ? ", " : ""),
4685 control_values_input[idx]);
4686 tcnt += ccnt;
4687 }
4688 return tcnt;
4689}
4690
4691
62433e31
MI		 4692static const char *pvr2_pathway_state_name(int id)
4693{
4694 switch (id) {
4695 case PVR2_PATHWAY_ANALOG: return "analog";
4696 case PVR2_PATHWAY_DIGITAL: return "digital";
4697 default: return "unknown";
4698 }
4699}
4700
4701
681c7399
MI		 4702static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4703 char *buf,unsigned int acnt)
4704{
4705 switch (which) {
4706 case 0:
4707 return scnprintf(
4708 buf,acnt,
e9db1ff2 4709 "driver:%s%s%s%s%s <mode=%s>",
681c7399
MI		 4710 (hdw->flag_ok ? " <ok>" : " <fail>"),
4711 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4712 (hdw->flag_disconnected ? " <disconnected>" :
4713 " <connected>"),
4714 (hdw->flag_tripped ? " <tripped>" : ""),
62433e31
MI		 4715 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4716 pvr2_pathway_state_name(hdw->pathway_state));
4717
681c7399
MI		 4718 case 1:
4719 return scnprintf(
4720 buf,acnt,
4721 "pipeline:%s%s%s%s",
4722 (hdw->state_pipeline_idle ? " <idle>" : ""),
4723 (hdw->state_pipeline_config ?
4724 " <configok>" : " <stale>"),
4725 (hdw->state_pipeline_req ? " <req>" : ""),
4726 (hdw->state_pipeline_pause ? " <pause>" : ""));
4727 case 2:
4728 return scnprintf(
4729 buf,acnt,
62433e31 4730 "worker:%s%s%s%s%s%s%s",
681c7399
MI		 4731 (hdw->state_decoder_run ?
4732 " <decode:run>" :
4733 (hdw->state_decoder_quiescent ?
4734 "" : " <decode:stop>")),
4735 (hdw->state_decoder_quiescent ?
4736 " <decode:quiescent>" : ""),
4737 (hdw->state_encoder_ok ?
4738 "" : " <encode:init>"),
4739 (hdw->state_encoder_run ?
d913d630
MI		 4740 (hdw->state_encoder_runok ?
4741 " <encode:run>" :
4742 " <encode:firstrun>") :
4743 (hdw->state_encoder_runok ?
4744 " <encode:stop>" :
4745 " <encode:virgin>")),
681c7399
MI		 4746 (hdw->state_encoder_config ?
4747 " <encode:configok>" :
4748 (hdw->state_encoder_waitok ?
b9a37d91 4749 "" : " <encode:waitok>")),
681c7399 4750 (hdw->state_usbstream_run ?
62433e31
MI		 4751 " <usb:run>" : " <usb:stop>"),
4752 (hdw->state_pathway_ok ?
e9db1ff2 4753 " <pathway:ok>" : ""));
681c7399
MI		 4754 case 3:
4755 return scnprintf(
4756 buf,acnt,
4757 "state: %s",
4758 pvr2_get_state_name(hdw->master_state));
ad0992e9 4759 case 4: {
1cb03b76
MI		 4760 unsigned int tcnt = 0;
4761 unsigned int ccnt;
4762
4763 ccnt = scnprintf(buf,
4764 acnt,
4765 "Hardware supported inputs: ");
4766 tcnt += ccnt;
4767 tcnt += print_input_mask(hdw->input_avail_mask,
4768 buf+tcnt,
4769 acnt-tcnt);
4770 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4771 ccnt = scnprintf(buf+tcnt,
4772 acnt-tcnt,
4773 "; allowed inputs: ");
4774 tcnt += ccnt;
4775 tcnt += print_input_mask(hdw->input_allowed_mask,
4776 buf+tcnt,
4777 acnt-tcnt);
4778 }
4779 return tcnt;
4780 }
4781 case 5: {
ad0992e9
MI		 4782 struct pvr2_stream_stats stats;
4783 if (!hdw->vid_stream) break;
4784 pvr2_stream_get_stats(hdw->vid_stream,
4785 &stats,
4786 0);
4787 return scnprintf(
4788 buf,acnt,
4789 "Bytes streamed=%u"
4790 " URBs: queued=%u idle=%u ready=%u"
4791 " processed=%u failed=%u",
4792 stats.bytes_processed,
4793 stats.buffers_in_queue,
4794 stats.buffers_in_idle,
4795 stats.buffers_in_ready,
4796 stats.buffers_processed,
4797 stats.buffers_failed);
4798 }
858f910e
MI		 4799 case 6: {
4800 struct v4l2_subdev *sd;
4801 unsigned int tcnt = 0;
4802 unsigned int ccnt;
4803 const char *p;
4804 unsigned int id;
4805 ccnt = scnprintf(buf,
4806 acnt,
4807 "Associted v4l2_subdev drivers:");
4808 tcnt += ccnt;
4809 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4810 id = sd->grp_id;
4811 p = NULL;
4812 if (id < ARRAY_SIZE(module_names)) {
4813 p = module_names[id];
4814 }
4815 if (!p) p = "(unknown)";
4816 ccnt = scnprintf(buf + tcnt,
4817 acnt - tcnt,
4818 " %s (%u)", p, id);
4819 }
4820 return tcnt;
4821 }
681c7399
MI		 4822 default: break;
4823 }
4824 return 0;
4825}
4826
4827
4828unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4829 char *buf,unsigned int acnt)
4830{
4831 unsigned int bcnt,ccnt,idx;
4832 bcnt = 0;
4833 LOCK_TAKE(hdw->big_lock);
4834 for (idx = 0; ; idx++) {
4835 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4836 if (!ccnt) break;
4837 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4838 if (!acnt) break;
4839 buf[0] = '\n'; ccnt = 1;
4840 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4841 }
4842 LOCK_GIVE(hdw->big_lock);
4843 return bcnt;
4844}
4845
4846
4847static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4848{
4849 char buf[128];
4850 unsigned int idx,ccnt;
4851
4852 for (idx = 0; ; idx++) {
4853 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4854 if (!ccnt) break;
4855 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4856 }
4857}
4858
4859
4860/* Evaluate and update the driver's current state, taking various actions
4861 as appropriate for the update. */
4862static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4863{
4864 unsigned int st;
4865 int state_updated = 0;
4866 int callback_flag = 0;
1b9c18c5 4867 int analog_mode;
681c7399
MI		 4868
4869 pvr2_trace(PVR2_TRACE_STBITS,
4870 "Drive state check START");
4871 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4872 pvr2_hdw_state_log_state(hdw);
4873 }
4874
4875 /* Process all state and get back over disposition */
4876 state_updated = pvr2_hdw_state_update(hdw);
4877
1b9c18c5
MI		 4878 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4879
681c7399
MI		 4880 /* Update master state based upon all other states. */
4881 if (!hdw->flag_ok) {
4882 st = PVR2_STATE_DEAD;
4883 } else if (hdw->fw1_state != FW1_STATE_OK) {
4884 st = PVR2_STATE_COLD;
72998b71
MI		 4885 } else if ((analog_mode ||
4886 hdw->hdw_desc->flag_digital_requires_cx23416) &&
4887 !hdw->state_encoder_ok) {
681c7399 4888 st = PVR2_STATE_WARM;
1b9c18c5
MI		 4889 } else if (hdw->flag_tripped ||
4890 (analog_mode && hdw->flag_decoder_missed)) {
681c7399 4891 st = PVR2_STATE_ERROR;
62433e31 4892 } else if (hdw->state_usbstream_run &&
1b9c18c5 4893 (!analog_mode ||
62433e31 4894 (hdw->state_encoder_run && hdw->state_decoder_run))) {
681c7399
MI		 4895 st = PVR2_STATE_RUN;
4896 } else {
4897 st = PVR2_STATE_READY;
4898 }
4899 if (hdw->master_state != st) {
4900 pvr2_trace(PVR2_TRACE_STATE,
4901 "Device state change from %s to %s",
4902 pvr2_get_state_name(hdw->master_state),
4903 pvr2_get_state_name(st));
40381cb0 4904 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
681c7399
MI		 4905 hdw->master_state = st;
4906 state_updated = !0;
4907 callback_flag = !0;
4908 }
4909 if (state_updated) {
4910 /* Trigger anyone waiting on any state changes here. */
4911 wake_up(&hdw->state_wait_data);
4912 }
4913
4914 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4915 pvr2_hdw_state_log_state(hdw);
4916 }
4917 pvr2_trace(PVR2_TRACE_STBITS,
4918 "Drive state check DONE callback=%d",callback_flag);
4919
4920 return callback_flag;
4921}
4922
4923
4924/* Cause kernel thread to check / update driver state */
4925static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4926{
4927 if (hdw->state_stale) return;
4928 hdw->state_stale = !0;
4929 trace_stbit("state_stale",hdw->state_stale);
4930 queue_work(hdw->workqueue,&hdw->workpoll);
4931}
4932
4933
d855497e
MI		 4934int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4935{
4936 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4937}
4938
4939
4940int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4941{
4942 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4943}
4944
4945
4946int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4947{
4948 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4949}
4950
4951
4952int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4953{
4954 u32 cval,nval;
4955 int ret;
4956 if (~msk) {
4957 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4958 if (ret) return ret;
4959 nval = (cval & ~msk) | (val & msk);
4960 pvr2_trace(PVR2_TRACE_GPIO,
4961 "GPIO direction changing 0x%x:0x%x"
4962 " from 0x%x to 0x%x",
4963 msk,val,cval,nval);
4964 } else {
4965 nval = val;
4966 pvr2_trace(PVR2_TRACE_GPIO,
4967 "GPIO direction changing to 0x%x",nval);
4968 }
4969 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4970}
4971
4972
4973int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4974{
4975 u32 cval,nval;
4976 int ret;
4977 if (~msk) {
4978 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
4979 if (ret) return ret;
4980 nval = (cval & ~msk) | (val & msk);
4981 pvr2_trace(PVR2_TRACE_GPIO,
4982 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
4983 msk,val,cval,nval);
4984 } else {
4985 nval = val;
4986 pvr2_trace(PVR2_TRACE_GPIO,
4987 "GPIO output changing to 0x%x",nval);
4988 }
4989 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
4990}
4991
4992
a51f5000
MI		 4993void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
4994{
40f07111
MI		 4995 struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
4996 memset(vtp, 0, sizeof(*vtp));
2641df36 4997 hdw->tuner_signal_stale = 0;
a51f5000 4998 pvr2_i2c_core_status_poll(hdw);
40f07111
MI		 4999 /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5000 using v4l2-subdev - therefore we can't support that AT ALL right
5001 now. (Of course, no sub-drivers seem to implement it either.
5002 But now it's a a chicken and egg problem...) */
5003 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5004 &hdw->tuner_signal_info);
2641df36 5005 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
40f07111
MI		 5006 " type=%u strength=%u audio=0x%x cap=0x%x"
5007 " low=%u hi=%u",
5008 vtp->type,
5009 vtp->signal, vtp->rxsubchans, vtp->capability,
5010 vtp->rangelow, vtp->rangehigh);
2641df36
MI		 5011
5012 /* We have to do this to avoid getting into constant polling if
5013 there's nobody to answer a poll of cropcap info. */
5014 hdw->cropcap_stale = 0;
a51f5000
MI		 5015}
5016
5017
7fb20fa3
MI		 5018unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5019{
5020 return hdw->input_avail_mask;
5021}
5022
5023
1cb03b76
MI		 5024unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5025{
5026 return hdw->input_allowed_mask;
5027}
5028
5029
5030static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5031{
5032 if (hdw->input_val != v) {
5033 hdw->input_val = v;
5034 hdw->input_dirty = !0;
5035 }
5036
5037 /* Handle side effects - if we switch to a mode that needs the RF
5038 tuner, then select the right frequency choice as well and mark
5039 it dirty. */
5040 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5041 hdw->freqSelector = 0;
5042 hdw->freqDirty = !0;
5043 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5044 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5045 hdw->freqSelector = 1;
5046 hdw->freqDirty = !0;
5047 }
5048 return 0;
5049}
5050
5051
5052int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5053 unsigned int change_mask,
5054 unsigned int change_val)
5055{
5056 int ret = 0;
5057 unsigned int nv,m,idx;
5058 LOCK_TAKE(hdw->big_lock);
5059 do {
5060 nv = hdw->input_allowed_mask & ~change_mask;
5061 nv |= (change_val & change_mask);
5062 nv &= hdw->input_avail_mask;
5063 if (!nv) {
5064 /* No legal modes left; return error instead. */
5065 ret = -EPERM;
5066 break;
5067 }
5068 hdw->input_allowed_mask = nv;
5069 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5070 /* Current mode is still in the allowed mask, so
5071 we're done. */
5072 break;
5073 }
5074 /* Select and switch to a mode that is still in the allowed
5075 mask */
5076 if (!hdw->input_allowed_mask) {
5077 /* Nothing legal; give up */
5078 break;
5079 }
5080 m = hdw->input_allowed_mask;
5081 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5082 if (!((1 << idx) & m)) continue;
5083 pvr2_hdw_set_input(hdw,idx);
5084 break;
5085 }
5086 } while (0);
5087 LOCK_GIVE(hdw->big_lock);
5088 return ret;
5089}
5090
5091
e61b6fc5 5092/* Find I2C address of eeprom */
07e337ee 5093static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 5094{
5095 int result;
5096 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 5097 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 5098 result = pvr2_send_request(hdw,
5099 hdw->cmd_buffer,1,
5100 hdw->cmd_buffer,1);
5101 if (result < 0) break;
5102 result = hdw->cmd_buffer[0];
5103 } while(0); LOCK_GIVE(hdw->ctl_lock);
5104 return result;
5105}
5106
5107
32ffa9ae 5108int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
aecde8b5
HV		 5109 struct v4l2_dbg_match *match, u64 reg_id,
5110 int setFl, u64 *val_ptr)
32ffa9ae
MI		 5111{
5112#ifdef CONFIG_VIDEO_ADV_DEBUG
32ffa9ae 5113 struct pvr2_i2c_client *cp;
aecde8b5 5114 struct v4l2_dbg_register req;
6d98816f
MI		 5115 int stat = 0;
5116 int okFl = 0;
32ffa9ae 5117
201f5c9c
MI		 5118 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5119
aecde8b5 5120 req.match = *match;
32ffa9ae
MI		 5121 req.reg = reg_id;
5122 if (setFl) req.val = *val_ptr;
d8f5b9ba
MI		 5123 /* It would be nice to know if a sub-device answered the request */
5124 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5125 if (!setFl) *val_ptr = req.val;
5126 if (!okFl) mutex_lock(&hdw->i2c_list_lock); do {
e77e2c2f 5127 list_for_each_entry(cp, &hdw->i2c_clients, list) {
8481a750
MI		 5128 if (!v4l2_chip_match_i2c_client(
5129 cp->client,
aecde8b5 5130 &req.match)) {
f3d092b8
HV		 5131 continue;
5132 }
32ffa9ae 5133 stat = pvr2_i2c_client_cmd(
52ebc763
TP		 5134 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
5135 VIDIOC_DBG_G_REGISTER),&req);
32ffa9ae 5136 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 5137 okFl = !0;
5138 break;
32ffa9ae
MI		 5139 }
5140 } while (0); mutex_unlock(&hdw->i2c_list_lock);
6d98816f
MI		 5141 if (okFl) {
5142 return stat;
5143 }
32ffa9ae
MI		 5144 return -EINVAL;
5145#else
5146 return -ENOSYS;
5147#endif
5148}
5149
5150
d855497e
MI		 5151/*
5152 Stuff for Emacs to see, in order to encourage consistent editing style:
5153 *** Local Variables: ***
5154 *** mode: c ***
5155 *** fill-column: 75 ***
5156 *** tab-width: 8 ***
5157 *** c-basic-offset: 8 ***
5158 *** End: ***
5159 */
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