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V4L/DVB (7302): pvrusb2: Improve control validation for enumerations
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
3 * $Id$
4 *
5 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#include <linux/errno.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/firmware.h>
d855497e 26#include <linux/videodev2.h>
32ffa9ae 27#include <media/v4l2-common.h>
d855497e
MI		 28#include "pvrusb2.h"
29#include "pvrusb2-std.h"
30#include "pvrusb2-util.h"
31#include "pvrusb2-hdw.h"
32#include "pvrusb2-i2c-core.h"
33#include "pvrusb2-tuner.h"
34#include "pvrusb2-eeprom.h"
35#include "pvrusb2-hdw-internal.h"
36#include "pvrusb2-encoder.h"
37#include "pvrusb2-debug.h"
8d364363 38#include "pvrusb2-fx2-cmd.h"
d855497e 39
1bde0289
MI		 40#define TV_MIN_FREQ 55250000L
41#define TV_MAX_FREQ 850000000L
25d8527a 42
a0fd1cb1 43static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 44static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e 45
ff699e6b 46static int ctlchg;
d855497e 47static int initusbreset = 1;
ff699e6b 48static int procreload;
d855497e
MI		 49static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
50static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
51static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
ff699e6b 52static int init_pause_msec;
d855497e
MI		 53
54module_param(ctlchg, int, S_IRUGO|S_IWUSR);
55MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
56module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
57MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
58module_param(initusbreset, int, S_IRUGO|S_IWUSR);
59MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
60module_param(procreload, int, S_IRUGO|S_IWUSR);
61MODULE_PARM_DESC(procreload,
62 "Attempt init failure recovery with firmware reload");
63module_param_array(tuner, int, NULL, 0444);
64MODULE_PARM_DESC(tuner,"specify installed tuner type");
65module_param_array(video_std, int, NULL, 0444);
66MODULE_PARM_DESC(video_std,"specify initial video standard");
67module_param_array(tolerance, int, NULL, 0444);
68MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
69
70#define PVR2_CTL_WRITE_ENDPOINT 0x01
71#define PVR2_CTL_READ_ENDPOINT 0x81
72
73#define PVR2_GPIO_IN 0x9008
74#define PVR2_GPIO_OUT 0x900c
75#define PVR2_GPIO_DIR 0x9020
76
77#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
78
79#define PVR2_FIRMWARE_ENDPOINT 0x02
80
81/* size of a firmware chunk */
82#define FIRMWARE_CHUNK_SIZE 0x2000
83
b30d2441
MI		 84/* Define the list of additional controls we'll dynamically construct based
85 on query of the cx2341x module. */
86struct pvr2_mpeg_ids {
87 const char *strid;
88 int id;
89};
90static const struct pvr2_mpeg_ids mpeg_ids[] = {
91 {
92 .strid = "audio_layer",
93 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
94 },{
95 .strid = "audio_bitrate",
96 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
97 },{
98 /* Already using audio_mode elsewhere :-( */
99 .strid = "mpeg_audio_mode",
100 .id = V4L2_CID_MPEG_AUDIO_MODE,
101 },{
102 .strid = "mpeg_audio_mode_extension",
103 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
104 },{
105 .strid = "audio_emphasis",
106 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
107 },{
108 .strid = "audio_crc",
109 .id = V4L2_CID_MPEG_AUDIO_CRC,
110 },{
111 .strid = "video_aspect",
112 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
113 },{
114 .strid = "video_b_frames",
115 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
116 },{
117 .strid = "video_gop_size",
118 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
119 },{
120 .strid = "video_gop_closure",
121 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 122 },{
123 .strid = "video_bitrate_mode",
124 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
125 },{
126 .strid = "video_bitrate",
127 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
128 },{
129 .strid = "video_bitrate_peak",
130 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
131 },{
132 .strid = "video_temporal_decimation",
133 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
134 },{
135 .strid = "stream_type",
136 .id = V4L2_CID_MPEG_STREAM_TYPE,
137 },{
138 .strid = "video_spatial_filter_mode",
139 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
140 },{
141 .strid = "video_spatial_filter",
142 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
143 },{
144 .strid = "video_luma_spatial_filter_type",
145 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
146 },{
147 .strid = "video_chroma_spatial_filter_type",
148 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
149 },{
150 .strid = "video_temporal_filter_mode",
151 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
152 },{
153 .strid = "video_temporal_filter",
154 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
155 },{
156 .strid = "video_median_filter_type",
157 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
158 },{
159 .strid = "video_luma_median_filter_top",
160 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
161 },{
162 .strid = "video_luma_median_filter_bottom",
163 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
164 },{
165 .strid = "video_chroma_median_filter_top",
166 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
167 },{
168 .strid = "video_chroma_median_filter_bottom",
169 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
170 }
171};
eca8ebfc 172#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 173
434449f4 174
d855497e 175static const char *control_values_srate[] = {
434449f4
MI		 176 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
177 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
178 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 179};
180
181
d855497e 182
d855497e
MI		 183static const char *control_values_input[] = {
184 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
29bf5b1d 185 [PVR2_CVAL_INPUT_DTV] = "dtv",
d855497e
MI		 186 [PVR2_CVAL_INPUT_RADIO] = "radio",
187 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
188 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
189};
190
191
192static const char *control_values_audiomode[] = {
193 [V4L2_TUNER_MODE_MONO] = "Mono",
194 [V4L2_TUNER_MODE_STEREO] = "Stereo",
195 [V4L2_TUNER_MODE_LANG1] = "Lang1",
196 [V4L2_TUNER_MODE_LANG2] = "Lang2",
197 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
198};
199
200
201static const char *control_values_hsm[] = {
202 [PVR2_CVAL_HSM_FAIL] = "Fail",
203 [PVR2_CVAL_HSM_HIGH] = "High",
204 [PVR2_CVAL_HSM_FULL] = "Full",
205};
206
207
681c7399
MI		 208static const char *pvr2_state_names[] = {
209 [PVR2_STATE_NONE] = "none",
210 [PVR2_STATE_DEAD] = "dead",
211 [PVR2_STATE_COLD] = "cold",
212 [PVR2_STATE_WARM] = "warm",
213 [PVR2_STATE_ERROR] = "error",
214 [PVR2_STATE_READY] = "ready",
215 [PVR2_STATE_RUN] = "run",
d855497e
MI		 216};
217
681c7399
MI		 218
219static void pvr2_hdw_state_sched(struct pvr2_hdw *);
220static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 221static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399
MI		 222static void pvr2_hdw_worker_i2c(struct work_struct *work);
223static void pvr2_hdw_worker_poll(struct work_struct *work);
224static void pvr2_hdw_worker_init(struct work_struct *work);
225static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
226static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
227static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 228static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 229static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 230static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 231static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
232static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
681c7399
MI		 233static void pvr2_hdw_quiescent_timeout(unsigned long);
234static void pvr2_hdw_encoder_wait_timeout(unsigned long);
07e337ee
AB		 235static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
236 unsigned int timeout,int probe_fl,
237 void *write_data,unsigned int write_len,
238 void *read_data,unsigned int read_len);
d855497e 239
681c7399
MI		 240
241static void trace_stbit(const char *name,int val)
242{
243 pvr2_trace(PVR2_TRACE_STBITS,
244 "State bit %s <-- %s",
245 name,(val ? "true" : "false"));
246}
247
d855497e
MI		 248static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
249{
250 struct pvr2_hdw *hdw = cptr->hdw;
251 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
252 *vp = hdw->freqTable[hdw->freqProgSlot-1];
253 } else {
254 *vp = 0;
255 }
256 return 0;
257}
258
259static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
260{
261 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 262 unsigned int slotId = hdw->freqProgSlot;
263 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
264 hdw->freqTable[slotId-1] = v;
265 /* Handle side effects correctly - if we're tuned to this
266 slot, then forgot the slot id relation since the stored
267 frequency has been changed. */
268 if (hdw->freqSelector) {
269 if (hdw->freqSlotRadio == slotId) {
270 hdw->freqSlotRadio = 0;
271 }
272 } else {
273 if (hdw->freqSlotTelevision == slotId) {
274 hdw->freqSlotTelevision = 0;
275 }
276 }
d855497e
MI		 277 }
278 return 0;
279}
280
281static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
282{
283 *vp = cptr->hdw->freqProgSlot;
284 return 0;
285}
286
287static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
288{
289 struct pvr2_hdw *hdw = cptr->hdw;
290 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
291 hdw->freqProgSlot = v;
292 }
293 return 0;
294}
295
296static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
297{
1bde0289
MI		 298 struct pvr2_hdw *hdw = cptr->hdw;
299 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 300 return 0;
301}
302
1bde0289 303static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 304{
305 unsigned freq = 0;
306 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 307 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
308 if (slotId > 0) {
309 freq = hdw->freqTable[slotId-1];
310 if (!freq) return 0;
311 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 312 }
1bde0289
MI		 313 if (hdw->freqSelector) {
314 hdw->freqSlotRadio = slotId;
315 } else {
316 hdw->freqSlotTelevision = slotId;
d855497e
MI		 317 }
318 return 0;
319}
320
321static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
322{
1bde0289 323 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 324 return 0;
325}
326
327static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
328{
329 return cptr->hdw->freqDirty != 0;
330}
331
332static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
333{
334 cptr->hdw->freqDirty = 0;
335}
336
337static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
338{
1bde0289 339 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 340 return 0;
341}
342
3ad9fc37
MI		 343static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
344{
345 /* Actual maximum depends on the video standard in effect. */
346 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
347 *vp = 480;
348 } else {
349 *vp = 576;
350 }
351 return 0;
352}
353
354static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
355{
989eb154
MI		 356 /* Actual minimum depends on device digitizer type. */
357 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 358 *vp = 75;
359 } else {
360 *vp = 17;
361 }
362 return 0;
363}
364
1bde0289 365static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 366{
1bde0289
MI		 367 *vp = cptr->hdw->input_val;
368 return 0;
369}
370
29bf5b1d
MI		 371static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
372{
7fb20fa3 373 return ((1 << v) & cptr->hdw->input_avail_mask) != 0;
29bf5b1d
MI		 374}
375
1bde0289
MI		 376static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
377{
378 struct pvr2_hdw *hdw = cptr->hdw;
379
380 if (hdw->input_val != v) {
381 hdw->input_val = v;
382 hdw->input_dirty = !0;
383 }
384
385 /* Handle side effects - if we switch to a mode that needs the RF
386 tuner, then select the right frequency choice as well and mark
387 it dirty. */
388 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
389 hdw->freqSelector = 0;
390 hdw->freqDirty = !0;
29bf5b1d
MI		 391 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
392 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
1bde0289
MI		 393 hdw->freqSelector = 1;
394 hdw->freqDirty = !0;
5549f54f 395 }
1bde0289
MI		 396 return 0;
397}
398
399static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
400{
401 return cptr->hdw->input_dirty != 0;
402}
403
404static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
405{
406 cptr->hdw->input_dirty = 0;
407}
408
5549f54f 409
25d8527a
PK		 410static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
411{
644afdb9
MI		 412 unsigned long fv;
413 struct pvr2_hdw *hdw = cptr->hdw;
414 if (hdw->tuner_signal_stale) {
415 pvr2_i2c_core_status_poll(hdw);
416 }
417 fv = hdw->tuner_signal_info.rangehigh;
418 if (!fv) {
419 /* Safety fallback */
25d8527a 420 *vp = TV_MAX_FREQ;
644afdb9 421 return 0;
25d8527a 422 }
644afdb9
MI		 423 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
424 fv = (fv * 125) / 2;
425 } else {
426 fv = fv * 62500;
427 }
428 *vp = fv;
25d8527a
PK		 429 return 0;
430}
431
432static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
433{
644afdb9
MI		 434 unsigned long fv;
435 struct pvr2_hdw *hdw = cptr->hdw;
436 if (hdw->tuner_signal_stale) {
437 pvr2_i2c_core_status_poll(hdw);
438 }
439 fv = hdw->tuner_signal_info.rangelow;
440 if (!fv) {
441 /* Safety fallback */
25d8527a 442 *vp = TV_MIN_FREQ;
644afdb9
MI		 443 return 0;
444 }
445 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
446 fv = (fv * 125) / 2;
447 } else {
448 fv = fv * 62500;
25d8527a 449 }
644afdb9 450 *vp = fv;
25d8527a
PK		 451 return 0;
452}
453
b30d2441
MI		 454static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
455{
456 return cptr->hdw->enc_stale != 0;
457}
458
459static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
460{
461 cptr->hdw->enc_stale = 0;
681c7399 462 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 463}
464
465static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
466{
467 int ret;
468 struct v4l2_ext_controls cs;
469 struct v4l2_ext_control c1;
470 memset(&cs,0,sizeof(cs));
471 memset(&c1,0,sizeof(c1));
472 cs.controls = &c1;
473 cs.count = 1;
474 c1.id = cptr->info->v4l_id;
01f1e44f 475 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 476 VIDIOC_G_EXT_CTRLS);
477 if (ret) return ret;
478 *vp = c1.value;
479 return 0;
480}
481
482static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
483{
484 int ret;
681c7399 485 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 486 struct v4l2_ext_controls cs;
487 struct v4l2_ext_control c1;
488 memset(&cs,0,sizeof(cs));
489 memset(&c1,0,sizeof(c1));
490 cs.controls = &c1;
491 cs.count = 1;
492 c1.id = cptr->info->v4l_id;
493 c1.value = v;
681c7399
MI		 494 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
495 hdw->state_encoder_run, &cs,
b30d2441 496 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 497 if (ret == -EBUSY) {
498 /* Oops. cx2341x is telling us it's not safe to change
499 this control while we're capturing. Make a note of this
500 fact so that the pipeline will be stopped the next time
501 controls are committed. Then go on ahead and store this
502 change anyway. */
503 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
504 0, &cs,
505 VIDIOC_S_EXT_CTRLS);
506 if (!ret) hdw->enc_unsafe_stale = !0;
507 }
b30d2441 508 if (ret) return ret;
681c7399 509 hdw->enc_stale = !0;
b30d2441
MI		 510 return 0;
511}
512
513static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
514{
515 struct v4l2_queryctrl qctrl;
516 struct pvr2_ctl_info *info;
517 qctrl.id = cptr->info->v4l_id;
518 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
519 /* Strip out the const so we can adjust a function pointer. It's
520 OK to do this here because we know this is a dynamically created
521 control, so the underlying storage for the info pointer is (a)
522 private to us, and (b) not in read-only storage. Either we do
523 this or we significantly complicate the underlying control
524 implementation. */
525 info = (struct pvr2_ctl_info *)(cptr->info);
526 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
527 if (info->set_value) {
a0fd1cb1 528 info->set_value = NULL;
b30d2441
MI		 529 }
530 } else {
531 if (!(info->set_value)) {
532 info->set_value = ctrl_cx2341x_set;
533 }
534 }
535 return qctrl.flags;
536}
537
d855497e
MI		 538static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
539{
681c7399
MI		 540 *vp = cptr->hdw->state_pipeline_req;
541 return 0;
542}
543
544static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
545{
546 *vp = cptr->hdw->master_state;
d855497e
MI		 547 return 0;
548}
549
550static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
551{
552 int result = pvr2_hdw_is_hsm(cptr->hdw);
553 *vp = PVR2_CVAL_HSM_FULL;
554 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
555 if (result) *vp = PVR2_CVAL_HSM_HIGH;
556 return 0;
557}
558
559static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
560{
561 *vp = cptr->hdw->std_mask_avail;
562 return 0;
563}
564
565static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
566{
567 struct pvr2_hdw *hdw = cptr->hdw;
568 v4l2_std_id ns;
569 ns = hdw->std_mask_avail;
570 ns = (ns & ~m) | (v & m);
571 if (ns == hdw->std_mask_avail) return 0;
572 hdw->std_mask_avail = ns;
573 pvr2_hdw_internal_set_std_avail(hdw);
574 pvr2_hdw_internal_find_stdenum(hdw);
575 return 0;
576}
577
578static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
579 char *bufPtr,unsigned int bufSize,
580 unsigned int *len)
581{
582 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
583 return 0;
584}
585
586static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
587 const char *bufPtr,unsigned int bufSize,
588 int *mskp,int *valp)
589{
590 int ret;
591 v4l2_std_id id;
592 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
593 if (ret < 0) return ret;
594 if (mskp) *mskp = id;
595 if (valp) *valp = id;
596 return 0;
597}
598
599static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
600{
601 *vp = cptr->hdw->std_mask_cur;
602 return 0;
603}
604
605static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
606{
607 struct pvr2_hdw *hdw = cptr->hdw;
608 v4l2_std_id ns;
609 ns = hdw->std_mask_cur;
610 ns = (ns & ~m) | (v & m);
611 if (ns == hdw->std_mask_cur) return 0;
612 hdw->std_mask_cur = ns;
613 hdw->std_dirty = !0;
614 pvr2_hdw_internal_find_stdenum(hdw);
615 return 0;
616}
617
618static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
619{
620 return cptr->hdw->std_dirty != 0;
621}
622
623static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
624{
625 cptr->hdw->std_dirty = 0;
626}
627
628static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
629{
18103c57
MI		 630 struct pvr2_hdw *hdw = cptr->hdw;
631 pvr2_i2c_core_status_poll(hdw);
632 *vp = hdw->tuner_signal_info.signal;
633 return 0;
634}
635
636static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
637{
638 int val = 0;
639 unsigned int subchan;
640 struct pvr2_hdw *hdw = cptr->hdw;
644afdb9 641 pvr2_i2c_core_status_poll(hdw);
18103c57
MI		 642 subchan = hdw->tuner_signal_info.rxsubchans;
643 if (subchan & V4L2_TUNER_SUB_MONO) {
644 val |= (1 << V4L2_TUNER_MODE_MONO);
645 }
646 if (subchan & V4L2_TUNER_SUB_STEREO) {
647 val |= (1 << V4L2_TUNER_MODE_STEREO);
648 }
649 if (subchan & V4L2_TUNER_SUB_LANG1) {
650 val |= (1 << V4L2_TUNER_MODE_LANG1);
651 }
652 if (subchan & V4L2_TUNER_SUB_LANG2) {
653 val |= (1 << V4L2_TUNER_MODE_LANG2);
654 }
655 *vp = val;
d855497e
MI		 656 return 0;
657}
658
d855497e
MI		 659
660static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
661{
662 struct pvr2_hdw *hdw = cptr->hdw;
663 if (v < 0) return -EINVAL;
664 if (v > hdw->std_enum_cnt) return -EINVAL;
665 hdw->std_enum_cur = v;
666 if (!v) return 0;
667 v--;
668 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
669 hdw->std_mask_cur = hdw->std_defs[v].id;
670 hdw->std_dirty = !0;
671 return 0;
672}
673
674
675static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
676{
677 *vp = cptr->hdw->std_enum_cur;
678 return 0;
679}
680
681
682static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
683{
684 return cptr->hdw->std_dirty != 0;
685}
686
687
688static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
689{
690 cptr->hdw->std_dirty = 0;
691}
692
693
694#define DEFINT(vmin,vmax) \
695 .type = pvr2_ctl_int, \
696 .def.type_int.min_value = vmin, \
697 .def.type_int.max_value = vmax
698
699#define DEFENUM(tab) \
700 .type = pvr2_ctl_enum, \
27c7b710 701 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 702 .def.type_enum.value_names = tab
703
33213963
MI		 704#define DEFBOOL \
705 .type = pvr2_ctl_bool
706
d855497e
MI		 707#define DEFMASK(msk,tab) \
708 .type = pvr2_ctl_bitmask, \
709 .def.type_bitmask.valid_bits = msk, \
710 .def.type_bitmask.bit_names = tab
711
712#define DEFREF(vname) \
713 .set_value = ctrl_set_##vname, \
714 .get_value = ctrl_get_##vname, \
715 .is_dirty = ctrl_isdirty_##vname, \
716 .clear_dirty = ctrl_cleardirty_##vname
717
718
719#define VCREATE_FUNCS(vname) \
720static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
721{*vp = cptr->hdw->vname##_val; return 0;} \
722static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
723{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
724static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
725{return cptr->hdw->vname##_dirty != 0;} \
726static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
727{cptr->hdw->vname##_dirty = 0;}
728
729VCREATE_FUNCS(brightness)
730VCREATE_FUNCS(contrast)
731VCREATE_FUNCS(saturation)
732VCREATE_FUNCS(hue)
733VCREATE_FUNCS(volume)
734VCREATE_FUNCS(balance)
735VCREATE_FUNCS(bass)
736VCREATE_FUNCS(treble)
737VCREATE_FUNCS(mute)
c05c0462
MI		 738VCREATE_FUNCS(audiomode)
739VCREATE_FUNCS(res_hor)
740VCREATE_FUNCS(res_ver)
d855497e 741VCREATE_FUNCS(srate)
d855497e 742
d855497e
MI		 743/* Table definition of all controls which can be manipulated */
744static const struct pvr2_ctl_info control_defs[] = {
745 {
746 .v4l_id = V4L2_CID_BRIGHTNESS,
747 .desc = "Brightness",
748 .name = "brightness",
749 .default_value = 128,
750 DEFREF(brightness),
751 DEFINT(0,255),
752 },{
753 .v4l_id = V4L2_CID_CONTRAST,
754 .desc = "Contrast",
755 .name = "contrast",
756 .default_value = 68,
757 DEFREF(contrast),
758 DEFINT(0,127),
759 },{
760 .v4l_id = V4L2_CID_SATURATION,
761 .desc = "Saturation",
762 .name = "saturation",
763 .default_value = 64,
764 DEFREF(saturation),
765 DEFINT(0,127),
766 },{
767 .v4l_id = V4L2_CID_HUE,
768 .desc = "Hue",
769 .name = "hue",
770 .default_value = 0,
771 DEFREF(hue),
772 DEFINT(-128,127),
773 },{
774 .v4l_id = V4L2_CID_AUDIO_VOLUME,
775 .desc = "Volume",
776 .name = "volume",
139eecf9 777 .default_value = 62000,
d855497e
MI		 778 DEFREF(volume),
779 DEFINT(0,65535),
780 },{
781 .v4l_id = V4L2_CID_AUDIO_BALANCE,
782 .desc = "Balance",
783 .name = "balance",
784 .default_value = 0,
785 DEFREF(balance),
786 DEFINT(-32768,32767),
787 },{
788 .v4l_id = V4L2_CID_AUDIO_BASS,
789 .desc = "Bass",
790 .name = "bass",
791 .default_value = 0,
792 DEFREF(bass),
793 DEFINT(-32768,32767),
794 },{
795 .v4l_id = V4L2_CID_AUDIO_TREBLE,
796 .desc = "Treble",
797 .name = "treble",
798 .default_value = 0,
799 DEFREF(treble),
800 DEFINT(-32768,32767),
801 },{
802 .v4l_id = V4L2_CID_AUDIO_MUTE,
803 .desc = "Mute",
804 .name = "mute",
805 .default_value = 0,
806 DEFREF(mute),
33213963 807 DEFBOOL,
c05c0462
MI		 808 },{
809 .desc = "Video Source",
810 .name = "input",
811 .internal_id = PVR2_CID_INPUT,
812 .default_value = PVR2_CVAL_INPUT_TV,
29bf5b1d 813 .check_value = ctrl_check_input,
c05c0462
MI		 814 DEFREF(input),
815 DEFENUM(control_values_input),
816 },{
817 .desc = "Audio Mode",
818 .name = "audio_mode",
819 .internal_id = PVR2_CID_AUDIOMODE,
820 .default_value = V4L2_TUNER_MODE_STEREO,
821 DEFREF(audiomode),
822 DEFENUM(control_values_audiomode),
823 },{
824 .desc = "Horizontal capture resolution",
825 .name = "resolution_hor",
826 .internal_id = PVR2_CID_HRES,
827 .default_value = 720,
828 DEFREF(res_hor),
3ad9fc37 829 DEFINT(19,720),
c05c0462
MI		 830 },{
831 .desc = "Vertical capture resolution",
832 .name = "resolution_ver",
833 .internal_id = PVR2_CID_VRES,
834 .default_value = 480,
835 DEFREF(res_ver),
3ad9fc37
MI		 836 DEFINT(17,576),
837 /* Hook in check for video standard and adjust maximum
838 depending on the standard. */
839 .get_max_value = ctrl_vres_max_get,
840 .get_min_value = ctrl_vres_min_get,
d855497e 841 },{
b30d2441 842 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 843 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
844 .desc = "Audio Sampling Frequency",
d855497e 845 .name = "srate",
d855497e
MI		 846 DEFREF(srate),
847 DEFENUM(control_values_srate),
d855497e
MI		 848 },{
849 .desc = "Tuner Frequency (Hz)",
850 .name = "frequency",
851 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 852 .default_value = 0,
d855497e
MI		 853 .set_value = ctrl_freq_set,
854 .get_value = ctrl_freq_get,
855 .is_dirty = ctrl_freq_is_dirty,
856 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 857 DEFINT(0,0),
25d8527a
PK		 858 /* Hook in check for input value (tv/radio) and adjust
859 max/min values accordingly */
860 .get_max_value = ctrl_freq_max_get,
861 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 862 },{
863 .desc = "Channel",
864 .name = "channel",
865 .set_value = ctrl_channel_set,
866 .get_value = ctrl_channel_get,
867 DEFINT(0,FREQTABLE_SIZE),
868 },{
869 .desc = "Channel Program Frequency",
870 .name = "freq_table_value",
871 .set_value = ctrl_channelfreq_set,
872 .get_value = ctrl_channelfreq_get,
644afdb9 873 DEFINT(0,0),
1bde0289
MI		 874 /* Hook in check for input value (tv/radio) and adjust
875 max/min values accordingly */
1bde0289
MI		 876 .get_max_value = ctrl_freq_max_get,
877 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 878 },{
879 .desc = "Channel Program ID",
880 .name = "freq_table_channel",
881 .set_value = ctrl_channelprog_set,
882 .get_value = ctrl_channelprog_get,
883 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 884 },{
885 .desc = "Streaming Enabled",
886 .name = "streaming_enabled",
887 .get_value = ctrl_streamingenabled_get,
33213963 888 DEFBOOL,
d855497e
MI		 889 },{
890 .desc = "USB Speed",
891 .name = "usb_speed",
892 .get_value = ctrl_hsm_get,
893 DEFENUM(control_values_hsm),
681c7399
MI		 894 },{
895 .desc = "Master State",
896 .name = "master_state",
897 .get_value = ctrl_masterstate_get,
898 DEFENUM(pvr2_state_names),
d855497e
MI		 899 },{
900 .desc = "Signal Present",
901 .name = "signal_present",
902 .get_value = ctrl_signal_get,
18103c57
MI		 903 DEFINT(0,65535),
904 },{
905 .desc = "Audio Modes Present",
906 .name = "audio_modes_present",
907 .get_value = ctrl_audio_modes_present_get,
908 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
909 v4l. Nothing outside of this module cares about this,
910 but I reuse it in order to also reuse the
911 control_values_audiomode string table. */
912 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
913 (1 << V4L2_TUNER_MODE_STEREO)|
914 (1 << V4L2_TUNER_MODE_LANG1)|
915 (1 << V4L2_TUNER_MODE_LANG2)),
916 control_values_audiomode),
d855497e
MI		 917 },{
918 .desc = "Video Standards Available Mask",
919 .name = "video_standard_mask_available",
920 .internal_id = PVR2_CID_STDAVAIL,
921 .skip_init = !0,
922 .get_value = ctrl_stdavail_get,
923 .set_value = ctrl_stdavail_set,
924 .val_to_sym = ctrl_std_val_to_sym,
925 .sym_to_val = ctrl_std_sym_to_val,
926 .type = pvr2_ctl_bitmask,
927 },{
928 .desc = "Video Standards In Use Mask",
929 .name = "video_standard_mask_active",
930 .internal_id = PVR2_CID_STDCUR,
931 .skip_init = !0,
932 .get_value = ctrl_stdcur_get,
933 .set_value = ctrl_stdcur_set,
934 .is_dirty = ctrl_stdcur_is_dirty,
935 .clear_dirty = ctrl_stdcur_clear_dirty,
936 .val_to_sym = ctrl_std_val_to_sym,
937 .sym_to_val = ctrl_std_sym_to_val,
938 .type = pvr2_ctl_bitmask,
d855497e
MI		 939 },{
940 .desc = "Video Standard Name",
941 .name = "video_standard",
942 .internal_id = PVR2_CID_STDENUM,
943 .skip_init = !0,
944 .get_value = ctrl_stdenumcur_get,
945 .set_value = ctrl_stdenumcur_set,
946 .is_dirty = ctrl_stdenumcur_is_dirty,
947 .clear_dirty = ctrl_stdenumcur_clear_dirty,
948 .type = pvr2_ctl_enum,
949 }
950};
951
eca8ebfc 952#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 953
954
955const char *pvr2_config_get_name(enum pvr2_config cfg)
956{
957 switch (cfg) {
958 case pvr2_config_empty: return "empty";
959 case pvr2_config_mpeg: return "mpeg";
960 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 961 case pvr2_config_pcm: return "pcm";
962 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 963 }
964 return "<unknown>";
965}
966
967
968struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
969{
970 return hdw->usb_dev;
971}
972
973
974unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
975{
976 return hdw->serial_number;
977}
978
31a18547
MI		 979
980const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
981{
982 return hdw->bus_info;
983}
984
985
1bde0289
MI		 986unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
987{
988 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
989}
990
991/* Set the currently tuned frequency and account for all possible
992 driver-core side effects of this action. */
993void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
994{
7c74e57e 995 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 996 if (hdw->freqSelector) {
997 /* Swing over to radio frequency selection */
998 hdw->freqSelector = 0;
999 hdw->freqDirty = !0;
1000 }
1bde0289
MI		 1001 if (hdw->freqValRadio != val) {
1002 hdw->freqValRadio = val;
1003 hdw->freqSlotRadio = 0;
7c74e57e 1004 hdw->freqDirty = !0;
1bde0289 1005 }
7c74e57e 1006 } else {
1bde0289
MI		 1007 if (!(hdw->freqSelector)) {
1008 /* Swing over to television frequency selection */
1009 hdw->freqSelector = 1;
1010 hdw->freqDirty = !0;
1011 }
1bde0289
MI		 1012 if (hdw->freqValTelevision != val) {
1013 hdw->freqValTelevision = val;
1014 hdw->freqSlotTelevision = 0;
7c74e57e 1015 hdw->freqDirty = !0;
1bde0289 1016 }
1bde0289
MI		 1017 }
1018}
1019
d855497e
MI		 1020int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1021{
1022 return hdw->unit_number;
1023}
1024
1025
1026/* Attempt to locate one of the given set of files. Messages are logged
1027 appropriate to what has been found. The return value will be 0 or
1028 greater on success (it will be the index of the file name found) and
1029 fw_entry will be filled in. Otherwise a negative error is returned on
1030 failure. If the return value is -ENOENT then no viable firmware file
1031 could be located. */
1032static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1033 const struct firmware **fw_entry,
1034 const char *fwtypename,
1035 unsigned int fwcount,
1036 const char *fwnames[])
1037{
1038 unsigned int idx;
1039 int ret = -EINVAL;
1040 for (idx = 0; idx < fwcount; idx++) {
1041 ret = request_firmware(fw_entry,
1042 fwnames[idx],
1043 &hdw->usb_dev->dev);
1044 if (!ret) {
1045 trace_firmware("Located %s firmware: %s;"
1046 " uploading...",
1047 fwtypename,
1048 fwnames[idx]);
1049 return idx;
1050 }
1051 if (ret == -ENOENT) continue;
1052 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1053 "request_firmware fatal error with code=%d",ret);
1054 return ret;
1055 }
1056 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1057 "***WARNING***"
1058 " Device %s firmware"
1059 " seems to be missing.",
1060 fwtypename);
1061 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1062 "Did you install the pvrusb2 firmware files"
1063 " in their proper location?");
1064 if (fwcount == 1) {
1065 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1066 "request_firmware unable to locate %s file %s",
1067 fwtypename,fwnames[0]);
1068 } else {
1069 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1070 "request_firmware unable to locate"
1071 " one of the following %s files:",
1072 fwtypename);
1073 for (idx = 0; idx < fwcount; idx++) {
1074 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1075 "request_firmware: Failed to find %s",
1076 fwnames[idx]);
1077 }
1078 }
1079 return ret;
1080}
1081
1082
1083/*
1084 * pvr2_upload_firmware1().
1085 *
1086 * Send the 8051 firmware to the device. After the upload, arrange for
1087 * device to re-enumerate.
1088 *
1089 * NOTE : the pointer to the firmware data given by request_firmware()
1090 * is not suitable for an usb transaction.
1091 *
1092 */
07e337ee 1093static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1094{
a0fd1cb1 1095 const struct firmware *fw_entry = NULL;
d855497e
MI		 1096 void *fw_ptr;
1097 unsigned int pipe;
1098 int ret;
1099 u16 address;
1d643a37 1100
989eb154 1101 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1102 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1103 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1104 "Connected device type defines"
1105 " no firmware to upload; ignoring firmware");
1106 return -ENOTTY;
1d643a37
MI		 1107 }
1108
d855497e
MI		 1109 hdw->fw1_state = FW1_STATE_FAILED; // default result
1110
1111 trace_firmware("pvr2_upload_firmware1");
1112
1113 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1114 hdw->hdw_desc->fx2_firmware.cnt,
1115 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1116 if (ret < 0) {
1117 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1118 return ret;
1119 }
1120
1121 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1122 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1123
1124 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1125
1126 if (fw_entry->size != 0x2000){
1127 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1128 release_firmware(fw_entry);
1129 return -ENOMEM;
1130 }
1131
1132 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1133 if (fw_ptr == NULL){
1134 release_firmware(fw_entry);
1135 return -ENOMEM;
1136 }
1137
1138 /* We have to hold the CPU during firmware upload. */
1139 pvr2_hdw_cpureset_assert(hdw,1);
1140
1141 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1142 chunk. */
1143
1144 ret = 0;
1145 for(address = 0; address < fw_entry->size; address += 0x800) {
1146 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1147 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1148 0, fw_ptr, 0x800, HZ);
1149 }
1150
1151 trace_firmware("Upload done, releasing device's CPU");
1152
1153 /* Now release the CPU. It will disconnect and reconnect later. */
1154 pvr2_hdw_cpureset_assert(hdw,0);
1155
1156 kfree(fw_ptr);
1157 release_firmware(fw_entry);
1158
1159 trace_firmware("Upload done (%d bytes sent)",ret);
1160
1161 /* We should have written 8192 bytes */
1162 if (ret == 8192) {
1163 hdw->fw1_state = FW1_STATE_RELOAD;
1164 return 0;
1165 }
1166
1167 return -EIO;
1168}
1169
1170
1171/*
1172 * pvr2_upload_firmware2()
1173 *
1174 * This uploads encoder firmware on endpoint 2.
1175 *
1176 */
1177
1178int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1179{
a0fd1cb1 1180 const struct firmware *fw_entry = NULL;
d855497e 1181 void *fw_ptr;
90060d32 1182 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1183 int actual_length;
1184 int ret = 0;
1185 int fwidx;
1186 static const char *fw_files[] = {
1187 CX2341X_FIRM_ENC_FILENAME,
1188 };
1189
989eb154 1190 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1191 return 0;
1192 }
1193
d855497e
MI		 1194 trace_firmware("pvr2_upload_firmware2");
1195
1196 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1197 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1198 if (ret < 0) return ret;
1199 fwidx = ret;
1200 ret = 0;
b30d2441
MI		 1201 /* Since we're about to completely reinitialize the encoder,
1202 invalidate our cached copy of its configuration state. Next
1203 time we configure the encoder, then we'll fully configure it. */
1204 hdw->enc_cur_valid = 0;
d855497e
MI		 1205
1206 /* First prepare firmware loading */
1207 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1208 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1209 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1210 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1211 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1212 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1213 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1214 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1215 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1216 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1217 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1218 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1219 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1220 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1221 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1222 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
567d7115
MI		 1223 LOCK_TAKE(hdw->ctl_lock); do {
1224 hdw->cmd_buffer[0] = FX2CMD_FWPOST1;
89952d13 1225 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
567d7115
MI		 1226 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1227 hdw->cmd_buffer[1] = 0;
89952d13 1228 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
567d7115 1229 } while (0); LOCK_GIVE(hdw->ctl_lock);
d855497e
MI		 1230
1231 if (ret) {
1232 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1233 "firmware2 upload prep failed, ret=%d",ret);
1234 release_firmware(fw_entry);
1235 return ret;
1236 }
1237
1238 /* Now send firmware */
1239
1240 fw_len = fw_entry->size;
1241
90060d32 1242 if (fw_len % sizeof(u32)) {
d855497e
MI		 1243 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1244 "size of %s firmware"
48dc30a1 1245 " must be a multiple of %zu bytes",
90060d32 1246 fw_files[fwidx],sizeof(u32));
d855497e
MI		 1247 release_firmware(fw_entry);
1248 return -1;
1249 }
1250
1251 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1252 if (fw_ptr == NULL){
1253 release_firmware(fw_entry);
1254 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1255 "failed to allocate memory for firmware2 upload");
1256 return -ENOMEM;
1257 }
1258
1259 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1260
90060d32
MI		 1261 fw_done = 0;
1262 for (fw_done = 0; fw_done < fw_len;) {
1263 bcnt = fw_len - fw_done;
1264 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1265 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1266 /* Usbsnoop log shows that we must swap bytes... */
1267 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1268 ((u32 *)fw_ptr)[icnt] =
1269 ___swab32(((u32 *)fw_ptr)[icnt]);
1270
1271 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1272 &actual_length, HZ);
90060d32
MI		 1273 ret |= (actual_length != bcnt);
1274 if (ret) break;
1275 fw_done += bcnt;
d855497e
MI		 1276 }
1277
1278 trace_firmware("upload of %s : %i / %i ",
1279 fw_files[fwidx],fw_done,fw_len);
1280
1281 kfree(fw_ptr);
1282 release_firmware(fw_entry);
1283
1284 if (ret) {
1285 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1286 "firmware2 upload transfer failure");
1287 return ret;
1288 }
1289
1290 /* Finish upload */
1291
1292 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1293 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
567d7115
MI		 1294 LOCK_TAKE(hdw->ctl_lock); do {
1295 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1296 hdw->cmd_buffer[1] = 0;
89952d13 1297 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
567d7115 1298 } while (0); LOCK_GIVE(hdw->ctl_lock);
d855497e
MI		 1299
1300 if (ret) {
1301 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1302 "firmware2 upload post-proc failure");
d855497e
MI		 1303 }
1304 return ret;
1305}
1306
1307
681c7399
MI		 1308static const char *pvr2_get_state_name(unsigned int st)
1309{
1310 if (st < ARRAY_SIZE(pvr2_state_names)) {
1311 return pvr2_state_names[st];
d855497e 1312 }
681c7399 1313 return "???";
d855497e
MI		 1314}
1315
681c7399 1316static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1317{
681c7399
MI		 1318 if (!hdw->decoder_ctrl) {
1319 if (!hdw->flag_decoder_missed) {
1320 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1321 "WARNING: No decoder present");
1322 hdw->flag_decoder_missed = !0;
1323 trace_stbit("flag_decoder_missed",
1324 hdw->flag_decoder_missed);
1325 }
1326 return -EIO;
1327 }
1328 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1329 return 0;
d855497e
MI		 1330}
1331
1332
681c7399 1333void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
d855497e 1334{
681c7399
MI		 1335 if (hdw->decoder_ctrl == ptr) return;
1336 hdw->decoder_ctrl = ptr;
1337 if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1338 hdw->flag_decoder_missed = 0;
1339 trace_stbit("flag_decoder_missed",
1340 hdw->flag_decoder_missed);
1341 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1342 "Decoder has appeared");
1343 pvr2_hdw_state_sched(hdw);
1344 }
d855497e
MI		 1345}
1346
1347
681c7399 1348int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1349{
681c7399 1350 return hdw->master_state;
d855497e
MI		 1351}
1352
1353
681c7399 1354static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1355{
681c7399
MI		 1356 if (!hdw->flag_tripped) return 0;
1357 hdw->flag_tripped = 0;
1358 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1359 "Clearing driver error statuss");
1360 return !0;
d855497e
MI		 1361}
1362
1363
681c7399 1364int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1365{
681c7399 1366 int fl;
d855497e 1367 LOCK_TAKE(hdw->big_lock); do {
681c7399 1368 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1369 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1370 if (fl) pvr2_hdw_state_sched(hdw);
1371 return 0;
d855497e
MI		 1372}
1373
1374
681c7399 1375const char *pvr2_hdw_get_state_name(unsigned int id)
d855497e 1376{
681c7399
MI		 1377 if (id >= ARRAY_SIZE(pvr2_state_names)) return NULL;
1378 return pvr2_state_names[id];
d855497e
MI		 1379}
1380
1381
1382int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1383{
681c7399 1384 return hdw->state_pipeline_req != 0;
d855497e
MI		 1385}
1386
1387
1388int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1389{
681c7399 1390 int ret,st;
d855497e 1391 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1392 pvr2_hdw_untrip_unlocked(hdw);
1393 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1394 hdw->state_pipeline_req = enable_flag != 0;
1395 pvr2_trace(PVR2_TRACE_START_STOP,
1396 "/*--TRACE_STREAM--*/ %s",
1397 enable_flag ? "enable" : "disable");
1398 }
1399 pvr2_hdw_state_sched(hdw);
d855497e 1400 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1401 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1402 if (enable_flag) {
1403 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1404 if (st != PVR2_STATE_READY) return -EIO;
1405 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1406 }
1407 }
d855497e
MI		 1408 return 0;
1409}
1410
1411
1412int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1413{
681c7399 1414 int fl;
d855497e 1415 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1416 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1417 hdw->desired_stream_type = config;
1418 hdw->state_pipeline_config = 0;
1419 trace_stbit("state_pipeline_config",
1420 hdw->state_pipeline_config);
1421 pvr2_hdw_state_sched(hdw);
1422 }
d855497e 1423 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1424 if (fl) return 0;
1425 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1426}
1427
1428
1429static int get_default_tuner_type(struct pvr2_hdw *hdw)
1430{
1431 int unit_number = hdw->unit_number;
1432 int tp = -1;
1433 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1434 tp = tuner[unit_number];
1435 }
1436 if (tp < 0) return -EINVAL;
1437 hdw->tuner_type = tp;
aaf7884d 1438 hdw->tuner_updated = !0;
d855497e
MI		 1439 return 0;
1440}
1441
1442
1443static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1444{
1445 int unit_number = hdw->unit_number;
1446 int tp = 0;
1447 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1448 tp = video_std[unit_number];
6a540254 1449 if (tp) return tp;
d855497e 1450 }
6a540254 1451 return 0;
d855497e
MI		 1452}
1453
1454
1455static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1456{
1457 int unit_number = hdw->unit_number;
1458 int tp = 0;
1459 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1460 tp = tolerance[unit_number];
1461 }
1462 return tp;
1463}
1464
1465
1466static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1467{
1468 /* Try a harmless request to fetch the eeprom's address over
1469 endpoint 1. See what happens. Only the full FX2 image can
1470 respond to this. If this probe fails then likely the FX2
1471 firmware needs be loaded. */
1472 int result;
1473 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1474 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1475 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1476 hdw->cmd_buffer,1,
1477 hdw->cmd_buffer,1);
1478 if (result < 0) break;
1479 } while(0); LOCK_GIVE(hdw->ctl_lock);
1480 if (result) {
1481 pvr2_trace(PVR2_TRACE_INIT,
1482 "Probe of device endpoint 1 result status %d",
1483 result);
1484 } else {
1485 pvr2_trace(PVR2_TRACE_INIT,
1486 "Probe of device endpoint 1 succeeded");
1487 }
1488 return result == 0;
1489}
1490
9f66d4ea
MI		 1491struct pvr2_std_hack {
1492 v4l2_std_id pat; /* Pattern to match */
1493 v4l2_std_id msk; /* Which bits we care about */
1494 v4l2_std_id std; /* What additional standards or default to set */
1495};
1496
1497/* This data structure labels specific combinations of standards from
1498 tveeprom that we'll try to recognize. If we recognize one, then assume
1499 a specified default standard to use. This is here because tveeprom only
1500 tells us about available standards not the intended default standard (if
1501 any) for the device in question. We guess the default based on what has
1502 been reported as available. Note that this is only for guessing a
1503 default - which can always be overridden explicitly - and if the user
1504 has otherwise named a default then that default will always be used in
1505 place of this table. */
1506const static struct pvr2_std_hack std_eeprom_maps[] = {
1507 { /* PAL(B/G) */
1508 .pat = V4L2_STD_B|V4L2_STD_GH,
1509 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1510 },
1511 { /* NTSC(M) */
1512 .pat = V4L2_STD_MN,
1513 .std = V4L2_STD_NTSC_M,
1514 },
1515 { /* PAL(I) */
1516 .pat = V4L2_STD_PAL_I,
1517 .std = V4L2_STD_PAL_I,
1518 },
1519 { /* SECAM(L/L') */
1520 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1521 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1522 },
1523 { /* PAL(D/D1/K) */
1524 .pat = V4L2_STD_DK,
ea2562d9 1525 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
9f66d4ea
MI		 1526 },
1527};
1528
d855497e
MI		 1529static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1530{
1531 char buf[40];
1532 unsigned int bcnt;
3d290bdb 1533 v4l2_std_id std1,std2,std3;
d855497e
MI		 1534
1535 std1 = get_default_standard(hdw);
3d290bdb 1536 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
d855497e
MI		 1537
1538 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1539 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1540 "Supported video standard(s) reported available"
1541 " in hardware: %.*s",
d855497e
MI		 1542 bcnt,buf);
1543
1544 hdw->std_mask_avail = hdw->std_mask_eeprom;
1545
3d290bdb 1546 std2 = (std1|std3) & ~hdw->std_mask_avail;
d855497e
MI		 1547 if (std2) {
1548 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1549 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1550 "Expanding supported video standards"
1551 " to include: %.*s",
1552 bcnt,buf);
1553 hdw->std_mask_avail |= std2;
1554 }
1555
1556 pvr2_hdw_internal_set_std_avail(hdw);
1557
1558 if (std1) {
1559 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1560 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1561 "Initial video standard forced to %.*s",
1562 bcnt,buf);
1563 hdw->std_mask_cur = std1;
1564 hdw->std_dirty = !0;
1565 pvr2_hdw_internal_find_stdenum(hdw);
1566 return;
1567 }
3d290bdb
MI		 1568 if (std3) {
1569 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1570 pvr2_trace(PVR2_TRACE_STD,
1571 "Initial video standard"
1572 " (determined by device type): %.*s",bcnt,buf);
1573 hdw->std_mask_cur = std3;
1574 hdw->std_dirty = !0;
1575 pvr2_hdw_internal_find_stdenum(hdw);
1576 return;
1577 }
d855497e 1578
9f66d4ea
MI		 1579 {
1580 unsigned int idx;
1581 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1582 if (std_eeprom_maps[idx].msk ?
1583 ((std_eeprom_maps[idx].pat ^
1584 hdw->std_mask_eeprom) &
1585 std_eeprom_maps[idx].msk) :
1586 (std_eeprom_maps[idx].pat !=
1587 hdw->std_mask_eeprom)) continue;
1588 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1589 std_eeprom_maps[idx].std);
56585386 1590 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1591 "Initial video standard guessed as %.*s",
1592 bcnt,buf);
1593 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1594 hdw->std_dirty = !0;
1595 pvr2_hdw_internal_find_stdenum(hdw);
1596 return;
1597 }
1598 }
1599
d855497e
MI		 1600 if (hdw->std_enum_cnt > 1) {
1601 // Autoselect the first listed standard
1602 hdw->std_enum_cur = 1;
1603 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1604 hdw->std_dirty = !0;
56585386 1605 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1606 "Initial video standard auto-selected to %s",
1607 hdw->std_defs[hdw->std_enum_cur-1].name);
1608 return;
1609 }
1610
0885ba1d 1611 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1612 "Unable to select a viable initial video standard");
1613}
1614
1615
1616static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1617{
1618 int ret;
1619 unsigned int idx;
1620 struct pvr2_ctrl *cptr;
1621 int reloadFl = 0;
989eb154 1622 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 1623 if (!reloadFl) {
1624 reloadFl =
1625 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1626 == 0);
1627 if (reloadFl) {
1628 pvr2_trace(PVR2_TRACE_INIT,
1629 "USB endpoint config looks strange"
1630 "; possibly firmware needs to be"
1631 " loaded");
1632 }
d855497e 1633 }
1d643a37
MI		 1634 if (!reloadFl) {
1635 reloadFl = !pvr2_hdw_check_firmware(hdw);
1636 if (reloadFl) {
1637 pvr2_trace(PVR2_TRACE_INIT,
1638 "Check for FX2 firmware failed"
1639 "; possibly firmware needs to be"
1640 " loaded");
1641 }
d855497e 1642 }
1d643a37
MI		 1643 if (reloadFl) {
1644 if (pvr2_upload_firmware1(hdw) != 0) {
1645 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1646 "Failure uploading firmware1");
1647 }
1648 return;
d855497e 1649 }
d855497e
MI		 1650 }
1651 hdw->fw1_state = FW1_STATE_OK;
1652
1653 if (initusbreset) {
1654 pvr2_hdw_device_reset(hdw);
1655 }
1656 if (!pvr2_hdw_dev_ok(hdw)) return;
1657
989eb154
MI		 1658 for (idx = 0; idx < hdw->hdw_desc->client_modules.cnt; idx++) {
1659 request_module(hdw->hdw_desc->client_modules.lst[idx]);
d855497e
MI		 1660 }
1661
989eb154 1662 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 1663 pvr2_hdw_cmd_powerup(hdw);
1664 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 1665 }
1666
1667 // This step MUST happen after the earlier powerup step.
1668 pvr2_i2c_core_init(hdw);
1669 if (!pvr2_hdw_dev_ok(hdw)) return;
1670
c05c0462 1671 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 1672 cptr = hdw->controls + idx;
1673 if (cptr->info->skip_init) continue;
1674 if (!cptr->info->set_value) continue;
1675 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1676 }
1677
1bde0289
MI		 1678 /* Set up special default values for the television and radio
1679 frequencies here. It's not really important what these defaults
1680 are, but I set them to something usable in the Chicago area just
1681 to make driver testing a little easier. */
1682
1683 /* US Broadcast channel 7 (175.25 MHz) */
1684 hdw->freqValTelevision = 175250000L;
1685 /* 104.3 MHz, a usable FM station for my area */
1686 hdw->freqValRadio = 104300000L;
1687
d855497e
MI		 1688 // Do not use pvr2_reset_ctl_endpoints() here. It is not
1689 // thread-safe against the normal pvr2_send_request() mechanism.
1690 // (We should make it thread safe).
1691
aaf7884d
MI		 1692 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
1693 ret = pvr2_hdw_get_eeprom_addr(hdw);
d855497e 1694 if (!pvr2_hdw_dev_ok(hdw)) return;
aaf7884d
MI		 1695 if (ret < 0) {
1696 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1697 "Unable to determine location of eeprom,"
1698 " skipping");
1699 } else {
1700 hdw->eeprom_addr = ret;
1701 pvr2_eeprom_analyze(hdw);
1702 if (!pvr2_hdw_dev_ok(hdw)) return;
1703 }
1704 } else {
1705 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
1706 hdw->tuner_updated = !0;
1707 hdw->std_mask_eeprom = V4L2_STD_ALL;
d855497e
MI		 1708 }
1709
1710 pvr2_hdw_setup_std(hdw);
1711
1712 if (!get_default_tuner_type(hdw)) {
1713 pvr2_trace(PVR2_TRACE_INIT,
1714 "pvr2_hdw_setup: Tuner type overridden to %d",
1715 hdw->tuner_type);
1716 }
1717
d855497e
MI		 1718 pvr2_i2c_core_check_stale(hdw);
1719 hdw->tuner_updated = 0;
1720
1721 if (!pvr2_hdw_dev_ok(hdw)) return;
1722
681c7399 1723 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 1724
1725 hdw->vid_stream = pvr2_stream_create();
1726 if (!pvr2_hdw_dev_ok(hdw)) return;
1727 pvr2_trace(PVR2_TRACE_INIT,
1728 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1729 if (hdw->vid_stream) {
1730 idx = get_default_error_tolerance(hdw);
1731 if (idx) {
1732 pvr2_trace(PVR2_TRACE_INIT,
1733 "pvr2_hdw_setup: video stream %p"
1734 " setting tolerance %u",
1735 hdw->vid_stream,idx);
1736 }
1737 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1738 PVR2_VID_ENDPOINT,idx);
1739 }
1740
1741 if (!pvr2_hdw_dev_ok(hdw)) return;
1742
d855497e 1743 hdw->flag_init_ok = !0;
681c7399
MI		 1744
1745 pvr2_hdw_state_sched(hdw);
d855497e
MI		 1746}
1747
1748
681c7399
MI		 1749/* Set up the structure and attempt to put the device into a usable state.
1750 This can be a time-consuming operation, which is why it is not done
1751 internally as part of the create() step. */
1752static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 1753{
1754 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 1755 do {
d855497e
MI		 1756 pvr2_hdw_setup_low(hdw);
1757 pvr2_trace(PVR2_TRACE_INIT,
1758 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 1759 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 1760 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 1761 if (hdw->flag_init_ok) {
d855497e
MI		 1762 pvr2_trace(
1763 PVR2_TRACE_INFO,
1764 "Device initialization"
1765 " completed successfully.");
1766 break;
1767 }
1768 if (hdw->fw1_state == FW1_STATE_RELOAD) {
1769 pvr2_trace(
1770 PVR2_TRACE_INFO,
1771 "Device microcontroller firmware"
1772 " (re)loaded; it should now reset"
1773 " and reconnect.");
1774 break;
1775 }
1776 pvr2_trace(
1777 PVR2_TRACE_ERROR_LEGS,
1778 "Device initialization was not successful.");
1779 if (hdw->fw1_state == FW1_STATE_MISSING) {
1780 pvr2_trace(
1781 PVR2_TRACE_ERROR_LEGS,
1782 "Giving up since device"
1783 " microcontroller firmware"
1784 " appears to be missing.");
1785 break;
1786 }
1787 }
1788 if (procreload) {
1789 pvr2_trace(
1790 PVR2_TRACE_ERROR_LEGS,
1791 "Attempting pvrusb2 recovery by reloading"
1792 " primary firmware.");
1793 pvr2_trace(
1794 PVR2_TRACE_ERROR_LEGS,
1795 "If this works, device should disconnect"
1796 " and reconnect in a sane state.");
1797 hdw->fw1_state = FW1_STATE_UNKNOWN;
1798 pvr2_upload_firmware1(hdw);
1799 } else {
1800 pvr2_trace(
1801 PVR2_TRACE_ERROR_LEGS,
1802 "***WARNING*** pvrusb2 device hardware"
1803 " appears to be jammed"
1804 " and I can't clear it.");
1805 pvr2_trace(
1806 PVR2_TRACE_ERROR_LEGS,
1807 "You might need to power cycle"
1808 " the pvrusb2 device"
1809 " in order to recover.");
1810 }
681c7399 1811 } while (0);
d855497e 1812 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 1813}
1814
1815
1816/* Create and return a structure for interacting with the underlying
1817 hardware */
1818struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1819 const struct usb_device_id *devid)
1820{
7fb20fa3 1821 unsigned int idx,cnt1,cnt2,m;
d855497e 1822 struct pvr2_hdw *hdw;
d855497e
MI		 1823 int valid_std_mask;
1824 struct pvr2_ctrl *cptr;
989eb154 1825 const struct pvr2_device_desc *hdw_desc;
d855497e 1826 __u8 ifnum;
b30d2441
MI		 1827 struct v4l2_queryctrl qctrl;
1828 struct pvr2_ctl_info *ciptr;
d855497e 1829
d130fa8a 1830 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
d855497e 1831
ca545f7c 1832 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 1833 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 1834 hdw,hdw_desc->description);
d855497e 1835 if (!hdw) goto fail;
681c7399
MI		 1836
1837 init_timer(&hdw->quiescent_timer);
1838 hdw->quiescent_timer.data = (unsigned long)hdw;
1839 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
1840
1841 init_timer(&hdw->encoder_wait_timer);
1842 hdw->encoder_wait_timer.data = (unsigned long)hdw;
1843 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
1844
1845 hdw->master_state = PVR2_STATE_DEAD;
1846
1847 init_waitqueue_head(&hdw->state_wait_data);
1848
18103c57 1849 hdw->tuner_signal_stale = !0;
b30d2441 1850 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 1851
7fb20fa3
MI		 1852 /* Calculate which inputs are OK */
1853 m = 0;
1854 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
1855 if (hdw_desc->flag_has_digitaltuner) m |= 1 << PVR2_CVAL_INPUT_DTV;
1856 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
1857 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
1858 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
1859 hdw->input_avail_mask = m;
1860
c05c0462 1861 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 1862 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 1863 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 1864 GFP_KERNEL);
1865 if (!hdw->controls) goto fail;
989eb154 1866 hdw->hdw_desc = hdw_desc;
c05c0462
MI		 1867 for (idx = 0; idx < hdw->control_cnt; idx++) {
1868 cptr = hdw->controls + idx;
1869 cptr->hdw = hdw;
1870 }
d855497e
MI		 1871 for (idx = 0; idx < 32; idx++) {
1872 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1873 }
c05c0462 1874 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 1875 cptr = hdw->controls + idx;
d855497e
MI		 1876 cptr->info = control_defs+idx;
1877 }
b30d2441 1878 /* Define and configure additional controls from cx2341x module. */
ca545f7c 1879 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 1880 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1881 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 1882 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1883 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1884 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1885 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1886 ciptr->name = mpeg_ids[idx].strid;
1887 ciptr->v4l_id = mpeg_ids[idx].id;
1888 ciptr->skip_init = !0;
1889 ciptr->get_value = ctrl_cx2341x_get;
1890 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1891 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1892 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1893 qctrl.id = ciptr->v4l_id;
1894 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1895 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1896 ciptr->set_value = ctrl_cx2341x_set;
1897 }
1898 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1899 PVR2_CTLD_INFO_DESC_SIZE);
1900 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
1901 ciptr->default_value = qctrl.default_value;
1902 switch (qctrl.type) {
1903 default:
1904 case V4L2_CTRL_TYPE_INTEGER:
1905 ciptr->type = pvr2_ctl_int;
1906 ciptr->def.type_int.min_value = qctrl.minimum;
1907 ciptr->def.type_int.max_value = qctrl.maximum;
1908 break;
1909 case V4L2_CTRL_TYPE_BOOLEAN:
1910 ciptr->type = pvr2_ctl_bool;
1911 break;
1912 case V4L2_CTRL_TYPE_MENU:
1913 ciptr->type = pvr2_ctl_enum;
1914 ciptr->def.type_enum.value_names =
1915 cx2341x_ctrl_get_menu(ciptr->v4l_id);
1916 for (cnt1 = 0;
1917 ciptr->def.type_enum.value_names[cnt1] != NULL;
1918 cnt1++) { }
1919 ciptr->def.type_enum.count = cnt1;
1920 break;
1921 }
1922 cptr->info = ciptr;
1923 }
d855497e
MI		 1924
1925 // Initialize video standard enum dynamic control
1926 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1927 if (cptr) {
1928 memcpy(&hdw->std_info_enum,cptr->info,
1929 sizeof(hdw->std_info_enum));
1930 cptr->info = &hdw->std_info_enum;
1931
1932 }
1933 // Initialize control data regarding video standard masks
1934 valid_std_mask = pvr2_std_get_usable();
1935 for (idx = 0; idx < 32; idx++) {
1936 if (!(valid_std_mask & (1 << idx))) continue;
1937 cnt1 = pvr2_std_id_to_str(
1938 hdw->std_mask_names[idx],
1939 sizeof(hdw->std_mask_names[idx])-1,
1940 1 << idx);
1941 hdw->std_mask_names[idx][cnt1] = 0;
1942 }
1943 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1944 if (cptr) {
1945 memcpy(&hdw->std_info_avail,cptr->info,
1946 sizeof(hdw->std_info_avail));
1947 cptr->info = &hdw->std_info_avail;
1948 hdw->std_info_avail.def.type_bitmask.bit_names =
1949 hdw->std_mask_ptrs;
1950 hdw->std_info_avail.def.type_bitmask.valid_bits =
1951 valid_std_mask;
1952 }
1953 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1954 if (cptr) {
1955 memcpy(&hdw->std_info_cur,cptr->info,
1956 sizeof(hdw->std_info_cur));
1957 cptr->info = &hdw->std_info_cur;
1958 hdw->std_info_cur.def.type_bitmask.bit_names =
1959 hdw->std_mask_ptrs;
1960 hdw->std_info_avail.def.type_bitmask.valid_bits =
1961 valid_std_mask;
1962 }
1963
1964 hdw->eeprom_addr = -1;
1965 hdw->unit_number = -1;
8079384e
MI		 1966 hdw->v4l_minor_number_video = -1;
1967 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 1968 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 1969 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1970 if (!hdw->ctl_write_buffer) goto fail;
1971 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1972 if (!hdw->ctl_read_buffer) goto fail;
1973 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
1974 if (!hdw->ctl_write_urb) goto fail;
1975 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
1976 if (!hdw->ctl_read_urb) goto fail;
1977
8df0c87c 1978 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 1979 for (idx = 0; idx < PVR_NUM; idx++) {
1980 if (unit_pointers[idx]) continue;
1981 hdw->unit_number = idx;
1982 unit_pointers[idx] = hdw;
1983 break;
1984 }
8df0c87c 1985 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 1986
1987 cnt1 = 0;
1988 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
1989 cnt1 += cnt2;
1990 if (hdw->unit_number >= 0) {
1991 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
1992 ('a' + hdw->unit_number));
1993 cnt1 += cnt2;
1994 }
1995 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
1996 hdw->name[cnt1] = 0;
1997
681c7399
MI		 1998 hdw->workqueue = create_singlethread_workqueue(hdw->name);
1999 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2000 INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2001 INIT_WORK(&hdw->workinit,pvr2_hdw_worker_init);
2002
d855497e
MI		 2003 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2004 hdw->unit_number,hdw->name);
2005
2006 hdw->tuner_type = -1;
2007 hdw->flag_ok = !0;
d855497e
MI		 2008
2009 hdw->usb_intf = intf;
2010 hdw->usb_dev = interface_to_usbdev(intf);
2011
31a18547
MI		 2012 scnprintf(hdw->bus_info,sizeof(hdw->bus_info),
2013 "usb %s address %d",
2014 hdw->usb_dev->dev.bus_id,
2015 hdw->usb_dev->devnum);
2016
d855497e
MI		 2017 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2018 usb_set_interface(hdw->usb_dev,ifnum,0);
2019
2020 mutex_init(&hdw->ctl_lock_mutex);
2021 mutex_init(&hdw->big_lock_mutex);
2022
681c7399 2023 queue_work(hdw->workqueue,&hdw->workinit);
d855497e
MI		 2024 return hdw;
2025 fail:
2026 if (hdw) {
681c7399
MI		 2027 del_timer_sync(&hdw->quiescent_timer);
2028 del_timer_sync(&hdw->encoder_wait_timer);
2029 if (hdw->workqueue) {
2030 flush_workqueue(hdw->workqueue);
2031 destroy_workqueue(hdw->workqueue);
2032 hdw->workqueue = NULL;
2033 }
5e55d2ce
MK		 2034 usb_free_urb(hdw->ctl_read_urb);
2035 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2036 kfree(hdw->ctl_read_buffer);
2037 kfree(hdw->ctl_write_buffer);
2038 kfree(hdw->controls);
2039 kfree(hdw->mpeg_ctrl_info);
681c7399
MI		 2040 kfree(hdw->std_defs);
2041 kfree(hdw->std_enum_names);
d855497e
MI		 2042 kfree(hdw);
2043 }
a0fd1cb1 2044 return NULL;
d855497e
MI		 2045}
2046
2047
2048/* Remove _all_ associations between this driver and the underlying USB
2049 layer. */
07e337ee 2050static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2051{
2052 if (hdw->flag_disconnected) return;
2053 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2054 if (hdw->ctl_read_urb) {
2055 usb_kill_urb(hdw->ctl_read_urb);
2056 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2057 hdw->ctl_read_urb = NULL;
d855497e
MI		 2058 }
2059 if (hdw->ctl_write_urb) {
2060 usb_kill_urb(hdw->ctl_write_urb);
2061 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2062 hdw->ctl_write_urb = NULL;
d855497e
MI		 2063 }
2064 if (hdw->ctl_read_buffer) {
2065 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2066 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2067 }
2068 if (hdw->ctl_write_buffer) {
2069 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2070 hdw->ctl_write_buffer = NULL;
d855497e 2071 }
d855497e 2072 hdw->flag_disconnected = !0;
a0fd1cb1
MI		 2073 hdw->usb_dev = NULL;
2074 hdw->usb_intf = NULL;
681c7399 2075 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2076}
2077
2078
2079/* Destroy hardware interaction structure */
2080void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2081{
401c27ce 2082 if (!hdw) return;
d855497e 2083 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2084 del_timer_sync(&hdw->quiescent_timer);
2085 del_timer_sync(&hdw->encoder_wait_timer);
2086 if (hdw->workqueue) {
2087 flush_workqueue(hdw->workqueue);
2088 destroy_workqueue(hdw->workqueue);
2089 hdw->workqueue = NULL;
2090 }
d855497e
MI		 2091 if (hdw->fw_buffer) {
2092 kfree(hdw->fw_buffer);
a0fd1cb1 2093 hdw->fw_buffer = NULL;
d855497e
MI		 2094 }
2095 if (hdw->vid_stream) {
2096 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2097 hdw->vid_stream = NULL;
d855497e 2098 }
d855497e
MI		 2099 if (hdw->decoder_ctrl) {
2100 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2101 }
2102 pvr2_i2c_core_done(hdw);
2103 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2104 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2105 if ((hdw->unit_number >= 0) &&
2106 (hdw->unit_number < PVR_NUM) &&
2107 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2108 unit_pointers[hdw->unit_number] = NULL;
d855497e 2109 }
8df0c87c 2110 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2111 kfree(hdw->controls);
2112 kfree(hdw->mpeg_ctrl_info);
2113 kfree(hdw->std_defs);
2114 kfree(hdw->std_enum_names);
d855497e
MI		 2115 kfree(hdw);
2116}
2117
2118
d855497e
MI		 2119int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2120{
2121 return (hdw && hdw->flag_ok);
2122}
2123
2124
2125/* Called when hardware has been unplugged */
2126void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2127{
2128 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2129 LOCK_TAKE(hdw->big_lock);
2130 LOCK_TAKE(hdw->ctl_lock);
2131 pvr2_hdw_remove_usb_stuff(hdw);
2132 LOCK_GIVE(hdw->ctl_lock);
2133 LOCK_GIVE(hdw->big_lock);
2134}
2135
2136
2137// Attempt to autoselect an appropriate value for std_enum_cur given
2138// whatever is currently in std_mask_cur
07e337ee 2139static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2140{
2141 unsigned int idx;
2142 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2143 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2144 hdw->std_enum_cur = idx;
2145 return;
2146 }
2147 }
2148 hdw->std_enum_cur = 0;
2149}
2150
2151
2152// Calculate correct set of enumerated standards based on currently known
2153// set of available standards bits.
07e337ee 2154static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2155{
2156 struct v4l2_standard *newstd;
2157 unsigned int std_cnt;
2158 unsigned int idx;
2159
2160 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2161
2162 if (hdw->std_defs) {
2163 kfree(hdw->std_defs);
a0fd1cb1 2164 hdw->std_defs = NULL;
d855497e
MI		 2165 }
2166 hdw->std_enum_cnt = 0;
2167 if (hdw->std_enum_names) {
2168 kfree(hdw->std_enum_names);
a0fd1cb1 2169 hdw->std_enum_names = NULL;
d855497e
MI		 2170 }
2171
2172 if (!std_cnt) {
2173 pvr2_trace(
2174 PVR2_TRACE_ERROR_LEGS,
2175 "WARNING: Failed to identify any viable standards");
2176 }
2177 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2178 hdw->std_enum_names[0] = "none";
2179 for (idx = 0; idx < std_cnt; idx++) {
2180 hdw->std_enum_names[idx+1] =
2181 newstd[idx].name;
2182 }
2183 // Set up the dynamic control for this standard
2184 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2185 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2186 hdw->std_defs = newstd;
2187 hdw->std_enum_cnt = std_cnt+1;
2188 hdw->std_enum_cur = 0;
2189 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2190}
2191
2192
2193int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2194 struct v4l2_standard *std,
2195 unsigned int idx)
2196{
2197 int ret = -EINVAL;
2198 if (!idx) return ret;
2199 LOCK_TAKE(hdw->big_lock); do {
2200 if (idx >= hdw->std_enum_cnt) break;
2201 idx--;
2202 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2203 ret = 0;
2204 } while (0); LOCK_GIVE(hdw->big_lock);
2205 return ret;
2206}
2207
2208
2209/* Get the number of defined controls */
2210unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2211{
c05c0462 2212 return hdw->control_cnt;
d855497e
MI		 2213}
2214
2215
2216/* Retrieve a control handle given its index (0..count-1) */
2217struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2218 unsigned int idx)
2219{
a0fd1cb1 2220 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2221 return hdw->controls + idx;
2222}
2223
2224
2225/* Retrieve a control handle given its index (0..count-1) */
2226struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2227 unsigned int ctl_id)
2228{
2229 struct pvr2_ctrl *cptr;
2230 unsigned int idx;
2231 int i;
2232
2233 /* This could be made a lot more efficient, but for now... */
c05c0462 2234 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2235 cptr = hdw->controls + idx;
2236 i = cptr->info->internal_id;
2237 if (i && (i == ctl_id)) return cptr;
2238 }
a0fd1cb1 2239 return NULL;
d855497e
MI		 2240}
2241
2242
a761f431 2243/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2244struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2245{
2246 struct pvr2_ctrl *cptr;
2247 unsigned int idx;
2248 int i;
2249
2250 /* This could be made a lot more efficient, but for now... */
c05c0462 2251 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2252 cptr = hdw->controls + idx;
2253 i = cptr->info->v4l_id;
2254 if (i && (i == ctl_id)) return cptr;
2255 }
a0fd1cb1 2256 return NULL;
d855497e
MI		 2257}
2258
2259
a761f431
MI		 2260/* Given a V4L ID for its immediate predecessor, retrieve the control
2261 structure associated with it. */
2262struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2263 unsigned int ctl_id)
2264{
2265 struct pvr2_ctrl *cptr,*cp2;
2266 unsigned int idx;
2267 int i;
2268
2269 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2270 cp2 = NULL;
a761f431
MI		 2271 for (idx = 0; idx < hdw->control_cnt; idx++) {
2272 cptr = hdw->controls + idx;
2273 i = cptr->info->v4l_id;
2274 if (!i) continue;
2275 if (i <= ctl_id) continue;
2276 if (cp2 && (cp2->info->v4l_id < i)) continue;
2277 cp2 = cptr;
2278 }
2279 return cp2;
a0fd1cb1 2280 return NULL;
a761f431
MI		 2281}
2282
2283
d855497e
MI		 2284static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2285{
2286 switch (tp) {
2287 case pvr2_ctl_int: return "integer";
2288 case pvr2_ctl_enum: return "enum";
33213963 2289 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2290 case pvr2_ctl_bitmask: return "bitmask";
2291 }
2292 return "";
2293}
2294
2295
681c7399
MI		 2296/* Figure out if we need to commit control changes. If so, mark internal
2297 state flags to indicate this fact and return true. Otherwise do nothing
2298 else and return false. */
2299static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 2300{
d855497e
MI		 2301 unsigned int idx;
2302 struct pvr2_ctrl *cptr;
2303 int value;
2304 int commit_flag = 0;
2305 char buf[100];
2306 unsigned int bcnt,ccnt;
2307
c05c0462 2308 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e 2309 cptr = hdw->controls + idx;
5fa1247a 2310 if (!cptr->info->is_dirty) continue;
d855497e 2311 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 2312 commit_flag = !0;
d855497e 2313
fe23a280 2314 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 2315 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2316 cptr->info->name);
2317 value = 0;
2318 cptr->info->get_value(cptr,&value);
2319 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2320 buf+bcnt,
2321 sizeof(buf)-bcnt,&ccnt);
2322 bcnt += ccnt;
2323 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2324 get_ctrl_typename(cptr->info->type));
2325 pvr2_trace(PVR2_TRACE_CTL,
2326 "/*--TRACE_COMMIT--*/ %.*s",
2327 bcnt,buf);
2328 }
2329
2330 if (!commit_flag) {
2331 /* Nothing has changed */
2332 return 0;
2333 }
2334
681c7399
MI		 2335 hdw->state_pipeline_config = 0;
2336 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2337 pvr2_hdw_state_sched(hdw);
2338
2339 return !0;
2340}
2341
2342
2343/* Perform all operations needed to commit all control changes. This must
2344 be performed in synchronization with the pipeline state and is thus
2345 expected to be called as part of the driver's worker thread. Return
2346 true if commit successful, otherwise return false to indicate that
2347 commit isn't possible at this time. */
2348static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
2349{
2350 unsigned int idx;
2351 struct pvr2_ctrl *cptr;
2352 int disruptive_change;
2353
d855497e
MI		 2354 /* When video standard changes, reset the hres and vres values -
2355 but if the user has pending changes there, then let the changes
2356 take priority. */
2357 if (hdw->std_dirty) {
2358 /* Rewrite the vertical resolution to be appropriate to the
2359 video standard that has been selected. */
2360 int nvres;
2361 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2362 nvres = 480;
2363 } else {
2364 nvres = 576;
2365 }
2366 if (nvres != hdw->res_ver_val) {
2367 hdw->res_ver_val = nvres;
2368 hdw->res_ver_dirty = !0;
2369 }
d855497e
MI		 2370 }
2371
681c7399
MI		 2372 /* If any of the below has changed, then we can't do the update
2373 while the pipeline is running. Pipeline must be paused first
2374 and decoder -> encoder connection be made quiescent before we
2375 can proceed. */
2376 disruptive_change =
2377 (hdw->std_dirty ||
2378 hdw->enc_unsafe_stale ||
2379 hdw->srate_dirty ||
2380 hdw->res_ver_dirty ||
2381 hdw->res_hor_dirty ||
2382 hdw->input_dirty ||
2383 (hdw->active_stream_type != hdw->desired_stream_type));
2384 if (disruptive_change && !hdw->state_pipeline_idle) {
2385 /* Pipeline is not idle; we can't proceed. Arrange to
2386 cause pipeline to stop so that we can try this again
2387 later.... */
2388 hdw->state_pipeline_pause = !0;
2389 return 0;
275b2e28
PK		 2390 }
2391
b30d2441
MI		 2392 if (hdw->srate_dirty) {
2393 /* Write new sample rate into control structure since
2394 * the master copy is stale. We must track srate
2395 * separate from the mpeg control structure because
2396 * other logic also uses this value. */
2397 struct v4l2_ext_controls cs;
2398 struct v4l2_ext_control c1;
2399 memset(&cs,0,sizeof(cs));
2400 memset(&c1,0,sizeof(c1));
2401 cs.controls = &c1;
2402 cs.count = 1;
2403 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2404 c1.value = hdw->srate_val;
01f1e44f 2405 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 2406 }
c05c0462 2407
d855497e
MI		 2408 /* Scan i2c core at this point - before we clear all the dirty
2409 bits. Various parts of the i2c core will notice dirty bits as
2410 appropriate and arrange to broadcast or directly send updates to
2411 the client drivers in order to keep everything in sync */
2412 pvr2_i2c_core_check_stale(hdw);
2413
c05c0462 2414 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2415 cptr = hdw->controls + idx;
2416 if (!cptr->info->clear_dirty) continue;
2417 cptr->info->clear_dirty(cptr);
2418 }
2419
681c7399
MI		 2420 if (hdw->active_stream_type != hdw->desired_stream_type) {
2421 /* Handle any side effects of stream config here */
2422 hdw->active_stream_type = hdw->desired_stream_type;
2423 }
2424
d855497e
MI		 2425 /* Now execute i2c core update */
2426 pvr2_i2c_core_sync(hdw);
2427
681c7399
MI		 2428 if (hdw->state_encoder_run) {
2429 /* If encoder isn't running, then this will get worked out
2430 later when we start the encoder. */
2431 if (pvr2_encoder_adjust(hdw) < 0) return !0;
2432 }
d855497e 2433
681c7399
MI		 2434 hdw->state_pipeline_config = !0;
2435 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2436 return !0;
d855497e
MI		 2437}
2438
2439
2440int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2441{
681c7399
MI		 2442 int fl;
2443 LOCK_TAKE(hdw->big_lock);
2444 fl = pvr2_hdw_commit_setup(hdw);
2445 LOCK_GIVE(hdw->big_lock);
2446 if (!fl) return 0;
2447 return pvr2_hdw_wait(hdw,0);
2448}
2449
2450
2451static void pvr2_hdw_worker_i2c(struct work_struct *work)
2452{
2453 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
d855497e 2454 LOCK_TAKE(hdw->big_lock); do {
681c7399 2455 pvr2_i2c_core_sync(hdw);
d855497e 2456 } while (0); LOCK_GIVE(hdw->big_lock);
d855497e
MI		 2457}
2458
2459
681c7399 2460static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 2461{
681c7399
MI		 2462 int fl = 0;
2463 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 2464 LOCK_TAKE(hdw->big_lock); do {
681c7399 2465 fl = pvr2_hdw_state_eval(hdw);
d855497e 2466 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 2467 if (fl && hdw->state_func) {
2468 hdw->state_func(hdw->state_data);
2469 }
d855497e
MI		 2470}
2471
2472
681c7399 2473static void pvr2_hdw_worker_init(struct work_struct *work)
d855497e 2474{
681c7399 2475 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workinit);
d855497e 2476 LOCK_TAKE(hdw->big_lock); do {
681c7399 2477 pvr2_hdw_setup(hdw);
d855497e
MI		 2478 } while (0); LOCK_GIVE(hdw->big_lock);
2479}
2480
2481
681c7399 2482static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 2483{
681c7399
MI		 2484 return wait_event_interruptible(
2485 hdw->state_wait_data,
2486 (hdw->state_stale == 0) &&
2487 (!state || (hdw->master_state != state)));
2488}
2489
2490
2491void pvr2_hdw_set_state_callback(struct pvr2_hdw *hdw,
2492 void (*callback_func)(void *),
2493 void *callback_data)
2494{
2495 LOCK_TAKE(hdw->big_lock); do {
2496 hdw->state_data = callback_data;
2497 hdw->state_func = callback_func;
2498 } while (0); LOCK_GIVE(hdw->big_lock);
d855497e
MI		 2499}
2500
681c7399 2501
d855497e
MI		 2502/* Return name for this driver instance */
2503const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2504{
2505 return hdw->name;
2506}
2507
2508
78a47101
MI		 2509const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
2510{
2511 return hdw->hdw_desc->description;
2512}
2513
2514
2515const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
2516{
2517 return hdw->hdw_desc->shortname;
2518}
2519
2520
d855497e
MI		 2521int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2522{
2523 int result;
2524 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 2525 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 2526 result = pvr2_send_request(hdw,
2527 hdw->cmd_buffer,1,
2528 hdw->cmd_buffer,1);
2529 if (result < 0) break;
2530 result = (hdw->cmd_buffer[0] != 0);
2531 } while(0); LOCK_GIVE(hdw->ctl_lock);
2532 return result;
2533}
2534
2535
18103c57
MI		 2536/* Execute poll of tuner status */
2537void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 2538{
d855497e 2539 LOCK_TAKE(hdw->big_lock); do {
18103c57 2540 pvr2_i2c_core_status_poll(hdw);
d855497e 2541 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 2542}
2543
2544
2545/* Return information about the tuner */
2546int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
2547{
2548 LOCK_TAKE(hdw->big_lock); do {
2549 if (hdw->tuner_signal_stale) {
2550 pvr2_i2c_core_status_poll(hdw);
2551 }
2552 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
2553 } while (0); LOCK_GIVE(hdw->big_lock);
2554 return 0;
d855497e
MI		 2555}
2556
2557
2558/* Get handle to video output stream */
2559struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2560{
2561 return hp->vid_stream;
2562}
2563
2564
2565void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2566{
4f1a3e5b 2567 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e
MI		 2568 LOCK_TAKE(hdw->big_lock); do {
2569 hdw->log_requested = !0;
4f1a3e5b 2570 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
d855497e
MI		 2571 pvr2_i2c_core_check_stale(hdw);
2572 hdw->log_requested = 0;
2573 pvr2_i2c_core_sync(hdw);
b30d2441 2574 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 2575 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 2576 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 2577 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 2578 } while (0); LOCK_GIVE(hdw->big_lock);
2579}
2580
4db666cc
MI		 2581
2582/* Grab EEPROM contents, needed for direct method. */
2583#define EEPROM_SIZE 8192
2584#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
2585static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
2586{
2587 struct i2c_msg msg[2];
2588 u8 *eeprom;
2589 u8 iadd[2];
2590 u8 addr;
2591 u16 eepromSize;
2592 unsigned int offs;
2593 int ret;
2594 int mode16 = 0;
2595 unsigned pcnt,tcnt;
2596 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
2597 if (!eeprom) {
2598 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2599 "Failed to allocate memory"
2600 " required to read eeprom");
2601 return NULL;
2602 }
2603
2604 trace_eeprom("Value for eeprom addr from controller was 0x%x",
2605 hdw->eeprom_addr);
2606 addr = hdw->eeprom_addr;
2607 /* Seems that if the high bit is set, then the *real* eeprom
2608 address is shifted right now bit position (noticed this in
2609 newer PVR USB2 hardware) */
2610 if (addr & 0x80) addr >>= 1;
2611
2612 /* FX2 documentation states that a 16bit-addressed eeprom is
2613 expected if the I2C address is an odd number (yeah, this is
2614 strange but it's what they do) */
2615 mode16 = (addr & 1);
2616 eepromSize = (mode16 ? EEPROM_SIZE : 256);
2617 trace_eeprom("Examining %d byte eeprom at location 0x%x"
2618 " using %d bit addressing",eepromSize,addr,
2619 mode16 ? 16 : 8);
2620
2621 msg[0].addr = addr;
2622 msg[0].flags = 0;
2623 msg[0].len = mode16 ? 2 : 1;
2624 msg[0].buf = iadd;
2625 msg[1].addr = addr;
2626 msg[1].flags = I2C_M_RD;
2627
2628 /* We have to do the actual eeprom data fetch ourselves, because
2629 (1) we're only fetching part of the eeprom, and (2) if we were
2630 getting the whole thing our I2C driver can't grab it in one
2631 pass - which is what tveeprom is otherwise going to attempt */
2632 memset(eeprom,0,EEPROM_SIZE);
2633 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
2634 pcnt = 16;
2635 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
2636 offs = tcnt + (eepromSize - EEPROM_SIZE);
2637 if (mode16) {
2638 iadd[0] = offs >> 8;
2639 iadd[1] = offs;
2640 } else {
2641 iadd[0] = offs;
2642 }
2643 msg[1].len = pcnt;
2644 msg[1].buf = eeprom+tcnt;
2645 if ((ret = i2c_transfer(&hdw->i2c_adap,
2646 msg,ARRAY_SIZE(msg))) != 2) {
2647 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2648 "eeprom fetch set offs err=%d",ret);
2649 kfree(eeprom);
2650 return NULL;
2651 }
2652 }
2653 return eeprom;
2654}
2655
2656
2657void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
2658 int prom_flag,
2659 int enable_flag)
d855497e
MI		 2660{
2661 int ret;
2662 u16 address;
2663 unsigned int pipe;
2664 LOCK_TAKE(hdw->big_lock); do {
5fa1247a 2665 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
d855497e
MI		 2666
2667 if (!enable_flag) {
2668 pvr2_trace(PVR2_TRACE_FIRMWARE,
2669 "Cleaning up after CPU firmware fetch");
2670 kfree(hdw->fw_buffer);
a0fd1cb1 2671 hdw->fw_buffer = NULL;
d855497e 2672 hdw->fw_size = 0;
4db666cc
MI		 2673 if (hdw->fw_cpu_flag) {
2674 /* Now release the CPU. It will disconnect
2675 and reconnect later. */
2676 pvr2_hdw_cpureset_assert(hdw,0);
2677 }
d855497e
MI		 2678 break;
2679 }
2680
4db666cc
MI		 2681 hdw->fw_cpu_flag = (prom_flag == 0);
2682 if (hdw->fw_cpu_flag) {
2683 pvr2_trace(PVR2_TRACE_FIRMWARE,
2684 "Preparing to suck out CPU firmware");
2685 hdw->fw_size = 0x2000;
2686 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
2687 if (!hdw->fw_buffer) {
2688 hdw->fw_size = 0;
2689 break;
2690 }
d855497e 2691
4db666cc
MI		 2692 /* We have to hold the CPU during firmware upload. */
2693 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 2694
4db666cc
MI		 2695 /* download the firmware from address 0000-1fff in 2048
2696 (=0x800) bytes chunk. */
d855497e 2697
4db666cc
MI		 2698 pvr2_trace(PVR2_TRACE_FIRMWARE,
2699 "Grabbing CPU firmware");
2700 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2701 for(address = 0; address < hdw->fw_size;
2702 address += 0x800) {
2703 ret = usb_control_msg(hdw->usb_dev,pipe,
2704 0xa0,0xc0,
2705 address,0,
2706 hdw->fw_buffer+address,
2707 0x800,HZ);
2708 if (ret < 0) break;
2709 }
d855497e 2710
4db666cc
MI		 2711 pvr2_trace(PVR2_TRACE_FIRMWARE,
2712 "Done grabbing CPU firmware");
2713 } else {
2714 pvr2_trace(PVR2_TRACE_FIRMWARE,
2715 "Sucking down EEPROM contents");
2716 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
2717 if (!hdw->fw_buffer) {
2718 pvr2_trace(PVR2_TRACE_FIRMWARE,
2719 "EEPROM content suck failed.");
2720 break;
2721 }
2722 hdw->fw_size = EEPROM_SIZE;
2723 pvr2_trace(PVR2_TRACE_FIRMWARE,
2724 "Done sucking down EEPROM contents");
2725 }
d855497e
MI		 2726
2727 } while (0); LOCK_GIVE(hdw->big_lock);
2728}
2729
2730
2731/* Return true if we're in a mode for retrieval CPU firmware */
2732int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2733{
5fa1247a 2734 return hdw->fw_buffer != NULL;
d855497e
MI		 2735}
2736
2737
2738int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2739 char *buf,unsigned int cnt)
2740{
2741 int ret = -EINVAL;
2742 LOCK_TAKE(hdw->big_lock); do {
2743 if (!buf) break;
2744 if (!cnt) break;
2745
2746 if (!hdw->fw_buffer) {
2747 ret = -EIO;
2748 break;
2749 }
2750
2751 if (offs >= hdw->fw_size) {
2752 pvr2_trace(PVR2_TRACE_FIRMWARE,
2753 "Read firmware data offs=%d EOF",
2754 offs);
2755 ret = 0;
2756 break;
2757 }
2758
2759 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2760
2761 memcpy(buf,hdw->fw_buffer+offs,cnt);
2762
2763 pvr2_trace(PVR2_TRACE_FIRMWARE,
2764 "Read firmware data offs=%d cnt=%d",
2765 offs,cnt);
2766 ret = cnt;
2767 } while (0); LOCK_GIVE(hdw->big_lock);
2768
2769 return ret;
2770}
2771
2772
fd5a75fe 2773int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 2774 enum pvr2_v4l_type index)
d855497e 2775{
fd5a75fe 2776 switch (index) {
8079384e
MI		 2777 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
2778 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
2779 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 2780 default: return -1;
2781 }
d855497e
MI		 2782}
2783
2784
2fdf3d9c 2785/* Store a v4l minor device number */
fd5a75fe 2786void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 2787 enum pvr2_v4l_type index,int v)
d855497e 2788{
fd5a75fe 2789 switch (index) {
8079384e
MI		 2790 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
2791 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
2792 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 2793 default: break;
2794 }
d855497e
MI		 2795}
2796
2797
7d12e780 2798static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 2799{
2800 struct pvr2_hdw *hdw = urb->context;
2801 hdw->ctl_write_pend_flag = 0;
2802 if (hdw->ctl_read_pend_flag) return;
2803 complete(&hdw->ctl_done);
2804}
2805
2806
7d12e780 2807static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 2808{
2809 struct pvr2_hdw *hdw = urb->context;
2810 hdw->ctl_read_pend_flag = 0;
2811 if (hdw->ctl_write_pend_flag) return;
2812 complete(&hdw->ctl_done);
2813}
2814
2815
2816static void pvr2_ctl_timeout(unsigned long data)
2817{
2818 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2819 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2820 hdw->ctl_timeout_flag = !0;
5e55d2ce 2821 if (hdw->ctl_write_pend_flag)
d855497e 2822 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 2823 if (hdw->ctl_read_pend_flag)
d855497e 2824 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 2825 }
2826}
2827
2828
e61b6fc5
MI		 2829/* Issue a command and get a response from the device. This extended
2830 version includes a probe flag (which if set means that device errors
2831 should not be logged or treated as fatal) and a timeout in jiffies.
2832 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 2833static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2834 unsigned int timeout,int probe_fl,
2835 void *write_data,unsigned int write_len,
2836 void *read_data,unsigned int read_len)
d855497e
MI		 2837{
2838 unsigned int idx;
2839 int status = 0;
2840 struct timer_list timer;
2841 if (!hdw->ctl_lock_held) {
2842 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2843 "Attempted to execute control transfer"
2844 " without lock!!");
2845 return -EDEADLK;
2846 }
681c7399 2847 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 2848 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2849 "Attempted to execute control transfer"
2850 " when device not ok");
2851 return -EIO;
2852 }
2853 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2854 if (!probe_fl) {
2855 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2856 "Attempted to execute control transfer"
2857 " when USB is disconnected");
2858 }
2859 return -ENOTTY;
2860 }
2861
2862 /* Ensure that we have sane parameters */
2863 if (!write_data) write_len = 0;
2864 if (!read_data) read_len = 0;
2865 if (write_len > PVR2_CTL_BUFFSIZE) {
2866 pvr2_trace(
2867 PVR2_TRACE_ERROR_LEGS,
2868 "Attempted to execute %d byte"
2869 " control-write transfer (limit=%d)",
2870 write_len,PVR2_CTL_BUFFSIZE);
2871 return -EINVAL;
2872 }
2873 if (read_len > PVR2_CTL_BUFFSIZE) {
2874 pvr2_trace(
2875 PVR2_TRACE_ERROR_LEGS,
2876 "Attempted to execute %d byte"
2877 " control-read transfer (limit=%d)",
2878 write_len,PVR2_CTL_BUFFSIZE);
2879 return -EINVAL;
2880 }
2881 if ((!write_len) && (!read_len)) {
2882 pvr2_trace(
2883 PVR2_TRACE_ERROR_LEGS,
2884 "Attempted to execute null control transfer?");
2885 return -EINVAL;
2886 }
2887
2888
2889 hdw->cmd_debug_state = 1;
2890 if (write_len) {
2891 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2892 } else {
2893 hdw->cmd_debug_code = 0;
2894 }
2895 hdw->cmd_debug_write_len = write_len;
2896 hdw->cmd_debug_read_len = read_len;
2897
2898 /* Initialize common stuff */
2899 init_completion(&hdw->ctl_done);
2900 hdw->ctl_timeout_flag = 0;
2901 hdw->ctl_write_pend_flag = 0;
2902 hdw->ctl_read_pend_flag = 0;
2903 init_timer(&timer);
2904 timer.expires = jiffies + timeout;
2905 timer.data = (unsigned long)hdw;
2906 timer.function = pvr2_ctl_timeout;
2907
2908 if (write_len) {
2909 hdw->cmd_debug_state = 2;
2910 /* Transfer write data to internal buffer */
2911 for (idx = 0; idx < write_len; idx++) {
2912 hdw->ctl_write_buffer[idx] =
2913 ((unsigned char *)write_data)[idx];
2914 }
2915 /* Initiate a write request */
2916 usb_fill_bulk_urb(hdw->ctl_write_urb,
2917 hdw->usb_dev,
2918 usb_sndbulkpipe(hdw->usb_dev,
2919 PVR2_CTL_WRITE_ENDPOINT),
2920 hdw->ctl_write_buffer,
2921 write_len,
2922 pvr2_ctl_write_complete,
2923 hdw);
2924 hdw->ctl_write_urb->actual_length = 0;
2925 hdw->ctl_write_pend_flag = !0;
2926 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2927 if (status < 0) {
2928 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2929 "Failed to submit write-control"
2930 " URB status=%d",status);
2931 hdw->ctl_write_pend_flag = 0;
2932 goto done;
2933 }
2934 }
2935
2936 if (read_len) {
2937 hdw->cmd_debug_state = 3;
2938 memset(hdw->ctl_read_buffer,0x43,read_len);
2939 /* Initiate a read request */
2940 usb_fill_bulk_urb(hdw->ctl_read_urb,
2941 hdw->usb_dev,
2942 usb_rcvbulkpipe(hdw->usb_dev,
2943 PVR2_CTL_READ_ENDPOINT),
2944 hdw->ctl_read_buffer,
2945 read_len,
2946 pvr2_ctl_read_complete,
2947 hdw);
2948 hdw->ctl_read_urb->actual_length = 0;
2949 hdw->ctl_read_pend_flag = !0;
2950 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2951 if (status < 0) {
2952 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2953 "Failed to submit read-control"
2954 " URB status=%d",status);
2955 hdw->ctl_read_pend_flag = 0;
2956 goto done;
2957 }
2958 }
2959
2960 /* Start timer */
2961 add_timer(&timer);
2962
2963 /* Now wait for all I/O to complete */
2964 hdw->cmd_debug_state = 4;
2965 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2966 wait_for_completion(&hdw->ctl_done);
2967 }
2968 hdw->cmd_debug_state = 5;
2969
2970 /* Stop timer */
2971 del_timer_sync(&timer);
2972
2973 hdw->cmd_debug_state = 6;
2974 status = 0;
2975
2976 if (hdw->ctl_timeout_flag) {
2977 status = -ETIMEDOUT;
2978 if (!probe_fl) {
2979 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2980 "Timed out control-write");
2981 }
2982 goto done;
2983 }
2984
2985 if (write_len) {
2986 /* Validate results of write request */
2987 if ((hdw->ctl_write_urb->status != 0) &&
2988 (hdw->ctl_write_urb->status != -ENOENT) &&
2989 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2990 (hdw->ctl_write_urb->status != -ECONNRESET)) {
2991 /* USB subsystem is reporting some kind of failure
2992 on the write */
2993 status = hdw->ctl_write_urb->status;
2994 if (!probe_fl) {
2995 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2996 "control-write URB failure,"
2997 " status=%d",
2998 status);
2999 }
3000 goto done;
3001 }
3002 if (hdw->ctl_write_urb->actual_length < write_len) {
3003 /* Failed to write enough data */
3004 status = -EIO;
3005 if (!probe_fl) {
3006 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3007 "control-write URB short,"
3008 " expected=%d got=%d",
3009 write_len,
3010 hdw->ctl_write_urb->actual_length);
3011 }
3012 goto done;
3013 }
3014 }
3015 if (read_len) {
3016 /* Validate results of read request */
3017 if ((hdw->ctl_read_urb->status != 0) &&
3018 (hdw->ctl_read_urb->status != -ENOENT) &&
3019 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3020 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3021 /* USB subsystem is reporting some kind of failure
3022 on the read */
3023 status = hdw->ctl_read_urb->status;
3024 if (!probe_fl) {
3025 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3026 "control-read URB failure,"
3027 " status=%d",
3028 status);
3029 }
3030 goto done;
3031 }
3032 if (hdw->ctl_read_urb->actual_length < read_len) {
3033 /* Failed to read enough data */
3034 status = -EIO;
3035 if (!probe_fl) {
3036 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3037 "control-read URB short,"
3038 " expected=%d got=%d",
3039 read_len,
3040 hdw->ctl_read_urb->actual_length);
3041 }
3042 goto done;
3043 }
3044 /* Transfer retrieved data out from internal buffer */
3045 for (idx = 0; idx < read_len; idx++) {
3046 ((unsigned char *)read_data)[idx] =
3047 hdw->ctl_read_buffer[idx];
3048 }
3049 }
3050
3051 done:
3052
3053 hdw->cmd_debug_state = 0;
3054 if ((status < 0) && (!probe_fl)) {
681c7399 3055 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3056 }
3057 return status;
3058}
3059
3060
3061int pvr2_send_request(struct pvr2_hdw *hdw,
3062 void *write_data,unsigned int write_len,
3063 void *read_data,unsigned int read_len)
3064{
3065 return pvr2_send_request_ex(hdw,HZ*4,0,
3066 write_data,write_len,
3067 read_data,read_len);
3068}
3069
3070int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3071{
3072 int ret;
3073
3074 LOCK_TAKE(hdw->ctl_lock);
3075
8d364363 3076 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 3077 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3078 hdw->cmd_buffer[5] = 0;
3079 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3080 hdw->cmd_buffer[7] = reg & 0xff;
3081
3082
3083 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3084
3085 LOCK_GIVE(hdw->ctl_lock);
3086
3087 return ret;
3088}
3089
3090
07e337ee 3091static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 3092{
3093 int ret = 0;
3094
3095 LOCK_TAKE(hdw->ctl_lock);
3096
8d364363 3097 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 3098 hdw->cmd_buffer[1] = 0;
3099 hdw->cmd_buffer[2] = 0;
3100 hdw->cmd_buffer[3] = 0;
3101 hdw->cmd_buffer[4] = 0;
3102 hdw->cmd_buffer[5] = 0;
3103 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3104 hdw->cmd_buffer[7] = reg & 0xff;
3105
3106 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3107 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3108
3109 LOCK_GIVE(hdw->ctl_lock);
3110
3111 return ret;
3112}
3113
3114
681c7399 3115void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 3116{
3117 if (!hdw->flag_ok) return;
681c7399
MI		 3118 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3119 "Device being rendered inoperable");
d855497e 3120 if (hdw->vid_stream) {
a0fd1cb1 3121 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 3122 }
681c7399
MI		 3123 hdw->flag_ok = 0;
3124 trace_stbit("flag_ok",hdw->flag_ok);
3125 pvr2_hdw_state_sched(hdw);
d855497e
MI		 3126}
3127
3128
3129void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3130{
3131 int ret;
3132 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 3133 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
d855497e
MI		 3134 if (ret == 1) {
3135 ret = usb_reset_device(hdw->usb_dev);
3136 usb_unlock_device(hdw->usb_dev);
3137 } else {
3138 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3139 "Failed to lock USB device ret=%d",ret);
3140 }
3141 if (init_pause_msec) {
3142 pvr2_trace(PVR2_TRACE_INFO,
3143 "Waiting %u msec for hardware to settle",
3144 init_pause_msec);
3145 msleep(init_pause_msec);
3146 }
3147
3148}
3149
3150
3151void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3152{
3153 char da[1];
3154 unsigned int pipe;
3155 int ret;
3156
3157 if (!hdw->usb_dev) return;
3158
3159 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3160
3161 da[0] = val ? 0x01 : 0x00;
3162
3163 /* Write the CPUCS register on the 8051. The lsb of the register
3164 is the reset bit; a 1 asserts reset while a 0 clears it. */
3165 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3166 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3167 if (ret < 0) {
3168 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3169 "cpureset_assert(%d) error=%d",val,ret);
3170 pvr2_hdw_render_useless(hdw);
3171 }
3172}
3173
3174
3175int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3176{
3177 int status;
3178 LOCK_TAKE(hdw->ctl_lock); do {
3179 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
8d364363 3180 hdw->cmd_buffer[0] = FX2CMD_DEEP_RESET;
a0fd1cb1 3181 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
d855497e
MI		 3182 } while (0); LOCK_GIVE(hdw->ctl_lock);
3183 return status;
3184}
3185
3186
3187int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3188{
3189 int status;
3190 LOCK_TAKE(hdw->ctl_lock); do {
3191 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
8d364363 3192 hdw->cmd_buffer[0] = FX2CMD_POWER_ON;
a0fd1cb1 3193 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
d855497e
MI		 3194 } while (0); LOCK_GIVE(hdw->ctl_lock);
3195 return status;
3196}
3197
3198
3199int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3200{
3201 if (!hdw->decoder_ctrl) {
3202 pvr2_trace(PVR2_TRACE_INIT,
3203 "Unable to reset decoder: nothing attached");
3204 return -ENOTTY;
3205 }
3206
3207 if (!hdw->decoder_ctrl->force_reset) {
3208 pvr2_trace(PVR2_TRACE_INIT,
3209 "Unable to reset decoder: not implemented");
3210 return -ENOTTY;
3211 }
3212
3213 pvr2_trace(PVR2_TRACE_INIT,
3214 "Requesting decoder reset");
3215 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3216 return 0;
3217}
3218
3219
e61b6fc5 3220/* Stop / start video stream transport */
07e337ee 3221static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e
MI		 3222{
3223 int status;
3224 LOCK_TAKE(hdw->ctl_lock); do {
8d364363
MK		 3225 hdw->cmd_buffer[0] =
3226 (runFl ? FX2CMD_STREAMING_ON : FX2CMD_STREAMING_OFF);
a0fd1cb1 3227 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
d855497e 3228 } while (0); LOCK_GIVE(hdw->ctl_lock);
d855497e
MI		 3229 return status;
3230}
3231
3232
681c7399
MI		 3233/* Evaluate whether or not state_encoder_ok can change */
3234static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
3235{
3236 if (hdw->state_encoder_ok) return 0;
3237 if (hdw->flag_tripped) return 0;
3238 if (hdw->state_encoder_run) return 0;
3239 if (hdw->state_encoder_config) return 0;
3240 if (hdw->state_decoder_run) return 0;
3241 if (hdw->state_usbstream_run) return 0;
3242 if (pvr2_upload_firmware2(hdw) < 0) {
3243 hdw->flag_tripped = !0;
3244 trace_stbit("flag_tripped",hdw->flag_tripped);
3245 return !0;
3246 }
3247 hdw->state_encoder_ok = !0;
3248 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
3249 return !0;
3250}
3251
3252
3253/* Evaluate whether or not state_encoder_config can change */
3254static int state_eval_encoder_config(struct pvr2_hdw *hdw)
3255{
3256 if (hdw->state_encoder_config) {
3257 if (hdw->state_encoder_ok) {
3258 if (hdw->state_pipeline_req &&
3259 !hdw->state_pipeline_pause) return 0;
3260 }
3261 hdw->state_encoder_config = 0;
3262 hdw->state_encoder_waitok = 0;
3263 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3264 /* paranoia - solve race if timer just completed */
3265 del_timer_sync(&hdw->encoder_wait_timer);
3266 } else {
3267 if (!hdw->state_encoder_ok ||
3268 !hdw->state_pipeline_idle ||
3269 hdw->state_pipeline_pause ||
3270 !hdw->state_pipeline_req ||
3271 !hdw->state_pipeline_config) {
3272 /* We must reset the enforced wait interval if
3273 anything has happened that might have disturbed
3274 the encoder. This should be a rare case. */
3275 if (timer_pending(&hdw->encoder_wait_timer)) {
3276 del_timer_sync(&hdw->encoder_wait_timer);
3277 }
3278 if (hdw->state_encoder_waitok) {
3279 /* Must clear the state - therefore we did
3280 something to a state bit and must also
3281 return true. */
3282 hdw->state_encoder_waitok = 0;
3283 trace_stbit("state_encoder_waitok",
3284 hdw->state_encoder_waitok);
3285 return !0;
3286 }
3287 return 0;
3288 }
3289 if (!hdw->state_encoder_waitok) {
3290 if (!timer_pending(&hdw->encoder_wait_timer)) {
3291 /* waitok flag wasn't set and timer isn't
3292 running. Check flag once more to avoid
3293 a race then start the timer. This is
3294 the point when we measure out a minimal
3295 quiet interval before doing something to
3296 the encoder. */
3297 if (!hdw->state_encoder_waitok) {
3298 hdw->encoder_wait_timer.expires =
3299 jiffies + (HZ*50/1000);
3300 add_timer(&hdw->encoder_wait_timer);
3301 }
3302 }
3303 /* We can't continue until we know we have been
3304 quiet for the interval measured by this
3305 timer. */
3306 return 0;
3307 }
3308 pvr2_encoder_configure(hdw);
3309 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
3310 }
3311 trace_stbit("state_encoder_config",hdw->state_encoder_config);
3312 return !0;
3313}
3314
3315
3316/* Evaluate whether or not state_encoder_run can change */
3317static int state_eval_encoder_run(struct pvr2_hdw *hdw)
3318{
3319 if (hdw->state_encoder_run) {
3320 if (hdw->state_encoder_ok) {
3321 if (hdw->state_decoder_run) return 0;
3322 if (pvr2_encoder_stop(hdw) < 0) return !0;
3323 }
3324 hdw->state_encoder_run = 0;
3325 } else {
3326 if (!hdw->state_encoder_ok) return 0;
3327 if (!hdw->state_decoder_run) return 0;
3328 if (pvr2_encoder_start(hdw) < 0) return !0;
3329 hdw->state_encoder_run = !0;
3330 }
3331 trace_stbit("state_encoder_run",hdw->state_encoder_run);
3332 return !0;
3333}
3334
3335
3336/* Timeout function for quiescent timer. */
3337static void pvr2_hdw_quiescent_timeout(unsigned long data)
3338{
3339 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3340 hdw->state_decoder_quiescent = !0;
3341 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3342 hdw->state_stale = !0;
3343 queue_work(hdw->workqueue,&hdw->workpoll);
3344}
3345
3346
3347/* Timeout function for encoder wait timer. */
3348static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
3349{
3350 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3351 hdw->state_encoder_waitok = !0;
3352 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3353 hdw->state_stale = !0;
3354 queue_work(hdw->workqueue,&hdw->workpoll);
3355}
3356
3357
3358/* Evaluate whether or not state_decoder_run can change */
3359static int state_eval_decoder_run(struct pvr2_hdw *hdw)
3360{
3361 if (hdw->state_decoder_run) {
3362 if (hdw->state_encoder_ok) {
3363 if (hdw->state_pipeline_req &&
3364 !hdw->state_pipeline_pause) return 0;
3365 }
3366 if (!hdw->flag_decoder_missed) {
3367 pvr2_decoder_enable(hdw,0);
3368 }
3369 hdw->state_decoder_quiescent = 0;
3370 hdw->state_decoder_run = 0;
3371 /* paranoia - solve race if timer just completed */
3372 del_timer_sync(&hdw->quiescent_timer);
3373 } else {
3374 if (!hdw->state_decoder_quiescent) {
3375 if (!timer_pending(&hdw->quiescent_timer)) {
3376 /* We don't do something about the
3377 quiescent timer until right here because
3378 we also want to catch cases where the
3379 decoder was already not running (like
3380 after initialization) as opposed to
3381 knowing that we had just stopped it.
3382 The second flag check is here to cover a
3383 race - the timer could have run and set
3384 this flag just after the previous check
3385 but before we did the pending check. */
3386 if (!hdw->state_decoder_quiescent) {
3387 hdw->quiescent_timer.expires =
3388 jiffies + (HZ*50/1000);
3389 add_timer(&hdw->quiescent_timer);
3390 }
3391 }
3392 /* Don't allow decoder to start again until it has
3393 been quiesced first. This little detail should
3394 hopefully further stabilize the encoder. */
3395 return 0;
3396 }
3397 if (!hdw->state_pipeline_req ||
3398 hdw->state_pipeline_pause ||
3399 !hdw->state_pipeline_config ||
3400 !hdw->state_encoder_config ||
3401 !hdw->state_encoder_ok) return 0;
3402 del_timer_sync(&hdw->quiescent_timer);
3403 if (hdw->flag_decoder_missed) return 0;
3404 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
3405 hdw->state_decoder_quiescent = 0;
3406 hdw->state_decoder_run = !0;
3407 }
3408 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3409 trace_stbit("state_decoder_run",hdw->state_decoder_run);
3410 return !0;
3411}
3412
3413
3414/* Evaluate whether or not state_usbstream_run can change */
3415static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
3416{
3417 if (hdw->state_usbstream_run) {
3418 if (hdw->state_encoder_ok) {
3419 if (hdw->state_encoder_run) return 0;
3420 }
3421 pvr2_hdw_cmd_usbstream(hdw,0);
3422 hdw->state_usbstream_run = 0;
3423 } else {
3424 if (!hdw->state_encoder_ok ||
3425 !hdw->state_encoder_run ||
3426 !hdw->state_pipeline_req ||
3427 hdw->state_pipeline_pause) return 0;
3428 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
3429 hdw->state_usbstream_run = !0;
3430 }
3431 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
3432 return !0;
3433}
3434
3435
3436/* Attempt to configure pipeline, if needed */
3437static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
3438{
3439 if (hdw->state_pipeline_config ||
3440 hdw->state_pipeline_pause) return 0;
3441 pvr2_hdw_commit_execute(hdw);
3442 return !0;
3443}
3444
3445
3446/* Update pipeline idle and pipeline pause tracking states based on other
3447 inputs. This must be called whenever the other relevant inputs have
3448 changed. */
3449static int state_update_pipeline_state(struct pvr2_hdw *hdw)
3450{
3451 unsigned int st;
3452 int updatedFl = 0;
3453 /* Update pipeline state */
3454 st = !(hdw->state_encoder_run ||
3455 hdw->state_decoder_run ||
3456 hdw->state_usbstream_run ||
3457 (!hdw->state_decoder_quiescent));
3458 if (!st != !hdw->state_pipeline_idle) {
3459 hdw->state_pipeline_idle = st;
3460 updatedFl = !0;
3461 }
3462 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
3463 hdw->state_pipeline_pause = 0;
3464 updatedFl = !0;
3465 }
3466 return updatedFl;
3467}
3468
3469
3470typedef int (*state_eval_func)(struct pvr2_hdw *);
3471
3472/* Set of functions to be run to evaluate various states in the driver. */
3473const static state_eval_func eval_funcs[] = {
3474 state_eval_pipeline_config,
3475 state_eval_encoder_ok,
3476 state_eval_encoder_config,
3477 state_eval_decoder_run,
3478 state_eval_encoder_run,
3479 state_eval_usbstream_run,
3480};
3481
3482
3483/* Process various states and return true if we did anything interesting. */
3484static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
3485{
3486 unsigned int i;
3487 int state_updated = 0;
3488 int check_flag;
3489
3490 if (!hdw->state_stale) return 0;
3491 if ((hdw->fw1_state != FW1_STATE_OK) ||
3492 !hdw->flag_ok) {
3493 hdw->state_stale = 0;
3494 return !0;
3495 }
3496 /* This loop is the heart of the entire driver. It keeps trying to
3497 evaluate various bits of driver state until nothing changes for
3498 one full iteration. Each "bit of state" tracks some global
3499 aspect of the driver, e.g. whether decoder should run, if
3500 pipeline is configured, usb streaming is on, etc. We separately
3501 evaluate each of those questions based on other driver state to
3502 arrive at the correct running configuration. */
3503 do {
3504 check_flag = 0;
3505 state_update_pipeline_state(hdw);
3506 /* Iterate over each bit of state */
3507 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
3508 if ((*eval_funcs[i])(hdw)) {
3509 check_flag = !0;
3510 state_updated = !0;
3511 state_update_pipeline_state(hdw);
3512 }
3513 }
3514 } while (check_flag && hdw->flag_ok);
3515 hdw->state_stale = 0;
3516 trace_stbit("state_stale",hdw->state_stale);
3517 return state_updated;
3518}
3519
3520
3521static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
3522 char *buf,unsigned int acnt)
3523{
3524 switch (which) {
3525 case 0:
3526 return scnprintf(
3527 buf,acnt,
3528 "driver:%s%s%s%s%s",
3529 (hdw->flag_ok ? " <ok>" : " <fail>"),
3530 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
3531 (hdw->flag_disconnected ? " <disconnected>" :
3532 " <connected>"),
3533 (hdw->flag_tripped ? " <tripped>" : ""),
3534 (hdw->flag_decoder_missed ? " <no decoder>" : ""));
3535 case 1:
3536 return scnprintf(
3537 buf,acnt,
3538 "pipeline:%s%s%s%s",
3539 (hdw->state_pipeline_idle ? " <idle>" : ""),
3540 (hdw->state_pipeline_config ?
3541 " <configok>" : " <stale>"),
3542 (hdw->state_pipeline_req ? " <req>" : ""),
3543 (hdw->state_pipeline_pause ? " <pause>" : ""));
3544 case 2:
3545 return scnprintf(
3546 buf,acnt,
3547 "worker:%s%s%s%s%s%s",
3548 (hdw->state_decoder_run ?
3549 " <decode:run>" :
3550 (hdw->state_decoder_quiescent ?
3551 "" : " <decode:stop>")),
3552 (hdw->state_decoder_quiescent ?
3553 " <decode:quiescent>" : ""),
3554 (hdw->state_encoder_ok ?
3555 "" : " <encode:init>"),
3556 (hdw->state_encoder_run ?
3557 " <encode:run>" : " <encode:stop>"),
3558 (hdw->state_encoder_config ?
3559 " <encode:configok>" :
3560 (hdw->state_encoder_waitok ?
3561 "" : " <encode:wait>")),
3562 (hdw->state_usbstream_run ?
3563 " <usb:run>" : " <usb:stop>"));
3564 break;
3565 case 3:
3566 return scnprintf(
3567 buf,acnt,
3568 "state: %s",
3569 pvr2_get_state_name(hdw->master_state));
3570 break;
3571 default: break;
3572 }
3573 return 0;
3574}
3575
3576
3577unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
3578 char *buf,unsigned int acnt)
3579{
3580 unsigned int bcnt,ccnt,idx;
3581 bcnt = 0;
3582 LOCK_TAKE(hdw->big_lock);
3583 for (idx = 0; ; idx++) {
3584 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
3585 if (!ccnt) break;
3586 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
3587 if (!acnt) break;
3588 buf[0] = '\n'; ccnt = 1;
3589 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
3590 }
3591 LOCK_GIVE(hdw->big_lock);
3592 return bcnt;
3593}
3594
3595
3596static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
3597{
3598 char buf[128];
3599 unsigned int idx,ccnt;
3600
3601 for (idx = 0; ; idx++) {
3602 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
3603 if (!ccnt) break;
3604 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
3605 }
3606}
3607
3608
3609/* Evaluate and update the driver's current state, taking various actions
3610 as appropriate for the update. */
3611static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
3612{
3613 unsigned int st;
3614 int state_updated = 0;
3615 int callback_flag = 0;
3616
3617 pvr2_trace(PVR2_TRACE_STBITS,
3618 "Drive state check START");
3619 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
3620 pvr2_hdw_state_log_state(hdw);
3621 }
3622
3623 /* Process all state and get back over disposition */
3624 state_updated = pvr2_hdw_state_update(hdw);
3625
3626 /* Update master state based upon all other states. */
3627 if (!hdw->flag_ok) {
3628 st = PVR2_STATE_DEAD;
3629 } else if (hdw->fw1_state != FW1_STATE_OK) {
3630 st = PVR2_STATE_COLD;
3631 } else if (!hdw->state_encoder_ok) {
3632 st = PVR2_STATE_WARM;
3633 } else if (hdw->flag_tripped || hdw->flag_decoder_missed) {
3634 st = PVR2_STATE_ERROR;
3635 } else if (hdw->state_encoder_run &&
3636 hdw->state_decoder_run &&
3637 hdw->state_usbstream_run) {
3638 st = PVR2_STATE_RUN;
3639 } else {
3640 st = PVR2_STATE_READY;
3641 }
3642 if (hdw->master_state != st) {
3643 pvr2_trace(PVR2_TRACE_STATE,
3644 "Device state change from %s to %s",
3645 pvr2_get_state_name(hdw->master_state),
3646 pvr2_get_state_name(st));
3647 hdw->master_state = st;
3648 state_updated = !0;
3649 callback_flag = !0;
3650 }
3651 if (state_updated) {
3652 /* Trigger anyone waiting on any state changes here. */
3653 wake_up(&hdw->state_wait_data);
3654 }
3655
3656 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
3657 pvr2_hdw_state_log_state(hdw);
3658 }
3659 pvr2_trace(PVR2_TRACE_STBITS,
3660 "Drive state check DONE callback=%d",callback_flag);
3661
3662 return callback_flag;
3663}
3664
3665
3666/* Cause kernel thread to check / update driver state */
3667static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
3668{
3669 if (hdw->state_stale) return;
3670 hdw->state_stale = !0;
3671 trace_stbit("state_stale",hdw->state_stale);
3672 queue_work(hdw->workqueue,&hdw->workpoll);
3673}
3674
3675
3676void pvr2_hdw_get_debug_info_unlocked(const struct pvr2_hdw *hdw,
3677 struct pvr2_hdw_debug_info *ptr)
d855497e
MI		 3678{
3679 ptr->big_lock_held = hdw->big_lock_held;
3680 ptr->ctl_lock_held = hdw->ctl_lock_held;
d855497e
MI		 3681 ptr->flag_disconnected = hdw->flag_disconnected;
3682 ptr->flag_init_ok = hdw->flag_init_ok;
681c7399
MI		 3683 ptr->flag_ok = hdw->flag_ok;
3684 ptr->fw1_state = hdw->fw1_state;
3685 ptr->flag_decoder_missed = hdw->flag_decoder_missed;
3686 ptr->flag_tripped = hdw->flag_tripped;
3687 ptr->state_encoder_ok = hdw->state_encoder_ok;
3688 ptr->state_encoder_run = hdw->state_encoder_run;
3689 ptr->state_decoder_run = hdw->state_decoder_run;
3690 ptr->state_usbstream_run = hdw->state_usbstream_run;
3691 ptr->state_decoder_quiescent = hdw->state_decoder_quiescent;
3692 ptr->state_pipeline_config = hdw->state_pipeline_config;
3693 ptr->state_pipeline_req = hdw->state_pipeline_req;
3694 ptr->state_pipeline_pause = hdw->state_pipeline_pause;
3695 ptr->state_pipeline_idle = hdw->state_pipeline_idle;
d855497e
MI		 3696 ptr->cmd_debug_state = hdw->cmd_debug_state;
3697 ptr->cmd_code = hdw->cmd_debug_code;
3698 ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
3699 ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
3700 ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
3701 ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
3702 ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
3703 ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
3704 ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
3705}
3706
3707
681c7399
MI		 3708void pvr2_hdw_get_debug_info_locked(struct pvr2_hdw *hdw,
3709 struct pvr2_hdw_debug_info *ptr)
3710{
3711 LOCK_TAKE(hdw->ctl_lock); do {
3712 pvr2_hdw_get_debug_info_unlocked(hdw,ptr);
3713 } while(0); LOCK_GIVE(hdw->ctl_lock);
3714}
3715
3716
d855497e
MI		 3717int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
3718{
3719 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
3720}
3721
3722
3723int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
3724{
3725 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
3726}
3727
3728
3729int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
3730{
3731 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
3732}
3733
3734
3735int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
3736{
3737 u32 cval,nval;
3738 int ret;
3739 if (~msk) {
3740 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
3741 if (ret) return ret;
3742 nval = (cval & ~msk) | (val & msk);
3743 pvr2_trace(PVR2_TRACE_GPIO,
3744 "GPIO direction changing 0x%x:0x%x"
3745 " from 0x%x to 0x%x",
3746 msk,val,cval,nval);
3747 } else {
3748 nval = val;
3749 pvr2_trace(PVR2_TRACE_GPIO,
3750 "GPIO direction changing to 0x%x",nval);
3751 }
3752 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
3753}
3754
3755
3756int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
3757{
3758 u32 cval,nval;
3759 int ret;
3760 if (~msk) {
3761 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
3762 if (ret) return ret;
3763 nval = (cval & ~msk) | (val & msk);
3764 pvr2_trace(PVR2_TRACE_GPIO,
3765 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
3766 msk,val,cval,nval);
3767 } else {
3768 nval = val;
3769 pvr2_trace(PVR2_TRACE_GPIO,
3770 "GPIO output changing to 0x%x",nval);
3771 }
3772 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
3773}
3774
3775
7fb20fa3
MI		 3776unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
3777{
3778 return hdw->input_avail_mask;
3779}
3780
3781
e61b6fc5 3782/* Find I2C address of eeprom */
07e337ee 3783static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 3784{
3785 int result;
3786 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3787 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 3788 result = pvr2_send_request(hdw,
3789 hdw->cmd_buffer,1,
3790 hdw->cmd_buffer,1);
3791 if (result < 0) break;
3792 result = hdw->cmd_buffer[0];
3793 } while(0); LOCK_GIVE(hdw->ctl_lock);
3794 return result;
3795}
3796
3797
32ffa9ae 3798int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
f3d092b8
HV		 3799 u32 match_type, u32 match_chip, u64 reg_id,
3800 int setFl,u64 *val_ptr)
32ffa9ae
MI		 3801{
3802#ifdef CONFIG_VIDEO_ADV_DEBUG
32ffa9ae
MI		 3803 struct pvr2_i2c_client *cp;
3804 struct v4l2_register req;
6d98816f
MI		 3805 int stat = 0;
3806 int okFl = 0;
32ffa9ae 3807
201f5c9c
MI		 3808 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
3809
f3d092b8
HV		 3810 req.match_type = match_type;
3811 req.match_chip = match_chip;
32ffa9ae
MI		 3812 req.reg = reg_id;
3813 if (setFl) req.val = *val_ptr;
3814 mutex_lock(&hdw->i2c_list_lock); do {
e77e2c2f 3815 list_for_each_entry(cp, &hdw->i2c_clients, list) {
8481a750
MI		 3816 if (!v4l2_chip_match_i2c_client(
3817 cp->client,
3818 req.match_type, req.match_chip)) {
f3d092b8
HV		 3819 continue;
3820 }
32ffa9ae 3821 stat = pvr2_i2c_client_cmd(
52ebc763
TP		 3822 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
3823 VIDIOC_DBG_G_REGISTER),&req);
32ffa9ae 3824 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 3825 okFl = !0;
3826 break;
32ffa9ae
MI		 3827 }
3828 } while (0); mutex_unlock(&hdw->i2c_list_lock);
6d98816f
MI		 3829 if (okFl) {
3830 return stat;
3831 }
32ffa9ae
MI		 3832 return -EINVAL;
3833#else
3834 return -ENOSYS;
3835#endif
3836}
3837
3838
d855497e
MI		 3839/*
3840 Stuff for Emacs to see, in order to encourage consistent editing style:
3841 *** Local Variables: ***
3842 *** mode: c ***
3843 *** fill-column: 75 ***
3844 *** tab-width: 8 ***
3845 *** c-basic-offset: 8 ***
3846 *** End: ***
3847 */
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