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V4L/DVB (7669): pxa_camera: Add support for YUV modes
[mirror_ubuntu-jammy-kernel.git] / drivers / media / video / pxa_camera.c
CommitLineData
3bc43840
GL		 1/*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
3bc43840
GL		 13#include <linux/init.h>
14#include <linux/module.h>
7102b773 15#include <linux/io.h>
3bc43840
GL		 16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/errno.h>
19#include <linux/fs.h>
20#include <linux/interrupt.h>
21#include <linux/kernel.h>
22#include <linux/mm.h>
23#include <linux/moduleparam.h>
24#include <linux/time.h>
25#include <linux/version.h>
26#include <linux/device.h>
27#include <linux/platform_device.h>
28#include <linux/mutex.h>
29#include <linux/clk.h>
30
31#include <media/v4l2-common.h>
32#include <media/v4l2-dev.h>
33#include <media/soc_camera.h>
34
35#include <linux/videodev2.h>
36
37#include <asm/dma.h>
38#include <asm/arch/pxa-regs.h>
39#include <asm/arch/camera.h>
40
41#define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
42#define PXA_CAM_DRV_NAME "pxa27x-camera"
43
7102b773
GL		 44#define CICR0_SIM_MP (0 << 24)
45#define CICR0_SIM_SP (1 << 24)
46#define CICR0_SIM_MS (2 << 24)
47#define CICR0_SIM_EP (3 << 24)
48#define CICR0_SIM_ES (4 << 24)
49
50#define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
51#define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
a5462e5b
MR		 52#define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
53#define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
54#define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
7102b773
GL		 55
56#define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
57#define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
58#define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
59#define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
60#define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
61
62#define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
63#define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
64#define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
65#define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
66
3bc43840
GL		 67#define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
68 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
69 CICR0_EOFM | CICR0_FOM)
70
71static DEFINE_MUTEX(camera_lock);
72
73/*
74 * Structures
75 */
a5462e5b
MR		 76enum pxa_camera_active_dma {
77 DMA_Y = 0x1,
78 DMA_U = 0x2,
79 DMA_V = 0x4,
80};
81
82/* descriptor needed for the PXA DMA engine */
83struct pxa_cam_dma {
84 dma_addr_t sg_dma;
85 struct pxa_dma_desc *sg_cpu;
86 size_t sg_size;
87 int sglen;
88};
3bc43840
GL		 89
90/* buffer for one video frame */
91struct pxa_buffer {
92 /* common v4l buffer stuff -- must be first */
93 struct videobuf_buffer vb;
94
95 const struct soc_camera_data_format *fmt;
96
a5462e5b
MR		 97 /* our descriptor lists for Y, U and V channels */
98 struct pxa_cam_dma dmas[3];
99
3bc43840 100 int inwork;
a5462e5b
MR		 101
102 enum pxa_camera_active_dma active_dma;
3bc43840
GL		 103};
104
105struct pxa_framebuffer_queue {
106 dma_addr_t sg_last_dma;
107 struct pxa_dma_desc *sg_last_cpu;
108};
109
110struct pxa_camera_dev {
111 struct device *dev;
112 /* PXA27x is only supposed to handle one camera on its Quick Capture
113 * interface. If anyone ever builds hardware to enable more than
114 * one camera, they will have to modify this driver too */
115 struct soc_camera_device *icd;
116 struct clk *clk;
117
118 unsigned int irq;
119 void __iomem *base;
a5462e5b
MR		 120
121 unsigned int dma_chans[3];
3bc43840 122
3bc43840
GL		 123 struct pxacamera_platform_data *pdata;
124 struct resource *res;
125 unsigned long platform_flags;
126 unsigned long platform_mclk_10khz;
127
128 struct list_head capture;
129
130 spinlock_t lock;
131
3bc43840
GL		 132 struct pxa_buffer *active;
133};
134
135static const char *pxa_cam_driver_description = "PXA_Camera";
136
137static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
138
139/*
140 * Videobuf operations
141 */
7102b773
GL		 142static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
143 unsigned int *size)
3bc43840
GL		 144{
145 struct soc_camera_device *icd = vq->priv_data;
146
147 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
148
a5462e5b
MR		 149 /* planar capture requires Y, U and V buffers to be page aligned */
150 if (icd->current_fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
151 *size = PAGE_ALIGN(icd->width * icd->height); /* Y pages */
152 *size += PAGE_ALIGN(icd->width * icd->height / 2); /* U pages */
153 *size += PAGE_ALIGN(icd->width * icd->height / 2); /* V pages */
154 } else {
155 *size = icd->width * icd->height *
156 ((icd->current_fmt->depth + 7) >> 3);
157 }
3bc43840
GL		 158
159 if (0 == *count)
160 *count = 32;
161 while (*size * *count > vid_limit * 1024 * 1024)
162 (*count)--;
163
164 return 0;
165}
166
167static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
168{
169 struct soc_camera_device *icd = vq->priv_data;
170 struct soc_camera_host *ici =
171 to_soc_camera_host(icd->dev.parent);
172 struct pxa_camera_dev *pcdev = ici->priv;
173 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
a5462e5b 174 int i;
3bc43840
GL		 175
176 BUG_ON(in_interrupt());
177
7e28adb2 178 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 179 &buf->vb, buf->vb.baddr, buf->vb.bsize);
180
181 /* This waits until this buffer is out of danger, i.e., until it is no
182 * longer in STATE_QUEUED or STATE_ACTIVE */
183 videobuf_waiton(&buf->vb, 0, 0);
184 videobuf_dma_unmap(vq, dma);
185 videobuf_dma_free(dma);
186
a5462e5b
MR		 187 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
188 if (buf->dmas[i].sg_cpu)
189 dma_free_coherent(pcdev->dev, buf->dmas[i].sg_size,
190 buf->dmas[i].sg_cpu,
191 buf->dmas[i].sg_dma);
192 buf->dmas[i].sg_cpu = NULL;
193 }
3bc43840
GL		 194
195 buf->vb.state = VIDEOBUF_NEEDS_INIT;
196}
197
a5462e5b
MR		 198static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
199 struct pxa_buffer *buf,
200 struct videobuf_dmabuf *dma, int channel,
201 int sglen, int sg_start, int cibr,
202 unsigned int size)
203{
204 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
205 int i;
206
207 if (pxa_dma->sg_cpu)
208 dma_free_coherent(pcdev->dev, pxa_dma->sg_size,
209 pxa_dma->sg_cpu, pxa_dma->sg_dma);
210
211 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
212 pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->dev, pxa_dma->sg_size,
213 &pxa_dma->sg_dma, GFP_KERNEL);
214 if (!pxa_dma->sg_cpu)
215 return -ENOMEM;
216
217 pxa_dma->sglen = sglen;
218
219 for (i = 0; i < sglen; i++) {
220 int sg_i = sg_start + i;
221 struct scatterlist *sg = dma->sglist;
222 unsigned int dma_len = sg_dma_len(&sg[sg_i]), xfer_len;
223
224 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
225 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(&sg[sg_i]);
226
227 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
228 xfer_len = (min(dma_len, size) + 7) & ~7;
229
230 pxa_dma->sg_cpu[i].dcmd =
231 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
232 size -= dma_len;
233 pxa_dma->sg_cpu[i].ddadr =
234 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
235 }
236
237 pxa_dma->sg_cpu[sglen - 1].ddadr = DDADR_STOP;
238 pxa_dma->sg_cpu[sglen - 1].dcmd |= DCMD_ENDIRQEN;
239
240 return 0;
241}
242
7102b773
GL		 243static int pxa_videobuf_prepare(struct videobuf_queue *vq,
244 struct videobuf_buffer *vb, enum v4l2_field field)
3bc43840
GL		 245{
246 struct soc_camera_device *icd = vq->priv_data;
247 struct soc_camera_host *ici =
248 to_soc_camera_host(icd->dev.parent);
249 struct pxa_camera_dev *pcdev = ici->priv;
250 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
a5462e5b
MR		 251 int ret;
252 int sglen_y, sglen_yu = 0, sglen_u = 0, sglen_v = 0;
253 int size_y, size_u = 0, size_v = 0;
3bc43840 254
7e28adb2 255 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 256 vb, vb->baddr, vb->bsize);
257
258 /* Added list head initialization on alloc */
259 WARN_ON(!list_empty(&vb->queue));
260
261#ifdef DEBUG
262 /* This can be useful if you want to see if we actually fill
263 * the buffer with something */
264 memset((void *)vb->baddr, 0xaa, vb->bsize);
265#endif
266
267 BUG_ON(NULL == icd->current_fmt);
268
269 /* I think, in buf_prepare you only have to protect global data,
270 * the actual buffer is yours */
271 buf->inwork = 1;
272
273 if (buf->fmt != icd->current_fmt ||
274 vb->width != icd->width ||
275 vb->height != icd->height ||
276 vb->field != field) {
277 buf->fmt = icd->current_fmt;
278 vb->width = icd->width;
279 vb->height = icd->height;
280 vb->field = field;
281 vb->state = VIDEOBUF_NEEDS_INIT;
282 }
283
284 vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3);
285 if (0 != vb->baddr && vb->bsize < vb->size) {
286 ret = -EINVAL;
287 goto out;
288 }
289
290 if (vb->state == VIDEOBUF_NEEDS_INIT) {
291 unsigned int size = vb->size;
292 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
293
294 ret = videobuf_iolock(vq, vb, NULL);
295 if (ret)
296 goto fail;
297
a5462e5b
MR		 298 if (buf->fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
299 /* FIXME the calculations should be more precise */
300 sglen_y = dma->sglen / 2;
301 sglen_u = sglen_v = dma->sglen / 4 + 1;
302 sglen_yu = sglen_y + sglen_u;
303 size_y = size / 2;
304 size_u = size_v = size / 4;
305 } else {
306 sglen_y = dma->sglen;
307 size_y = size;
308 }
309
310 /* init DMA for Y channel */
311 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, sglen_y,
312 0, 0x28, size_y);
3bc43840 313
a5462e5b
MR		 314 if (ret) {
315 dev_err(pcdev->dev,
316 "DMA initialization for Y/RGB failed\n");
3bc43840
GL		 317 goto fail;
318 }
319
a5462e5b
MR		 320 if (buf->fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
321 /* init DMA for U channel */
322 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, sglen_u,
323 sglen_y, 0x30, size_u);
324 if (ret) {
325 dev_err(pcdev->dev,
326 "DMA initialization for U failed\n");
327 goto fail_u;
328 }
329
330 /* init DMA for V channel */
331 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, sglen_v,
332 sglen_yu, 0x38, size_v);
333 if (ret) {
334 dev_err(pcdev->dev,
335 "DMA initialization for V failed\n");
336 goto fail_v;
337 }
3bc43840 338 }
3bc43840
GL		 339
340 vb->state = VIDEOBUF_PREPARED;
341 }
342
343 buf->inwork = 0;
a5462e5b
MR		 344 buf->active_dma = DMA_Y;
345 if (buf->fmt->fourcc == V4L2_PIX_FMT_YUV422P)
346 buf->active_dma |= DMA_U | DMA_V;
3bc43840
GL		 347
348 return 0;
349
a5462e5b
MR		 350fail_v:
351 dma_free_coherent(pcdev->dev, buf->dmas[1].sg_size,
352 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
353fail_u:
354 dma_free_coherent(pcdev->dev, buf->dmas[0].sg_size,
355 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
3bc43840
GL		 356fail:
357 free_buffer(vq, buf);
358out:
359 buf->inwork = 0;
360 return ret;
361}
362
7102b773
GL		 363static void pxa_videobuf_queue(struct videobuf_queue *vq,
364 struct videobuf_buffer *vb)
3bc43840
GL		 365{
366 struct soc_camera_device *icd = vq->priv_data;
367 struct soc_camera_host *ici =
368 to_soc_camera_host(icd->dev.parent);
369 struct pxa_camera_dev *pcdev = ici->priv;
370 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
7102b773 371 struct pxa_buffer *active;
3bc43840
GL		 372 unsigned long flags;
373
7e28adb2 374 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 375 vb, vb->baddr, vb->bsize);
376 spin_lock_irqsave(&pcdev->lock, flags);
377
378 list_add_tail(&vb->queue, &pcdev->capture);
379
380 vb->state = VIDEOBUF_ACTIVE;
7102b773 381 active = pcdev->active;
3bc43840 382
7102b773 383 if (!active) {
3bc43840 384 CIFR |= CIFR_RESET_F;
a5462e5b
MR		 385 DDADR(pcdev->dma_chans[0]) = buf->dmas[0].sg_dma;
386 DCSR(pcdev->dma_chans[0]) = DCSR_RUN;
387
388 if (buf->fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
389 DDADR(pcdev->dma_chans[1]) = buf->dmas[1].sg_dma;
390 DCSR(pcdev->dma_chans[1]) = DCSR_RUN;
391
392 DDADR(pcdev->dma_chans[2]) = buf->dmas[2].sg_dma;
393 DCSR(pcdev->dma_chans[2]) = DCSR_RUN;
394 }
395
3bc43840
GL		 396 pcdev->active = buf;
397 CICR0 |= CICR0_ENB;
398 } else {
a5462e5b
MR		 399 struct pxa_cam_dma *buf_dma;
400 struct pxa_cam_dma *act_dma;
401 int channels = 1;
402 int nents;
403 int i;
404
405 if (buf->fmt->fourcc == V4L2_PIX_FMT_YUV422P)
406 channels = 3;
407
408 for (i = 0; i < channels; i++) {
409 buf_dma = &buf->dmas[i];
410 act_dma = &active->dmas[i];
411 nents = buf_dma->sglen;
412
413 /* Stop DMA engine */
414 DCSR(pcdev->dma_chans[i]) = 0;
415
416 /* Add the descriptors we just initialized to
417 the currently running chain */
418 act_dma->sg_cpu[act_dma->sglen - 1].ddadr =
419 buf_dma->sg_dma;
420
421 /* Setup a dummy descriptor with the DMA engines current
422 * state
3bc43840 423 */
a5462e5b
MR		 424 buf_dma->sg_cpu[nents].dsadr =
425 pcdev->res->start + 0x28 + i*8; /* CIBRx */
426 buf_dma->sg_cpu[nents].dtadr =
427 DTADR(pcdev->dma_chans[i]);
428 buf_dma->sg_cpu[nents].dcmd =
429 DCMD(pcdev->dma_chans[i]);
430
431 if (DDADR(pcdev->dma_chans[i]) == DDADR_STOP) {
432 /* The DMA engine is on the last
433 descriptor, set the next descriptors
434 address to the descriptors we just
435 initialized */
436 buf_dma->sg_cpu[nents].ddadr = buf_dma->sg_dma;
437 } else {
438 buf_dma->sg_cpu[nents].ddadr =
439 DDADR(pcdev->dma_chans[i]);
440 }
441
442 /* The next descriptor is the dummy descriptor */
443 DDADR(pcdev->dma_chans[i]) = buf_dma->sg_dma + nents *
444 sizeof(struct pxa_dma_desc);
445
446 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
3bc43840 447 }
3bc43840 448#ifdef DEBUG
a5462e5b 449 if (CISR & (CISR_IFO_0 | CISR_IFO_1 | CISR_IFO_2)) {
3bc43840 450 dev_warn(pcdev->dev, "FIFO overrun\n");
a5462e5b
MR		 451 for (i = 0; i < channels; i++)
452 DDADR(pcdev->dma_chans[i]) =
453 pcdev->active->dmas[i].sg_dma;
3bc43840
GL		 454
455 CICR0 &= ~CICR0_ENB;
456 CIFR |= CIFR_RESET_F;
a5462e5b
MR		 457 for (i = 0; i < channels; i++)
458 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
3bc43840 459 CICR0 |= CICR0_ENB;
a5462e5b 460 }
3bc43840 461#endif
3bc43840
GL		 462 }
463
464 spin_unlock_irqrestore(&pcdev->lock, flags);
3bc43840
GL		 465}
466
467static void pxa_videobuf_release(struct videobuf_queue *vq,
468 struct videobuf_buffer *vb)
469{
470 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
471#ifdef DEBUG
472 struct soc_camera_device *icd = vq->priv_data;
473
7e28adb2 474 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 475 vb, vb->baddr, vb->bsize);
476
477 switch (vb->state) {
478 case VIDEOBUF_ACTIVE:
7e28adb2 479 dev_dbg(&icd->dev, "%s (active)\n", __func__);
3bc43840
GL		 480 break;
481 case VIDEOBUF_QUEUED:
7e28adb2 482 dev_dbg(&icd->dev, "%s (queued)\n", __func__);
3bc43840
GL		 483 break;
484 case VIDEOBUF_PREPARED:
7e28adb2 485 dev_dbg(&icd->dev, "%s (prepared)\n", __func__);
3bc43840
GL		 486 break;
487 default:
7e28adb2 488 dev_dbg(&icd->dev, "%s (unknown)\n", __func__);
3bc43840
GL		 489 break;
490 }
491#endif
492
493 free_buffer(vq, buf);
494}
495
a5462e5b
MR		 496static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
497 struct videobuf_buffer *vb,
498 struct pxa_buffer *buf)
499{
500 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
501 list_del_init(&vb->queue);
502 vb->state = VIDEOBUF_DONE;
503 do_gettimeofday(&vb->ts);
504 vb->field_count++;
505 wake_up(&vb->done);
506
507 if (list_empty(&pcdev->capture)) {
508 pcdev->active = NULL;
509 DCSR(pcdev->dma_chans[0]) = 0;
510 DCSR(pcdev->dma_chans[1]) = 0;
511 DCSR(pcdev->dma_chans[2]) = 0;
512 CICR0 &= ~CICR0_ENB;
513 return;
514 }
515
516 pcdev->active = list_entry(pcdev->capture.next,
517 struct pxa_buffer, vb.queue);
518}
519
520static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
521 enum pxa_camera_active_dma act_dma)
3bc43840 522{
3bc43840
GL		 523 struct pxa_buffer *buf;
524 unsigned long flags;
525 unsigned int status;
526 struct videobuf_buffer *vb;
527
528 spin_lock_irqsave(&pcdev->lock, flags);
529
a5462e5b
MR		 530 status = DCSR(channel);
531 DCSR(channel) = status | DCSR_ENDINTR;
7102b773 532
3bc43840 533 if (status & DCSR_BUSERR) {
7102b773 534 dev_err(pcdev->dev, "DMA Bus Error IRQ!\n");
3bc43840
GL		 535 goto out;
536 }
537
538 if (!(status & DCSR_ENDINTR)) {
7102b773
GL		 539 dev_err(pcdev->dev, "Unknown DMA IRQ source, "
540 "status: 0x%08x\n", status);
3bc43840
GL		 541 goto out;
542 }
543
3bc43840 544 if (!pcdev->active) {
7102b773 545 dev_err(pcdev->dev, "DMA End IRQ with no active buffer!\n");
3bc43840
GL		 546 goto out;
547 }
548
549 vb = &pcdev->active->vb;
550 buf = container_of(vb, struct pxa_buffer, vb);
551 WARN_ON(buf->inwork || list_empty(&vb->queue));
7e28adb2 552 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 553 vb, vb->baddr, vb->bsize);
554
a5462e5b
MR		 555 buf->active_dma &= ~act_dma;
556 if (!buf->active_dma)
557 pxa_camera_wakeup(pcdev, vb, buf);
3bc43840
GL		 558
559out:
560 spin_unlock_irqrestore(&pcdev->lock, flags);
561}
562
a5462e5b
MR		 563static void pxa_camera_dma_irq_y(int channel, void *data)
564{
565 struct pxa_camera_dev *pcdev = data;
566 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
567}
568
569static void pxa_camera_dma_irq_u(int channel, void *data)
570{
571 struct pxa_camera_dev *pcdev = data;
572 pxa_camera_dma_irq(channel, pcdev, DMA_U);
573}
574
575static void pxa_camera_dma_irq_v(int channel, void *data)
576{
577 struct pxa_camera_dev *pcdev = data;
578 pxa_camera_dma_irq(channel, pcdev, DMA_V);
579}
580
7102b773 581static struct videobuf_queue_ops pxa_videobuf_ops = {
3bc43840
GL		 582 .buf_setup = pxa_videobuf_setup,
583 .buf_prepare = pxa_videobuf_prepare,
584 .buf_queue = pxa_videobuf_queue,
585 .buf_release = pxa_videobuf_release,
586};
587
588static int mclk_get_divisor(struct pxa_camera_dev *pcdev)
589{
590 unsigned int mclk_10khz = pcdev->platform_mclk_10khz;
591 unsigned long div;
592 unsigned long lcdclk;
593
594 lcdclk = clk_get_rate(pcdev->clk) / 10000;
595
596 /* We verify platform_mclk_10khz != 0, so if anyone breaks it, here
597 * they get a nice Oops */
598 div = (lcdclk + 2 * mclk_10khz - 1) / (2 * mclk_10khz) - 1;
599
600 dev_dbg(pcdev->dev, "LCD clock %lukHz, target freq %dkHz, "
601 "divisor %lu\n", lcdclk * 10, mclk_10khz * 10, div);
602
603 return div;
604}
605
7102b773 606static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
3bc43840
GL		 607{
608 struct pxacamera_platform_data *pdata = pcdev->pdata;
609 u32 cicr4 = 0;
610
611 dev_dbg(pcdev->dev, "Registered platform device at %p data %p\n",
612 pcdev, pdata);
613
614 if (pdata && pdata->init) {
7e28adb2 615 dev_dbg(pcdev->dev, "%s: Init gpios\n", __func__);
3bc43840
GL		 616 pdata->init(pcdev->dev);
617 }
618
619 if (pdata && pdata->power) {
7e28adb2 620 dev_dbg(pcdev->dev, "%s: Power on camera\n", __func__);
3bc43840
GL		 621 pdata->power(pcdev->dev, 1);
622 }
623
624 if (pdata && pdata->reset) {
625 dev_dbg(pcdev->dev, "%s: Releasing camera reset\n",
7e28adb2 626 __func__);
3bc43840
GL		 627 pdata->reset(pcdev->dev, 1);
628 }
629
630 CICR0 = 0x3FF; /* disable all interrupts */
631
632 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
633 cicr4 |= CICR4_PCLK_EN;
634 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
635 cicr4 |= CICR4_MCLK_EN;
636 if (pcdev->platform_flags & PXA_CAMERA_PCP)
637 cicr4 |= CICR4_PCP;
638 if (pcdev->platform_flags & PXA_CAMERA_HSP)
639 cicr4 |= CICR4_HSP;
640 if (pcdev->platform_flags & PXA_CAMERA_VSP)
641 cicr4 |= CICR4_VSP;
642
643 CICR4 = mclk_get_divisor(pcdev) | cicr4;
644
645 clk_enable(pcdev->clk);
646}
647
7102b773 648static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
3bc43840
GL		 649{
650 struct pxacamera_platform_data *board = pcdev->pdata;
651
652 clk_disable(pcdev->clk);
653
654 if (board && board->reset) {
655 dev_dbg(pcdev->dev, "%s: Asserting camera reset\n",
7e28adb2 656 __func__);
3bc43840
GL		 657 board->reset(pcdev->dev, 0);
658 }
659
660 if (board && board->power) {
7e28adb2 661 dev_dbg(pcdev->dev, "%s: Power off camera\n", __func__);
3bc43840
GL		 662 board->power(pcdev->dev, 0);
663 }
664}
665
666static irqreturn_t pxa_camera_irq(int irq, void *data)
667{
668 struct pxa_camera_dev *pcdev = data;
669 unsigned int status = CISR;
670
671 dev_dbg(pcdev->dev, "Camera interrupt status 0x%x\n", status);
672
673 CISR = status;
3bc43840
GL		 674 return IRQ_HANDLED;
675}
676
677/* The following two functions absolutely depend on the fact, that
678 * there can be only one camera on PXA quick capture interface */
7102b773 679static int pxa_camera_add_device(struct soc_camera_device *icd)
3bc43840
GL		 680{
681 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
682 struct pxa_camera_dev *pcdev = ici->priv;
683 int ret;
684
685 mutex_lock(&camera_lock);
686
687 if (pcdev->icd) {
688 ret = -EBUSY;
689 goto ebusy;
690 }
691
692 dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n",
693 icd->devnum);
694
7102b773 695 pxa_camera_activate(pcdev);
3bc43840
GL		 696 ret = icd->ops->init(icd);
697
698 if (!ret)
699 pcdev->icd = icd;
700
701ebusy:
702 mutex_unlock(&camera_lock);
703
704 return ret;
705}
706
7102b773 707static void pxa_camera_remove_device(struct soc_camera_device *icd)
3bc43840
GL		 708{
709 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
710 struct pxa_camera_dev *pcdev = ici->priv;
711
712 BUG_ON(icd != pcdev->icd);
713
714 dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n",
715 icd->devnum);
716
717 /* disable capture, disable interrupts */
718 CICR0 = 0x3ff;
a5462e5b 719
3bc43840 720 /* Stop DMA engine */
a5462e5b
MR		 721 DCSR(pcdev->dma_chans[0]) = 0;
722 DCSR(pcdev->dma_chans[1]) = 0;
723 DCSR(pcdev->dma_chans[2]) = 0;
3bc43840
GL		 724
725 icd->ops->release(icd);
726
7102b773 727 pxa_camera_deactivate(pcdev);
3bc43840
GL		 728
729 pcdev->icd = NULL;
730}
731
ad5f2e85
GL		 732static int test_platform_param(struct pxa_camera_dev *pcdev,
733 unsigned char buswidth, unsigned long *flags)
3bc43840 734{
ad5f2e85
GL		 735 /*
736 * Platform specified synchronization and pixel clock polarities are
737 * only a recommendation and are only used during probing. The PXA270
738 * quick capture interface supports both.
739 */
740 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
741 SOCAM_MASTER : SOCAM_SLAVE) |
742 SOCAM_HSYNC_ACTIVE_HIGH |
743 SOCAM_HSYNC_ACTIVE_LOW |
744 SOCAM_VSYNC_ACTIVE_HIGH |
745 SOCAM_VSYNC_ACTIVE_LOW |
746 SOCAM_PCLK_SAMPLE_RISING |
747 SOCAM_PCLK_SAMPLE_FALLING;
3bc43840
GL		 748
749 /* If requested data width is supported by the platform, use it */
ad5f2e85 750 switch (buswidth) {
3bc43840 751 case 10:
ad5f2e85
GL		 752 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
753 return -EINVAL;
754 *flags |= SOCAM_DATAWIDTH_10;
3bc43840
GL		 755 break;
756 case 9:
ad5f2e85
GL		 757 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
758 return -EINVAL;
759 *flags |= SOCAM_DATAWIDTH_9;
3bc43840
GL		 760 break;
761 case 8:
ad5f2e85
GL		 762 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
763 return -EINVAL;
764 *flags |= SOCAM_DATAWIDTH_8;
3bc43840 765 }
ad5f2e85
GL		 766
767 return 0;
768}
769
770static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
771{
772 struct soc_camera_host *ici =
773 to_soc_camera_host(icd->dev.parent);
774 struct pxa_camera_dev *pcdev = ici->priv;
775 unsigned long dw, bpp, bus_flags, camera_flags, common_flags;
a5462e5b 776 u32 cicr0, cicr1, cicr4 = 0;
ad5f2e85
GL		 777 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
778
779 if (ret < 0)
780 return ret;
781
782 camera_flags = icd->ops->query_bus_param(icd);
783
784 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
785 if (!common_flags)
3bc43840
GL		 786 return -EINVAL;
787
ad5f2e85
GL		 788 /* Make choises, based on platform preferences */
789 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
790 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
791 if (pcdev->platform_flags & PXA_CAMERA_HSP)
792 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
793 else
794 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
795 }
796
797 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
798 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
799 if (pcdev->platform_flags & PXA_CAMERA_VSP)
800 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
801 else
802 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
803 }
804
805 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
806 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
807 if (pcdev->platform_flags & PXA_CAMERA_PCP)
808 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
809 else
810 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
811 }
812
813 ret = icd->ops->set_bus_param(icd, common_flags);
3bc43840
GL		 814 if (ret < 0)
815 return ret;
816
817 /* Datawidth is now guaranteed to be equal to one of the three values.
818 * We fix bit-per-pixel equal to data-width... */
ad5f2e85
GL		 819 switch (common_flags & SOCAM_DATAWIDTH_MASK) {
820 case SOCAM_DATAWIDTH_10:
821 icd->buswidth = 10;
3bc43840
GL		 822 dw = 4;
823 bpp = 0x40;
824 break;
ad5f2e85
GL		 825 case SOCAM_DATAWIDTH_9:
826 icd->buswidth = 9;
3bc43840
GL		 827 dw = 3;
828 bpp = 0x20;
829 break;
830 default:
831 /* Actually it can only be 8 now,
832 * default is just to silence compiler warnings */
ad5f2e85
GL		 833 case SOCAM_DATAWIDTH_8:
834 icd->buswidth = 8;
3bc43840
GL		 835 dw = 2;
836 bpp = 0;
837 }
838
839 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
840 cicr4 |= CICR4_PCLK_EN;
841 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
842 cicr4 |= CICR4_MCLK_EN;
ad5f2e85 843 if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
3bc43840 844 cicr4 |= CICR4_PCP;
ad5f2e85 845 if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
3bc43840 846 cicr4 |= CICR4_HSP;
ad5f2e85 847 if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
3bc43840
GL		 848 cicr4 |= CICR4_VSP;
849
850 cicr0 = CICR0;
851 if (cicr0 & CICR0_ENB)
852 CICR0 = cicr0 & ~CICR0_ENB;
a5462e5b
MR		 853
854 cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw;
855
856 switch (pixfmt) {
857 case V4L2_PIX_FMT_YUV422P:
858 cicr1 |= CICR1_YCBCR_F;
859 case V4L2_PIX_FMT_YUYV:
860 cicr1 |= CICR1_COLOR_SP_VAL(2);
861 break;
862 case V4L2_PIX_FMT_RGB555:
863 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
864 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
865 break;
866 case V4L2_PIX_FMT_RGB565:
867 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
868 break;
869 }
870
871 CICR1 = cicr1;
3bc43840 872 CICR2 = 0;
ad5f2e85 873 CICR3 = CICR3_LPF_VAL(icd->height - 1) |
3bc43840
GL		 874 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
875 CICR4 = mclk_get_divisor(pcdev) | cicr4;
876
877 /* CIF interrupts are not used, only DMA */
878 CICR0 = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
7102b773 879 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)) |
3bc43840
GL		 880 CICR0_DMAEN | CICR0_IRQ_MASK | (cicr0 & CICR0_ENB);
881
882 return 0;
883}
884
ad5f2e85
GL		 885static int pxa_camera_try_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
886{
887 struct soc_camera_host *ici =
888 to_soc_camera_host(icd->dev.parent);
889 struct pxa_camera_dev *pcdev = ici->priv;
890 unsigned long bus_flags, camera_flags;
891 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
892
893 if (ret < 0)
894 return ret;
895
896 camera_flags = icd->ops->query_bus_param(icd);
897
898 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
899}
900
901static int pxa_camera_set_fmt_cap(struct soc_camera_device *icd,
902 __u32 pixfmt, struct v4l2_rect *rect)
903{
904 return icd->ops->set_fmt_cap(icd, pixfmt, rect);
905}
906
907static int pxa_camera_try_fmt_cap(struct soc_camera_device *icd,
7102b773 908 struct v4l2_format *f)
3bc43840
GL		 909{
910 /* limit to pxa hardware capabilities */
911 if (f->fmt.pix.height < 32)
912 f->fmt.pix.height = 32;
913 if (f->fmt.pix.height > 2048)
914 f->fmt.pix.height = 2048;
915 if (f->fmt.pix.width < 48)
916 f->fmt.pix.width = 48;
917 if (f->fmt.pix.width > 2048)
918 f->fmt.pix.width = 2048;
919 f->fmt.pix.width &= ~0x01;
920
ad5f2e85
GL		 921 /* limit to sensor capabilities */
922 return icd->ops->try_fmt_cap(icd, f);
3bc43840
GL		 923}
924
7102b773
GL		 925static int pxa_camera_reqbufs(struct soc_camera_file *icf,
926 struct v4l2_requestbuffers *p)
3bc43840
GL		 927{
928 int i;
929
930 /* This is for locking debugging only. I removed spinlocks and now I
931 * check whether .prepare is ever called on a linked buffer, or whether
932 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
933 * it hadn't triggered */
934 for (i = 0; i < p->count; i++) {
935 struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
936 struct pxa_buffer, vb);
937 buf->inwork = 0;
938 INIT_LIST_HEAD(&buf->vb.queue);
939 }
940
941 return 0;
942}
943
7102b773 944static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
3bc43840
GL		 945{
946 struct soc_camera_file *icf = file->private_data;
947 struct pxa_buffer *buf;
948
949 buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
950 vb.stream);
951
952 poll_wait(file, &buf->vb.done, pt);
953
954 if (buf->vb.state == VIDEOBUF_DONE ||
955 buf->vb.state == VIDEOBUF_ERROR)
956 return POLLIN|POLLRDNORM;
957
958 return 0;
959}
960
7102b773
GL		 961static int pxa_camera_querycap(struct soc_camera_host *ici,
962 struct v4l2_capability *cap)
3bc43840
GL		 963{
964 /* cap->name is set by the firendly caller:-> */
965 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
966 cap->version = PXA_CAM_VERSION_CODE;
967 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
968
969 return 0;
970}
971
1a0063a9
GL		 972static spinlock_t *pxa_camera_spinlock_alloc(struct soc_camera_file *icf)
973{
974 struct soc_camera_host *ici =
975 to_soc_camera_host(icf->icd->dev.parent);
976 struct pxa_camera_dev *pcdev = ici->priv;
977
978 return &pcdev->lock;
979}
980
b8d9904c
GL		 981static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
982 .owner = THIS_MODULE,
983 .add = pxa_camera_add_device,
984 .remove = pxa_camera_remove_device,
985 .set_fmt_cap = pxa_camera_set_fmt_cap,
986 .try_fmt_cap = pxa_camera_try_fmt_cap,
987 .reqbufs = pxa_camera_reqbufs,
988 .poll = pxa_camera_poll,
989 .querycap = pxa_camera_querycap,
990 .try_bus_param = pxa_camera_try_bus_param,
991 .set_bus_param = pxa_camera_set_bus_param,
1a0063a9 992 .spinlock_alloc = pxa_camera_spinlock_alloc,
b8d9904c
GL		 993};
994
995/* Should be allocated dynamically too, but we have only one. */
3bc43840
GL		 996static struct soc_camera_host pxa_soc_camera_host = {
997 .drv_name = PXA_CAM_DRV_NAME,
7102b773 998 .vbq_ops = &pxa_videobuf_ops,
3bc43840 999 .msize = sizeof(struct pxa_buffer),
b8d9904c 1000 .ops = &pxa_soc_camera_host_ops,
3bc43840
GL		 1001};
1002
1003static int pxa_camera_probe(struct platform_device *pdev)
1004{
1005 struct pxa_camera_dev *pcdev;
1006 struct resource *res;
1007 void __iomem *base;
1008 unsigned int irq;
1009 int err = 0;
1010
1011 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1012 irq = platform_get_irq(pdev, 0);
1013 if (!res || !irq) {
1014 err = -ENODEV;
1015 goto exit;
1016 }
1017
1018 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1019 if (!pcdev) {
7102b773 1020 dev_err(&pdev->dev, "Could not allocate pcdev\n");
3bc43840
GL		 1021 err = -ENOMEM;
1022 goto exit;
1023 }
1024
1025 pcdev->clk = clk_get(&pdev->dev, "CAMCLK");
1026 if (IS_ERR(pcdev->clk)) {
1027 err = PTR_ERR(pcdev->clk);
1028 goto exit_kfree;
1029 }
1030
1031 dev_set_drvdata(&pdev->dev, pcdev);
1032 pcdev->res = res;
1033
1034 pcdev->pdata = pdev->dev.platform_data;
1035 pcdev->platform_flags = pcdev->pdata->flags;
ad5f2e85
GL		 1036 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1037 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
3bc43840
GL		 1038 /* Platform hasn't set available data widths. This is bad.
1039 * Warn and use a default. */
1040 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1041 "data widths, using default 10 bit\n");
1042 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1043 }
1044 pcdev->platform_mclk_10khz = pcdev->pdata->mclk_10khz;
1045 if (!pcdev->platform_mclk_10khz) {
1046 dev_warn(&pdev->dev,
1047 "mclk_10khz == 0! Please, fix your platform data. "
1048 "Using default 20MHz\n");
1049 pcdev->platform_mclk_10khz = 2000;
1050 }
1051
1052 INIT_LIST_HEAD(&pcdev->capture);
1053 spin_lock_init(&pcdev->lock);
1054
1055 /*
1056 * Request the regions.
1057 */
1058 if (!request_mem_region(res->start, res->end - res->start + 1,
1059 PXA_CAM_DRV_NAME)) {
1060 err = -EBUSY;
1061 goto exit_clk;
1062 }
1063
1064 base = ioremap(res->start, res->end - res->start + 1);
1065 if (!base) {
1066 err = -ENOMEM;
1067 goto exit_release;
1068 }
1069 pcdev->irq = irq;
1070 pcdev->base = base;
1071 pcdev->dev = &pdev->dev;
1072
1073 /* request dma */
a5462e5b
MR		 1074 pcdev->dma_chans[0] = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1075 pxa_camera_dma_irq_y, pcdev);
1076 if (pcdev->dma_chans[0] < 0) {
3bc43840
GL		 1077 dev_err(pcdev->dev, "Can't request DMA for Y\n");
1078 err = -ENOMEM;
1079 goto exit_iounmap;
1080 }
a5462e5b
MR		 1081 dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1082
1083 pcdev->dma_chans[1] = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1084 pxa_camera_dma_irq_u, pcdev);
1085 if (pcdev->dma_chans[1] < 0) {
1086 dev_err(pcdev->dev, "Can't request DMA for U\n");
1087 err = -ENOMEM;
1088 goto exit_free_dma_y;
1089 }
1090 dev_dbg(pcdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1091
1092 pcdev->dma_chans[2] = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1093 pxa_camera_dma_irq_v, pcdev);
1094 if (pcdev->dma_chans[0] < 0) {
1095 dev_err(pcdev->dev, "Can't request DMA for V\n");
1096 err = -ENOMEM;
1097 goto exit_free_dma_u;
1098 }
1099 dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
3bc43840 1100
a5462e5b
MR		 1101 DRCMR68 = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1102 DRCMR69 = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1103 DRCMR70 = pcdev->dma_chans[2] | DRCMR_MAPVLD;
3bc43840
GL		 1104
1105 /* request irq */
1106 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1107 pcdev);
1108 if (err) {
1109 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1110 goto exit_free_dma;
1111 }
1112
1113 pxa_soc_camera_host.priv = pcdev;
1114 pxa_soc_camera_host.dev.parent = &pdev->dev;
1115 pxa_soc_camera_host.nr = pdev->id;
b8d9904c 1116 err = soc_camera_host_register(&pxa_soc_camera_host);
3bc43840
GL		 1117 if (err)
1118 goto exit_free_irq;
1119
1120 return 0;
1121
1122exit_free_irq:
1123 free_irq(pcdev->irq, pcdev);
1124exit_free_dma:
a5462e5b
MR		 1125 pxa_free_dma(pcdev->dma_chans[2]);
1126exit_free_dma_u:
1127 pxa_free_dma(pcdev->dma_chans[1]);
1128exit_free_dma_y:
1129 pxa_free_dma(pcdev->dma_chans[0]);
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GL		 1130exit_iounmap:
1131 iounmap(base);
1132exit_release:
1133 release_mem_region(res->start, res->end - res->start + 1);
1134exit_clk:
1135 clk_put(pcdev->clk);
1136exit_kfree:
1137 kfree(pcdev);
1138exit:
1139 return err;
1140}
1141
1142static int __devexit pxa_camera_remove(struct platform_device *pdev)
1143{
1144 struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev);
1145 struct resource *res;
1146
1147 clk_put(pcdev->clk);
1148
a5462e5b
MR		 1149 pxa_free_dma(pcdev->dma_chans[0]);
1150 pxa_free_dma(pcdev->dma_chans[1]);
1151 pxa_free_dma(pcdev->dma_chans[2]);
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GL		 1152 free_irq(pcdev->irq, pcdev);
1153
1154 soc_camera_host_unregister(&pxa_soc_camera_host);
1155
1156 iounmap(pcdev->base);
1157
1158 res = pcdev->res;
1159 release_mem_region(res->start, res->end - res->start + 1);
1160
1161 kfree(pcdev);
1162
7102b773 1163 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
3bc43840 1164
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GL		 1165 return 0;
1166}
1167
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GL		 1168static struct platform_driver pxa_camera_driver = {
1169 .driver = {
1170 .name = PXA_CAM_DRV_NAME,
1171 },
1172 .probe = pxa_camera_probe,
1173 .remove = __exit_p(pxa_camera_remove),
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GL		 1174};
1175
1176
1177static int __devinit pxa_camera_init(void)
1178{
1179 return platform_driver_register(&pxa_camera_driver);
1180}
1181
1182static void __exit pxa_camera_exit(void)
1183{
1184 return platform_driver_unregister(&pxa_camera_driver);
1185}
1186
1187module_init(pxa_camera_init);
1188module_exit(pxa_camera_exit);
1189
1190MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1191MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1192MODULE_LICENSE("GPL");
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