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Merge branch 'for_rmk' of git://git.mnementh.co.uk/linux-2.6-im into devel
[mirror_ubuntu-zesty-kernel.git] / drivers / media / video / pxa_camera.c
CommitLineData
3bc43840
GL		 1/*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
3bc43840
GL		 13#include <linux/init.h>
14#include <linux/module.h>
7102b773 15#include <linux/io.h>
3bc43840
GL		 16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/errno.h>
19#include <linux/fs.h>
20#include <linux/interrupt.h>
21#include <linux/kernel.h>
22#include <linux/mm.h>
23#include <linux/moduleparam.h>
24#include <linux/time.h>
25#include <linux/version.h>
26#include <linux/device.h>
27#include <linux/platform_device.h>
28#include <linux/mutex.h>
29#include <linux/clk.h>
30
31#include <media/v4l2-common.h>
32#include <media/v4l2-dev.h>
092d3921 33#include <media/videobuf-dma-sg.h>
3bc43840
GL		 34#include <media/soc_camera.h>
35
36#include <linux/videodev2.h>
37
38#include <asm/dma.h>
a09e64fb
RK		 39#include <mach/pxa-regs.h>
40#include <mach/camera.h>
3bc43840 41
013132ca 42#include "pxa_camera.h"
3bc43840
GL		 43
44#define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
45#define PXA_CAM_DRV_NAME "pxa27x-camera"
46
7102b773
GL		 47#define CICR0_SIM_MP (0 << 24)
48#define CICR0_SIM_SP (1 << 24)
49#define CICR0_SIM_MS (2 << 24)
50#define CICR0_SIM_EP (3 << 24)
51#define CICR0_SIM_ES (4 << 24)
52
53#define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
54#define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
a5462e5b
MR		 55#define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
56#define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
57#define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
7102b773
GL		 58
59#define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
60#define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
61#define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
62#define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
63#define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
64
65#define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
66#define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
67#define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
68#define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
69
3bc43840
GL		 70#define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
71 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
72 CICR0_EOFM | CICR0_FOM)
73
74static DEFINE_MUTEX(camera_lock);
75
76/*
77 * Structures
78 */
a5462e5b
MR		 79enum pxa_camera_active_dma {
80 DMA_Y = 0x1,
81 DMA_U = 0x2,
82 DMA_V = 0x4,
83};
84
85/* descriptor needed for the PXA DMA engine */
86struct pxa_cam_dma {
87 dma_addr_t sg_dma;
88 struct pxa_dma_desc *sg_cpu;
89 size_t sg_size;
90 int sglen;
91};
3bc43840
GL		 92
93/* buffer for one video frame */
94struct pxa_buffer {
95 /* common v4l buffer stuff -- must be first */
96 struct videobuf_buffer vb;
97
98 const struct soc_camera_data_format *fmt;
99
a5462e5b
MR		 100 /* our descriptor lists for Y, U and V channels */
101 struct pxa_cam_dma dmas[3];
102
3bc43840 103 int inwork;
a5462e5b
MR		 104
105 enum pxa_camera_active_dma active_dma;
3bc43840
GL		 106};
107
3bc43840
GL		 108struct pxa_camera_dev {
109 struct device *dev;
110 /* PXA27x is only supposed to handle one camera on its Quick Capture
111 * interface. If anyone ever builds hardware to enable more than
112 * one camera, they will have to modify this driver too */
113 struct soc_camera_device *icd;
114 struct clk *clk;
115
116 unsigned int irq;
117 void __iomem *base;
a5462e5b 118
e7c50688 119 int channels;
a5462e5b 120 unsigned int dma_chans[3];
3bc43840 121
3bc43840
GL		 122 struct pxacamera_platform_data *pdata;
123 struct resource *res;
124 unsigned long platform_flags;
125 unsigned long platform_mclk_10khz;
126
127 struct list_head capture;
128
129 spinlock_t lock;
130
3bc43840 131 struct pxa_buffer *active;
5aa2110f 132 struct pxa_dma_desc *sg_tail[3];
3f6ac497
RJ		 133
134 u32 save_cicr[5];
3bc43840
GL		 135};
136
137static const char *pxa_cam_driver_description = "PXA_Camera";
138
139static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
140
141/*
142 * Videobuf operations
143 */
7102b773
GL		 144static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
145 unsigned int *size)
3bc43840
GL		 146{
147 struct soc_camera_device *icd = vq->priv_data;
5aa2110f
GL		 148 struct soc_camera_host *ici =
149 to_soc_camera_host(icd->dev.parent);
150 struct pxa_camera_dev *pcdev = ici->priv;
3bc43840
GL		 151
152 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
153
a5462e5b 154 /* planar capture requires Y, U and V buffers to be page aligned */
5aa2110f 155 if (pcdev->channels == 3) {
a5462e5b
MR		 156 *size = PAGE_ALIGN(icd->width * icd->height); /* Y pages */
157 *size += PAGE_ALIGN(icd->width * icd->height / 2); /* U pages */
158 *size += PAGE_ALIGN(icd->width * icd->height / 2); /* V pages */
159 } else {
160 *size = icd->width * icd->height *
161 ((icd->current_fmt->depth + 7) >> 3);
162 }
3bc43840
GL		 163
164 if (0 == *count)
165 *count = 32;
166 while (*size * *count > vid_limit * 1024 * 1024)
167 (*count)--;
168
169 return 0;
170}
171
172static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
173{
174 struct soc_camera_device *icd = vq->priv_data;
175 struct soc_camera_host *ici =
176 to_soc_camera_host(icd->dev.parent);
177 struct pxa_camera_dev *pcdev = ici->priv;
178 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
a5462e5b 179 int i;
3bc43840
GL		 180
181 BUG_ON(in_interrupt());
182
7e28adb2 183 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 184 &buf->vb, buf->vb.baddr, buf->vb.bsize);
185
186 /* This waits until this buffer is out of danger, i.e., until it is no
187 * longer in STATE_QUEUED or STATE_ACTIVE */
188 videobuf_waiton(&buf->vb, 0, 0);
189 videobuf_dma_unmap(vq, dma);
190 videobuf_dma_free(dma);
191
a5462e5b
MR		 192 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
193 if (buf->dmas[i].sg_cpu)
194 dma_free_coherent(pcdev->dev, buf->dmas[i].sg_size,
195 buf->dmas[i].sg_cpu,
196 buf->dmas[i].sg_dma);
197 buf->dmas[i].sg_cpu = NULL;
198 }
3bc43840
GL		 199
200 buf->vb.state = VIDEOBUF_NEEDS_INIT;
201}
202
a5462e5b
MR		 203static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
204 struct pxa_buffer *buf,
205 struct videobuf_dmabuf *dma, int channel,
206 int sglen, int sg_start, int cibr,
207 unsigned int size)
208{
209 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
210 int i;
211
212 if (pxa_dma->sg_cpu)
213 dma_free_coherent(pcdev->dev, pxa_dma->sg_size,
214 pxa_dma->sg_cpu, pxa_dma->sg_dma);
215
216 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
217 pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->dev, pxa_dma->sg_size,
218 &pxa_dma->sg_dma, GFP_KERNEL);
219 if (!pxa_dma->sg_cpu)
220 return -ENOMEM;
221
222 pxa_dma->sglen = sglen;
223
224 for (i = 0; i < sglen; i++) {
225 int sg_i = sg_start + i;
226 struct scatterlist *sg = dma->sglist;
227 unsigned int dma_len = sg_dma_len(&sg[sg_i]), xfer_len;
228
229 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
230 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(&sg[sg_i]);
231
232 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
233 xfer_len = (min(dma_len, size) + 7) & ~7;
234
235 pxa_dma->sg_cpu[i].dcmd =
236 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
237 size -= dma_len;
238 pxa_dma->sg_cpu[i].ddadr =
239 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
240 }
241
242 pxa_dma->sg_cpu[sglen - 1].ddadr = DDADR_STOP;
243 pxa_dma->sg_cpu[sglen - 1].dcmd |= DCMD_ENDIRQEN;
244
245 return 0;
246}
247
7102b773
GL		 248static int pxa_videobuf_prepare(struct videobuf_queue *vq,
249 struct videobuf_buffer *vb, enum v4l2_field field)
3bc43840
GL		 250{
251 struct soc_camera_device *icd = vq->priv_data;
252 struct soc_camera_host *ici =
253 to_soc_camera_host(icd->dev.parent);
254 struct pxa_camera_dev *pcdev = ici->priv;
255 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
a5462e5b
MR		 256 int ret;
257 int sglen_y, sglen_yu = 0, sglen_u = 0, sglen_v = 0;
258 int size_y, size_u = 0, size_v = 0;
3bc43840 259
7e28adb2 260 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 261 vb, vb->baddr, vb->bsize);
262
263 /* Added list head initialization on alloc */
264 WARN_ON(!list_empty(&vb->queue));
265
266#ifdef DEBUG
267 /* This can be useful if you want to see if we actually fill
268 * the buffer with something */
269 memset((void *)vb->baddr, 0xaa, vb->bsize);
270#endif
271
272 BUG_ON(NULL == icd->current_fmt);
273
274 /* I think, in buf_prepare you only have to protect global data,
275 * the actual buffer is yours */
276 buf->inwork = 1;
277
278 if (buf->fmt != icd->current_fmt ||
279 vb->width != icd->width ||
280 vb->height != icd->height ||
281 vb->field != field) {
282 buf->fmt = icd->current_fmt;
283 vb->width = icd->width;
284 vb->height = icd->height;
285 vb->field = field;
286 vb->state = VIDEOBUF_NEEDS_INIT;
287 }
288
289 vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3);
290 if (0 != vb->baddr && vb->bsize < vb->size) {
291 ret = -EINVAL;
292 goto out;
293 }
294
295 if (vb->state == VIDEOBUF_NEEDS_INIT) {
296 unsigned int size = vb->size;
297 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
298
299 ret = videobuf_iolock(vq, vb, NULL);
300 if (ret)
301 goto fail;
302
5aa2110f 303 if (pcdev->channels == 3) {
a5462e5b
MR		 304 /* FIXME the calculations should be more precise */
305 sglen_y = dma->sglen / 2;
306 sglen_u = sglen_v = dma->sglen / 4 + 1;
307 sglen_yu = sglen_y + sglen_u;
308 size_y = size / 2;
309 size_u = size_v = size / 4;
310 } else {
311 sglen_y = dma->sglen;
312 size_y = size;
313 }
314
315 /* init DMA for Y channel */
316 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, sglen_y,
317 0, 0x28, size_y);
3bc43840 318
a5462e5b
MR		 319 if (ret) {
320 dev_err(pcdev->dev,
321 "DMA initialization for Y/RGB failed\n");
3bc43840
GL		 322 goto fail;
323 }
324
5aa2110f 325 if (pcdev->channels == 3) {
a5462e5b
MR		 326 /* init DMA for U channel */
327 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, sglen_u,
328 sglen_y, 0x30, size_u);
329 if (ret) {
330 dev_err(pcdev->dev,
331 "DMA initialization for U failed\n");
332 goto fail_u;
333 }
334
335 /* init DMA for V channel */
336 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, sglen_v,
337 sglen_yu, 0x38, size_v);
338 if (ret) {
339 dev_err(pcdev->dev,
340 "DMA initialization for V failed\n");
341 goto fail_v;
342 }
3bc43840 343 }
3bc43840
GL		 344
345 vb->state = VIDEOBUF_PREPARED;
346 }
347
348 buf->inwork = 0;
a5462e5b 349 buf->active_dma = DMA_Y;
5aa2110f 350 if (pcdev->channels == 3)
a5462e5b 351 buf->active_dma |= DMA_U | DMA_V;
3bc43840
GL		 352
353 return 0;
354
a5462e5b
MR		 355fail_v:
356 dma_free_coherent(pcdev->dev, buf->dmas[1].sg_size,
357 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
358fail_u:
359 dma_free_coherent(pcdev->dev, buf->dmas[0].sg_size,
360 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
3bc43840
GL		 361fail:
362 free_buffer(vq, buf);
363out:
364 buf->inwork = 0;
365 return ret;
366}
367
7102b773
GL		 368static void pxa_videobuf_queue(struct videobuf_queue *vq,
369 struct videobuf_buffer *vb)
3bc43840
GL		 370{
371 struct soc_camera_device *icd = vq->priv_data;
372 struct soc_camera_host *ici =
373 to_soc_camera_host(icd->dev.parent);
374 struct pxa_camera_dev *pcdev = ici->priv;
375 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
7102b773 376 struct pxa_buffer *active;
3bc43840 377 unsigned long flags;
5aa2110f 378 int i;
3bc43840 379
7e28adb2 380 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 381 vb, vb->baddr, vb->bsize);
382 spin_lock_irqsave(&pcdev->lock, flags);
383
384 list_add_tail(&vb->queue, &pcdev->capture);
385
386 vb->state = VIDEOBUF_ACTIVE;
7102b773 387 active = pcdev->active;
3bc43840 388
7102b773 389 if (!active) {
3bc43840 390 CIFR |= CIFR_RESET_F;
a5462e5b 391
5aa2110f
GL		 392 for (i = 0; i < pcdev->channels; i++) {
393 DDADR(pcdev->dma_chans[i]) = buf->dmas[i].sg_dma;
394 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
395 pcdev->sg_tail[i] = buf->dmas[i].sg_cpu + buf->dmas[i].sglen - 1;
a5462e5b
MR		 396 }
397
3bc43840
GL		 398 pcdev->active = buf;
399 CICR0 |= CICR0_ENB;
400 } else {
a5462e5b
MR		 401 struct pxa_cam_dma *buf_dma;
402 struct pxa_cam_dma *act_dma;
a5462e5b 403 int nents;
a5462e5b 404
e7c50688 405 for (i = 0; i < pcdev->channels; i++) {
a5462e5b
MR		 406 buf_dma = &buf->dmas[i];
407 act_dma = &active->dmas[i];
408 nents = buf_dma->sglen;
409
410 /* Stop DMA engine */
411 DCSR(pcdev->dma_chans[i]) = 0;
412
413 /* Add the descriptors we just initialized to
414 the currently running chain */
5aa2110f
GL		 415 pcdev->sg_tail[i]->ddadr = buf_dma->sg_dma;
416 pcdev->sg_tail[i] = buf_dma->sg_cpu + buf_dma->sglen - 1;
a5462e5b
MR		 417
418 /* Setup a dummy descriptor with the DMA engines current
419 * state
3bc43840 420 */
a5462e5b
MR		 421 buf_dma->sg_cpu[nents].dsadr =
422 pcdev->res->start + 0x28 + i*8; /* CIBRx */
423 buf_dma->sg_cpu[nents].dtadr =
424 DTADR(pcdev->dma_chans[i]);
425 buf_dma->sg_cpu[nents].dcmd =
426 DCMD(pcdev->dma_chans[i]);
427
428 if (DDADR(pcdev->dma_chans[i]) == DDADR_STOP) {
429 /* The DMA engine is on the last
430 descriptor, set the next descriptors
431 address to the descriptors we just
432 initialized */
433 buf_dma->sg_cpu[nents].ddadr = buf_dma->sg_dma;
434 } else {
435 buf_dma->sg_cpu[nents].ddadr =
436 DDADR(pcdev->dma_chans[i]);
437 }
438
439 /* The next descriptor is the dummy descriptor */
440 DDADR(pcdev->dma_chans[i]) = buf_dma->sg_dma + nents *
441 sizeof(struct pxa_dma_desc);
442
443 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
3bc43840 444 }
3bc43840
GL		 445 }
446
447 spin_unlock_irqrestore(&pcdev->lock, flags);
3bc43840
GL		 448}
449
450static void pxa_videobuf_release(struct videobuf_queue *vq,
451 struct videobuf_buffer *vb)
452{
453 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
454#ifdef DEBUG
455 struct soc_camera_device *icd = vq->priv_data;
456
7e28adb2 457 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 458 vb, vb->baddr, vb->bsize);
459
460 switch (vb->state) {
461 case VIDEOBUF_ACTIVE:
7e28adb2 462 dev_dbg(&icd->dev, "%s (active)\n", __func__);
3bc43840
GL		 463 break;
464 case VIDEOBUF_QUEUED:
7e28adb2 465 dev_dbg(&icd->dev, "%s (queued)\n", __func__);
3bc43840
GL		 466 break;
467 case VIDEOBUF_PREPARED:
7e28adb2 468 dev_dbg(&icd->dev, "%s (prepared)\n", __func__);
3bc43840
GL		 469 break;
470 default:
7e28adb2 471 dev_dbg(&icd->dev, "%s (unknown)\n", __func__);
3bc43840
GL		 472 break;
473 }
474#endif
475
476 free_buffer(vq, buf);
477}
478
a5462e5b
MR		 479static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
480 struct videobuf_buffer *vb,
481 struct pxa_buffer *buf)
482{
483 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
484 list_del_init(&vb->queue);
485 vb->state = VIDEOBUF_DONE;
486 do_gettimeofday(&vb->ts);
487 vb->field_count++;
488 wake_up(&vb->done);
489
490 if (list_empty(&pcdev->capture)) {
491 pcdev->active = NULL;
492 DCSR(pcdev->dma_chans[0]) = 0;
493 DCSR(pcdev->dma_chans[1]) = 0;
494 DCSR(pcdev->dma_chans[2]) = 0;
495 CICR0 &= ~CICR0_ENB;
496 return;
497 }
498
499 pcdev->active = list_entry(pcdev->capture.next,
500 struct pxa_buffer, vb.queue);
501}
502
503static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
504 enum pxa_camera_active_dma act_dma)
3bc43840 505{
3bc43840
GL		 506 struct pxa_buffer *buf;
507 unsigned long flags;
e7c50688 508 u32 status, camera_status, overrun;
3bc43840
GL		 509 struct videobuf_buffer *vb;
510
511 spin_lock_irqsave(&pcdev->lock, flags);
512
a5462e5b
MR		 513 status = DCSR(channel);
514 DCSR(channel) = status | DCSR_ENDINTR;
7102b773 515
3bc43840 516 if (status & DCSR_BUSERR) {
7102b773 517 dev_err(pcdev->dev, "DMA Bus Error IRQ!\n");
3bc43840
GL		 518 goto out;
519 }
520
521 if (!(status & DCSR_ENDINTR)) {
7102b773
GL		 522 dev_err(pcdev->dev, "Unknown DMA IRQ source, "
523 "status: 0x%08x\n", status);
3bc43840
GL		 524 goto out;
525 }
526
3bc43840 527 if (!pcdev->active) {
7102b773 528 dev_err(pcdev->dev, "DMA End IRQ with no active buffer!\n");
3bc43840
GL		 529 goto out;
530 }
531
e7c50688
GL		 532 camera_status = CISR;
533 overrun = CISR_IFO_0;
534 if (pcdev->channels == 3)
535 overrun |= CISR_IFO_1 | CISR_IFO_2;
536 if (camera_status & overrun) {
537 dev_dbg(pcdev->dev, "FIFO overrun! CISR: %x\n", camera_status);
538 /* Stop the Capture Interface */
539 CICR0 &= ~CICR0_ENB;
540 /* Stop DMA */
541 DCSR(channel) = 0;
542 /* Reset the FIFOs */
543 CIFR |= CIFR_RESET_F;
544 /* Enable End-Of-Frame Interrupt */
545 CICR0 &= ~CICR0_EOFM;
546 /* Restart the Capture Interface */
547 CICR0 |= CICR0_ENB;
548 goto out;
549 }
550
3bc43840
GL		 551 vb = &pcdev->active->vb;
552 buf = container_of(vb, struct pxa_buffer, vb);
553 WARN_ON(buf->inwork || list_empty(&vb->queue));
7e28adb2 554 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
3bc43840
GL		 555 vb, vb->baddr, vb->bsize);
556
a5462e5b
MR		 557 buf->active_dma &= ~act_dma;
558 if (!buf->active_dma)
559 pxa_camera_wakeup(pcdev, vb, buf);
3bc43840
GL		 560
561out:
562 spin_unlock_irqrestore(&pcdev->lock, flags);
563}
564
a5462e5b
MR		 565static void pxa_camera_dma_irq_y(int channel, void *data)
566{
567 struct pxa_camera_dev *pcdev = data;
568 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
569}
570
571static void pxa_camera_dma_irq_u(int channel, void *data)
572{
573 struct pxa_camera_dev *pcdev = data;
574 pxa_camera_dma_irq(channel, pcdev, DMA_U);
575}
576
577static void pxa_camera_dma_irq_v(int channel, void *data)
578{
579 struct pxa_camera_dev *pcdev = data;
580 pxa_camera_dma_irq(channel, pcdev, DMA_V);
581}
582
7102b773 583static struct videobuf_queue_ops pxa_videobuf_ops = {
3bc43840
GL		 584 .buf_setup = pxa_videobuf_setup,
585 .buf_prepare = pxa_videobuf_prepare,
586 .buf_queue = pxa_videobuf_queue,
587 .buf_release = pxa_videobuf_release,
588};
589
a034d1b7 590static void pxa_camera_init_videobuf(struct videobuf_queue *q,
092d3921
PZ		 591 struct soc_camera_device *icd)
592{
a034d1b7
MD		 593 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
594 struct pxa_camera_dev *pcdev = ici->priv;
595
092d3921
PZ		 596 /* We must pass NULL as dev pointer, then all pci_* dma operations
597 * transform to normal dma_* ones. */
a034d1b7 598 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
092d3921
PZ		 599 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
600 sizeof(struct pxa_buffer), icd);
601}
602
3bc43840
GL		 603static int mclk_get_divisor(struct pxa_camera_dev *pcdev)
604{
605 unsigned int mclk_10khz = pcdev->platform_mclk_10khz;
606 unsigned long div;
607 unsigned long lcdclk;
608
609 lcdclk = clk_get_rate(pcdev->clk) / 10000;
610
611 /* We verify platform_mclk_10khz != 0, so if anyone breaks it, here
612 * they get a nice Oops */
613 div = (lcdclk + 2 * mclk_10khz - 1) / (2 * mclk_10khz) - 1;
614
615 dev_dbg(pcdev->dev, "LCD clock %lukHz, target freq %dkHz, "
616 "divisor %lu\n", lcdclk * 10, mclk_10khz * 10, div);
617
618 return div;
619}
620
7102b773 621static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
3bc43840
GL		 622{
623 struct pxacamera_platform_data *pdata = pcdev->pdata;
624 u32 cicr4 = 0;
625
626 dev_dbg(pcdev->dev, "Registered platform device at %p data %p\n",
627 pcdev, pdata);
628
629 if (pdata && pdata->init) {
7e28adb2 630 dev_dbg(pcdev->dev, "%s: Init gpios\n", __func__);
3bc43840
GL		 631 pdata->init(pcdev->dev);
632 }
633
3bc43840
GL		 634 CICR0 = 0x3FF; /* disable all interrupts */
635
636 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
637 cicr4 |= CICR4_PCLK_EN;
638 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
639 cicr4 |= CICR4_MCLK_EN;
640 if (pcdev->platform_flags & PXA_CAMERA_PCP)
641 cicr4 |= CICR4_PCP;
642 if (pcdev->platform_flags & PXA_CAMERA_HSP)
643 cicr4 |= CICR4_HSP;
644 if (pcdev->platform_flags & PXA_CAMERA_VSP)
645 cicr4 |= CICR4_VSP;
646
647 CICR4 = mclk_get_divisor(pcdev) | cicr4;
648
649 clk_enable(pcdev->clk);
650}
651
7102b773 652static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
3bc43840 653{
3bc43840 654 clk_disable(pcdev->clk);
3bc43840
GL		 655}
656
657static irqreturn_t pxa_camera_irq(int irq, void *data)
658{
659 struct pxa_camera_dev *pcdev = data;
660 unsigned int status = CISR;
661
662 dev_dbg(pcdev->dev, "Camera interrupt status 0x%x\n", status);
663
e7c50688
GL		 664 if (!status)
665 return IRQ_NONE;
666
3bc43840 667 CISR = status;
e7c50688
GL		 668
669 if (status & CISR_EOF) {
670 int i;
671 for (i = 0; i < pcdev->channels; i++) {
672 DDADR(pcdev->dma_chans[i]) =
673 pcdev->active->dmas[i].sg_dma;
674 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
675 }
676 CICR0 |= CICR0_EOFM;
677 }
678
3bc43840
GL		 679 return IRQ_HANDLED;
680}
681
682/* The following two functions absolutely depend on the fact, that
683 * there can be only one camera on PXA quick capture interface */
7102b773 684static int pxa_camera_add_device(struct soc_camera_device *icd)
3bc43840
GL		 685{
686 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
687 struct pxa_camera_dev *pcdev = ici->priv;
688 int ret;
689
690 mutex_lock(&camera_lock);
691
692 if (pcdev->icd) {
693 ret = -EBUSY;
694 goto ebusy;
695 }
696
697 dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n",
698 icd->devnum);
699
7102b773 700 pxa_camera_activate(pcdev);
3bc43840
GL		 701 ret = icd->ops->init(icd);
702
703 if (!ret)
704 pcdev->icd = icd;
705
706ebusy:
707 mutex_unlock(&camera_lock);
708
709 return ret;
710}
711
7102b773 712static void pxa_camera_remove_device(struct soc_camera_device *icd)
3bc43840
GL		 713{
714 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
715 struct pxa_camera_dev *pcdev = ici->priv;
716
717 BUG_ON(icd != pcdev->icd);
718
719 dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n",
720 icd->devnum);
721
722 /* disable capture, disable interrupts */
723 CICR0 = 0x3ff;
a5462e5b 724
3bc43840 725 /* Stop DMA engine */
a5462e5b
MR		 726 DCSR(pcdev->dma_chans[0]) = 0;
727 DCSR(pcdev->dma_chans[1]) = 0;
728 DCSR(pcdev->dma_chans[2]) = 0;
3bc43840
GL		 729
730 icd->ops->release(icd);
731
7102b773 732 pxa_camera_deactivate(pcdev);
3bc43840
GL		 733
734 pcdev->icd = NULL;
735}
736
ad5f2e85
GL		 737static int test_platform_param(struct pxa_camera_dev *pcdev,
738 unsigned char buswidth, unsigned long *flags)
3bc43840 739{
ad5f2e85
GL		 740 /*
741 * Platform specified synchronization and pixel clock polarities are
742 * only a recommendation and are only used during probing. The PXA270
743 * quick capture interface supports both.
744 */
745 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
746 SOCAM_MASTER : SOCAM_SLAVE) |
747 SOCAM_HSYNC_ACTIVE_HIGH |
748 SOCAM_HSYNC_ACTIVE_LOW |
749 SOCAM_VSYNC_ACTIVE_HIGH |
750 SOCAM_VSYNC_ACTIVE_LOW |
751 SOCAM_PCLK_SAMPLE_RISING |
752 SOCAM_PCLK_SAMPLE_FALLING;
3bc43840
GL		 753
754 /* If requested data width is supported by the platform, use it */
ad5f2e85 755 switch (buswidth) {
3bc43840 756 case 10:
ad5f2e85
GL		 757 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
758 return -EINVAL;
759 *flags |= SOCAM_DATAWIDTH_10;
3bc43840
GL		 760 break;
761 case 9:
ad5f2e85
GL		 762 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
763 return -EINVAL;
764 *flags |= SOCAM_DATAWIDTH_9;
3bc43840
GL		 765 break;
766 case 8:
ad5f2e85
GL		 767 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
768 return -EINVAL;
769 *flags |= SOCAM_DATAWIDTH_8;
3bc43840 770 }
ad5f2e85
GL		 771
772 return 0;
773}
774
775static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
776{
777 struct soc_camera_host *ici =
778 to_soc_camera_host(icd->dev.parent);
779 struct pxa_camera_dev *pcdev = ici->priv;
780 unsigned long dw, bpp, bus_flags, camera_flags, common_flags;
a5462e5b 781 u32 cicr0, cicr1, cicr4 = 0;
ad5f2e85
GL		 782 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
783
784 if (ret < 0)
785 return ret;
786
787 camera_flags = icd->ops->query_bus_param(icd);
788
789 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
790 if (!common_flags)
3bc43840
GL		 791 return -EINVAL;
792
e7c50688
GL		 793 pcdev->channels = 1;
794
ad5f2e85
GL		 795 /* Make choises, based on platform preferences */
796 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
797 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
798 if (pcdev->platform_flags & PXA_CAMERA_HSP)
799 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
800 else
801 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
802 }
803
804 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
805 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
806 if (pcdev->platform_flags & PXA_CAMERA_VSP)
807 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
808 else
809 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
810 }
811
812 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
813 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
814 if (pcdev->platform_flags & PXA_CAMERA_PCP)
815 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
816 else
817 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
818 }
819
820 ret = icd->ops->set_bus_param(icd, common_flags);
3bc43840
GL		 821 if (ret < 0)
822 return ret;
823
824 /* Datawidth is now guaranteed to be equal to one of the three values.
825 * We fix bit-per-pixel equal to data-width... */
ad5f2e85
GL		 826 switch (common_flags & SOCAM_DATAWIDTH_MASK) {
827 case SOCAM_DATAWIDTH_10:
828 icd->buswidth = 10;
3bc43840
GL		 829 dw = 4;
830 bpp = 0x40;
831 break;
ad5f2e85
GL		 832 case SOCAM_DATAWIDTH_9:
833 icd->buswidth = 9;
3bc43840
GL		 834 dw = 3;
835 bpp = 0x20;
836 break;
837 default:
838 /* Actually it can only be 8 now,
839 * default is just to silence compiler warnings */
ad5f2e85
GL		 840 case SOCAM_DATAWIDTH_8:
841 icd->buswidth = 8;
3bc43840
GL		 842 dw = 2;
843 bpp = 0;
844 }
845
846 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
847 cicr4 |= CICR4_PCLK_EN;
848 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
849 cicr4 |= CICR4_MCLK_EN;
ad5f2e85 850 if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
3bc43840 851 cicr4 |= CICR4_PCP;
ad5f2e85 852 if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
3bc43840 853 cicr4 |= CICR4_HSP;
ad5f2e85 854 if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
3bc43840
GL		 855 cicr4 |= CICR4_VSP;
856
857 cicr0 = CICR0;
858 if (cicr0 & CICR0_ENB)
859 CICR0 = cicr0 & ~CICR0_ENB;
a5462e5b
MR		 860
861 cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw;
862
863 switch (pixfmt) {
864 case V4L2_PIX_FMT_YUV422P:
e7c50688 865 pcdev->channels = 3;
a5462e5b
MR		 866 cicr1 |= CICR1_YCBCR_F;
867 case V4L2_PIX_FMT_YUYV:
868 cicr1 |= CICR1_COLOR_SP_VAL(2);
869 break;
870 case V4L2_PIX_FMT_RGB555:
871 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
872 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
873 break;
874 case V4L2_PIX_FMT_RGB565:
875 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
876 break;
877 }
878
879 CICR1 = cicr1;
3bc43840 880 CICR2 = 0;
ad5f2e85 881 CICR3 = CICR3_LPF_VAL(icd->height - 1) |
3bc43840
GL		 882 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
883 CICR4 = mclk_get_divisor(pcdev) | cicr4;
884
885 /* CIF interrupts are not used, only DMA */
886 CICR0 = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
7102b773 887 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)) |
3bc43840
GL		 888 CICR0_DMAEN | CICR0_IRQ_MASK | (cicr0 & CICR0_ENB);
889
890 return 0;
891}
892
ad5f2e85
GL		 893static int pxa_camera_try_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
894{
895 struct soc_camera_host *ici =
896 to_soc_camera_host(icd->dev.parent);
897 struct pxa_camera_dev *pcdev = ici->priv;
898 unsigned long bus_flags, camera_flags;
899 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
900
901 if (ret < 0)
902 return ret;
903
904 camera_flags = icd->ops->query_bus_param(icd);
905
906 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
907}
908
909static int pxa_camera_set_fmt_cap(struct soc_camera_device *icd,
910 __u32 pixfmt, struct v4l2_rect *rect)
911{
912 return icd->ops->set_fmt_cap(icd, pixfmt, rect);
913}
914
915static int pxa_camera_try_fmt_cap(struct soc_camera_device *icd,
7102b773 916 struct v4l2_format *f)
3bc43840
GL		 917{
918 /* limit to pxa hardware capabilities */
919 if (f->fmt.pix.height < 32)
920 f->fmt.pix.height = 32;
921 if (f->fmt.pix.height > 2048)
922 f->fmt.pix.height = 2048;
923 if (f->fmt.pix.width < 48)
924 f->fmt.pix.width = 48;
925 if (f->fmt.pix.width > 2048)
926 f->fmt.pix.width = 2048;
927 f->fmt.pix.width &= ~0x01;
928
ad5f2e85
GL		 929 /* limit to sensor capabilities */
930 return icd->ops->try_fmt_cap(icd, f);
3bc43840
GL		 931}
932
7102b773
GL		 933static int pxa_camera_reqbufs(struct soc_camera_file *icf,
934 struct v4l2_requestbuffers *p)
3bc43840
GL		 935{
936 int i;
937
938 /* This is for locking debugging only. I removed spinlocks and now I
939 * check whether .prepare is ever called on a linked buffer, or whether
940 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
941 * it hadn't triggered */
942 for (i = 0; i < p->count; i++) {
943 struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
944 struct pxa_buffer, vb);
945 buf->inwork = 0;
946 INIT_LIST_HEAD(&buf->vb.queue);
947 }
948
949 return 0;
950}
951
7102b773 952static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
3bc43840
GL		 953{
954 struct soc_camera_file *icf = file->private_data;
955 struct pxa_buffer *buf;
956
957 buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
958 vb.stream);
959
960 poll_wait(file, &buf->vb.done, pt);
961
962 if (buf->vb.state == VIDEOBUF_DONE ||
963 buf->vb.state == VIDEOBUF_ERROR)
964 return POLLIN|POLLRDNORM;
965
966 return 0;
967}
968
7102b773
GL		 969static int pxa_camera_querycap(struct soc_camera_host *ici,
970 struct v4l2_capability *cap)
3bc43840
GL		 971{
972 /* cap->name is set by the firendly caller:-> */
973 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
974 cap->version = PXA_CAM_VERSION_CODE;
975 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
976
977 return 0;
978}
979
3f6ac497
RJ		 980static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state)
981{
982 struct soc_camera_host *ici =
983 to_soc_camera_host(icd->dev.parent);
984 struct pxa_camera_dev *pcdev = ici->priv;
985 int i = 0, ret = 0;
986
987 pcdev->save_cicr[i++] = CICR0;
988 pcdev->save_cicr[i++] = CICR1;
989 pcdev->save_cicr[i++] = CICR2;
990 pcdev->save_cicr[i++] = CICR3;
991 pcdev->save_cicr[i++] = CICR4;
992
993 if ((pcdev->icd) && (pcdev->icd->ops->suspend))
994 ret = pcdev->icd->ops->suspend(pcdev->icd, state);
995
996 return ret;
997}
998
999static int pxa_camera_resume(struct soc_camera_device *icd)
1000{
1001 struct soc_camera_host *ici =
1002 to_soc_camera_host(icd->dev.parent);
1003 struct pxa_camera_dev *pcdev = ici->priv;
1004 int i = 0, ret = 0;
1005
87f3dd77
EM		 1006 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1007 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1008 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
3f6ac497
RJ		 1009
1010 CICR0 = pcdev->save_cicr[i++] & ~CICR0_ENB;
1011 CICR1 = pcdev->save_cicr[i++];
1012 CICR2 = pcdev->save_cicr[i++];
1013 CICR3 = pcdev->save_cicr[i++];
1014 CICR4 = pcdev->save_cicr[i++];
1015
1016 if ((pcdev->icd) && (pcdev->icd->ops->resume))
1017 ret = pcdev->icd->ops->resume(pcdev->icd);
1018
1019 /* Restart frame capture if active buffer exists */
1020 if (!ret && pcdev->active) {
1021 /* Reset the FIFOs */
1022 CIFR |= CIFR_RESET_F;
1023 /* Enable End-Of-Frame Interrupt */
1024 CICR0 &= ~CICR0_EOFM;
1025 /* Restart the Capture Interface */
1026 CICR0 |= CICR0_ENB;
1027 }
1028
1029 return ret;
1030}
1031
b8d9904c
GL		 1032static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1033 .owner = THIS_MODULE,
1034 .add = pxa_camera_add_device,
1035 .remove = pxa_camera_remove_device,
3f6ac497
RJ		 1036 .suspend = pxa_camera_suspend,
1037 .resume = pxa_camera_resume,
b8d9904c
GL		 1038 .set_fmt_cap = pxa_camera_set_fmt_cap,
1039 .try_fmt_cap = pxa_camera_try_fmt_cap,
092d3921 1040 .init_videobuf = pxa_camera_init_videobuf,
b8d9904c
GL		 1041 .reqbufs = pxa_camera_reqbufs,
1042 .poll = pxa_camera_poll,
1043 .querycap = pxa_camera_querycap,
1044 .try_bus_param = pxa_camera_try_bus_param,
1045 .set_bus_param = pxa_camera_set_bus_param,
1046};
1047
1048/* Should be allocated dynamically too, but we have only one. */
3bc43840
GL		 1049static struct soc_camera_host pxa_soc_camera_host = {
1050 .drv_name = PXA_CAM_DRV_NAME,
b8d9904c 1051 .ops = &pxa_soc_camera_host_ops,
3bc43840
GL		 1052};
1053
1054static int pxa_camera_probe(struct platform_device *pdev)
1055{
1056 struct pxa_camera_dev *pcdev;
1057 struct resource *res;
1058 void __iomem *base;
02da4659 1059 int irq;
3bc43840
GL		 1060 int err = 0;
1061
1062 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1063 irq = platform_get_irq(pdev, 0);
02da4659 1064 if (!res || irq < 0) {
3bc43840
GL		 1065 err = -ENODEV;
1066 goto exit;
1067 }
1068
1069 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1070 if (!pcdev) {
7102b773 1071 dev_err(&pdev->dev, "Could not allocate pcdev\n");
3bc43840
GL		 1072 err = -ENOMEM;
1073 goto exit;
1074 }
1075
e0d8b13a 1076 pcdev->clk = clk_get(&pdev->dev, NULL);
3bc43840
GL		 1077 if (IS_ERR(pcdev->clk)) {
1078 err = PTR_ERR(pcdev->clk);
1079 goto exit_kfree;
1080 }
1081
1082 dev_set_drvdata(&pdev->dev, pcdev);
1083 pcdev->res = res;
1084
1085 pcdev->pdata = pdev->dev.platform_data;
1086 pcdev->platform_flags = pcdev->pdata->flags;
ad5f2e85
GL		 1087 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1088 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
3bc43840
GL		 1089 /* Platform hasn't set available data widths. This is bad.
1090 * Warn and use a default. */
1091 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1092 "data widths, using default 10 bit\n");
1093 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1094 }
1095 pcdev->platform_mclk_10khz = pcdev->pdata->mclk_10khz;
1096 if (!pcdev->platform_mclk_10khz) {
1097 dev_warn(&pdev->dev,
1098 "mclk_10khz == 0! Please, fix your platform data. "
1099 "Using default 20MHz\n");
1100 pcdev->platform_mclk_10khz = 2000;
1101 }
1102
1103 INIT_LIST_HEAD(&pcdev->capture);
1104 spin_lock_init(&pcdev->lock);
1105
1106 /*
1107 * Request the regions.
1108 */
1109 if (!request_mem_region(res->start, res->end - res->start + 1,
1110 PXA_CAM_DRV_NAME)) {
1111 err = -EBUSY;
1112 goto exit_clk;
1113 }
1114
1115 base = ioremap(res->start, res->end - res->start + 1);
1116 if (!base) {
1117 err = -ENOMEM;
1118 goto exit_release;
1119 }
1120 pcdev->irq = irq;
1121 pcdev->base = base;
1122 pcdev->dev = &pdev->dev;
1123
1124 /* request dma */
de3e3b82 1125 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1126 pxa_camera_dma_irq_y, pcdev);
1127 if (err < 0) {
3bc43840 1128 dev_err(pcdev->dev, "Can't request DMA for Y\n");
3bc43840
GL		 1129 goto exit_iounmap;
1130 }
de3e3b82 1131 pcdev->dma_chans[0] = err;
a5462e5b
MR		 1132 dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1133
de3e3b82 1134 err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1135 pxa_camera_dma_irq_u, pcdev);
1136 if (err < 0) {
a5462e5b 1137 dev_err(pcdev->dev, "Can't request DMA for U\n");
a5462e5b
MR		 1138 goto exit_free_dma_y;
1139 }
de3e3b82 1140 pcdev->dma_chans[1] = err;
a5462e5b
MR		 1141 dev_dbg(pcdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1142
de3e3b82 1143 err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1144 pxa_camera_dma_irq_v, pcdev);
1145 if (err < 0) {
a5462e5b 1146 dev_err(pcdev->dev, "Can't request DMA for V\n");
a5462e5b
MR		 1147 goto exit_free_dma_u;
1148 }
de3e3b82 1149 pcdev->dma_chans[2] = err;
a5462e5b 1150 dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
3bc43840 1151
87f3dd77
EM		 1152 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1153 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1154 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
3bc43840
GL		 1155
1156 /* request irq */
1157 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1158 pcdev);
1159 if (err) {
1160 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1161 goto exit_free_dma;
1162 }
1163
1164 pxa_soc_camera_host.priv = pcdev;
1165 pxa_soc_camera_host.dev.parent = &pdev->dev;
1166 pxa_soc_camera_host.nr = pdev->id;
b8d9904c 1167 err = soc_camera_host_register(&pxa_soc_camera_host);
3bc43840
GL		 1168 if (err)
1169 goto exit_free_irq;
1170
1171 return 0;
1172
1173exit_free_irq:
1174 free_irq(pcdev->irq, pcdev);
1175exit_free_dma:
a5462e5b
MR		 1176 pxa_free_dma(pcdev->dma_chans[2]);
1177exit_free_dma_u:
1178 pxa_free_dma(pcdev->dma_chans[1]);
1179exit_free_dma_y:
1180 pxa_free_dma(pcdev->dma_chans[0]);
3bc43840
GL		 1181exit_iounmap:
1182 iounmap(base);
1183exit_release:
1184 release_mem_region(res->start, res->end - res->start + 1);
1185exit_clk:
1186 clk_put(pcdev->clk);
1187exit_kfree:
1188 kfree(pcdev);
1189exit:
1190 return err;
1191}
1192
1193static int __devexit pxa_camera_remove(struct platform_device *pdev)
1194{
1195 struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev);
1196 struct resource *res;
1197
1198 clk_put(pcdev->clk);
1199
a5462e5b
MR		 1200 pxa_free_dma(pcdev->dma_chans[0]);
1201 pxa_free_dma(pcdev->dma_chans[1]);
1202 pxa_free_dma(pcdev->dma_chans[2]);
3bc43840
GL		 1203 free_irq(pcdev->irq, pcdev);
1204
1205 soc_camera_host_unregister(&pxa_soc_camera_host);
1206
1207 iounmap(pcdev->base);
1208
1209 res = pcdev->res;
1210 release_mem_region(res->start, res->end - res->start + 1);
1211
1212 kfree(pcdev);
1213
7102b773 1214 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
3bc43840 1215
3bc43840
GL		 1216 return 0;
1217}
1218
3bc43840
GL		 1219static struct platform_driver pxa_camera_driver = {
1220 .driver = {
1221 .name = PXA_CAM_DRV_NAME,
1222 },
1223 .probe = pxa_camera_probe,
1224 .remove = __exit_p(pxa_camera_remove),
3bc43840
GL		 1225};
1226
1227
1228static int __devinit pxa_camera_init(void)
1229{
1230 return platform_driver_register(&pxa_camera_driver);
1231}
1232
1233static void __exit pxa_camera_exit(void)
1234{
01c1e4ca 1235 platform_driver_unregister(&pxa_camera_driver);
3bc43840
GL		 1236}
1237
1238module_init(pxa_camera_init);
1239module_exit(pxa_camera_exit);
1240
1241MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1242MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1243MODULE_LICENSE("GPL");
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