]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * |
3 | * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs] | |
4 | * | |
86ddd96f MCC |
5 | * Extended 3 / 2005 by Hartmut Hackmann to support various |
6 | * cards with the tda10046 DVB-T channel decoder | |
7 | * | |
1da177e4 LT |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/init.h> | |
24 | #include <linux/list.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/kthread.h> | |
30 | #include <linux/suspend.h> | |
31 | ||
32 | #include "saa7134-reg.h" | |
33 | #include "saa7134.h" | |
5e453dc7 | 34 | #include <media/v4l2-common.h> |
a78d0bfa | 35 | #include "dvb-pll.h" |
5823b3a6 | 36 | #include <dvb_frontend.h> |
1da177e4 | 37 | |
1f10c7af AQ |
38 | #include "mt352.h" |
39 | #include "mt352_priv.h" /* FIXME */ | |
40 | #include "tda1004x.h" | |
41 | #include "nxt200x.h" | |
bc36a686 | 42 | #include "tuner-xc2028.h" |
1da177e4 | 43 | |
e2ac28fa IL |
44 | #include "tda10086.h" |
45 | #include "tda826x.h" | |
8ce47dad | 46 | #include "tda827x.h" |
e2ac28fa | 47 | #include "isl6421.h" |
4b1431ca | 48 | #include "isl6405.h" |
6ab465a8 | 49 | #include "lnbp21.h" |
cb89cd33 | 50 | #include "tuner-simple.h" |
8ce47dad | 51 | |
1da177e4 LT |
52 | MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]"); |
53 | MODULE_LICENSE("GPL"); | |
54 | ||
ff699e6b | 55 | static unsigned int antenna_pwr; |
86ddd96f | 56 | |
1da177e4 LT |
57 | module_param(antenna_pwr, int, 0444); |
58 | MODULE_PARM_DESC(antenna_pwr,"enable antenna power (Pinnacle 300i)"); | |
59 | ||
ff699e6b | 60 | static int use_frontend; |
b331daa0 SB |
61 | module_param(use_frontend, int, 0644); |
62 | MODULE_PARM_DESC(use_frontend,"for cards with multiple frontends (0: terrestrial, 1: satellite)"); | |
1f683cd8 | 63 | |
ff699e6b | 64 | static int debug; |
58ef4f92 HH |
65 | module_param(debug, int, 0644); |
66 | MODULE_PARM_DESC(debug, "Turn on/off module debugging (default:off)."); | |
67 | ||
cf3c34c8 TP |
68 | #define dprintk(fmt, arg...) do { if (debug) \ |
69 | printk(KERN_DEBUG "%s/dvb: " fmt, dev->name , ## arg); } while(0) | |
70 | ||
71 | /* Print a warning */ | |
72 | #define wprintk(fmt, arg...) \ | |
73 | printk(KERN_WARNING "%s/dvb: " fmt, dev->name, ## arg) | |
58ef4f92 HH |
74 | |
75 | /* ------------------------------------------------------------------ | |
76 | * mt352 based DVB-T cards | |
77 | */ | |
78 | ||
1da177e4 LT |
79 | static int pinnacle_antenna_pwr(struct saa7134_dev *dev, int on) |
80 | { | |
81 | u32 ok; | |
82 | ||
83 | if (!on) { | |
84 | saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 26)); | |
85 | saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26)); | |
86 | return 0; | |
87 | } | |
88 | ||
89 | saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 26)); | |
90 | saa_setl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26)); | |
91 | udelay(10); | |
92 | ||
93 | saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 28)); | |
94 | saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 28)); | |
95 | udelay(10); | |
96 | saa_setl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 28)); | |
97 | udelay(10); | |
98 | ok = saa_readl(SAA7134_GPIO_GPSTATUS0) & (1 << 27); | |
5823b3a6 | 99 | dprintk("%s %s\n", __func__, ok ? "on" : "off"); |
1da177e4 LT |
100 | |
101 | if (!ok) | |
102 | saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26)); | |
103 | return ok; | |
104 | } | |
105 | ||
106 | static int mt352_pinnacle_init(struct dvb_frontend* fe) | |
107 | { | |
108 | static u8 clock_config [] = { CLOCK_CTL, 0x3d, 0x28 }; | |
109 | static u8 reset [] = { RESET, 0x80 }; | |
110 | static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 }; | |
111 | static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0xa0 }; | |
112 | static u8 capt_range_cfg[] = { CAPT_RANGE, 0x31 }; | |
113 | static u8 fsm_ctl_cfg[] = { 0x7b, 0x04 }; | |
114 | static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x0f }; | |
115 | static u8 scan_ctl_cfg [] = { SCAN_CTL, 0x0d }; | |
116 | static u8 irq_cfg [] = { INTERRUPT_EN_0, 0x00, 0x00, 0x00, 0x00 }; | |
117 | struct saa7134_dev *dev= fe->dvb->priv; | |
118 | ||
5823b3a6 | 119 | dprintk("%s called\n", __func__); |
1da177e4 LT |
120 | |
121 | mt352_write(fe, clock_config, sizeof(clock_config)); | |
122 | udelay(200); | |
123 | mt352_write(fe, reset, sizeof(reset)); | |
124 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | |
125 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | |
126 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | |
127 | mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg)); | |
128 | ||
129 | mt352_write(fe, fsm_ctl_cfg, sizeof(fsm_ctl_cfg)); | |
130 | mt352_write(fe, scan_ctl_cfg, sizeof(scan_ctl_cfg)); | |
131 | mt352_write(fe, irq_cfg, sizeof(irq_cfg)); | |
df8cf706 | 132 | |
1da177e4 LT |
133 | return 0; |
134 | } | |
135 | ||
a78d0bfa JAR |
136 | static int mt352_aver777_init(struct dvb_frontend* fe) |
137 | { | |
138 | static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x2d }; | |
139 | static u8 reset [] = { RESET, 0x80 }; | |
140 | static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 }; | |
141 | static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0xa0 }; | |
142 | static u8 capt_range_cfg[] = { CAPT_RANGE, 0x33 }; | |
143 | ||
144 | mt352_write(fe, clock_config, sizeof(clock_config)); | |
145 | udelay(200); | |
146 | mt352_write(fe, reset, sizeof(reset)); | |
147 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | |
148 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | |
149 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | |
150 | ||
151 | return 0; | |
152 | } | |
153 | ||
95a2fdb6 MCC |
154 | static int mt352_aver_a16d_init(struct dvb_frontend *fe) |
155 | { | |
156 | static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x2d }; | |
157 | static u8 reset [] = { RESET, 0x80 }; | |
158 | static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 }; | |
159 | static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0xa0 }; | |
160 | static u8 capt_range_cfg[] = { CAPT_RANGE, 0x33 }; | |
161 | ||
162 | mt352_write(fe, clock_config, sizeof(clock_config)); | |
163 | udelay(200); | |
164 | mt352_write(fe, reset, sizeof(reset)); | |
165 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | |
166 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | |
167 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | |
168 | ||
169 | return 0; | |
170 | } | |
171 | ||
172 | ||
173 | ||
0463f12c AQ |
174 | static int mt352_pinnacle_tuner_set_params(struct dvb_frontend* fe, |
175 | struct dvb_frontend_parameters* params) | |
1da177e4 | 176 | { |
df8cf706 HH |
177 | u8 off[] = { 0x00, 0xf1}; |
178 | u8 on[] = { 0x00, 0x71}; | |
179 | struct i2c_msg msg = {.addr=0x43, .flags=0, .buf=off, .len = sizeof(off)}; | |
180 | ||
1da177e4 LT |
181 | struct saa7134_dev *dev = fe->dvb->priv; |
182 | struct v4l2_frequency f; | |
183 | ||
184 | /* set frequency (mt2050) */ | |
185 | f.tuner = 0; | |
186 | f.type = V4L2_TUNER_DIGITAL_TV; | |
187 | f.frequency = params->frequency / 1000 * 16 / 1000; | |
dea74869 PB |
188 | if (fe->ops.i2c_gate_ctrl) |
189 | fe->ops.i2c_gate_ctrl(fe, 1); | |
df8cf706 | 190 | i2c_transfer(&dev->i2c_adap, &msg, 1); |
1da177e4 | 191 | saa7134_i2c_call_clients(dev,VIDIOC_S_FREQUENCY,&f); |
df8cf706 | 192 | msg.buf = on; |
dea74869 PB |
193 | if (fe->ops.i2c_gate_ctrl) |
194 | fe->ops.i2c_gate_ctrl(fe, 1); | |
df8cf706 | 195 | i2c_transfer(&dev->i2c_adap, &msg, 1); |
1da177e4 LT |
196 | |
197 | pinnacle_antenna_pwr(dev, antenna_pwr); | |
198 | ||
199 | /* mt352 setup */ | |
0463f12c | 200 | return mt352_pinnacle_init(fe); |
1da177e4 LT |
201 | } |
202 | ||
203 | static struct mt352_config pinnacle_300i = { | |
204 | .demod_address = 0x3c >> 1, | |
205 | .adc_clock = 20333, | |
206 | .if2 = 36150, | |
207 | .no_tuner = 1, | |
208 | .demod_init = mt352_pinnacle_init, | |
1da177e4 | 209 | }; |
a78d0bfa JAR |
210 | |
211 | static struct mt352_config avermedia_777 = { | |
212 | .demod_address = 0xf, | |
213 | .demod_init = mt352_aver777_init, | |
a78d0bfa | 214 | }; |
1da177e4 | 215 | |
95a2fdb6 MCC |
216 | static struct mt352_config avermedia_16d = { |
217 | .demod_address = 0xf, | |
218 | .demod_init = mt352_aver_a16d_init, | |
219 | }; | |
220 | ||
bc36a686 MCC |
221 | static struct mt352_config avermedia_e506r_mt352_dev = { |
222 | .demod_address = (0x1e >> 1), | |
223 | .no_tuner = 1, | |
224 | }; | |
225 | ||
58ef4f92 HH |
226 | /* ================================================================== |
227 | * tda1004x based DVB-T cards, helper functions | |
228 | */ | |
229 | ||
230 | static int philips_tda1004x_request_firmware(struct dvb_frontend *fe, | |
231 | const struct firmware **fw, char *name) | |
1da177e4 LT |
232 | { |
233 | struct saa7134_dev *dev = fe->dvb->priv; | |
58ef4f92 HH |
234 | return request_firmware(fw, name, &dev->pci->dev); |
235 | } | |
236 | ||
58ef4f92 HH |
237 | /* ------------------------------------------------------------------ |
238 | * these tuners are tu1216, td1316(a) | |
239 | */ | |
240 | ||
241 | static int philips_tda6651_pll_set(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) | |
242 | { | |
243 | struct saa7134_dev *dev = fe->dvb->priv; | |
244 | struct tda1004x_state *state = fe->demodulator_priv; | |
245 | u8 addr = state->config->tuner_address; | |
86ddd96f | 246 | u8 tuner_buf[4]; |
2cf36ac4 | 247 | struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tuner_buf,.len = |
86ddd96f MCC |
248 | sizeof(tuner_buf) }; |
249 | int tuner_frequency = 0; | |
250 | u8 band, cp, filter; | |
251 | ||
252 | /* determine charge pump */ | |
253 | tuner_frequency = params->frequency + 36166000; | |
254 | if (tuner_frequency < 87000000) | |
255 | return -EINVAL; | |
256 | else if (tuner_frequency < 130000000) | |
257 | cp = 3; | |
258 | else if (tuner_frequency < 160000000) | |
259 | cp = 5; | |
260 | else if (tuner_frequency < 200000000) | |
261 | cp = 6; | |
262 | else if (tuner_frequency < 290000000) | |
263 | cp = 3; | |
264 | else if (tuner_frequency < 420000000) | |
265 | cp = 5; | |
266 | else if (tuner_frequency < 480000000) | |
267 | cp = 6; | |
268 | else if (tuner_frequency < 620000000) | |
269 | cp = 3; | |
270 | else if (tuner_frequency < 830000000) | |
271 | cp = 5; | |
272 | else if (tuner_frequency < 895000000) | |
273 | cp = 7; | |
274 | else | |
275 | return -EINVAL; | |
276 | ||
277 | /* determine band */ | |
278 | if (params->frequency < 49000000) | |
279 | return -EINVAL; | |
280 | else if (params->frequency < 161000000) | |
281 | band = 1; | |
282 | else if (params->frequency < 444000000) | |
283 | band = 2; | |
284 | else if (params->frequency < 861000000) | |
285 | band = 4; | |
286 | else | |
287 | return -EINVAL; | |
288 | ||
289 | /* setup PLL filter */ | |
290 | switch (params->u.ofdm.bandwidth) { | |
291 | case BANDWIDTH_6_MHZ: | |
292 | filter = 0; | |
293 | break; | |
294 | ||
295 | case BANDWIDTH_7_MHZ: | |
296 | filter = 0; | |
297 | break; | |
298 | ||
299 | case BANDWIDTH_8_MHZ: | |
300 | filter = 1; | |
301 | break; | |
1da177e4 | 302 | |
86ddd96f MCC |
303 | default: |
304 | return -EINVAL; | |
305 | } | |
306 | ||
307 | /* calculate divisor | |
308 | * ((36166000+((1000000/6)/2)) + Finput)/(1000000/6) | |
1da177e4 | 309 | */ |
86ddd96f MCC |
310 | tuner_frequency = (((params->frequency / 1000) * 6) + 217496) / 1000; |
311 | ||
312 | /* setup tuner buffer */ | |
313 | tuner_buf[0] = (tuner_frequency >> 8) & 0x7f; | |
314 | tuner_buf[1] = tuner_frequency & 0xff; | |
315 | tuner_buf[2] = 0xca; | |
316 | tuner_buf[3] = (cp << 5) | (filter << 3) | band; | |
317 | ||
dea74869 PB |
318 | if (fe->ops.i2c_gate_ctrl) |
319 | fe->ops.i2c_gate_ctrl(fe, 1); | |
58ef4f92 | 320 | if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1) { |
cf3c34c8 TP |
321 | wprintk("could not write to tuner at addr: 0x%02x\n", |
322 | addr << 1); | |
86ddd96f | 323 | return -EIO; |
58ef4f92 | 324 | } |
2cf36ac4 HH |
325 | msleep(1); |
326 | return 0; | |
327 | } | |
328 | ||
58ef4f92 | 329 | static int philips_tu1216_init(struct dvb_frontend *fe) |
2cf36ac4 HH |
330 | { |
331 | struct saa7134_dev *dev = fe->dvb->priv; | |
58ef4f92 HH |
332 | struct tda1004x_state *state = fe->demodulator_priv; |
333 | u8 addr = state->config->tuner_address; | |
2cf36ac4 HH |
334 | static u8 tu1216_init[] = { 0x0b, 0xf5, 0x85, 0xab }; |
335 | struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tu1216_init,.len = sizeof(tu1216_init) }; | |
86ddd96f | 336 | |
2cf36ac4 | 337 | /* setup PLL configuration */ |
dea74869 PB |
338 | if (fe->ops.i2c_gate_ctrl) |
339 | fe->ops.i2c_gate_ctrl(fe, 1); | |
2cf36ac4 HH |
340 | if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1) |
341 | return -EIO; | |
86ddd96f | 342 | msleep(1); |
2cf36ac4 | 343 | |
1da177e4 LT |
344 | return 0; |
345 | } | |
346 | ||
2cf36ac4 HH |
347 | /* ------------------------------------------------------------------ */ |
348 | ||
2cf36ac4 | 349 | static struct tda1004x_config philips_tu1216_60_config = { |
86ddd96f MCC |
350 | .demod_address = 0x8, |
351 | .invert = 1, | |
2cf36ac4 | 352 | .invert_oclk = 0, |
86ddd96f MCC |
353 | .xtal_freq = TDA10046_XTAL_4M, |
354 | .agc_config = TDA10046_AGC_DEFAULT, | |
355 | .if_freq = TDA10046_FREQ_3617, | |
58ef4f92 HH |
356 | .tuner_address = 0x60, |
357 | .request_firmware = philips_tda1004x_request_firmware | |
86ddd96f MCC |
358 | }; |
359 | ||
2cf36ac4 HH |
360 | static struct tda1004x_config philips_tu1216_61_config = { |
361 | ||
362 | .demod_address = 0x8, | |
363 | .invert = 1, | |
364 | .invert_oclk = 0, | |
365 | .xtal_freq = TDA10046_XTAL_4M, | |
366 | .agc_config = TDA10046_AGC_DEFAULT, | |
367 | .if_freq = TDA10046_FREQ_3617, | |
58ef4f92 HH |
368 | .tuner_address = 0x61, |
369 | .request_firmware = philips_tda1004x_request_firmware | |
2cf36ac4 HH |
370 | }; |
371 | ||
372 | /* ------------------------------------------------------------------ */ | |
373 | ||
cbb94521 | 374 | static int philips_td1316_tuner_init(struct dvb_frontend *fe) |
2cf36ac4 HH |
375 | { |
376 | struct saa7134_dev *dev = fe->dvb->priv; | |
58ef4f92 HH |
377 | struct tda1004x_state *state = fe->demodulator_priv; |
378 | u8 addr = state->config->tuner_address; | |
2cf36ac4 | 379 | static u8 msg[] = { 0x0b, 0xf5, 0x86, 0xab }; |
58ef4f92 | 380 | struct i2c_msg init_msg = {.addr = addr,.flags = 0,.buf = msg,.len = sizeof(msg) }; |
2cf36ac4 HH |
381 | |
382 | /* setup PLL configuration */ | |
dea74869 PB |
383 | if (fe->ops.i2c_gate_ctrl) |
384 | fe->ops.i2c_gate_ctrl(fe, 1); | |
2cf36ac4 HH |
385 | if (i2c_transfer(&dev->i2c_adap, &init_msg, 1) != 1) |
386 | return -EIO; | |
2cf36ac4 HH |
387 | return 0; |
388 | } | |
389 | ||
a79ddae9 | 390 | static int philips_td1316_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) |
2cf36ac4 | 391 | { |
58ef4f92 HH |
392 | return philips_tda6651_pll_set(fe, params); |
393 | } | |
394 | ||
395 | static int philips_td1316_tuner_sleep(struct dvb_frontend *fe) | |
396 | { | |
397 | struct saa7134_dev *dev = fe->dvb->priv; | |
398 | struct tda1004x_state *state = fe->demodulator_priv; | |
399 | u8 addr = state->config->tuner_address; | |
400 | static u8 msg[] = { 0x0b, 0xdc, 0x86, 0xa4 }; | |
401 | struct i2c_msg analog_msg = {.addr = addr,.flags = 0,.buf = msg,.len = sizeof(msg) }; | |
402 | ||
403 | /* switch the tuner to analog mode */ | |
404 | if (fe->ops.i2c_gate_ctrl) | |
405 | fe->ops.i2c_gate_ctrl(fe, 1); | |
406 | if (i2c_transfer(&dev->i2c_adap, &analog_msg, 1) != 1) | |
407 | return -EIO; | |
408 | return 0; | |
2cf36ac4 HH |
409 | } |
410 | ||
58ef4f92 HH |
411 | /* ------------------------------------------------------------------ */ |
412 | ||
cbb94521 HH |
413 | static int philips_europa_tuner_init(struct dvb_frontend *fe) |
414 | { | |
415 | struct saa7134_dev *dev = fe->dvb->priv; | |
416 | static u8 msg[] = { 0x00, 0x40}; | |
417 | struct i2c_msg init_msg = {.addr = 0x43,.flags = 0,.buf = msg,.len = sizeof(msg) }; | |
418 | ||
419 | ||
420 | if (philips_td1316_tuner_init(fe)) | |
421 | return -EIO; | |
422 | msleep(1); | |
423 | if (i2c_transfer(&dev->i2c_adap, &init_msg, 1) != 1) | |
424 | return -EIO; | |
425 | ||
426 | return 0; | |
427 | } | |
428 | ||
a79ddae9 | 429 | static int philips_europa_tuner_sleep(struct dvb_frontend *fe) |
2cf36ac4 HH |
430 | { |
431 | struct saa7134_dev *dev = fe->dvb->priv; | |
2cf36ac4 | 432 | |
58ef4f92 HH |
433 | static u8 msg[] = { 0x00, 0x14 }; |
434 | struct i2c_msg analog_msg = {.addr = 0x43,.flags = 0,.buf = msg,.len = sizeof(msg) }; | |
435 | ||
436 | if (philips_td1316_tuner_sleep(fe)) | |
437 | return -EIO; | |
2cf36ac4 HH |
438 | |
439 | /* switch the board to analog mode */ | |
dea74869 PB |
440 | if (fe->ops.i2c_gate_ctrl) |
441 | fe->ops.i2c_gate_ctrl(fe, 1); | |
2cf36ac4 | 442 | i2c_transfer(&dev->i2c_adap, &analog_msg, 1); |
a79ddae9 AQ |
443 | return 0; |
444 | } | |
445 | ||
446 | static int philips_europa_demod_sleep(struct dvb_frontend *fe) | |
447 | { | |
448 | struct saa7134_dev *dev = fe->dvb->priv; | |
449 | ||
450 | if (dev->original_demod_sleep) | |
451 | dev->original_demod_sleep(fe); | |
dea74869 | 452 | fe->ops.i2c_gate_ctrl(fe, 1); |
a79ddae9 | 453 | return 0; |
2cf36ac4 HH |
454 | } |
455 | ||
456 | static struct tda1004x_config philips_europa_config = { | |
457 | ||
458 | .demod_address = 0x8, | |
459 | .invert = 0, | |
460 | .invert_oclk = 0, | |
461 | .xtal_freq = TDA10046_XTAL_4M, | |
462 | .agc_config = TDA10046_AGC_IFO_AUTO_POS, | |
463 | .if_freq = TDA10046_FREQ_052, | |
58ef4f92 HH |
464 | .tuner_address = 0x61, |
465 | .request_firmware = philips_tda1004x_request_firmware | |
2cf36ac4 HH |
466 | }; |
467 | ||
408b664a | 468 | static struct tda1004x_config medion_cardbus = { |
86ddd96f MCC |
469 | .demod_address = 0x08, |
470 | .invert = 1, | |
471 | .invert_oclk = 0, | |
472 | .xtal_freq = TDA10046_XTAL_16M, | |
473 | .agc_config = TDA10046_AGC_IFO_AUTO_NEG, | |
474 | .if_freq = TDA10046_FREQ_3613, | |
58ef4f92 HH |
475 | .tuner_address = 0x61, |
476 | .request_firmware = philips_tda1004x_request_firmware | |
86ddd96f MCC |
477 | }; |
478 | ||
58ef4f92 HH |
479 | /* ------------------------------------------------------------------ |
480 | * tda 1004x based cards with philips silicon tuner | |
481 | */ | |
482 | ||
58ef4f92 HH |
483 | static int tda8290_i2c_gate_ctrl( struct dvb_frontend* fe, int enable) |
484 | { | |
58ef4f92 HH |
485 | struct tda1004x_state *state = fe->demodulator_priv; |
486 | ||
487 | u8 addr = state->config->i2c_gate; | |
488 | static u8 tda8290_close[] = { 0x21, 0xc0}; | |
489 | static u8 tda8290_open[] = { 0x21, 0x80}; | |
490 | struct i2c_msg tda8290_msg = {.addr = addr,.flags = 0, .len = 2}; | |
491 | if (enable) { | |
492 | tda8290_msg.buf = tda8290_close; | |
493 | } else { | |
494 | tda8290_msg.buf = tda8290_open; | |
495 | } | |
06be3035 | 496 | if (i2c_transfer(state->i2c, &tda8290_msg, 1) != 1) { |
cf3c34c8 TP |
497 | struct saa7134_dev *dev = fe->dvb->priv; |
498 | wprintk("could not access tda8290 I2C gate\n"); | |
58ef4f92 HH |
499 | return -EIO; |
500 | } | |
501 | msleep(20); | |
502 | return 0; | |
503 | } | |
504 | ||
58ef4f92 | 505 | static int philips_tda827x_tuner_init(struct dvb_frontend *fe) |
90e9df7f | 506 | { |
90e9df7f | 507 | struct saa7134_dev *dev = fe->dvb->priv; |
58ef4f92 | 508 | struct tda1004x_state *state = fe->demodulator_priv; |
8ce47dad | 509 | |
58ef4f92 HH |
510 | switch (state->config->antenna_switch) { |
511 | case 0: break; | |
512 | case 1: dprintk("setting GPIO21 to 0 (TV antenna?)\n"); | |
513 | saa7134_set_gpio(dev, 21, 0); | |
514 | break; | |
515 | case 2: dprintk("setting GPIO21 to 1 (Radio antenna?)\n"); | |
516 | saa7134_set_gpio(dev, 21, 1); | |
517 | break; | |
587d2fd7 | 518 | } |
587d2fd7 HH |
519 | return 0; |
520 | } | |
521 | ||
58ef4f92 | 522 | static int philips_tda827x_tuner_sleep(struct dvb_frontend *fe) |
587d2fd7 | 523 | { |
58ef4f92 HH |
524 | struct saa7134_dev *dev = fe->dvb->priv; |
525 | struct tda1004x_state *state = fe->demodulator_priv; | |
8ce47dad | 526 | |
58ef4f92 HH |
527 | switch (state->config->antenna_switch) { |
528 | case 0: break; | |
529 | case 1: dprintk("setting GPIO21 to 1 (Radio antenna?)\n"); | |
530 | saa7134_set_gpio(dev, 21, 1); | |
531 | break; | |
532 | case 2: dprintk("setting GPIO21 to 0 (TV antenna?)\n"); | |
533 | saa7134_set_gpio(dev, 21, 0); | |
534 | break; | |
535 | } | |
587d2fd7 | 536 | return 0; |
2d6b5f62 | 537 | } |
90e9df7f | 538 | |
7bff4b4d HH |
539 | static void configure_tda827x_fe(struct saa7134_dev *dev, struct tda1004x_config *cdec_conf, |
540 | struct tda827x_config *tuner_conf) | |
90e9df7f | 541 | { |
7bff4b4d | 542 | dev->dvb.frontend = dvb_attach(tda10046_attach, cdec_conf, &dev->i2c_adap); |
58ef4f92 | 543 | if (dev->dvb.frontend) { |
7bff4b4d | 544 | if (cdec_conf->i2c_gate) |
58ef4f92 | 545 | dev->dvb.frontend->ops.i2c_gate_ctrl = tda8290_i2c_gate_ctrl; |
7bff4b4d HH |
546 | if (dvb_attach(tda827x_attach, dev->dvb.frontend, cdec_conf->tuner_address, |
547 | &dev->i2c_adap, tuner_conf) == NULL) { | |
cf3c34c8 | 548 | wprintk("no tda827x tuner found at addr: %02x\n", |
7bff4b4d | 549 | cdec_conf->tuner_address); |
ede2200d | 550 | } |
58ef4f92 | 551 | } |
90e9df7f HH |
552 | } |
553 | ||
58ef4f92 | 554 | /* ------------------------------------------------------------------ */ |
261f5081 | 555 | |
7bff4b4d HH |
556 | static struct tda827x_config tda827x_cfg_0 = { |
557 | .tuner_callback = saa7134_tuner_callback, | |
558 | .init = philips_tda827x_tuner_init, | |
559 | .sleep = philips_tda827x_tuner_sleep, | |
560 | .config = 0, | |
561 | .switch_addr = 0 | |
562 | }; | |
563 | ||
564 | static struct tda827x_config tda827x_cfg_1 = { | |
565 | .tuner_callback = saa7134_tuner_callback, | |
566 | .init = philips_tda827x_tuner_init, | |
567 | .sleep = philips_tda827x_tuner_sleep, | |
568 | .config = 1, | |
569 | .switch_addr = 0x4b | |
570 | }; | |
571 | ||
572 | static struct tda827x_config tda827x_cfg_2 = { | |
573 | .tuner_callback = saa7134_tuner_callback, | |
574 | .init = philips_tda827x_tuner_init, | |
575 | .sleep = philips_tda827x_tuner_sleep, | |
576 | .config = 2, | |
577 | .switch_addr = 0x4b | |
578 | }; | |
579 | ||
580 | static struct tda827x_config tda827x_cfg_2_sw42 = { | |
581 | .tuner_callback = saa7134_tuner_callback, | |
582 | .init = philips_tda827x_tuner_init, | |
583 | .sleep = philips_tda827x_tuner_sleep, | |
584 | .config = 2, | |
585 | .switch_addr = 0x42 | |
586 | }; | |
587 | ||
588 | /* ------------------------------------------------------------------ */ | |
589 | ||
58ef4f92 | 590 | static struct tda1004x_config tda827x_lifeview_config = { |
90e9df7f HH |
591 | .demod_address = 0x08, |
592 | .invert = 1, | |
593 | .invert_oclk = 0, | |
594 | .xtal_freq = TDA10046_XTAL_16M, | |
1bb0e866 HH |
595 | .agc_config = TDA10046_AGC_TDA827X, |
596 | .gpio_config = TDA10046_GP11_I, | |
550a9a5e | 597 | .if_freq = TDA10046_FREQ_045, |
58ef4f92 HH |
598 | .tuner_address = 0x60, |
599 | .request_firmware = philips_tda1004x_request_firmware | |
550a9a5e | 600 | }; |
550a9a5e | 601 | |
58ef4f92 HH |
602 | static struct tda1004x_config philips_tiger_config = { |
603 | .demod_address = 0x08, | |
604 | .invert = 1, | |
605 | .invert_oclk = 0, | |
606 | .xtal_freq = TDA10046_XTAL_16M, | |
607 | .agc_config = TDA10046_AGC_TDA827X, | |
608 | .gpio_config = TDA10046_GP11_I, | |
609 | .if_freq = TDA10046_FREQ_045, | |
610 | .i2c_gate = 0x4b, | |
611 | .tuner_address = 0x61, | |
58ef4f92 HH |
612 | .antenna_switch= 1, |
613 | .request_firmware = philips_tda1004x_request_firmware | |
614 | }; | |
550a9a5e HH |
615 | |
616 | static struct tda1004x_config cinergy_ht_config = { | |
617 | .demod_address = 0x08, | |
618 | .invert = 1, | |
619 | .invert_oclk = 0, | |
620 | .xtal_freq = TDA10046_XTAL_16M, | |
1bb0e866 HH |
621 | .agc_config = TDA10046_AGC_TDA827X, |
622 | .gpio_config = TDA10046_GP01_I, | |
90e9df7f | 623 | .if_freq = TDA10046_FREQ_045, |
58ef4f92 HH |
624 | .i2c_gate = 0x4b, |
625 | .tuner_address = 0x61, | |
58ef4f92 | 626 | .request_firmware = philips_tda1004x_request_firmware |
90e9df7f HH |
627 | }; |
628 | ||
58ef4f92 HH |
629 | static struct tda1004x_config cinergy_ht_pci_config = { |
630 | .demod_address = 0x08, | |
631 | .invert = 1, | |
632 | .invert_oclk = 0, | |
633 | .xtal_freq = TDA10046_XTAL_16M, | |
634 | .agc_config = TDA10046_AGC_TDA827X, | |
635 | .gpio_config = TDA10046_GP01_I, | |
636 | .if_freq = TDA10046_FREQ_045, | |
637 | .i2c_gate = 0x4b, | |
638 | .tuner_address = 0x60, | |
58ef4f92 HH |
639 | .request_firmware = philips_tda1004x_request_firmware |
640 | }; | |
641 | ||
642 | static struct tda1004x_config philips_tiger_s_config = { | |
643 | .demod_address = 0x08, | |
644 | .invert = 1, | |
645 | .invert_oclk = 0, | |
646 | .xtal_freq = TDA10046_XTAL_16M, | |
647 | .agc_config = TDA10046_AGC_TDA827X, | |
648 | .gpio_config = TDA10046_GP01_I, | |
649 | .if_freq = TDA10046_FREQ_045, | |
650 | .i2c_gate = 0x4b, | |
651 | .tuner_address = 0x61, | |
58ef4f92 HH |
652 | .antenna_switch= 1, |
653 | .request_firmware = philips_tda1004x_request_firmware | |
654 | }; | |
df42eaf2 | 655 | |
587d2fd7 HH |
656 | static struct tda1004x_config pinnacle_pctv_310i_config = { |
657 | .demod_address = 0x08, | |
658 | .invert = 1, | |
659 | .invert_oclk = 0, | |
660 | .xtal_freq = TDA10046_XTAL_16M, | |
1bb0e866 HH |
661 | .agc_config = TDA10046_AGC_TDA827X, |
662 | .gpio_config = TDA10046_GP11_I, | |
587d2fd7 | 663 | .if_freq = TDA10046_FREQ_045, |
58ef4f92 HH |
664 | .i2c_gate = 0x4b, |
665 | .tuner_address = 0x61, | |
58ef4f92 | 666 | .request_firmware = philips_tda1004x_request_firmware |
587d2fd7 HH |
667 | }; |
668 | ||
c6e53daf TG |
669 | static struct tda1004x_config hauppauge_hvr_1110_config = { |
670 | .demod_address = 0x08, | |
671 | .invert = 1, | |
672 | .invert_oclk = 0, | |
673 | .xtal_freq = TDA10046_XTAL_16M, | |
1bb0e866 HH |
674 | .agc_config = TDA10046_AGC_TDA827X, |
675 | .gpio_config = TDA10046_GP11_I, | |
c6e53daf | 676 | .if_freq = TDA10046_FREQ_045, |
58ef4f92 HH |
677 | .i2c_gate = 0x4b, |
678 | .tuner_address = 0x61, | |
679 | .request_firmware = philips_tda1004x_request_firmware | |
c6e53daf TG |
680 | }; |
681 | ||
83646817 HH |
682 | static struct tda1004x_config asus_p7131_dual_config = { |
683 | .demod_address = 0x08, | |
684 | .invert = 1, | |
685 | .invert_oclk = 0, | |
686 | .xtal_freq = TDA10046_XTAL_16M, | |
1bb0e866 HH |
687 | .agc_config = TDA10046_AGC_TDA827X, |
688 | .gpio_config = TDA10046_GP11_I, | |
83646817 | 689 | .if_freq = TDA10046_FREQ_045, |
58ef4f92 HH |
690 | .i2c_gate = 0x4b, |
691 | .tuner_address = 0x61, | |
58ef4f92 HH |
692 | .antenna_switch= 2, |
693 | .request_firmware = philips_tda1004x_request_firmware | |
83646817 HH |
694 | }; |
695 | ||
420f32fe NS |
696 | static struct tda1004x_config lifeview_trio_config = { |
697 | .demod_address = 0x09, | |
698 | .invert = 1, | |
699 | .invert_oclk = 0, | |
700 | .xtal_freq = TDA10046_XTAL_16M, | |
1bb0e866 HH |
701 | .agc_config = TDA10046_AGC_TDA827X, |
702 | .gpio_config = TDA10046_GP00_I, | |
420f32fe | 703 | .if_freq = TDA10046_FREQ_045, |
58ef4f92 HH |
704 | .tuner_address = 0x60, |
705 | .request_firmware = philips_tda1004x_request_firmware | |
420f32fe NS |
706 | }; |
707 | ||
58ef4f92 | 708 | static struct tda1004x_config tevion_dvbt220rf_config = { |
df42eaf2 HH |
709 | .demod_address = 0x08, |
710 | .invert = 1, | |
711 | .invert_oclk = 0, | |
712 | .xtal_freq = TDA10046_XTAL_16M, | |
1bb0e866 | 713 | .agc_config = TDA10046_AGC_TDA827X, |
58ef4f92 | 714 | .gpio_config = TDA10046_GP11_I, |
df42eaf2 | 715 | .if_freq = TDA10046_FREQ_045, |
58ef4f92 HH |
716 | .tuner_address = 0x60, |
717 | .request_firmware = philips_tda1004x_request_firmware | |
df42eaf2 HH |
718 | }; |
719 | ||
58ef4f92 | 720 | static struct tda1004x_config md8800_dvbt_config = { |
3dfb729f PH |
721 | .demod_address = 0x08, |
722 | .invert = 1, | |
723 | .invert_oclk = 0, | |
724 | .xtal_freq = TDA10046_XTAL_16M, | |
1bb0e866 | 725 | .agc_config = TDA10046_AGC_TDA827X, |
58ef4f92 | 726 | .gpio_config = TDA10046_GP01_I, |
3dfb729f | 727 | .if_freq = TDA10046_FREQ_045, |
58ef4f92 HH |
728 | .i2c_gate = 0x4b, |
729 | .tuner_address = 0x60, | |
58ef4f92 | 730 | .request_firmware = philips_tda1004x_request_firmware |
3dfb729f PH |
731 | }; |
732 | ||
e06cea4c HH |
733 | static struct tda1004x_config asus_p7131_4871_config = { |
734 | .demod_address = 0x08, | |
735 | .invert = 1, | |
736 | .invert_oclk = 0, | |
737 | .xtal_freq = TDA10046_XTAL_16M, | |
738 | .agc_config = TDA10046_AGC_TDA827X, | |
739 | .gpio_config = TDA10046_GP01_I, | |
740 | .if_freq = TDA10046_FREQ_045, | |
741 | .i2c_gate = 0x4b, | |
742 | .tuner_address = 0x61, | |
e06cea4c HH |
743 | .antenna_switch= 2, |
744 | .request_firmware = philips_tda1004x_request_firmware | |
745 | }; | |
746 | ||
f3eec0c0 | 747 | static struct tda1004x_config asus_p7131_hybrid_lna_config = { |
e06cea4c HH |
748 | .demod_address = 0x08, |
749 | .invert = 1, | |
750 | .invert_oclk = 0, | |
751 | .xtal_freq = TDA10046_XTAL_16M, | |
752 | .agc_config = TDA10046_AGC_TDA827X, | |
753 | .gpio_config = TDA10046_GP11_I, | |
754 | .if_freq = TDA10046_FREQ_045, | |
755 | .i2c_gate = 0x4b, | |
756 | .tuner_address = 0x61, | |
e06cea4c HH |
757 | .antenna_switch= 2, |
758 | .request_firmware = philips_tda1004x_request_firmware | |
759 | }; | |
261f5081 | 760 | |
b39423a9 SF |
761 | static struct tda1004x_config kworld_dvb_t_210_config = { |
762 | .demod_address = 0x08, | |
763 | .invert = 1, | |
764 | .invert_oclk = 0, | |
765 | .xtal_freq = TDA10046_XTAL_16M, | |
766 | .agc_config = TDA10046_AGC_TDA827X, | |
767 | .gpio_config = TDA10046_GP11_I, | |
768 | .if_freq = TDA10046_FREQ_045, | |
769 | .i2c_gate = 0x4b, | |
770 | .tuner_address = 0x61, | |
b39423a9 SF |
771 | .antenna_switch= 1, |
772 | .request_firmware = philips_tda1004x_request_firmware | |
773 | }; | |
261f5081 | 774 | |
d90d9f5a ES |
775 | static struct tda1004x_config avermedia_super_007_config = { |
776 | .demod_address = 0x08, | |
777 | .invert = 1, | |
778 | .invert_oclk = 0, | |
779 | .xtal_freq = TDA10046_XTAL_16M, | |
780 | .agc_config = TDA10046_AGC_TDA827X, | |
781 | .gpio_config = TDA10046_GP01_I, | |
782 | .if_freq = TDA10046_FREQ_045, | |
783 | .i2c_gate = 0x4b, | |
784 | .tuner_address = 0x60, | |
d90d9f5a ES |
785 | .antenna_switch= 1, |
786 | .request_firmware = philips_tda1004x_request_firmware | |
787 | }; | |
788 | ||
4ba24373 HP |
789 | static struct tda1004x_config twinhan_dtv_dvb_3056_config = { |
790 | .demod_address = 0x08, | |
791 | .invert = 1, | |
792 | .invert_oclk = 0, | |
793 | .xtal_freq = TDA10046_XTAL_16M, | |
794 | .agc_config = TDA10046_AGC_TDA827X, | |
795 | .gpio_config = TDA10046_GP01_I, | |
796 | .if_freq = TDA10046_FREQ_045, | |
797 | .i2c_gate = 0x42, | |
798 | .tuner_address = 0x61, | |
4ba24373 HP |
799 | .antenna_switch = 1, |
800 | .request_firmware = philips_tda1004x_request_firmware | |
801 | }; | |
802 | ||
58ef4f92 HH |
803 | /* ------------------------------------------------------------------ |
804 | * special case: this card uses saa713x GPIO22 for the mode switch | |
805 | */ | |
5eda227f | 806 | |
58ef4f92 | 807 | static int ads_duo_tuner_init(struct dvb_frontend *fe) |
5eda227f HH |
808 | { |
809 | struct saa7134_dev *dev = fe->dvb->priv; | |
58ef4f92 HH |
810 | philips_tda827x_tuner_init(fe); |
811 | /* route TDA8275a AGC input to the channel decoder */ | |
06be3035 | 812 | saa7134_set_gpio(dev, 22, 1); |
5eda227f HH |
813 | return 0; |
814 | } | |
815 | ||
58ef4f92 | 816 | static int ads_duo_tuner_sleep(struct dvb_frontend *fe) |
5eda227f | 817 | { |
5eda227f | 818 | struct saa7134_dev *dev = fe->dvb->priv; |
58ef4f92 | 819 | /* route TDA8275a AGC input to the analog IF chip*/ |
06be3035 | 820 | saa7134_set_gpio(dev, 22, 0); |
58ef4f92 HH |
821 | philips_tda827x_tuner_sleep(fe); |
822 | return 0; | |
5eda227f HH |
823 | } |
824 | ||
8ce47dad | 825 | static struct tda827x_config ads_duo_cfg = { |
7bff4b4d | 826 | .tuner_callback = saa7134_tuner_callback, |
8ce47dad | 827 | .init = ads_duo_tuner_init, |
7bff4b4d HH |
828 | .sleep = ads_duo_tuner_sleep, |
829 | .config = 0 | |
8ce47dad MK |
830 | }; |
831 | ||
58ef4f92 | 832 | static struct tda1004x_config ads_tech_duo_config = { |
5eda227f HH |
833 | .demod_address = 0x08, |
834 | .invert = 1, | |
835 | .invert_oclk = 0, | |
836 | .xtal_freq = TDA10046_XTAL_16M, | |
1bb0e866 | 837 | .agc_config = TDA10046_AGC_TDA827X, |
58ef4f92 | 838 | .gpio_config = TDA10046_GP00_I, |
5eda227f | 839 | .if_freq = TDA10046_FREQ_045, |
58ef4f92 HH |
840 | .tuner_address = 0x61, |
841 | .request_firmware = philips_tda1004x_request_firmware | |
5eda227f HH |
842 | }; |
843 | ||
58ef4f92 HH |
844 | /* ================================================================== |
845 | * tda10086 based DVB-S cards, helper functions | |
846 | */ | |
847 | ||
e2ac28fa IL |
848 | static struct tda10086_config flydvbs = { |
849 | .demod_address = 0x0e, | |
850 | .invert = 0, | |
ea75baf4 | 851 | .diseqc_tone = 0, |
e2ac28fa IL |
852 | }; |
853 | ||
1b1cee35 HH |
854 | /* ------------------------------------------------------------------ |
855 | * special case: lnb supply is connected to the gated i2c | |
856 | */ | |
857 | ||
858 | static int md8800_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) | |
859 | { | |
860 | int res = -EIO; | |
861 | struct saa7134_dev *dev = fe->dvb->priv; | |
862 | if (fe->ops.i2c_gate_ctrl) { | |
863 | fe->ops.i2c_gate_ctrl(fe, 1); | |
864 | if (dev->original_set_voltage) | |
865 | res = dev->original_set_voltage(fe, voltage); | |
866 | fe->ops.i2c_gate_ctrl(fe, 0); | |
867 | } | |
868 | return res; | |
869 | }; | |
870 | ||
871 | static int md8800_set_high_voltage(struct dvb_frontend *fe, long arg) | |
872 | { | |
873 | int res = -EIO; | |
874 | struct saa7134_dev *dev = fe->dvb->priv; | |
875 | if (fe->ops.i2c_gate_ctrl) { | |
876 | fe->ops.i2c_gate_ctrl(fe, 1); | |
877 | if (dev->original_set_high_voltage) | |
878 | res = dev->original_set_high_voltage(fe, arg); | |
879 | fe->ops.i2c_gate_ctrl(fe, 0); | |
880 | } | |
881 | return res; | |
882 | }; | |
883 | ||
5823b3a6 HH |
884 | static int md8800_set_voltage2(struct dvb_frontend *fe, fe_sec_voltage_t voltage) |
885 | { | |
886 | struct saa7134_dev *dev = fe->dvb->priv; | |
887 | u8 wbuf[2] = { 0x1f, 00 }; | |
888 | u8 rbuf; | |
889 | struct i2c_msg msg[] = { { .addr = 0x08, .flags = 0, .buf = wbuf, .len = 1 }, | |
890 | { .addr = 0x08, .flags = I2C_M_RD, .buf = &rbuf, .len = 1 } }; | |
891 | ||
892 | if (i2c_transfer(&dev->i2c_adap, msg, 2) != 2) | |
893 | return -EIO; | |
894 | /* NOTE: this assumes that gpo1 is used, it might be bit 5 (gpo2) */ | |
895 | if (voltage == SEC_VOLTAGE_18) | |
896 | wbuf[1] = rbuf | 0x10; | |
897 | else | |
898 | wbuf[1] = rbuf & 0xef; | |
899 | msg[0].len = 2; | |
900 | i2c_transfer(&dev->i2c_adap, msg, 1); | |
901 | return 0; | |
902 | } | |
903 | ||
904 | static int md8800_set_high_voltage2(struct dvb_frontend *fe, long arg) | |
905 | { | |
906 | struct saa7134_dev *dev = fe->dvb->priv; | |
907 | wprintk("%s: sorry can't set high LNB supply voltage from here\n", __func__); | |
908 | return -EIO; | |
909 | } | |
910 | ||
58ef4f92 HH |
911 | /* ================================================================== |
912 | * nxt200x based ATSC cards, helper functions | |
913 | */ | |
90e9df7f | 914 | |
3b64e8e2 MK |
915 | static struct nxt200x_config avertvhda180 = { |
916 | .demod_address = 0x0a, | |
3b64e8e2 | 917 | }; |
3e1410ad AB |
918 | |
919 | static struct nxt200x_config kworldatsc110 = { | |
920 | .demod_address = 0x0a, | |
3e1410ad | 921 | }; |
3b64e8e2 | 922 | |
58ef4f92 HH |
923 | /* ================================================================== |
924 | * Core code | |
925 | */ | |
1da177e4 LT |
926 | |
927 | static int dvb_init(struct saa7134_dev *dev) | |
928 | { | |
1c4f76ab | 929 | int ret; |
bc36a686 MCC |
930 | int attach_xc3028 = 0; |
931 | ||
1da177e4 LT |
932 | /* init struct videobuf_dvb */ |
933 | dev->ts.nr_bufs = 32; | |
934 | dev->ts.nr_packets = 32*4; | |
935 | dev->dvb.name = dev->name; | |
0705135e GL |
936 | videobuf_queue_sg_init(&dev->dvb.dvbq, &saa7134_ts_qops, |
937 | &dev->pci->dev, &dev->slock, | |
1da177e4 LT |
938 | V4L2_BUF_TYPE_VIDEO_CAPTURE, |
939 | V4L2_FIELD_ALTERNATE, | |
940 | sizeof(struct saa7134_buf), | |
941 | dev); | |
942 | ||
943 | switch (dev->board) { | |
944 | case SAA7134_BOARD_PINNACLE_300I_DVBT_PAL: | |
cf3c34c8 | 945 | dprintk("pinnacle 300i dvb setup\n"); |
2bfe031d | 946 | dev->dvb.frontend = dvb_attach(mt352_attach, &pinnacle_300i, |
f7b54b10 | 947 | &dev->i2c_adap); |
6b3ccab7 | 948 | if (dev->dvb.frontend) { |
dea74869 | 949 | dev->dvb.frontend->ops.tuner_ops.set_params = mt352_pinnacle_tuner_set_params; |
6b3ccab7 | 950 | } |
1da177e4 | 951 | break; |
a78d0bfa | 952 | case SAA7134_BOARD_AVERMEDIA_777: |
515c208d | 953 | case SAA7134_BOARD_AVERMEDIA_A16AR: |
cf3c34c8 | 954 | dprintk("avertv 777 dvb setup\n"); |
2bfe031d | 955 | dev->dvb.frontend = dvb_attach(mt352_attach, &avermedia_777, |
f7b54b10 | 956 | &dev->i2c_adap); |
6b3ccab7 | 957 | if (dev->dvb.frontend) { |
fb147e97 MK |
958 | dvb_attach(simple_tuner_attach, dev->dvb.frontend, |
959 | &dev->i2c_adap, 0x61, | |
960 | TUNER_PHILIPS_TD1316); | |
6b3ccab7 | 961 | } |
a78d0bfa | 962 | break; |
95a2fdb6 MCC |
963 | case SAA7134_BOARD_AVERMEDIA_A16D: |
964 | dprintk("avertv A16D dvb setup\n"); | |
965 | dev->dvb.frontend = dvb_attach(mt352_attach, &avermedia_16d, | |
966 | &dev->i2c_adap); | |
967 | attach_xc3028 = 1; | |
968 | break; | |
1da177e4 | 969 | case SAA7134_BOARD_MD7134: |
f7b54b10 MK |
970 | dev->dvb.frontend = dvb_attach(tda10046_attach, |
971 | &medion_cardbus, | |
972 | &dev->i2c_adap); | |
6b3ccab7 | 973 | if (dev->dvb.frontend) { |
cb89cd33 MK |
974 | dvb_attach(simple_tuner_attach, dev->dvb.frontend, |
975 | &dev->i2c_adap, medion_cardbus.tuner_address, | |
976 | TUNER_PHILIPS_FMD1216ME_MK3); | |
6b3ccab7 | 977 | } |
1da177e4 | 978 | break; |
86ddd96f | 979 | case SAA7134_BOARD_PHILIPS_TOUGH: |
f7b54b10 MK |
980 | dev->dvb.frontend = dvb_attach(tda10046_attach, |
981 | &philips_tu1216_60_config, | |
982 | &dev->i2c_adap); | |
6b3ccab7 | 983 | if (dev->dvb.frontend) { |
58ef4f92 HH |
984 | dev->dvb.frontend->ops.tuner_ops.init = philips_tu1216_init; |
985 | dev->dvb.frontend->ops.tuner_ops.set_params = philips_tda6651_pll_set; | |
6b3ccab7 | 986 | } |
86ddd96f MCC |
987 | break; |
988 | case SAA7134_BOARD_FLYDVBTDUO: | |
10b7a903 | 989 | case SAA7134_BOARD_FLYDVBT_DUO_CARDBUS: |
7bff4b4d | 990 | configure_tda827x_fe(dev, &tda827x_lifeview_config, &tda827x_cfg_0); |
86ddd96f | 991 | break; |
2cf36ac4 | 992 | case SAA7134_BOARD_PHILIPS_EUROPA: |
2cf36ac4 | 993 | case SAA7134_BOARD_VIDEOMATE_DVBT_300: |
f7b54b10 MK |
994 | dev->dvb.frontend = dvb_attach(tda10046_attach, |
995 | &philips_europa_config, | |
996 | &dev->i2c_adap); | |
6b3ccab7 | 997 | if (dev->dvb.frontend) { |
588f9831 HH |
998 | dev->original_demod_sleep = dev->dvb.frontend->ops.sleep; |
999 | dev->dvb.frontend->ops.sleep = philips_europa_demod_sleep; | |
dea74869 PB |
1000 | dev->dvb.frontend->ops.tuner_ops.init = philips_europa_tuner_init; |
1001 | dev->dvb.frontend->ops.tuner_ops.sleep = philips_europa_tuner_sleep; | |
1002 | dev->dvb.frontend->ops.tuner_ops.set_params = philips_td1316_tuner_set_params; | |
6b3ccab7 | 1003 | } |
2cf36ac4 HH |
1004 | break; |
1005 | case SAA7134_BOARD_VIDEOMATE_DVBT_200: | |
f7b54b10 MK |
1006 | dev->dvb.frontend = dvb_attach(tda10046_attach, |
1007 | &philips_tu1216_61_config, | |
1008 | &dev->i2c_adap); | |
6b3ccab7 | 1009 | if (dev->dvb.frontend) { |
58ef4f92 HH |
1010 | dev->dvb.frontend->ops.tuner_ops.init = philips_tu1216_init; |
1011 | dev->dvb.frontend->ops.tuner_ops.set_params = philips_tda6651_pll_set; | |
6b3ccab7 | 1012 | } |
2cf36ac4 | 1013 | break; |
b39423a9 | 1014 | case SAA7134_BOARD_KWORLD_DVBT_210: |
7bff4b4d | 1015 | configure_tda827x_fe(dev, &kworld_dvb_t_210_config, &tda827x_cfg_2); |
b39423a9 | 1016 | break; |
90e9df7f | 1017 | case SAA7134_BOARD_PHILIPS_TIGER: |
7bff4b4d | 1018 | configure_tda827x_fe(dev, &philips_tiger_config, &tda827x_cfg_0); |
587d2fd7 HH |
1019 | break; |
1020 | case SAA7134_BOARD_PINNACLE_PCTV_310i: | |
7bff4b4d | 1021 | configure_tda827x_fe(dev, &pinnacle_pctv_310i_config, &tda827x_cfg_1); |
90e9df7f | 1022 | break; |
c6e53daf | 1023 | case SAA7134_BOARD_HAUPPAUGE_HVR1110: |
7bff4b4d | 1024 | configure_tda827x_fe(dev, &hauppauge_hvr_1110_config, &tda827x_cfg_1); |
c6e53daf | 1025 | break; |
d4b0aba4 | 1026 | case SAA7134_BOARD_ASUSTeK_P7131_DUAL: |
7bff4b4d | 1027 | configure_tda827x_fe(dev, &asus_p7131_dual_config, &tda827x_cfg_0); |
d4b0aba4 | 1028 | break; |
3d8466ec | 1029 | case SAA7134_BOARD_FLYDVBT_LR301: |
7bff4b4d | 1030 | configure_tda827x_fe(dev, &tda827x_lifeview_config, &tda827x_cfg_0); |
3d8466ec | 1031 | break; |
420f32fe | 1032 | case SAA7134_BOARD_FLYDVB_TRIO: |
ea75baf4 | 1033 | if(! use_frontend) { /* terrestrial */ |
7bff4b4d HH |
1034 | configure_tda827x_fe(dev, &lifeview_trio_config, &tda827x_cfg_0); |
1035 | } else { /* satellite */ | |
1f683cd8 NS |
1036 | dev->dvb.frontend = dvb_attach(tda10086_attach, &flydvbs, &dev->i2c_adap); |
1037 | if (dev->dvb.frontend) { | |
1038 | if (dvb_attach(tda826x_attach, dev->dvb.frontend, 0x63, | |
1039 | &dev->i2c_adap, 0) == NULL) { | |
5823b3a6 | 1040 | wprintk("%s: Lifeview Trio, No tda826x found!\n", __func__); |
1f683cd8 NS |
1041 | } |
1042 | if (dvb_attach(isl6421_attach, dev->dvb.frontend, &dev->i2c_adap, | |
1043 | 0x08, 0, 0) == NULL) { | |
5823b3a6 | 1044 | wprintk("%s: Lifeview Trio, No ISL6421 found!\n", __func__); |
1f683cd8 NS |
1045 | } |
1046 | } | |
6b3ccab7 | 1047 | } |
420f32fe | 1048 | break; |
df42eaf2 | 1049 | case SAA7134_BOARD_ADS_DUO_CARDBUS_PTV331: |
58ef4f92 | 1050 | case SAA7134_BOARD_FLYDVBT_HYBRID_CARDBUS: |
f7b54b10 MK |
1051 | dev->dvb.frontend = dvb_attach(tda10046_attach, |
1052 | &ads_tech_duo_config, | |
1053 | &dev->i2c_adap); | |
6b3ccab7 | 1054 | if (dev->dvb.frontend) { |
ede2200d | 1055 | if (dvb_attach(tda827x_attach,dev->dvb.frontend, |
7bff4b4d HH |
1056 | ads_tech_duo_config.tuner_address, &dev->i2c_adap, |
1057 | &ads_duo_cfg) == NULL) { | |
cf3c34c8 | 1058 | wprintk("no tda827x tuner found at addr: %02x\n", |
ede2200d HH |
1059 | ads_tech_duo_config.tuner_address); |
1060 | } | |
6b3ccab7 | 1061 | } |
df42eaf2 | 1062 | break; |
3dfb729f | 1063 | case SAA7134_BOARD_TEVION_DVBT_220RF: |
7bff4b4d | 1064 | configure_tda827x_fe(dev, &tevion_dvbt220rf_config, &tda827x_cfg_0); |
d95b8942 | 1065 | break; |
5eda227f | 1066 | case SAA7134_BOARD_MEDION_MD8800_QUADRO: |
4b1431ca | 1067 | if (!use_frontend) { /* terrestrial */ |
7bff4b4d | 1068 | configure_tda827x_fe(dev, &md8800_dvbt_config, &tda827x_cfg_0); |
4b1431ca HH |
1069 | } else { /* satellite */ |
1070 | dev->dvb.frontend = dvb_attach(tda10086_attach, | |
1071 | &flydvbs, &dev->i2c_adap); | |
1072 | if (dev->dvb.frontend) { | |
5823b3a6 HH |
1073 | struct dvb_frontend *fe = dev->dvb.frontend; |
1074 | u8 dev_id = dev->eedata[2]; | |
1075 | u8 data = 0xc4; | |
1076 | struct i2c_msg msg = {.addr = 0x08, .flags = 0, .len = 1}; | |
1077 | ||
4b1431ca HH |
1078 | if (dvb_attach(tda826x_attach, dev->dvb.frontend, |
1079 | 0x60, &dev->i2c_adap, 0) == NULL) | |
1080 | wprintk("%s: Medion Quadro, no tda826x " | |
5823b3a6 HH |
1081 | "found !\n", __func__); |
1082 | if (dev_id != 0x08) { | |
1083 | /* we need to open the i2c gate (we know it exists) */ | |
1084 | fe->ops.i2c_gate_ctrl(fe, 1); | |
1085 | if (dvb_attach(isl6405_attach, fe, | |
1086 | &dev->i2c_adap, 0x08, 0, 0) == NULL) | |
1087 | wprintk("%s: Medion Quadro, no ISL6405 " | |
1088 | "found !\n", __func__); | |
e9c1ac9d HH |
1089 | if (dev_id == 0x07) { |
1090 | /* fire up the 2nd section of the LNB supply since | |
1091 | we can't do this from the other section */ | |
1092 | msg.buf = &data; | |
1093 | i2c_transfer(&dev->i2c_adap, &msg, 1); | |
1094 | } | |
5823b3a6 HH |
1095 | fe->ops.i2c_gate_ctrl(fe, 0); |
1096 | dev->original_set_voltage = fe->ops.set_voltage; | |
1097 | fe->ops.set_voltage = md8800_set_voltage; | |
1098 | dev->original_set_high_voltage = fe->ops.enable_high_lnb_voltage; | |
1099 | fe->ops.enable_high_lnb_voltage = md8800_set_high_voltage; | |
1100 | } else { | |
1101 | fe->ops.set_voltage = md8800_set_voltage2; | |
1102 | fe->ops.enable_high_lnb_voltage = md8800_set_high_voltage2; | |
1103 | } | |
4b1431ca HH |
1104 | } |
1105 | } | |
5eda227f | 1106 | break; |
3b64e8e2 | 1107 | case SAA7134_BOARD_AVERMEDIA_AVERTVHD_A180: |
f7b54b10 MK |
1108 | dev->dvb.frontend = dvb_attach(nxt200x_attach, &avertvhda180, |
1109 | &dev->i2c_adap); | |
a79ddae9 | 1110 | if (dev->dvb.frontend) { |
4ad8eee5 | 1111 | dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, |
47a9991e | 1112 | NULL, DVB_PLL_TDHU2); |
a79ddae9 | 1113 | } |
3b64e8e2 | 1114 | break; |
3e1410ad | 1115 | case SAA7134_BOARD_KWORLD_ATSC110: |
f7b54b10 MK |
1116 | dev->dvb.frontend = dvb_attach(nxt200x_attach, &kworldatsc110, |
1117 | &dev->i2c_adap); | |
a79ddae9 | 1118 | if (dev->dvb.frontend) { |
62ff817a MK |
1119 | dvb_attach(simple_tuner_attach, dev->dvb.frontend, |
1120 | &dev->i2c_adap, 0x61, | |
1121 | TUNER_PHILIPS_TUV1236D); | |
a79ddae9 | 1122 | } |
3e1410ad | 1123 | break; |
e2ac28fa | 1124 | case SAA7134_BOARD_FLYDVBS_LR300: |
f7b54b10 MK |
1125 | dev->dvb.frontend = dvb_attach(tda10086_attach, &flydvbs, |
1126 | &dev->i2c_adap); | |
e2ac28fa | 1127 | if (dev->dvb.frontend) { |
f7b54b10 MK |
1128 | if (dvb_attach(tda826x_attach, dev->dvb.frontend, 0x60, |
1129 | &dev->i2c_adap, 0) == NULL) { | |
5823b3a6 | 1130 | wprintk("%s: No tda826x found!\n", __func__); |
e2ac28fa | 1131 | } |
f7b54b10 MK |
1132 | if (dvb_attach(isl6421_attach, dev->dvb.frontend, |
1133 | &dev->i2c_adap, 0x08, 0, 0) == NULL) { | |
5823b3a6 | 1134 | wprintk("%s: No ISL6421 found!\n", __func__); |
e2ac28fa IL |
1135 | } |
1136 | } | |
1137 | break; | |
cf146ca4 | 1138 | case SAA7134_BOARD_ASUS_EUROPA2_HYBRID: |
0e8f4cc5 MS |
1139 | dev->dvb.frontend = dvb_attach(tda10046_attach, |
1140 | &medion_cardbus, | |
1141 | &dev->i2c_adap); | |
cf146ca4 HH |
1142 | if (dev->dvb.frontend) { |
1143 | dev->original_demod_sleep = dev->dvb.frontend->ops.sleep; | |
1144 | dev->dvb.frontend->ops.sleep = philips_europa_demod_sleep; | |
b7754d74 | 1145 | |
cb89cd33 MK |
1146 | dvb_attach(simple_tuner_attach, dev->dvb.frontend, |
1147 | &dev->i2c_adap, medion_cardbus.tuner_address, | |
1148 | TUNER_PHILIPS_FMD1216ME_MK3); | |
cf146ca4 HH |
1149 | } |
1150 | break; | |
cbb94521 HH |
1151 | case SAA7134_BOARD_VIDEOMATE_DVBT_200A: |
1152 | dev->dvb.frontend = dvb_attach(tda10046_attach, | |
1153 | &philips_europa_config, | |
1154 | &dev->i2c_adap); | |
1155 | if (dev->dvb.frontend) { | |
1156 | dev->dvb.frontend->ops.tuner_ops.init = philips_td1316_tuner_init; | |
1157 | dev->dvb.frontend->ops.tuner_ops.set_params = philips_td1316_tuner_set_params; | |
1158 | } | |
1159 | break; | |
550a9a5e | 1160 | case SAA7134_BOARD_CINERGY_HT_PCMCIA: |
7bff4b4d | 1161 | configure_tda827x_fe(dev, &cinergy_ht_config, &tda827x_cfg_0); |
9de271e6 MK |
1162 | break; |
1163 | case SAA7134_BOARD_CINERGY_HT_PCI: | |
7bff4b4d | 1164 | configure_tda827x_fe(dev, &cinergy_ht_pci_config, &tda827x_cfg_0); |
58ef4f92 HH |
1165 | break; |
1166 | case SAA7134_BOARD_PHILIPS_TIGER_S: | |
7bff4b4d | 1167 | configure_tda827x_fe(dev, &philips_tiger_s_config, &tda827x_cfg_2); |
550a9a5e | 1168 | break; |
e06cea4c | 1169 | case SAA7134_BOARD_ASUS_P7131_4871: |
7bff4b4d | 1170 | configure_tda827x_fe(dev, &asus_p7131_4871_config, &tda827x_cfg_2); |
e06cea4c | 1171 | break; |
f3eec0c0 | 1172 | case SAA7134_BOARD_ASUSTeK_P7131_HYBRID_LNA: |
7bff4b4d | 1173 | configure_tda827x_fe(dev, &asus_p7131_hybrid_lna_config, &tda827x_cfg_2); |
e06cea4c | 1174 | break; |
d90d9f5a | 1175 | case SAA7134_BOARD_AVERMEDIA_SUPER_007: |
7bff4b4d | 1176 | configure_tda827x_fe(dev, &avermedia_super_007_config, &tda827x_cfg_0); |
d90d9f5a | 1177 | break; |
4ba24373 | 1178 | case SAA7134_BOARD_TWINHAN_DTV_DVB_3056: |
7bff4b4d | 1179 | configure_tda827x_fe(dev, &twinhan_dtv_dvb_3056_config, &tda827x_cfg_2_sw42); |
4ba24373 | 1180 | break; |
6ab465a8 HH |
1181 | case SAA7134_BOARD_PHILIPS_SNAKE: |
1182 | dev->dvb.frontend = dvb_attach(tda10086_attach, &flydvbs, | |
1183 | &dev->i2c_adap); | |
1184 | if (dev->dvb.frontend) { | |
1185 | if (dvb_attach(tda826x_attach, dev->dvb.frontend, 0x60, | |
1186 | &dev->i2c_adap, 0) == NULL) | |
5823b3a6 | 1187 | wprintk("%s: No tda826x found!\n", __func__); |
6ab465a8 HH |
1188 | if (dvb_attach(lnbp21_attach, dev->dvb.frontend, |
1189 | &dev->i2c_adap, 0, 0) == NULL) | |
5823b3a6 | 1190 | wprintk("%s: No lnbp21 found!\n", __func__); |
6ab465a8 HH |
1191 | } |
1192 | break; | |
7b5b3f17 | 1193 | case SAA7134_BOARD_CREATIX_CTX953: |
7bff4b4d | 1194 | configure_tda827x_fe(dev, &md8800_dvbt_config, &tda827x_cfg_0); |
7b5b3f17 | 1195 | break; |
6a6179b6 | 1196 | case SAA7134_BOARD_MSI_TVANYWHERE_AD11: |
7bff4b4d | 1197 | configure_tda827x_fe(dev, &philips_tiger_s_config, &tda827x_cfg_2); |
6a6179b6 | 1198 | break; |
bc36a686 MCC |
1199 | case SAA7134_BOARD_AVERMEDIA_CARDBUS_506: |
1200 | dev->dvb.frontend = dvb_attach(mt352_attach, | |
1201 | &avermedia_e506r_mt352_dev, | |
1202 | &dev->i2c_adap); | |
1203 | attach_xc3028 = 1; | |
1204 | break; | |
637afdb5 HH |
1205 | case SAA7134_BOARD_MD7134_BRIDGE_2: |
1206 | dev->dvb.frontend = dvb_attach(tda10086_attach, | |
1207 | &flydvbs, &dev->i2c_adap); | |
1208 | if (dev->dvb.frontend) { | |
1209 | struct dvb_frontend *fe; | |
1210 | if (dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60, | |
1211 | &dev->i2c_adap, DVB_PLL_PHILIPS_SD1878_TDA8261) == NULL) | |
1212 | wprintk("%s: MD7134 DVB-S, no SD1878 " | |
5823b3a6 | 1213 | "found !\n", __func__); |
637afdb5 HH |
1214 | /* we need to open the i2c gate (we know it exists) */ |
1215 | fe = dev->dvb.frontend; | |
1216 | fe->ops.i2c_gate_ctrl(fe, 1); | |
1217 | if (dvb_attach(isl6405_attach, fe, | |
1218 | &dev->i2c_adap, 0x08, 0, 0) == NULL) | |
1219 | wprintk("%s: MD7134 DVB-S, no ISL6405 " | |
5823b3a6 | 1220 | "found !\n", __func__); |
637afdb5 HH |
1221 | fe->ops.i2c_gate_ctrl(fe, 0); |
1222 | dev->original_set_voltage = fe->ops.set_voltage; | |
1223 | fe->ops.set_voltage = md8800_set_voltage; | |
1224 | dev->original_set_high_voltage = fe->ops.enable_high_lnb_voltage; | |
1225 | fe->ops.enable_high_lnb_voltage = md8800_set_high_voltage; | |
1226 | } | |
1227 | break; | |
1da177e4 | 1228 | default: |
cf3c34c8 | 1229 | wprintk("Huh? unknown DVB card?\n"); |
1da177e4 LT |
1230 | break; |
1231 | } | |
1232 | ||
bc36a686 MCC |
1233 | if (attach_xc3028) { |
1234 | struct dvb_frontend *fe; | |
1235 | struct xc2028_config cfg = { | |
1236 | .i2c_adap = &dev->i2c_adap, | |
1237 | .i2c_addr = 0x61, | |
bc36a686 | 1238 | }; |
95a2fdb6 MCC |
1239 | |
1240 | if (!dev->dvb.frontend) | |
1241 | return -1; | |
1242 | ||
bc36a686 MCC |
1243 | fe = dvb_attach(xc2028_attach, dev->dvb.frontend, &cfg); |
1244 | if (!fe) { | |
1245 | printk(KERN_ERR "%s/2: xc3028 attach failed\n", | |
1246 | dev->name); | |
1247 | dvb_frontend_detach(dev->dvb.frontend); | |
1248 | dvb_unregister_frontend(dev->dvb.frontend); | |
1249 | dev->dvb.frontend = NULL; | |
1250 | return -1; | |
1251 | } | |
1252 | } | |
1253 | ||
1da177e4 | 1254 | if (NULL == dev->dvb.frontend) { |
cf3c34c8 | 1255 | printk(KERN_ERR "%s/dvb: frontend initialization failed\n", dev->name); |
1da177e4 LT |
1256 | return -1; |
1257 | } | |
1258 | ||
1259 | /* register everything else */ | |
1c4f76ab HH |
1260 | ret = videobuf_dvb_register(&dev->dvb, THIS_MODULE, dev, &dev->pci->dev); |
1261 | ||
1262 | /* this sequence is necessary to make the tda1004x load its firmware | |
1263 | * and to enter analog mode of hybrid boards | |
1264 | */ | |
1265 | if (!ret) { | |
1266 | if (dev->dvb.frontend->ops.init) | |
1267 | dev->dvb.frontend->ops.init(dev->dvb.frontend); | |
1268 | if (dev->dvb.frontend->ops.sleep) | |
1269 | dev->dvb.frontend->ops.sleep(dev->dvb.frontend); | |
9971f4f1 HH |
1270 | if (dev->dvb.frontend->ops.tuner_ops.sleep) |
1271 | dev->dvb.frontend->ops.tuner_ops.sleep(dev->dvb.frontend); | |
1c4f76ab HH |
1272 | } |
1273 | return ret; | |
1da177e4 LT |
1274 | } |
1275 | ||
1276 | static int dvb_fini(struct saa7134_dev *dev) | |
1277 | { | |
7f171123 MCC |
1278 | /* FIXME: I suspect that this code is bogus, since the entry for |
1279 | Pinnacle 300I DVB-T PAL already defines the proper init to allow | |
1280 | the detection of mt2032 (TDA9887_PORT2_INACTIVE) | |
1281 | */ | |
1282 | if (dev->board == SAA7134_BOARD_PINNACLE_300I_DVBT_PAL) { | |
1283 | struct v4l2_priv_tun_config tda9887_cfg; | |
1284 | static int on = TDA9887_PRESENT | TDA9887_PORT2_INACTIVE; | |
1285 | ||
1286 | tda9887_cfg.tuner = TUNER_TDA9887; | |
1287 | tda9887_cfg.priv = &on; | |
1da177e4 | 1288 | |
1da177e4 | 1289 | /* otherwise we don't detect the tuner on next insmod */ |
7f171123 | 1290 | saa7134_i2c_call_clients(dev, TUNER_SET_CONFIG, &tda9887_cfg); |
5823b3a6 | 1291 | } else if (dev->board == SAA7134_BOARD_MEDION_MD8800_QUADRO) { |
e9c1ac9d | 1292 | if ((dev->eedata[2] == 0x07) && use_frontend) { |
5823b3a6 HH |
1293 | /* turn off the 2nd lnb supply */ |
1294 | u8 data = 0x80; | |
1295 | struct i2c_msg msg = {.addr = 0x08, .buf = &data, .flags = 0, .len = 1}; | |
1296 | struct dvb_frontend *fe; | |
1297 | fe = dev->dvb.frontend; | |
1298 | if (fe->ops.i2c_gate_ctrl) { | |
1299 | fe->ops.i2c_gate_ctrl(fe, 1); | |
1300 | i2c_transfer(&dev->i2c_adap, &msg, 1); | |
1301 | fe->ops.i2c_gate_ctrl(fe, 0); | |
1302 | } | |
1303 | } | |
7f171123 | 1304 | } |
9950c1b5 MCC |
1305 | if (dev->dvb.frontend) |
1306 | videobuf_dvb_unregister(&dev->dvb); | |
1da177e4 LT |
1307 | return 0; |
1308 | } | |
1309 | ||
1310 | static struct saa7134_mpeg_ops dvb_ops = { | |
1311 | .type = SAA7134_MPEG_DVB, | |
1312 | .init = dvb_init, | |
1313 | .fini = dvb_fini, | |
1314 | }; | |
1315 | ||
1316 | static int __init dvb_register(void) | |
1317 | { | |
1318 | return saa7134_ts_register(&dvb_ops); | |
1319 | } | |
1320 | ||
1321 | static void __exit dvb_unregister(void) | |
1322 | { | |
1323 | saa7134_ts_unregister(&dvb_ops); | |
1324 | } | |
1325 | ||
1326 | module_init(dvb_register); | |
1327 | module_exit(dvb_unregister); | |
1328 | ||
1329 | /* ------------------------------------------------------------------ */ | |
1330 | /* | |
1331 | * Local variables: | |
1332 | * c-basic-offset: 8 | |
1333 | * End: | |
1334 | */ |