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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * |
3 | * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs] | |
4 | * | |
86ddd96f MCC |
5 | * Extended 3 / 2005 by Hartmut Hackmann to support various |
6 | * cards with the tda10046 DVB-T channel decoder | |
7 | * | |
1da177e4 LT |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/init.h> | |
24 | #include <linux/list.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/kthread.h> | |
30 | #include <linux/suspend.h> | |
31 | ||
32 | #include "saa7134-reg.h" | |
33 | #include "saa7134.h" | |
5e453dc7 | 34 | #include <media/v4l2-common.h> |
a78d0bfa | 35 | #include "dvb-pll.h" |
1da177e4 | 36 | |
1f10c7af AQ |
37 | #include "mt352.h" |
38 | #include "mt352_priv.h" /* FIXME */ | |
39 | #include "tda1004x.h" | |
40 | #include "nxt200x.h" | |
1da177e4 | 41 | |
e2ac28fa IL |
42 | #include "tda10086.h" |
43 | #include "tda826x.h" | |
8ce47dad | 44 | #include "tda827x.h" |
e2ac28fa | 45 | #include "isl6421.h" |
8ce47dad | 46 | |
1da177e4 LT |
47 | MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]"); |
48 | MODULE_LICENSE("GPL"); | |
49 | ||
50 | static unsigned int antenna_pwr = 0; | |
86ddd96f | 51 | |
1da177e4 LT |
52 | module_param(antenna_pwr, int, 0444); |
53 | MODULE_PARM_DESC(antenna_pwr,"enable antenna power (Pinnacle 300i)"); | |
54 | ||
b331daa0 SB |
55 | static int use_frontend = 0; |
56 | module_param(use_frontend, int, 0644); | |
57 | MODULE_PARM_DESC(use_frontend,"for cards with multiple frontends (0: terrestrial, 1: satellite)"); | |
1f683cd8 | 58 | |
58ef4f92 HH |
59 | static int debug = 0; |
60 | module_param(debug, int, 0644); | |
61 | MODULE_PARM_DESC(debug, "Turn on/off module debugging (default:off)."); | |
62 | ||
cf3c34c8 TP |
63 | #define dprintk(fmt, arg...) do { if (debug) \ |
64 | printk(KERN_DEBUG "%s/dvb: " fmt, dev->name , ## arg); } while(0) | |
65 | ||
66 | /* Print a warning */ | |
67 | #define wprintk(fmt, arg...) \ | |
68 | printk(KERN_WARNING "%s/dvb: " fmt, dev->name, ## arg) | |
58ef4f92 HH |
69 | |
70 | /* ------------------------------------------------------------------ | |
71 | * mt352 based DVB-T cards | |
72 | */ | |
73 | ||
1da177e4 LT |
74 | static int pinnacle_antenna_pwr(struct saa7134_dev *dev, int on) |
75 | { | |
76 | u32 ok; | |
77 | ||
78 | if (!on) { | |
79 | saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 26)); | |
80 | saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26)); | |
81 | return 0; | |
82 | } | |
83 | ||
84 | saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 26)); | |
85 | saa_setl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26)); | |
86 | udelay(10); | |
87 | ||
88 | saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 28)); | |
89 | saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 28)); | |
90 | udelay(10); | |
91 | saa_setl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 28)); | |
92 | udelay(10); | |
93 | ok = saa_readl(SAA7134_GPIO_GPSTATUS0) & (1 << 27); | |
cf3c34c8 | 94 | dprintk("%s %s\n", __FUNCTION__, ok ? "on" : "off"); |
1da177e4 LT |
95 | |
96 | if (!ok) | |
97 | saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26)); | |
98 | return ok; | |
99 | } | |
100 | ||
101 | static int mt352_pinnacle_init(struct dvb_frontend* fe) | |
102 | { | |
103 | static u8 clock_config [] = { CLOCK_CTL, 0x3d, 0x28 }; | |
104 | static u8 reset [] = { RESET, 0x80 }; | |
105 | static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 }; | |
106 | static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0xa0 }; | |
107 | static u8 capt_range_cfg[] = { CAPT_RANGE, 0x31 }; | |
108 | static u8 fsm_ctl_cfg[] = { 0x7b, 0x04 }; | |
109 | static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x0f }; | |
110 | static u8 scan_ctl_cfg [] = { SCAN_CTL, 0x0d }; | |
111 | static u8 irq_cfg [] = { INTERRUPT_EN_0, 0x00, 0x00, 0x00, 0x00 }; | |
112 | struct saa7134_dev *dev= fe->dvb->priv; | |
113 | ||
cf3c34c8 | 114 | dprintk("%s called\n", __FUNCTION__); |
1da177e4 LT |
115 | |
116 | mt352_write(fe, clock_config, sizeof(clock_config)); | |
117 | udelay(200); | |
118 | mt352_write(fe, reset, sizeof(reset)); | |
119 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | |
120 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | |
121 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | |
122 | mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg)); | |
123 | ||
124 | mt352_write(fe, fsm_ctl_cfg, sizeof(fsm_ctl_cfg)); | |
125 | mt352_write(fe, scan_ctl_cfg, sizeof(scan_ctl_cfg)); | |
126 | mt352_write(fe, irq_cfg, sizeof(irq_cfg)); | |
df8cf706 | 127 | |
1da177e4 LT |
128 | return 0; |
129 | } | |
130 | ||
a78d0bfa JAR |
131 | static int mt352_aver777_init(struct dvb_frontend* fe) |
132 | { | |
133 | static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x2d }; | |
134 | static u8 reset [] = { RESET, 0x80 }; | |
135 | static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 }; | |
136 | static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0xa0 }; | |
137 | static u8 capt_range_cfg[] = { CAPT_RANGE, 0x33 }; | |
138 | ||
139 | mt352_write(fe, clock_config, sizeof(clock_config)); | |
140 | udelay(200); | |
141 | mt352_write(fe, reset, sizeof(reset)); | |
142 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | |
143 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | |
144 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | |
145 | ||
146 | return 0; | |
147 | } | |
148 | ||
0463f12c AQ |
149 | static int mt352_pinnacle_tuner_set_params(struct dvb_frontend* fe, |
150 | struct dvb_frontend_parameters* params) | |
1da177e4 | 151 | { |
df8cf706 HH |
152 | u8 off[] = { 0x00, 0xf1}; |
153 | u8 on[] = { 0x00, 0x71}; | |
154 | struct i2c_msg msg = {.addr=0x43, .flags=0, .buf=off, .len = sizeof(off)}; | |
155 | ||
1da177e4 LT |
156 | struct saa7134_dev *dev = fe->dvb->priv; |
157 | struct v4l2_frequency f; | |
158 | ||
159 | /* set frequency (mt2050) */ | |
160 | f.tuner = 0; | |
161 | f.type = V4L2_TUNER_DIGITAL_TV; | |
162 | f.frequency = params->frequency / 1000 * 16 / 1000; | |
dea74869 PB |
163 | if (fe->ops.i2c_gate_ctrl) |
164 | fe->ops.i2c_gate_ctrl(fe, 1); | |
df8cf706 | 165 | i2c_transfer(&dev->i2c_adap, &msg, 1); |
1da177e4 | 166 | saa7134_i2c_call_clients(dev,VIDIOC_S_FREQUENCY,&f); |
df8cf706 | 167 | msg.buf = on; |
dea74869 PB |
168 | if (fe->ops.i2c_gate_ctrl) |
169 | fe->ops.i2c_gate_ctrl(fe, 1); | |
df8cf706 | 170 | i2c_transfer(&dev->i2c_adap, &msg, 1); |
1da177e4 LT |
171 | |
172 | pinnacle_antenna_pwr(dev, antenna_pwr); | |
173 | ||
174 | /* mt352 setup */ | |
0463f12c | 175 | return mt352_pinnacle_init(fe); |
1da177e4 LT |
176 | } |
177 | ||
bd4956b8 | 178 | static int mt352_aver777_tuner_calc_regs(struct dvb_frontend *fe, struct dvb_frontend_parameters *params, u8* pllbuf, int buf_len) |
a78d0bfa | 179 | { |
a79ddae9 AQ |
180 | if (buf_len < 5) |
181 | return -EINVAL; | |
182 | ||
183 | pllbuf[0] = 0x61; | |
a78d0bfa JAR |
184 | dvb_pll_configure(&dvb_pll_philips_td1316, pllbuf+1, |
185 | params->frequency, | |
186 | params->u.ofdm.bandwidth); | |
a79ddae9 | 187 | return 5; |
a78d0bfa JAR |
188 | } |
189 | ||
1da177e4 LT |
190 | static struct mt352_config pinnacle_300i = { |
191 | .demod_address = 0x3c >> 1, | |
192 | .adc_clock = 20333, | |
193 | .if2 = 36150, | |
194 | .no_tuner = 1, | |
195 | .demod_init = mt352_pinnacle_init, | |
1da177e4 | 196 | }; |
a78d0bfa JAR |
197 | |
198 | static struct mt352_config avermedia_777 = { | |
199 | .demod_address = 0xf, | |
200 | .demod_init = mt352_aver777_init, | |
a78d0bfa | 201 | }; |
1da177e4 | 202 | |
58ef4f92 HH |
203 | /* ================================================================== |
204 | * tda1004x based DVB-T cards, helper functions | |
205 | */ | |
206 | ||
207 | static int philips_tda1004x_request_firmware(struct dvb_frontend *fe, | |
208 | const struct firmware **fw, char *name) | |
1da177e4 LT |
209 | { |
210 | struct saa7134_dev *dev = fe->dvb->priv; | |
58ef4f92 HH |
211 | return request_firmware(fw, name, &dev->pci->dev); |
212 | } | |
213 | ||
58ef4f92 HH |
214 | /* ------------------------------------------------------------------ |
215 | * these tuners are tu1216, td1316(a) | |
216 | */ | |
217 | ||
218 | static int philips_tda6651_pll_set(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) | |
219 | { | |
220 | struct saa7134_dev *dev = fe->dvb->priv; | |
221 | struct tda1004x_state *state = fe->demodulator_priv; | |
222 | u8 addr = state->config->tuner_address; | |
86ddd96f | 223 | u8 tuner_buf[4]; |
2cf36ac4 | 224 | struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tuner_buf,.len = |
86ddd96f MCC |
225 | sizeof(tuner_buf) }; |
226 | int tuner_frequency = 0; | |
227 | u8 band, cp, filter; | |
228 | ||
229 | /* determine charge pump */ | |
230 | tuner_frequency = params->frequency + 36166000; | |
231 | if (tuner_frequency < 87000000) | |
232 | return -EINVAL; | |
233 | else if (tuner_frequency < 130000000) | |
234 | cp = 3; | |
235 | else if (tuner_frequency < 160000000) | |
236 | cp = 5; | |
237 | else if (tuner_frequency < 200000000) | |
238 | cp = 6; | |
239 | else if (tuner_frequency < 290000000) | |
240 | cp = 3; | |
241 | else if (tuner_frequency < 420000000) | |
242 | cp = 5; | |
243 | else if (tuner_frequency < 480000000) | |
244 | cp = 6; | |
245 | else if (tuner_frequency < 620000000) | |
246 | cp = 3; | |
247 | else if (tuner_frequency < 830000000) | |
248 | cp = 5; | |
249 | else if (tuner_frequency < 895000000) | |
250 | cp = 7; | |
251 | else | |
252 | return -EINVAL; | |
253 | ||
254 | /* determine band */ | |
255 | if (params->frequency < 49000000) | |
256 | return -EINVAL; | |
257 | else if (params->frequency < 161000000) | |
258 | band = 1; | |
259 | else if (params->frequency < 444000000) | |
260 | band = 2; | |
261 | else if (params->frequency < 861000000) | |
262 | band = 4; | |
263 | else | |
264 | return -EINVAL; | |
265 | ||
266 | /* setup PLL filter */ | |
267 | switch (params->u.ofdm.bandwidth) { | |
268 | case BANDWIDTH_6_MHZ: | |
269 | filter = 0; | |
270 | break; | |
271 | ||
272 | case BANDWIDTH_7_MHZ: | |
273 | filter = 0; | |
274 | break; | |
275 | ||
276 | case BANDWIDTH_8_MHZ: | |
277 | filter = 1; | |
278 | break; | |
1da177e4 | 279 | |
86ddd96f MCC |
280 | default: |
281 | return -EINVAL; | |
282 | } | |
283 | ||
284 | /* calculate divisor | |
285 | * ((36166000+((1000000/6)/2)) + Finput)/(1000000/6) | |
1da177e4 | 286 | */ |
86ddd96f MCC |
287 | tuner_frequency = (((params->frequency / 1000) * 6) + 217496) / 1000; |
288 | ||
289 | /* setup tuner buffer */ | |
290 | tuner_buf[0] = (tuner_frequency >> 8) & 0x7f; | |
291 | tuner_buf[1] = tuner_frequency & 0xff; | |
292 | tuner_buf[2] = 0xca; | |
293 | tuner_buf[3] = (cp << 5) | (filter << 3) | band; | |
294 | ||
dea74869 PB |
295 | if (fe->ops.i2c_gate_ctrl) |
296 | fe->ops.i2c_gate_ctrl(fe, 1); | |
58ef4f92 | 297 | if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1) { |
cf3c34c8 TP |
298 | wprintk("could not write to tuner at addr: 0x%02x\n", |
299 | addr << 1); | |
86ddd96f | 300 | return -EIO; |
58ef4f92 | 301 | } |
2cf36ac4 HH |
302 | msleep(1); |
303 | return 0; | |
304 | } | |
305 | ||
58ef4f92 | 306 | static int philips_tu1216_init(struct dvb_frontend *fe) |
2cf36ac4 HH |
307 | { |
308 | struct saa7134_dev *dev = fe->dvb->priv; | |
58ef4f92 HH |
309 | struct tda1004x_state *state = fe->demodulator_priv; |
310 | u8 addr = state->config->tuner_address; | |
2cf36ac4 HH |
311 | static u8 tu1216_init[] = { 0x0b, 0xf5, 0x85, 0xab }; |
312 | struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tu1216_init,.len = sizeof(tu1216_init) }; | |
86ddd96f | 313 | |
2cf36ac4 | 314 | /* setup PLL configuration */ |
dea74869 PB |
315 | if (fe->ops.i2c_gate_ctrl) |
316 | fe->ops.i2c_gate_ctrl(fe, 1); | |
2cf36ac4 HH |
317 | if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1) |
318 | return -EIO; | |
86ddd96f | 319 | msleep(1); |
2cf36ac4 | 320 | |
1da177e4 LT |
321 | return 0; |
322 | } | |
323 | ||
2cf36ac4 HH |
324 | /* ------------------------------------------------------------------ */ |
325 | ||
2cf36ac4 | 326 | static struct tda1004x_config philips_tu1216_60_config = { |
86ddd96f MCC |
327 | .demod_address = 0x8, |
328 | .invert = 1, | |
2cf36ac4 | 329 | .invert_oclk = 0, |
86ddd96f MCC |
330 | .xtal_freq = TDA10046_XTAL_4M, |
331 | .agc_config = TDA10046_AGC_DEFAULT, | |
332 | .if_freq = TDA10046_FREQ_3617, | |
58ef4f92 HH |
333 | .tuner_address = 0x60, |
334 | .request_firmware = philips_tda1004x_request_firmware | |
86ddd96f MCC |
335 | }; |
336 | ||
2cf36ac4 HH |
337 | static struct tda1004x_config philips_tu1216_61_config = { |
338 | ||
339 | .demod_address = 0x8, | |
340 | .invert = 1, | |
341 | .invert_oclk = 0, | |
342 | .xtal_freq = TDA10046_XTAL_4M, | |
343 | .agc_config = TDA10046_AGC_DEFAULT, | |
344 | .if_freq = TDA10046_FREQ_3617, | |
58ef4f92 HH |
345 | .tuner_address = 0x61, |
346 | .request_firmware = philips_tda1004x_request_firmware | |
2cf36ac4 HH |
347 | }; |
348 | ||
349 | /* ------------------------------------------------------------------ */ | |
350 | ||
cbb94521 | 351 | static int philips_td1316_tuner_init(struct dvb_frontend *fe) |
2cf36ac4 HH |
352 | { |
353 | struct saa7134_dev *dev = fe->dvb->priv; | |
58ef4f92 HH |
354 | struct tda1004x_state *state = fe->demodulator_priv; |
355 | u8 addr = state->config->tuner_address; | |
2cf36ac4 | 356 | static u8 msg[] = { 0x0b, 0xf5, 0x86, 0xab }; |
58ef4f92 | 357 | struct i2c_msg init_msg = {.addr = addr,.flags = 0,.buf = msg,.len = sizeof(msg) }; |
2cf36ac4 HH |
358 | |
359 | /* setup PLL configuration */ | |
dea74869 PB |
360 | if (fe->ops.i2c_gate_ctrl) |
361 | fe->ops.i2c_gate_ctrl(fe, 1); | |
2cf36ac4 HH |
362 | if (i2c_transfer(&dev->i2c_adap, &init_msg, 1) != 1) |
363 | return -EIO; | |
2cf36ac4 HH |
364 | return 0; |
365 | } | |
366 | ||
a79ddae9 | 367 | static int philips_td1316_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) |
2cf36ac4 | 368 | { |
58ef4f92 HH |
369 | return philips_tda6651_pll_set(fe, params); |
370 | } | |
371 | ||
372 | static int philips_td1316_tuner_sleep(struct dvb_frontend *fe) | |
373 | { | |
374 | struct saa7134_dev *dev = fe->dvb->priv; | |
375 | struct tda1004x_state *state = fe->demodulator_priv; | |
376 | u8 addr = state->config->tuner_address; | |
377 | static u8 msg[] = { 0x0b, 0xdc, 0x86, 0xa4 }; | |
378 | struct i2c_msg analog_msg = {.addr = addr,.flags = 0,.buf = msg,.len = sizeof(msg) }; | |
379 | ||
380 | /* switch the tuner to analog mode */ | |
381 | if (fe->ops.i2c_gate_ctrl) | |
382 | fe->ops.i2c_gate_ctrl(fe, 1); | |
383 | if (i2c_transfer(&dev->i2c_adap, &analog_msg, 1) != 1) | |
384 | return -EIO; | |
385 | return 0; | |
2cf36ac4 HH |
386 | } |
387 | ||
58ef4f92 HH |
388 | /* ------------------------------------------------------------------ */ |
389 | ||
cbb94521 HH |
390 | static int philips_europa_tuner_init(struct dvb_frontend *fe) |
391 | { | |
392 | struct saa7134_dev *dev = fe->dvb->priv; | |
393 | static u8 msg[] = { 0x00, 0x40}; | |
394 | struct i2c_msg init_msg = {.addr = 0x43,.flags = 0,.buf = msg,.len = sizeof(msg) }; | |
395 | ||
396 | ||
397 | if (philips_td1316_tuner_init(fe)) | |
398 | return -EIO; | |
399 | msleep(1); | |
400 | if (i2c_transfer(&dev->i2c_adap, &init_msg, 1) != 1) | |
401 | return -EIO; | |
402 | ||
403 | return 0; | |
404 | } | |
405 | ||
a79ddae9 | 406 | static int philips_europa_tuner_sleep(struct dvb_frontend *fe) |
2cf36ac4 HH |
407 | { |
408 | struct saa7134_dev *dev = fe->dvb->priv; | |
2cf36ac4 | 409 | |
58ef4f92 HH |
410 | static u8 msg[] = { 0x00, 0x14 }; |
411 | struct i2c_msg analog_msg = {.addr = 0x43,.flags = 0,.buf = msg,.len = sizeof(msg) }; | |
412 | ||
413 | if (philips_td1316_tuner_sleep(fe)) | |
414 | return -EIO; | |
2cf36ac4 HH |
415 | |
416 | /* switch the board to analog mode */ | |
dea74869 PB |
417 | if (fe->ops.i2c_gate_ctrl) |
418 | fe->ops.i2c_gate_ctrl(fe, 1); | |
2cf36ac4 | 419 | i2c_transfer(&dev->i2c_adap, &analog_msg, 1); |
a79ddae9 AQ |
420 | return 0; |
421 | } | |
422 | ||
423 | static int philips_europa_demod_sleep(struct dvb_frontend *fe) | |
424 | { | |
425 | struct saa7134_dev *dev = fe->dvb->priv; | |
426 | ||
427 | if (dev->original_demod_sleep) | |
428 | dev->original_demod_sleep(fe); | |
dea74869 | 429 | fe->ops.i2c_gate_ctrl(fe, 1); |
a79ddae9 | 430 | return 0; |
2cf36ac4 HH |
431 | } |
432 | ||
433 | static struct tda1004x_config philips_europa_config = { | |
434 | ||
435 | .demod_address = 0x8, | |
436 | .invert = 0, | |
437 | .invert_oclk = 0, | |
438 | .xtal_freq = TDA10046_XTAL_4M, | |
439 | .agc_config = TDA10046_AGC_IFO_AUTO_POS, | |
440 | .if_freq = TDA10046_FREQ_052, | |
58ef4f92 HH |
441 | .tuner_address = 0x61, |
442 | .request_firmware = philips_tda1004x_request_firmware | |
2cf36ac4 HH |
443 | }; |
444 | ||
445 | /* ------------------------------------------------------------------ */ | |
86ddd96f | 446 | |
a79ddae9 | 447 | static int philips_fmd1216_tuner_init(struct dvb_frontend *fe) |
86ddd96f MCC |
448 | { |
449 | struct saa7134_dev *dev = fe->dvb->priv; | |
58ef4f92 HH |
450 | struct tda1004x_state *state = fe->demodulator_priv; |
451 | u8 addr = state->config->tuner_address; | |
86ddd96f MCC |
452 | /* this message is to set up ATC and ALC */ |
453 | static u8 fmd1216_init[] = { 0x0b, 0xdc, 0x9c, 0xa0 }; | |
58ef4f92 | 454 | struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = fmd1216_init,.len = sizeof(fmd1216_init) }; |
86ddd96f | 455 | |
dea74869 PB |
456 | if (fe->ops.i2c_gate_ctrl) |
457 | fe->ops.i2c_gate_ctrl(fe, 1); | |
86ddd96f MCC |
458 | if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1) |
459 | return -EIO; | |
460 | msleep(1); | |
461 | ||
462 | return 0; | |
463 | } | |
464 | ||
a79ddae9 | 465 | static int philips_fmd1216_tuner_sleep(struct dvb_frontend *fe) |
86ddd96f MCC |
466 | { |
467 | struct saa7134_dev *dev = fe->dvb->priv; | |
58ef4f92 HH |
468 | struct tda1004x_state *state = fe->demodulator_priv; |
469 | u8 addr = state->config->tuner_address; | |
86ddd96f | 470 | /* this message actually turns the tuner back to analog mode */ |
cf83ac43 | 471 | u8 fmd1216_init[] = { 0x0b, 0xdc, 0x9c, 0x60 }; |
58ef4f92 | 472 | struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = fmd1216_init,.len = sizeof(fmd1216_init) }; |
86ddd96f | 473 | |
dea74869 PB |
474 | if (fe->ops.i2c_gate_ctrl) |
475 | fe->ops.i2c_gate_ctrl(fe, 1); | |
86ddd96f MCC |
476 | i2c_transfer(&dev->i2c_adap, &tuner_msg, 1); |
477 | msleep(1); | |
478 | fmd1216_init[2] = 0x86; | |
479 | fmd1216_init[3] = 0x54; | |
dea74869 PB |
480 | if (fe->ops.i2c_gate_ctrl) |
481 | fe->ops.i2c_gate_ctrl(fe, 1); | |
86ddd96f MCC |
482 | i2c_transfer(&dev->i2c_adap, &tuner_msg, 1); |
483 | msleep(1); | |
a79ddae9 | 484 | return 0; |
86ddd96f MCC |
485 | } |
486 | ||
a79ddae9 | 487 | static int philips_fmd1216_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) |
86ddd96f MCC |
488 | { |
489 | struct saa7134_dev *dev = fe->dvb->priv; | |
58ef4f92 HH |
490 | struct tda1004x_state *state = fe->demodulator_priv; |
491 | u8 addr = state->config->tuner_address; | |
86ddd96f | 492 | u8 tuner_buf[4]; |
58ef4f92 | 493 | struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tuner_buf,.len = |
86ddd96f MCC |
494 | sizeof(tuner_buf) }; |
495 | int tuner_frequency = 0; | |
496 | int divider = 0; | |
497 | u8 band, mode, cp; | |
498 | ||
499 | /* determine charge pump */ | |
500 | tuner_frequency = params->frequency + 36130000; | |
501 | if (tuner_frequency < 87000000) | |
502 | return -EINVAL; | |
503 | /* low band */ | |
504 | else if (tuner_frequency < 180000000) { | |
505 | band = 1; | |
506 | mode = 7; | |
507 | cp = 0; | |
508 | } else if (tuner_frequency < 195000000) { | |
509 | band = 1; | |
510 | mode = 6; | |
511 | cp = 1; | |
512 | /* mid band */ | |
513 | } else if (tuner_frequency < 366000000) { | |
514 | if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) { | |
515 | band = 10; | |
516 | } else { | |
517 | band = 2; | |
518 | } | |
519 | mode = 7; | |
520 | cp = 0; | |
521 | } else if (tuner_frequency < 478000000) { | |
522 | if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) { | |
523 | band = 10; | |
524 | } else { | |
525 | band = 2; | |
526 | } | |
527 | mode = 6; | |
528 | cp = 1; | |
529 | /* high band */ | |
530 | } else if (tuner_frequency < 662000000) { | |
531 | if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) { | |
532 | band = 12; | |
533 | } else { | |
534 | band = 4; | |
535 | } | |
536 | mode = 7; | |
537 | cp = 0; | |
538 | } else if (tuner_frequency < 840000000) { | |
539 | if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) { | |
540 | band = 12; | |
541 | } else { | |
542 | band = 4; | |
543 | } | |
544 | mode = 6; | |
545 | cp = 1; | |
546 | } else { | |
547 | if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) { | |
548 | band = 12; | |
549 | } else { | |
550 | band = 4; | |
551 | } | |
552 | mode = 7; | |
553 | cp = 1; | |
554 | ||
555 | } | |
556 | /* calculate divisor */ | |
557 | /* ((36166000 + Finput) / 166666) rounded! */ | |
558 | divider = (tuner_frequency + 83333) / 166667; | |
559 | ||
560 | /* setup tuner buffer */ | |
561 | tuner_buf[0] = (divider >> 8) & 0x7f; | |
562 | tuner_buf[1] = divider & 0xff; | |
563 | tuner_buf[2] = 0x80 | (cp << 6) | (mode << 3) | 4; | |
564 | tuner_buf[3] = 0x40 | band; | |
565 | ||
dea74869 PB |
566 | if (fe->ops.i2c_gate_ctrl) |
567 | fe->ops.i2c_gate_ctrl(fe, 1); | |
58ef4f92 | 568 | if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1) { |
cf3c34c8 TP |
569 | wprintk("could not write to tuner at addr: 0x%02x\n", |
570 | addr << 1); | |
86ddd96f | 571 | return -EIO; |
58ef4f92 | 572 | } |
86ddd96f MCC |
573 | return 0; |
574 | } | |
575 | ||
408b664a | 576 | static struct tda1004x_config medion_cardbus = { |
86ddd96f MCC |
577 | .demod_address = 0x08, |
578 | .invert = 1, | |
579 | .invert_oclk = 0, | |
580 | .xtal_freq = TDA10046_XTAL_16M, | |
581 | .agc_config = TDA10046_AGC_IFO_AUTO_NEG, | |
582 | .if_freq = TDA10046_FREQ_3613, | |
58ef4f92 HH |
583 | .tuner_address = 0x61, |
584 | .request_firmware = philips_tda1004x_request_firmware | |
86ddd96f MCC |
585 | }; |
586 | ||
58ef4f92 HH |
587 | /* ------------------------------------------------------------------ |
588 | * tda 1004x based cards with philips silicon tuner | |
589 | */ | |
590 | ||
591 | static void philips_tda827x_lna_gain(struct dvb_frontend *fe, int high) | |
592 | { | |
593 | struct saa7134_dev *dev = fe->dvb->priv; | |
594 | struct tda1004x_state *state = fe->demodulator_priv; | |
595 | u8 addr = state->config->i2c_gate; | |
596 | u8 config = state->config->tuner_config; | |
597 | u8 GP00_CF[] = {0x20, 0x01}; | |
598 | u8 GP00_LEV[] = {0x22, 0x00}; | |
599 | ||
600 | struct i2c_msg msg = {.addr = addr,.flags = 0,.buf = GP00_CF, .len = 2}; | |
601 | if (config) { | |
602 | if (high) { | |
603 | dprintk("setting LNA to high gain\n"); | |
604 | } else { | |
605 | dprintk("setting LNA to low gain\n"); | |
606 | } | |
607 | } | |
608 | switch (config) { | |
609 | case 0: /* no LNA */ | |
610 | break; | |
611 | case 1: /* switch is GPIO 0 of tda8290 */ | |
612 | case 2: | |
613 | /* turn Vsync off */ | |
614 | saa7134_set_gpio(dev, 22, 0); | |
615 | GP00_LEV[1] = high ? 0 : 1; | |
616 | if (i2c_transfer(&dev->i2c_adap, &msg, 1) != 1) { | |
cf3c34c8 TP |
617 | wprintk("could not access tda8290 at addr: 0x%02x\n", |
618 | addr << 1); | |
58ef4f92 HH |
619 | return; |
620 | } | |
621 | msg.buf = GP00_LEV; | |
622 | if (config == 2) | |
623 | GP00_LEV[1] = high ? 1 : 0; | |
624 | i2c_transfer(&dev->i2c_adap, &msg, 1); | |
625 | break; | |
626 | case 3: /* switch with GPIO of saa713x */ | |
627 | saa7134_set_gpio(dev, 22, high); | |
628 | break; | |
629 | } | |
630 | } | |
631 | ||
632 | static int tda8290_i2c_gate_ctrl( struct dvb_frontend* fe, int enable) | |
633 | { | |
58ef4f92 HH |
634 | struct tda1004x_state *state = fe->demodulator_priv; |
635 | ||
636 | u8 addr = state->config->i2c_gate; | |
637 | static u8 tda8290_close[] = { 0x21, 0xc0}; | |
638 | static u8 tda8290_open[] = { 0x21, 0x80}; | |
639 | struct i2c_msg tda8290_msg = {.addr = addr,.flags = 0, .len = 2}; | |
640 | if (enable) { | |
641 | tda8290_msg.buf = tda8290_close; | |
642 | } else { | |
643 | tda8290_msg.buf = tda8290_open; | |
644 | } | |
06be3035 | 645 | if (i2c_transfer(state->i2c, &tda8290_msg, 1) != 1) { |
cf3c34c8 TP |
646 | struct saa7134_dev *dev = fe->dvb->priv; |
647 | wprintk("could not access tda8290 I2C gate\n"); | |
58ef4f92 HH |
648 | return -EIO; |
649 | } | |
650 | msleep(20); | |
651 | return 0; | |
652 | } | |
653 | ||
86ddd96f MCC |
654 | /* ------------------------------------------------------------------ */ |
655 | ||
58ef4f92 | 656 | static int philips_tda827x_tuner_init(struct dvb_frontend *fe) |
90e9df7f | 657 | { |
90e9df7f | 658 | struct saa7134_dev *dev = fe->dvb->priv; |
58ef4f92 | 659 | struct tda1004x_state *state = fe->demodulator_priv; |
8ce47dad | 660 | |
58ef4f92 HH |
661 | switch (state->config->antenna_switch) { |
662 | case 0: break; | |
663 | case 1: dprintk("setting GPIO21 to 0 (TV antenna?)\n"); | |
664 | saa7134_set_gpio(dev, 21, 0); | |
665 | break; | |
666 | case 2: dprintk("setting GPIO21 to 1 (Radio antenna?)\n"); | |
667 | saa7134_set_gpio(dev, 21, 1); | |
668 | break; | |
587d2fd7 | 669 | } |
587d2fd7 HH |
670 | return 0; |
671 | } | |
672 | ||
58ef4f92 | 673 | static int philips_tda827x_tuner_sleep(struct dvb_frontend *fe) |
587d2fd7 | 674 | { |
58ef4f92 HH |
675 | struct saa7134_dev *dev = fe->dvb->priv; |
676 | struct tda1004x_state *state = fe->demodulator_priv; | |
8ce47dad | 677 | |
58ef4f92 HH |
678 | switch (state->config->antenna_switch) { |
679 | case 0: break; | |
680 | case 1: dprintk("setting GPIO21 to 1 (Radio antenna?)\n"); | |
681 | saa7134_set_gpio(dev, 21, 1); | |
682 | break; | |
683 | case 2: dprintk("setting GPIO21 to 0 (TV antenna?)\n"); | |
684 | saa7134_set_gpio(dev, 21, 0); | |
685 | break; | |
686 | } | |
587d2fd7 | 687 | return 0; |
2d6b5f62 | 688 | } |
90e9df7f | 689 | |
8ce47dad MK |
690 | static struct tda827x_config tda827x_cfg = { |
691 | .lna_gain = philips_tda827x_lna_gain, | |
692 | .init = philips_tda827x_tuner_init, | |
693 | .sleep = philips_tda827x_tuner_sleep | |
694 | }; | |
90e9df7f | 695 | |
b8bc76d8 | 696 | static void configure_tda827x_fe(struct saa7134_dev *dev, struct tda1004x_config *tda_conf) |
90e9df7f | 697 | { |
58ef4f92 HH |
698 | dev->dvb.frontend = dvb_attach(tda10046_attach, tda_conf, &dev->i2c_adap); |
699 | if (dev->dvb.frontend) { | |
700 | if (tda_conf->i2c_gate) | |
701 | dev->dvb.frontend->ops.i2c_gate_ctrl = tda8290_i2c_gate_ctrl; | |
ede2200d HH |
702 | if (dvb_attach(tda827x_attach, dev->dvb.frontend, tda_conf->tuner_address, |
703 | &dev->i2c_adap,&tda827x_cfg) == NULL) { | |
cf3c34c8 | 704 | wprintk("no tda827x tuner found at addr: %02x\n", |
ede2200d HH |
705 | tda_conf->tuner_address); |
706 | } | |
58ef4f92 | 707 | } |
90e9df7f HH |
708 | } |
709 | ||
58ef4f92 HH |
710 | /* ------------------------------------------------------------------ */ |
711 | static struct tda1004x_config tda827x_lifeview_config = { | |
90e9df7f HH |
712 | .demod_address = 0x08, |
713 | .invert = 1, | |
714 | .invert_oclk = 0, | |
715 | .xtal_freq = TDA10046_XTAL_16M, | |
1bb0e866 HH |
716 | .agc_config = TDA10046_AGC_TDA827X, |
717 | .gpio_config = TDA10046_GP11_I, | |
550a9a5e | 718 | .if_freq = TDA10046_FREQ_045, |
58ef4f92 HH |
719 | .tuner_address = 0x60, |
720 | .request_firmware = philips_tda1004x_request_firmware | |
550a9a5e | 721 | }; |
550a9a5e | 722 | |
58ef4f92 HH |
723 | static struct tda1004x_config philips_tiger_config = { |
724 | .demod_address = 0x08, | |
725 | .invert = 1, | |
726 | .invert_oclk = 0, | |
727 | .xtal_freq = TDA10046_XTAL_16M, | |
728 | .agc_config = TDA10046_AGC_TDA827X, | |
729 | .gpio_config = TDA10046_GP11_I, | |
730 | .if_freq = TDA10046_FREQ_045, | |
731 | .i2c_gate = 0x4b, | |
732 | .tuner_address = 0x61, | |
733 | .tuner_config = 0, | |
734 | .antenna_switch= 1, | |
735 | .request_firmware = philips_tda1004x_request_firmware | |
736 | }; | |
550a9a5e HH |
737 | |
738 | static struct tda1004x_config cinergy_ht_config = { | |
739 | .demod_address = 0x08, | |
740 | .invert = 1, | |
741 | .invert_oclk = 0, | |
742 | .xtal_freq = TDA10046_XTAL_16M, | |
1bb0e866 HH |
743 | .agc_config = TDA10046_AGC_TDA827X, |
744 | .gpio_config = TDA10046_GP01_I, | |
90e9df7f | 745 | .if_freq = TDA10046_FREQ_045, |
58ef4f92 HH |
746 | .i2c_gate = 0x4b, |
747 | .tuner_address = 0x61, | |
748 | .tuner_config = 0, | |
749 | .request_firmware = philips_tda1004x_request_firmware | |
90e9df7f HH |
750 | }; |
751 | ||
58ef4f92 HH |
752 | static struct tda1004x_config cinergy_ht_pci_config = { |
753 | .demod_address = 0x08, | |
754 | .invert = 1, | |
755 | .invert_oclk = 0, | |
756 | .xtal_freq = TDA10046_XTAL_16M, | |
757 | .agc_config = TDA10046_AGC_TDA827X, | |
758 | .gpio_config = TDA10046_GP01_I, | |
759 | .if_freq = TDA10046_FREQ_045, | |
760 | .i2c_gate = 0x4b, | |
761 | .tuner_address = 0x60, | |
762 | .tuner_config = 0, | |
763 | .request_firmware = philips_tda1004x_request_firmware | |
764 | }; | |
765 | ||
766 | static struct tda1004x_config philips_tiger_s_config = { | |
767 | .demod_address = 0x08, | |
768 | .invert = 1, | |
769 | .invert_oclk = 0, | |
770 | .xtal_freq = TDA10046_XTAL_16M, | |
771 | .agc_config = TDA10046_AGC_TDA827X, | |
772 | .gpio_config = TDA10046_GP01_I, | |
773 | .if_freq = TDA10046_FREQ_045, | |
774 | .i2c_gate = 0x4b, | |
775 | .tuner_address = 0x61, | |
776 | .tuner_config = 2, | |
777 | .antenna_switch= 1, | |
778 | .request_firmware = philips_tda1004x_request_firmware | |
779 | }; | |
df42eaf2 | 780 | |
587d2fd7 HH |
781 | static struct tda1004x_config pinnacle_pctv_310i_config = { |
782 | .demod_address = 0x08, | |
783 | .invert = 1, | |
784 | .invert_oclk = 0, | |
785 | .xtal_freq = TDA10046_XTAL_16M, | |
1bb0e866 HH |
786 | .agc_config = TDA10046_AGC_TDA827X, |
787 | .gpio_config = TDA10046_GP11_I, | |
587d2fd7 | 788 | .if_freq = TDA10046_FREQ_045, |
58ef4f92 HH |
789 | .i2c_gate = 0x4b, |
790 | .tuner_address = 0x61, | |
791 | .tuner_config = 1, | |
792 | .request_firmware = philips_tda1004x_request_firmware | |
587d2fd7 HH |
793 | }; |
794 | ||
c6e53daf TG |
795 | static struct tda1004x_config hauppauge_hvr_1110_config = { |
796 | .demod_address = 0x08, | |
797 | .invert = 1, | |
798 | .invert_oclk = 0, | |
799 | .xtal_freq = TDA10046_XTAL_16M, | |
1bb0e866 HH |
800 | .agc_config = TDA10046_AGC_TDA827X, |
801 | .gpio_config = TDA10046_GP11_I, | |
c6e53daf | 802 | .if_freq = TDA10046_FREQ_045, |
58ef4f92 HH |
803 | .i2c_gate = 0x4b, |
804 | .tuner_address = 0x61, | |
805 | .request_firmware = philips_tda1004x_request_firmware | |
c6e53daf TG |
806 | }; |
807 | ||
83646817 HH |
808 | static struct tda1004x_config asus_p7131_dual_config = { |
809 | .demod_address = 0x08, | |
810 | .invert = 1, | |
811 | .invert_oclk = 0, | |
812 | .xtal_freq = TDA10046_XTAL_16M, | |
1bb0e866 HH |
813 | .agc_config = TDA10046_AGC_TDA827X, |
814 | .gpio_config = TDA10046_GP11_I, | |
83646817 | 815 | .if_freq = TDA10046_FREQ_045, |
58ef4f92 HH |
816 | .i2c_gate = 0x4b, |
817 | .tuner_address = 0x61, | |
818 | .tuner_config = 0, | |
819 | .antenna_switch= 2, | |
820 | .request_firmware = philips_tda1004x_request_firmware | |
83646817 HH |
821 | }; |
822 | ||
420f32fe NS |
823 | static struct tda1004x_config lifeview_trio_config = { |
824 | .demod_address = 0x09, | |
825 | .invert = 1, | |
826 | .invert_oclk = 0, | |
827 | .xtal_freq = TDA10046_XTAL_16M, | |
1bb0e866 HH |
828 | .agc_config = TDA10046_AGC_TDA827X, |
829 | .gpio_config = TDA10046_GP00_I, | |
420f32fe | 830 | .if_freq = TDA10046_FREQ_045, |
58ef4f92 HH |
831 | .tuner_address = 0x60, |
832 | .request_firmware = philips_tda1004x_request_firmware | |
420f32fe NS |
833 | }; |
834 | ||
58ef4f92 | 835 | static struct tda1004x_config tevion_dvbt220rf_config = { |
df42eaf2 HH |
836 | .demod_address = 0x08, |
837 | .invert = 1, | |
838 | .invert_oclk = 0, | |
839 | .xtal_freq = TDA10046_XTAL_16M, | |
1bb0e866 | 840 | .agc_config = TDA10046_AGC_TDA827X, |
58ef4f92 | 841 | .gpio_config = TDA10046_GP11_I, |
df42eaf2 | 842 | .if_freq = TDA10046_FREQ_045, |
58ef4f92 HH |
843 | .tuner_address = 0x60, |
844 | .request_firmware = philips_tda1004x_request_firmware | |
df42eaf2 HH |
845 | }; |
846 | ||
58ef4f92 | 847 | static struct tda1004x_config md8800_dvbt_config = { |
3dfb729f PH |
848 | .demod_address = 0x08, |
849 | .invert = 1, | |
850 | .invert_oclk = 0, | |
851 | .xtal_freq = TDA10046_XTAL_16M, | |
1bb0e866 | 852 | .agc_config = TDA10046_AGC_TDA827X, |
58ef4f92 | 853 | .gpio_config = TDA10046_GP01_I, |
3dfb729f | 854 | .if_freq = TDA10046_FREQ_045, |
58ef4f92 HH |
855 | .i2c_gate = 0x4b, |
856 | .tuner_address = 0x60, | |
857 | .tuner_config = 0, | |
858 | .request_firmware = philips_tda1004x_request_firmware | |
3dfb729f PH |
859 | }; |
860 | ||
58ef4f92 HH |
861 | /* ------------------------------------------------------------------ |
862 | * special case: this card uses saa713x GPIO22 for the mode switch | |
863 | */ | |
5eda227f | 864 | |
58ef4f92 | 865 | static int ads_duo_tuner_init(struct dvb_frontend *fe) |
5eda227f HH |
866 | { |
867 | struct saa7134_dev *dev = fe->dvb->priv; | |
58ef4f92 HH |
868 | philips_tda827x_tuner_init(fe); |
869 | /* route TDA8275a AGC input to the channel decoder */ | |
06be3035 | 870 | saa7134_set_gpio(dev, 22, 1); |
5eda227f HH |
871 | return 0; |
872 | } | |
873 | ||
58ef4f92 | 874 | static int ads_duo_tuner_sleep(struct dvb_frontend *fe) |
5eda227f | 875 | { |
5eda227f | 876 | struct saa7134_dev *dev = fe->dvb->priv; |
58ef4f92 | 877 | /* route TDA8275a AGC input to the analog IF chip*/ |
06be3035 | 878 | saa7134_set_gpio(dev, 22, 0); |
58ef4f92 HH |
879 | philips_tda827x_tuner_sleep(fe); |
880 | return 0; | |
5eda227f HH |
881 | } |
882 | ||
8ce47dad MK |
883 | static struct tda827x_config ads_duo_cfg = { |
884 | .lna_gain = philips_tda827x_lna_gain, | |
885 | .init = ads_duo_tuner_init, | |
886 | .sleep = ads_duo_tuner_sleep | |
887 | }; | |
888 | ||
58ef4f92 | 889 | static struct tda1004x_config ads_tech_duo_config = { |
5eda227f HH |
890 | .demod_address = 0x08, |
891 | .invert = 1, | |
892 | .invert_oclk = 0, | |
893 | .xtal_freq = TDA10046_XTAL_16M, | |
1bb0e866 | 894 | .agc_config = TDA10046_AGC_TDA827X, |
58ef4f92 | 895 | .gpio_config = TDA10046_GP00_I, |
5eda227f | 896 | .if_freq = TDA10046_FREQ_045, |
58ef4f92 HH |
897 | .tuner_address = 0x61, |
898 | .request_firmware = philips_tda1004x_request_firmware | |
5eda227f HH |
899 | }; |
900 | ||
58ef4f92 HH |
901 | /* ================================================================== |
902 | * tda10086 based DVB-S cards, helper functions | |
903 | */ | |
904 | ||
e2ac28fa IL |
905 | static struct tda10086_config flydvbs = { |
906 | .demod_address = 0x0e, | |
907 | .invert = 0, | |
908 | }; | |
909 | ||
58ef4f92 HH |
910 | /* ================================================================== |
911 | * nxt200x based ATSC cards, helper functions | |
912 | */ | |
90e9df7f | 913 | |
3b64e8e2 MK |
914 | static struct nxt200x_config avertvhda180 = { |
915 | .demod_address = 0x0a, | |
3b64e8e2 | 916 | }; |
3e1410ad | 917 | |
fbc81c07 CM |
918 | static int nxt200x_set_pll_input(u8 *buf, int input) |
919 | { | |
920 | if (input) | |
921 | buf[3] |= 0x08; | |
922 | else | |
923 | buf[3] &= ~0x08; | |
924 | return 0; | |
925 | } | |
926 | ||
3e1410ad AB |
927 | static struct nxt200x_config kworldatsc110 = { |
928 | .demod_address = 0x0a, | |
fbc81c07 | 929 | .set_pll_input = nxt200x_set_pll_input, |
3e1410ad | 930 | }; |
3b64e8e2 | 931 | |
58ef4f92 HH |
932 | /* ================================================================== |
933 | * Core code | |
934 | */ | |
1da177e4 LT |
935 | |
936 | static int dvb_init(struct saa7134_dev *dev) | |
937 | { | |
1c4f76ab | 938 | int ret; |
1da177e4 LT |
939 | /* init struct videobuf_dvb */ |
940 | dev->ts.nr_bufs = 32; | |
941 | dev->ts.nr_packets = 32*4; | |
942 | dev->dvb.name = dev->name; | |
943 | videobuf_queue_init(&dev->dvb.dvbq, &saa7134_ts_qops, | |
944 | dev->pci, &dev->slock, | |
945 | V4L2_BUF_TYPE_VIDEO_CAPTURE, | |
946 | V4L2_FIELD_ALTERNATE, | |
947 | sizeof(struct saa7134_buf), | |
948 | dev); | |
949 | ||
950 | switch (dev->board) { | |
951 | case SAA7134_BOARD_PINNACLE_300I_DVBT_PAL: | |
cf3c34c8 | 952 | dprintk("pinnacle 300i dvb setup\n"); |
2bfe031d | 953 | dev->dvb.frontend = dvb_attach(mt352_attach, &pinnacle_300i, |
f7b54b10 | 954 | &dev->i2c_adap); |
6b3ccab7 | 955 | if (dev->dvb.frontend) { |
dea74869 | 956 | dev->dvb.frontend->ops.tuner_ops.set_params = mt352_pinnacle_tuner_set_params; |
6b3ccab7 | 957 | } |
1da177e4 | 958 | break; |
a78d0bfa | 959 | case SAA7134_BOARD_AVERMEDIA_777: |
515c208d | 960 | case SAA7134_BOARD_AVERMEDIA_A16AR: |
cf3c34c8 | 961 | dprintk("avertv 777 dvb setup\n"); |
2bfe031d | 962 | dev->dvb.frontend = dvb_attach(mt352_attach, &avermedia_777, |
f7b54b10 | 963 | &dev->i2c_adap); |
6b3ccab7 | 964 | if (dev->dvb.frontend) { |
dea74869 | 965 | dev->dvb.frontend->ops.tuner_ops.calc_regs = mt352_aver777_tuner_calc_regs; |
6b3ccab7 | 966 | } |
a78d0bfa | 967 | break; |
1da177e4 | 968 | case SAA7134_BOARD_MD7134: |
f7b54b10 MK |
969 | dev->dvb.frontend = dvb_attach(tda10046_attach, |
970 | &medion_cardbus, | |
971 | &dev->i2c_adap); | |
6b3ccab7 | 972 | if (dev->dvb.frontend) { |
dea74869 PB |
973 | dev->dvb.frontend->ops.tuner_ops.init = philips_fmd1216_tuner_init; |
974 | dev->dvb.frontend->ops.tuner_ops.sleep = philips_fmd1216_tuner_sleep; | |
975 | dev->dvb.frontend->ops.tuner_ops.set_params = philips_fmd1216_tuner_set_params; | |
6b3ccab7 | 976 | } |
1da177e4 | 977 | break; |
86ddd96f | 978 | case SAA7134_BOARD_PHILIPS_TOUGH: |
f7b54b10 MK |
979 | dev->dvb.frontend = dvb_attach(tda10046_attach, |
980 | &philips_tu1216_60_config, | |
981 | &dev->i2c_adap); | |
6b3ccab7 | 982 | if (dev->dvb.frontend) { |
58ef4f92 HH |
983 | dev->dvb.frontend->ops.tuner_ops.init = philips_tu1216_init; |
984 | dev->dvb.frontend->ops.tuner_ops.set_params = philips_tda6651_pll_set; | |
6b3ccab7 | 985 | } |
86ddd96f MCC |
986 | break; |
987 | case SAA7134_BOARD_FLYDVBTDUO: | |
10b7a903 | 988 | case SAA7134_BOARD_FLYDVBT_DUO_CARDBUS: |
b8bc76d8 | 989 | configure_tda827x_fe(dev, &tda827x_lifeview_config); |
86ddd96f | 990 | break; |
2cf36ac4 | 991 | case SAA7134_BOARD_PHILIPS_EUROPA: |
2cf36ac4 | 992 | case SAA7134_BOARD_VIDEOMATE_DVBT_300: |
f7b54b10 MK |
993 | dev->dvb.frontend = dvb_attach(tda10046_attach, |
994 | &philips_europa_config, | |
995 | &dev->i2c_adap); | |
6b3ccab7 | 996 | if (dev->dvb.frontend) { |
588f9831 HH |
997 | dev->original_demod_sleep = dev->dvb.frontend->ops.sleep; |
998 | dev->dvb.frontend->ops.sleep = philips_europa_demod_sleep; | |
dea74869 PB |
999 | dev->dvb.frontend->ops.tuner_ops.init = philips_europa_tuner_init; |
1000 | dev->dvb.frontend->ops.tuner_ops.sleep = philips_europa_tuner_sleep; | |
1001 | dev->dvb.frontend->ops.tuner_ops.set_params = philips_td1316_tuner_set_params; | |
6b3ccab7 | 1002 | } |
2cf36ac4 HH |
1003 | break; |
1004 | case SAA7134_BOARD_VIDEOMATE_DVBT_200: | |
f7b54b10 MK |
1005 | dev->dvb.frontend = dvb_attach(tda10046_attach, |
1006 | &philips_tu1216_61_config, | |
1007 | &dev->i2c_adap); | |
6b3ccab7 | 1008 | if (dev->dvb.frontend) { |
58ef4f92 HH |
1009 | dev->dvb.frontend->ops.tuner_ops.init = philips_tu1216_init; |
1010 | dev->dvb.frontend->ops.tuner_ops.set_params = philips_tda6651_pll_set; | |
6b3ccab7 | 1011 | } |
2cf36ac4 | 1012 | break; |
90e9df7f | 1013 | case SAA7134_BOARD_PHILIPS_TIGER: |
b8bc76d8 | 1014 | configure_tda827x_fe(dev, &philips_tiger_config); |
587d2fd7 HH |
1015 | break; |
1016 | case SAA7134_BOARD_PINNACLE_PCTV_310i: | |
b8bc76d8 | 1017 | configure_tda827x_fe(dev, &pinnacle_pctv_310i_config); |
90e9df7f | 1018 | break; |
c6e53daf | 1019 | case SAA7134_BOARD_HAUPPAUGE_HVR1110: |
b8bc76d8 | 1020 | configure_tda827x_fe(dev, &hauppauge_hvr_1110_config); |
c6e53daf | 1021 | break; |
d4b0aba4 | 1022 | case SAA7134_BOARD_ASUSTeK_P7131_DUAL: |
b8bc76d8 | 1023 | configure_tda827x_fe(dev, &asus_p7131_dual_config); |
d4b0aba4 | 1024 | break; |
3d8466ec | 1025 | case SAA7134_BOARD_FLYDVBT_LR301: |
b8bc76d8 | 1026 | configure_tda827x_fe(dev, &tda827x_lifeview_config); |
3d8466ec | 1027 | break; |
420f32fe | 1028 | case SAA7134_BOARD_FLYDVB_TRIO: |
b331daa0 | 1029 | if(! use_frontend) { //terrestrial |
b8bc76d8 | 1030 | configure_tda827x_fe(dev, &lifeview_trio_config); |
1f683cd8 NS |
1031 | } else { //satellite |
1032 | dev->dvb.frontend = dvb_attach(tda10086_attach, &flydvbs, &dev->i2c_adap); | |
1033 | if (dev->dvb.frontend) { | |
1034 | if (dvb_attach(tda826x_attach, dev->dvb.frontend, 0x63, | |
1035 | &dev->i2c_adap, 0) == NULL) { | |
cf3c34c8 | 1036 | wprintk("%s: Lifeview Trio, No tda826x found!\n", __FUNCTION__); |
1f683cd8 NS |
1037 | } |
1038 | if (dvb_attach(isl6421_attach, dev->dvb.frontend, &dev->i2c_adap, | |
1039 | 0x08, 0, 0) == NULL) { | |
cf3c34c8 | 1040 | wprintk("%s: Lifeview Trio, No ISL6421 found!\n", __FUNCTION__); |
1f683cd8 NS |
1041 | } |
1042 | } | |
6b3ccab7 | 1043 | } |
420f32fe | 1044 | break; |
df42eaf2 | 1045 | case SAA7134_BOARD_ADS_DUO_CARDBUS_PTV331: |
58ef4f92 | 1046 | case SAA7134_BOARD_FLYDVBT_HYBRID_CARDBUS: |
f7b54b10 MK |
1047 | dev->dvb.frontend = dvb_attach(tda10046_attach, |
1048 | &ads_tech_duo_config, | |
1049 | &dev->i2c_adap); | |
6b3ccab7 | 1050 | if (dev->dvb.frontend) { |
ede2200d | 1051 | if (dvb_attach(tda827x_attach,dev->dvb.frontend, |
8ce47dad | 1052 | ads_tech_duo_config.tuner_address, |
ede2200d | 1053 | &dev->i2c_adap,&ads_duo_cfg) == NULL) { |
cf3c34c8 | 1054 | wprintk("no tda827x tuner found at addr: %02x\n", |
ede2200d HH |
1055 | ads_tech_duo_config.tuner_address); |
1056 | } | |
6b3ccab7 | 1057 | } |
df42eaf2 | 1058 | break; |
3dfb729f | 1059 | case SAA7134_BOARD_TEVION_DVBT_220RF: |
b8bc76d8 | 1060 | configure_tda827x_fe(dev, &tevion_dvbt220rf_config); |
d95b8942 | 1061 | break; |
5eda227f | 1062 | case SAA7134_BOARD_MEDION_MD8800_QUADRO: |
b8bc76d8 | 1063 | configure_tda827x_fe(dev, &md8800_dvbt_config); |
5eda227f | 1064 | break; |
3b64e8e2 | 1065 | case SAA7134_BOARD_AVERMEDIA_AVERTVHD_A180: |
f7b54b10 MK |
1066 | dev->dvb.frontend = dvb_attach(nxt200x_attach, &avertvhda180, |
1067 | &dev->i2c_adap); | |
a79ddae9 | 1068 | if (dev->dvb.frontend) { |
4ad8eee5 MK |
1069 | dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, |
1070 | NULL, &dvb_pll_tdhu2); | |
a79ddae9 | 1071 | } |
3b64e8e2 | 1072 | break; |
3e1410ad | 1073 | case SAA7134_BOARD_KWORLD_ATSC110: |
f7b54b10 MK |
1074 | dev->dvb.frontend = dvb_attach(nxt200x_attach, &kworldatsc110, |
1075 | &dev->i2c_adap); | |
a79ddae9 | 1076 | if (dev->dvb.frontend) { |
4ad8eee5 MK |
1077 | dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, |
1078 | NULL, &dvb_pll_tuv1236d); | |
a79ddae9 | 1079 | } |
3e1410ad | 1080 | break; |
e2ac28fa | 1081 | case SAA7134_BOARD_FLYDVBS_LR300: |
f7b54b10 MK |
1082 | dev->dvb.frontend = dvb_attach(tda10086_attach, &flydvbs, |
1083 | &dev->i2c_adap); | |
e2ac28fa | 1084 | if (dev->dvb.frontend) { |
f7b54b10 MK |
1085 | if (dvb_attach(tda826x_attach, dev->dvb.frontend, 0x60, |
1086 | &dev->i2c_adap, 0) == NULL) { | |
cf3c34c8 | 1087 | wprintk("%s: No tda826x found!\n", __FUNCTION__); |
e2ac28fa | 1088 | } |
f7b54b10 MK |
1089 | if (dvb_attach(isl6421_attach, dev->dvb.frontend, |
1090 | &dev->i2c_adap, 0x08, 0, 0) == NULL) { | |
cf3c34c8 | 1091 | wprintk("%s: No ISL6421 found!\n", __FUNCTION__); |
e2ac28fa IL |
1092 | } |
1093 | } | |
1094 | break; | |
cf146ca4 HH |
1095 | case SAA7134_BOARD_ASUS_EUROPA2_HYBRID: |
1096 | dev->dvb.frontend = tda10046_attach(&medion_cardbus, | |
1097 | &dev->i2c_adap); | |
1098 | if (dev->dvb.frontend) { | |
1099 | dev->original_demod_sleep = dev->dvb.frontend->ops.sleep; | |
1100 | dev->dvb.frontend->ops.sleep = philips_europa_demod_sleep; | |
1101 | dev->dvb.frontend->ops.tuner_ops.init = philips_fmd1216_tuner_init; | |
1102 | dev->dvb.frontend->ops.tuner_ops.sleep = philips_fmd1216_tuner_sleep; | |
1103 | dev->dvb.frontend->ops.tuner_ops.set_params = philips_fmd1216_tuner_set_params; | |
1104 | } | |
1105 | break; | |
cbb94521 HH |
1106 | case SAA7134_BOARD_VIDEOMATE_DVBT_200A: |
1107 | dev->dvb.frontend = dvb_attach(tda10046_attach, | |
1108 | &philips_europa_config, | |
1109 | &dev->i2c_adap); | |
1110 | if (dev->dvb.frontend) { | |
1111 | dev->dvb.frontend->ops.tuner_ops.init = philips_td1316_tuner_init; | |
1112 | dev->dvb.frontend->ops.tuner_ops.set_params = philips_td1316_tuner_set_params; | |
1113 | } | |
1114 | break; | |
550a9a5e | 1115 | case SAA7134_BOARD_CINERGY_HT_PCMCIA: |
b8bc76d8 | 1116 | configure_tda827x_fe(dev, &cinergy_ht_config); |
9de271e6 MK |
1117 | break; |
1118 | case SAA7134_BOARD_CINERGY_HT_PCI: | |
b8bc76d8 | 1119 | configure_tda827x_fe(dev, &cinergy_ht_pci_config); |
58ef4f92 HH |
1120 | break; |
1121 | case SAA7134_BOARD_PHILIPS_TIGER_S: | |
b8bc76d8 | 1122 | configure_tda827x_fe(dev, &philips_tiger_s_config); |
550a9a5e | 1123 | break; |
1da177e4 | 1124 | default: |
cf3c34c8 | 1125 | wprintk("Huh? unknown DVB card?\n"); |
1da177e4 LT |
1126 | break; |
1127 | } | |
1128 | ||
1129 | if (NULL == dev->dvb.frontend) { | |
cf3c34c8 | 1130 | printk(KERN_ERR "%s/dvb: frontend initialization failed\n", dev->name); |
1da177e4 LT |
1131 | return -1; |
1132 | } | |
1133 | ||
1134 | /* register everything else */ | |
1c4f76ab HH |
1135 | ret = videobuf_dvb_register(&dev->dvb, THIS_MODULE, dev, &dev->pci->dev); |
1136 | ||
1137 | /* this sequence is necessary to make the tda1004x load its firmware | |
1138 | * and to enter analog mode of hybrid boards | |
1139 | */ | |
1140 | if (!ret) { | |
1141 | if (dev->dvb.frontend->ops.init) | |
1142 | dev->dvb.frontend->ops.init(dev->dvb.frontend); | |
1143 | if (dev->dvb.frontend->ops.sleep) | |
1144 | dev->dvb.frontend->ops.sleep(dev->dvb.frontend); | |
1145 | } | |
1146 | return ret; | |
1da177e4 LT |
1147 | } |
1148 | ||
1149 | static int dvb_fini(struct saa7134_dev *dev) | |
1150 | { | |
1151 | static int on = TDA9887_PRESENT | TDA9887_PORT2_INACTIVE; | |
1152 | ||
1da177e4 LT |
1153 | switch (dev->board) { |
1154 | case SAA7134_BOARD_PINNACLE_300I_DVBT_PAL: | |
1155 | /* otherwise we don't detect the tuner on next insmod */ | |
1156 | saa7134_i2c_call_clients(dev,TDA9887_SET_CONFIG,&on); | |
1157 | break; | |
1158 | }; | |
1159 | videobuf_dvb_unregister(&dev->dvb); | |
1160 | return 0; | |
1161 | } | |
1162 | ||
1163 | static struct saa7134_mpeg_ops dvb_ops = { | |
1164 | .type = SAA7134_MPEG_DVB, | |
1165 | .init = dvb_init, | |
1166 | .fini = dvb_fini, | |
1167 | }; | |
1168 | ||
1169 | static int __init dvb_register(void) | |
1170 | { | |
1171 | return saa7134_ts_register(&dvb_ops); | |
1172 | } | |
1173 | ||
1174 | static void __exit dvb_unregister(void) | |
1175 | { | |
1176 | saa7134_ts_unregister(&dvb_ops); | |
1177 | } | |
1178 | ||
1179 | module_init(dvb_register); | |
1180 | module_exit(dvb_unregister); | |
1181 | ||
1182 | /* ------------------------------------------------------------------ */ | |
1183 | /* | |
1184 | * Local variables: | |
1185 | * c-basic-offset: 8 | |
1186 | * End: | |
1187 | */ |