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Commit | Line | Data |
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ed922a89 KM |
1 | /* |
2 | * tw9910 Video Driver | |
3 | * | |
4 | * Copyright (C) 2008 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ov772x driver, | |
8 | * | |
9 | * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
10 | * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> | |
11 | * Copyright (C) 2008 Magnus Damm | |
12 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/i2c.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/delay.h> | |
95d20109 | 25 | #include <linux/v4l2-mediabus.h> |
ed922a89 | 26 | #include <linux/videodev2.h> |
0d3263f9 | 27 | |
ed922a89 KM |
28 | #include <media/soc_camera.h> |
29 | #include <media/tw9910.h> | |
0d3263f9 GL |
30 | #include <media/v4l2-chip-ident.h> |
31 | #include <media/v4l2-subdev.h> | |
ed922a89 KM |
32 | |
33 | #define GET_ID(val) ((val & 0xF8) >> 3) | |
6d74e5f3 | 34 | #define GET_REV(val) (val & 0x07) |
ed922a89 KM |
35 | |
36 | /* | |
37 | * register offset | |
38 | */ | |
39 | #define ID 0x00 /* Product ID Code Register */ | |
40 | #define STATUS1 0x01 /* Chip Status Register I */ | |
41 | #define INFORM 0x02 /* Input Format */ | |
42 | #define OPFORM 0x03 /* Output Format Control Register */ | |
43 | #define DLYCTR 0x04 /* Hysteresis and HSYNC Delay Control */ | |
44 | #define OUTCTR1 0x05 /* Output Control I */ | |
45 | #define ACNTL1 0x06 /* Analog Control Register 1 */ | |
46 | #define CROP_HI 0x07 /* Cropping Register, High */ | |
47 | #define VDELAY_LO 0x08 /* Vertical Delay Register, Low */ | |
48 | #define VACTIVE_LO 0x09 /* Vertical Active Register, Low */ | |
49 | #define HDELAY_LO 0x0A /* Horizontal Delay Register, Low */ | |
50 | #define HACTIVE_LO 0x0B /* Horizontal Active Register, Low */ | |
51 | #define CNTRL1 0x0C /* Control Register I */ | |
52 | #define VSCALE_LO 0x0D /* Vertical Scaling Register, Low */ | |
53 | #define SCALE_HI 0x0E /* Scaling Register, High */ | |
54 | #define HSCALE_LO 0x0F /* Horizontal Scaling Register, Low */ | |
55 | #define BRIGHT 0x10 /* BRIGHTNESS Control Register */ | |
56 | #define CONTRAST 0x11 /* CONTRAST Control Register */ | |
57 | #define SHARPNESS 0x12 /* SHARPNESS Control Register I */ | |
58 | #define SAT_U 0x13 /* Chroma (U) Gain Register */ | |
59 | #define SAT_V 0x14 /* Chroma (V) Gain Register */ | |
60 | #define HUE 0x15 /* Hue Control Register */ | |
61 | #define CORING1 0x17 | |
62 | #define CORING2 0x18 /* Coring and IF compensation */ | |
63 | #define VBICNTL 0x19 /* VBI Control Register */ | |
64 | #define ACNTL2 0x1A /* Analog Control 2 */ | |
65 | #define OUTCTR2 0x1B /* Output Control 2 */ | |
66 | #define SDT 0x1C /* Standard Selection */ | |
67 | #define SDTR 0x1D /* Standard Recognition */ | |
68 | #define TEST 0x1F /* Test Control Register */ | |
69 | #define CLMPG 0x20 /* Clamping Gain */ | |
70 | #define IAGC 0x21 /* Individual AGC Gain */ | |
71 | #define AGCGAIN 0x22 /* AGC Gain */ | |
72 | #define PEAKWT 0x23 /* White Peak Threshold */ | |
73 | #define CLMPL 0x24 /* Clamp level */ | |
74 | #define SYNCT 0x25 /* Sync Amplitude */ | |
75 | #define MISSCNT 0x26 /* Sync Miss Count Register */ | |
76 | #define PCLAMP 0x27 /* Clamp Position Register */ | |
77 | #define VCNTL1 0x28 /* Vertical Control I */ | |
78 | #define VCNTL2 0x29 /* Vertical Control II */ | |
79 | #define CKILL 0x2A /* Color Killer Level Control */ | |
80 | #define COMB 0x2B /* Comb Filter Control */ | |
81 | #define LDLY 0x2C /* Luma Delay and H Filter Control */ | |
82 | #define MISC1 0x2D /* Miscellaneous Control I */ | |
83 | #define LOOP 0x2E /* LOOP Control Register */ | |
84 | #define MISC2 0x2F /* Miscellaneous Control II */ | |
85 | #define MVSN 0x30 /* Macrovision Detection */ | |
86 | #define STATUS2 0x31 /* Chip STATUS II */ | |
87 | #define HFREF 0x32 /* H monitor */ | |
88 | #define CLMD 0x33 /* CLAMP MODE */ | |
89 | #define IDCNTL 0x34 /* ID Detection Control */ | |
90 | #define CLCNTL1 0x35 /* Clamp Control I */ | |
91 | #define ANAPLLCTL 0x4C | |
92 | #define VBIMIN 0x4D | |
93 | #define HSLOWCTL 0x4E | |
94 | #define WSS3 0x4F | |
95 | #define FILLDATA 0x50 | |
96 | #define SDID 0x51 | |
97 | #define DID 0x52 | |
98 | #define WSS1 0x53 | |
99 | #define WSS2 0x54 | |
100 | #define VVBI 0x55 | |
101 | #define LCTL6 0x56 | |
102 | #define LCTL7 0x57 | |
103 | #define LCTL8 0x58 | |
104 | #define LCTL9 0x59 | |
105 | #define LCTL10 0x5A | |
106 | #define LCTL11 0x5B | |
107 | #define LCTL12 0x5C | |
108 | #define LCTL13 0x5D | |
109 | #define LCTL14 0x5E | |
110 | #define LCTL15 0x5F | |
111 | #define LCTL16 0x60 | |
112 | #define LCTL17 0x61 | |
113 | #define LCTL18 0x62 | |
114 | #define LCTL19 0x63 | |
115 | #define LCTL20 0x64 | |
116 | #define LCTL21 0x65 | |
117 | #define LCTL22 0x66 | |
118 | #define LCTL23 0x67 | |
119 | #define LCTL24 0x68 | |
120 | #define LCTL25 0x69 | |
121 | #define LCTL26 0x6A | |
faa58261 | 122 | #define HSBEGIN 0x6B |
ed922a89 KM |
123 | #define HSEND 0x6C |
124 | #define OVSDLY 0x6D | |
125 | #define OVSEND 0x6E | |
126 | #define VBIDELAY 0x6F | |
127 | ||
128 | /* | |
129 | * register detail | |
130 | */ | |
131 | ||
132 | /* INFORM */ | |
133 | #define FC27_ON 0x40 /* 1 : Input crystal clock frequency is 27MHz */ | |
134 | #define FC27_FF 0x00 /* 0 : Square pixel mode. */ | |
135 | /* Must use 24.54MHz for 60Hz field rate */ | |
136 | /* source or 29.5MHz for 50Hz field rate */ | |
137 | #define IFSEL_S 0x10 /* 01 : S-video decoding */ | |
138 | #define IFSEL_C 0x00 /* 00 : Composite video decoding */ | |
139 | /* Y input video selection */ | |
140 | #define YSEL_M0 0x00 /* 00 : Mux0 selected */ | |
141 | #define YSEL_M1 0x04 /* 01 : Mux1 selected */ | |
142 | #define YSEL_M2 0x08 /* 10 : Mux2 selected */ | |
143 | #define YSEL_M3 0x10 /* 11 : Mux3 selected */ | |
144 | ||
145 | /* OPFORM */ | |
146 | #define MODE 0x80 /* 0 : CCIR601 compatible YCrCb 4:2:2 format */ | |
147 | /* 1 : ITU-R-656 compatible data sequence format */ | |
148 | #define LEN 0x40 /* 0 : 8-bit YCrCb 4:2:2 output format */ | |
149 | /* 1 : 16-bit YCrCb 4:2:2 output format.*/ | |
150 | #define LLCMODE 0x20 /* 1 : LLC output mode. */ | |
151 | /* 0 : free-run output mode */ | |
152 | #define AINC 0x10 /* Serial interface auto-indexing control */ | |
153 | /* 0 : auto-increment */ | |
154 | /* 1 : non-auto */ | |
155 | #define VSCTL 0x08 /* 1 : Vertical out ctrl by DVALID */ | |
156 | /* 0 : Vertical out ctrl by HACTIVE and DVALID */ | |
06f292e4 KM |
157 | #define OEN_TRI_SEL_MASK 0x07 |
158 | #define OEN_TRI_SEL_ALL_ON 0x00 /* Enable output for Rev0/Rev1 */ | |
159 | #define OEN_TRI_SEL_ALL_OFF_r0 0x06 /* All tri-stated for Rev0 */ | |
160 | #define OEN_TRI_SEL_ALL_OFF_r1 0x07 /* All tri-stated for Rev1 */ | |
ed922a89 KM |
161 | |
162 | /* OUTCTR1 */ | |
163 | #define VSP_LO 0x00 /* 0 : VS pin output polarity is active low */ | |
164 | #define VSP_HI 0x80 /* 1 : VS pin output polarity is active high. */ | |
165 | /* VS pin output control */ | |
166 | #define VSSL_VSYNC 0x00 /* 0 : VSYNC */ | |
167 | #define VSSL_VACT 0x10 /* 1 : VACT */ | |
168 | #define VSSL_FIELD 0x20 /* 2 : FIELD */ | |
169 | #define VSSL_VVALID 0x30 /* 3 : VVALID */ | |
170 | #define VSSL_ZERO 0x70 /* 7 : 0 */ | |
171 | #define HSP_LOW 0x00 /* 0 : HS pin output polarity is active low */ | |
172 | #define HSP_HI 0x08 /* 1 : HS pin output polarity is active high.*/ | |
173 | /* HS pin output control */ | |
174 | #define HSSL_HACT 0x00 /* 0 : HACT */ | |
175 | #define HSSL_HSYNC 0x01 /* 1 : HSYNC */ | |
176 | #define HSSL_DVALID 0x02 /* 2 : DVALID */ | |
177 | #define HSSL_HLOCK 0x03 /* 3 : HLOCK */ | |
178 | #define HSSL_ASYNCW 0x04 /* 4 : ASYNCW */ | |
179 | #define HSSL_ZERO 0x07 /* 7 : 0 */ | |
180 | ||
181 | /* ACNTL1 */ | |
182 | #define SRESET 0x80 /* resets the device to its default state | |
183 | * but all register content remain unchanged. | |
184 | * This bit is self-resetting. | |
185 | */ | |
607e5ad8 KM |
186 | #define ACNTL1_PDN_MASK 0x0e |
187 | #define CLK_PDN 0x08 /* system clock power down */ | |
188 | #define Y_PDN 0x04 /* Luma ADC power down */ | |
189 | #define C_PDN 0x02 /* Chroma ADC power down */ | |
190 | ||
191 | /* ACNTL2 */ | |
192 | #define ACNTL2_PDN_MASK 0x40 | |
193 | #define PLL_PDN 0x40 /* PLL power down */ | |
ed922a89 KM |
194 | |
195 | /* VBICNTL */ | |
5d28d525 GL |
196 | |
197 | /* RTSEL : control the real time signal output from the MPOUT pin */ | |
ed922a89 KM |
198 | #define RTSEL_MASK 0x07 |
199 | #define RTSEL_VLOSS 0x00 /* 0000 = Video loss */ | |
200 | #define RTSEL_HLOCK 0x01 /* 0001 = H-lock */ | |
201 | #define RTSEL_SLOCK 0x02 /* 0010 = S-lock */ | |
202 | #define RTSEL_VLOCK 0x03 /* 0011 = V-lock */ | |
203 | #define RTSEL_MONO 0x04 /* 0100 = MONO */ | |
204 | #define RTSEL_DET50 0x05 /* 0101 = DET50 */ | |
205 | #define RTSEL_FIELD 0x06 /* 0110 = FIELD */ | |
206 | #define RTSEL_RTCO 0x07 /* 0111 = RTCO ( Real Time Control ) */ | |
207 | ||
2ad90b71 GL |
208 | /* HSYNC start and end are constant for now */ |
209 | #define HSYNC_START 0x0260 | |
210 | #define HSYNC_END 0x0300 | |
211 | ||
ed922a89 KM |
212 | /* |
213 | * structure | |
214 | */ | |
215 | ||
216 | struct regval_list { | |
217 | unsigned char reg_num; | |
218 | unsigned char value; | |
219 | }; | |
220 | ||
221 | struct tw9910_scale_ctrl { | |
222 | char *name; | |
223 | unsigned short width; | |
224 | unsigned short height; | |
225 | u16 hscale; | |
226 | u16 vscale; | |
227 | }; | |
228 | ||
ed922a89 | 229 | struct tw9910_priv { |
906b1018 GL |
230 | struct v4l2_subdev subdev; |
231 | struct tw9910_video_info *info; | |
232 | const struct tw9910_scale_ctrl *scale; | |
2f0babb7 | 233 | v4l2_std_id norm; |
906b1018 | 234 | u32 revision; |
ed922a89 KM |
235 | }; |
236 | ||
ed922a89 KM |
237 | static const struct tw9910_scale_ctrl tw9910_ntsc_scales[] = { |
238 | { | |
239 | .name = "NTSC SQ", | |
240 | .width = 640, | |
241 | .height = 480, | |
242 | .hscale = 0x0100, | |
243 | .vscale = 0x0100, | |
244 | }, | |
245 | { | |
246 | .name = "NTSC CCIR601", | |
247 | .width = 720, | |
248 | .height = 480, | |
249 | .hscale = 0x0100, | |
250 | .vscale = 0x0100, | |
251 | }, | |
252 | { | |
253 | .name = "NTSC SQ (CIF)", | |
254 | .width = 320, | |
255 | .height = 240, | |
256 | .hscale = 0x0200, | |
257 | .vscale = 0x0200, | |
258 | }, | |
259 | { | |
260 | .name = "NTSC CCIR601 (CIF)", | |
261 | .width = 360, | |
262 | .height = 240, | |
263 | .hscale = 0x0200, | |
264 | .vscale = 0x0200, | |
265 | }, | |
266 | { | |
267 | .name = "NTSC SQ (QCIF)", | |
268 | .width = 160, | |
269 | .height = 120, | |
270 | .hscale = 0x0400, | |
271 | .vscale = 0x0400, | |
272 | }, | |
273 | { | |
274 | .name = "NTSC CCIR601 (QCIF)", | |
275 | .width = 180, | |
276 | .height = 120, | |
277 | .hscale = 0x0400, | |
278 | .vscale = 0x0400, | |
279 | }, | |
280 | }; | |
281 | ||
282 | static const struct tw9910_scale_ctrl tw9910_pal_scales[] = { | |
283 | { | |
284 | .name = "PAL SQ", | |
285 | .width = 768, | |
286 | .height = 576, | |
287 | .hscale = 0x0100, | |
288 | .vscale = 0x0100, | |
289 | }, | |
290 | { | |
291 | .name = "PAL CCIR601", | |
292 | .width = 720, | |
293 | .height = 576, | |
294 | .hscale = 0x0100, | |
295 | .vscale = 0x0100, | |
296 | }, | |
297 | { | |
298 | .name = "PAL SQ (CIF)", | |
299 | .width = 384, | |
300 | .height = 288, | |
301 | .hscale = 0x0200, | |
302 | .vscale = 0x0200, | |
303 | }, | |
304 | { | |
305 | .name = "PAL CCIR601 (CIF)", | |
306 | .width = 360, | |
307 | .height = 288, | |
308 | .hscale = 0x0200, | |
309 | .vscale = 0x0200, | |
310 | }, | |
311 | { | |
312 | .name = "PAL SQ (QCIF)", | |
313 | .width = 192, | |
314 | .height = 144, | |
315 | .hscale = 0x0400, | |
316 | .vscale = 0x0400, | |
317 | }, | |
318 | { | |
319 | .name = "PAL CCIR601 (QCIF)", | |
320 | .width = 180, | |
321 | .height = 144, | |
322 | .hscale = 0x0400, | |
323 | .vscale = 0x0400, | |
324 | }, | |
325 | }; | |
326 | ||
ed922a89 KM |
327 | /* |
328 | * general function | |
329 | */ | |
979ea1dd GL |
330 | static struct tw9910_priv *to_tw9910(const struct i2c_client *client) |
331 | { | |
96c75399 GL |
332 | return container_of(i2c_get_clientdata(client), struct tw9910_priv, |
333 | subdev); | |
979ea1dd GL |
334 | } |
335 | ||
20797083 KM |
336 | static int tw9910_mask_set(struct i2c_client *client, u8 command, |
337 | u8 mask, u8 set) | |
338 | { | |
339 | s32 val = i2c_smbus_read_byte_data(client, command); | |
340 | if (val < 0) | |
341 | return val; | |
342 | ||
343 | val &= ~mask; | |
344 | val |= set & mask; | |
345 | ||
346 | return i2c_smbus_write_byte_data(client, command, val); | |
347 | } | |
348 | ||
ed922a89 KM |
349 | static int tw9910_set_scale(struct i2c_client *client, |
350 | const struct tw9910_scale_ctrl *scale) | |
351 | { | |
352 | int ret; | |
353 | ||
354 | ret = i2c_smbus_write_byte_data(client, SCALE_HI, | |
355 | (scale->vscale & 0x0F00) >> 4 | | |
356 | (scale->hscale & 0x0F00) >> 8); | |
357 | if (ret < 0) | |
358 | return ret; | |
359 | ||
360 | ret = i2c_smbus_write_byte_data(client, HSCALE_LO, | |
361 | scale->hscale & 0x00FF); | |
362 | if (ret < 0) | |
363 | return ret; | |
364 | ||
365 | ret = i2c_smbus_write_byte_data(client, VSCALE_LO, | |
366 | scale->vscale & 0x00FF); | |
367 | ||
368 | return ret; | |
369 | } | |
370 | ||
2ad90b71 | 371 | static int tw9910_set_hsync(struct i2c_client *client) |
ed922a89 | 372 | { |
faa58261 | 373 | struct tw9910_priv *priv = to_tw9910(client); |
ed922a89 KM |
374 | int ret; |
375 | ||
376 | /* bit 10 - 3 */ | |
faa58261 | 377 | ret = i2c_smbus_write_byte_data(client, HSBEGIN, |
2ad90b71 | 378 | (HSYNC_START & 0x07F8) >> 3); |
ed922a89 KM |
379 | if (ret < 0) |
380 | return ret; | |
381 | ||
382 | /* bit 10 - 3 */ | |
383 | ret = i2c_smbus_write_byte_data(client, HSEND, | |
2ad90b71 | 384 | (HSYNC_END & 0x07F8) >> 3); |
ed922a89 KM |
385 | if (ret < 0) |
386 | return ret; | |
387 | ||
faa58261 | 388 | /* So far only revisions 0 and 1 have been seen */ |
ed922a89 | 389 | /* bit 2 - 0 */ |
faa58261 KM |
390 | if (1 == priv->revision) |
391 | ret = tw9910_mask_set(client, HSLOWCTL, 0x77, | |
2ad90b71 GL |
392 | (HSYNC_START & 0x0007) << 4 | |
393 | (HSYNC_END & 0x0007)); | |
ed922a89 KM |
394 | |
395 | return ret; | |
396 | } | |
397 | ||
ed922a89 KM |
398 | static void tw9910_reset(struct i2c_client *client) |
399 | { | |
607e5ad8 | 400 | tw9910_mask_set(client, ACNTL1, SRESET, SRESET); |
ed922a89 KM |
401 | msleep(1); |
402 | } | |
403 | ||
607e5ad8 KM |
404 | static int tw9910_power(struct i2c_client *client, int enable) |
405 | { | |
406 | int ret; | |
407 | u8 acntl1; | |
408 | u8 acntl2; | |
409 | ||
410 | if (enable) { | |
411 | acntl1 = 0; | |
412 | acntl2 = 0; | |
413 | } else { | |
414 | acntl1 = CLK_PDN | Y_PDN | C_PDN; | |
415 | acntl2 = PLL_PDN; | |
416 | } | |
417 | ||
418 | ret = tw9910_mask_set(client, ACNTL1, ACNTL1_PDN_MASK, acntl1); | |
419 | if (ret < 0) | |
420 | return ret; | |
421 | ||
422 | return tw9910_mask_set(client, ACNTL2, ACNTL2_PDN_MASK, acntl2); | |
423 | } | |
424 | ||
2f0babb7 | 425 | static const struct tw9910_scale_ctrl *tw9910_select_norm(v4l2_std_id norm, |
2ad90b71 | 426 | u32 width, u32 height) |
ed922a89 KM |
427 | { |
428 | const struct tw9910_scale_ctrl *scale; | |
429 | const struct tw9910_scale_ctrl *ret = NULL; | |
ed922a89 KM |
430 | __u32 diff = 0xffffffff, tmp; |
431 | int size, i; | |
432 | ||
433 | if (norm & V4L2_STD_NTSC) { | |
434 | scale = tw9910_ntsc_scales; | |
435 | size = ARRAY_SIZE(tw9910_ntsc_scales); | |
436 | } else if (norm & V4L2_STD_PAL) { | |
437 | scale = tw9910_pal_scales; | |
438 | size = ARRAY_SIZE(tw9910_pal_scales); | |
439 | } else { | |
440 | return NULL; | |
441 | } | |
442 | ||
443 | for (i = 0; i < size; i++) { | |
444 | tmp = abs(width - scale[i].width) + | |
445 | abs(height - scale[i].height); | |
446 | if (tmp < diff) { | |
447 | diff = tmp; | |
448 | ret = scale + i; | |
449 | } | |
450 | } | |
451 | ||
452 | return ret; | |
453 | } | |
454 | ||
455 | /* | |
5476ea8d | 456 | * subdevice operations |
ed922a89 | 457 | */ |
979ea1dd | 458 | static int tw9910_s_stream(struct v4l2_subdev *sd, int enable) |
ed922a89 | 459 | { |
c4ce6d14 | 460 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
979ea1dd | 461 | struct tw9910_priv *priv = to_tw9910(client); |
06f292e4 | 462 | u8 val; |
607e5ad8 | 463 | int ret; |
06f292e4 KM |
464 | |
465 | if (!enable) { | |
466 | switch (priv->revision) { | |
467 | case 0: | |
468 | val = OEN_TRI_SEL_ALL_OFF_r0; | |
469 | break; | |
470 | case 1: | |
471 | val = OEN_TRI_SEL_ALL_OFF_r1; | |
472 | break; | |
473 | default: | |
474 | dev_err(&client->dev, "un-supported revision\n"); | |
475 | return -EINVAL; | |
476 | } | |
477 | } else { | |
478 | val = OEN_TRI_SEL_ALL_ON; | |
ed922a89 | 479 | |
06f292e4 KM |
480 | if (!priv->scale) { |
481 | dev_err(&client->dev, "norm select error\n"); | |
482 | return -EPERM; | |
483 | } | |
ed922a89 | 484 | |
06f292e4 KM |
485 | dev_dbg(&client->dev, "%s %dx%d\n", |
486 | priv->scale->name, | |
487 | priv->scale->width, | |
488 | priv->scale->height); | |
489 | } | |
ed922a89 | 490 | |
607e5ad8 KM |
491 | ret = tw9910_mask_set(client, OPFORM, OEN_TRI_SEL_MASK, val); |
492 | if (ret < 0) | |
493 | return ret; | |
494 | ||
495 | return tw9910_power(client, enable); | |
ed922a89 KM |
496 | } |
497 | ||
2f0babb7 GL |
498 | static int tw9910_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) |
499 | { | |
500 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
501 | struct tw9910_priv *priv = to_tw9910(client); | |
502 | ||
503 | *norm = priv->norm; | |
504 | ||
505 | return 0; | |
506 | } | |
507 | ||
979ea1dd | 508 | static int tw9910_s_std(struct v4l2_subdev *sd, v4l2_std_id norm) |
ed922a89 | 509 | { |
2f0babb7 GL |
510 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
511 | struct tw9910_priv *priv = to_tw9910(client); | |
ed922a89 | 512 | |
2f0babb7 GL |
513 | if (!(norm & (V4L2_STD_NTSC | V4L2_STD_PAL))) |
514 | return -EINVAL; | |
ed922a89 | 515 | |
2f0babb7 GL |
516 | priv->norm = norm; |
517 | ||
518 | return 0; | |
ed922a89 KM |
519 | } |
520 | ||
979ea1dd GL |
521 | static int tw9910_g_chip_ident(struct v4l2_subdev *sd, |
522 | struct v4l2_dbg_chip_ident *id) | |
523 | { | |
c4ce6d14 | 524 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
6d74e5f3 KM |
525 | struct tw9910_priv *priv = to_tw9910(client); |
526 | ||
979ea1dd | 527 | id->ident = V4L2_IDENT_TW9910; |
6d74e5f3 | 528 | id->revision = priv->revision; |
979ea1dd GL |
529 | |
530 | return 0; | |
531 | } | |
532 | ||
ed922a89 | 533 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
979ea1dd GL |
534 | static int tw9910_g_register(struct v4l2_subdev *sd, |
535 | struct v4l2_dbg_register *reg) | |
ed922a89 | 536 | { |
c4ce6d14 | 537 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
ed922a89 KM |
538 | int ret; |
539 | ||
540 | if (reg->reg > 0xff) | |
541 | return -EINVAL; | |
542 | ||
40e2e092 | 543 | ret = i2c_smbus_read_byte_data(client, reg->reg); |
ed922a89 KM |
544 | if (ret < 0) |
545 | return ret; | |
546 | ||
5d28d525 GL |
547 | /* |
548 | * ret = int | |
ed922a89 KM |
549 | * reg->val = __u64 |
550 | */ | |
551 | reg->val = (__u64)ret; | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
979ea1dd GL |
556 | static int tw9910_s_register(struct v4l2_subdev *sd, |
557 | struct v4l2_dbg_register *reg) | |
ed922a89 | 558 | { |
c4ce6d14 | 559 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
ed922a89 KM |
560 | |
561 | if (reg->reg > 0xff || | |
562 | reg->val > 0xff) | |
563 | return -EINVAL; | |
564 | ||
40e2e092 | 565 | return i2c_smbus_write_byte_data(client, reg->reg, reg->val); |
ed922a89 KM |
566 | } |
567 | #endif | |
568 | ||
2ad90b71 | 569 | static int tw9910_set_frame(struct v4l2_subdev *sd, u32 *width, u32 *height) |
ed922a89 | 570 | { |
c4ce6d14 | 571 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
979ea1dd | 572 | struct tw9910_priv *priv = to_tw9910(client); |
2ad90b71 GL |
573 | int ret = -EINVAL; |
574 | u8 val; | |
ed922a89 KM |
575 | |
576 | /* | |
577 | * select suitable norm | |
578 | */ | |
2f0babb7 | 579 | priv->scale = tw9910_select_norm(priv->norm, *width, *height); |
ed922a89 | 580 | if (!priv->scale) |
6d756112 | 581 | goto tw9910_set_fmt_error; |
ed922a89 KM |
582 | |
583 | /* | |
584 | * reset hardware | |
585 | */ | |
40e2e092 | 586 | tw9910_reset(client); |
6d756112 | 587 | |
ed922a89 KM |
588 | /* |
589 | * set bus width | |
590 | */ | |
591 | val = 0x00; | |
592 | if (SOCAM_DATAWIDTH_16 == priv->info->buswidth) | |
593 | val = LEN; | |
594 | ||
40e2e092 | 595 | ret = tw9910_mask_set(client, OPFORM, LEN, val); |
ed922a89 | 596 | if (ret < 0) |
6d756112 | 597 | goto tw9910_set_fmt_error; |
ed922a89 KM |
598 | |
599 | /* | |
600 | * select MPOUT behavior | |
601 | */ | |
602 | switch (priv->info->mpout) { | |
603 | case TW9910_MPO_VLOSS: | |
604 | val = RTSEL_VLOSS; break; | |
605 | case TW9910_MPO_HLOCK: | |
606 | val = RTSEL_HLOCK; break; | |
607 | case TW9910_MPO_SLOCK: | |
608 | val = RTSEL_SLOCK; break; | |
609 | case TW9910_MPO_VLOCK: | |
610 | val = RTSEL_VLOCK; break; | |
611 | case TW9910_MPO_MONO: | |
612 | val = RTSEL_MONO; break; | |
613 | case TW9910_MPO_DET50: | |
614 | val = RTSEL_DET50; break; | |
615 | case TW9910_MPO_FIELD: | |
616 | val = RTSEL_FIELD; break; | |
617 | case TW9910_MPO_RTCO: | |
618 | val = RTSEL_RTCO; break; | |
619 | default: | |
620 | val = 0; | |
621 | } | |
622 | ||
40e2e092 | 623 | ret = tw9910_mask_set(client, VBICNTL, RTSEL_MASK, val); |
ed922a89 | 624 | if (ret < 0) |
6d756112 | 625 | goto tw9910_set_fmt_error; |
ed922a89 KM |
626 | |
627 | /* | |
628 | * set scale | |
629 | */ | |
40e2e092 | 630 | ret = tw9910_set_scale(client, priv->scale); |
ed922a89 | 631 | if (ret < 0) |
6d756112 | 632 | goto tw9910_set_fmt_error; |
ed922a89 | 633 | |
ed922a89 KM |
634 | /* |
635 | * set hsync | |
636 | */ | |
2ad90b71 | 637 | ret = tw9910_set_hsync(client); |
6d756112 KM |
638 | if (ret < 0) |
639 | goto tw9910_set_fmt_error; | |
640 | ||
2ad90b71 GL |
641 | *width = priv->scale->width; |
642 | *height = priv->scale->height; | |
123ab622 | 643 | |
6d756112 KM |
644 | return ret; |
645 | ||
646 | tw9910_set_fmt_error: | |
647 | ||
40e2e092 | 648 | tw9910_reset(client); |
6d756112 | 649 | priv->scale = NULL; |
ed922a89 KM |
650 | |
651 | return ret; | |
652 | } | |
653 | ||
6a6c8786 GL |
654 | static int tw9910_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) |
655 | { | |
c4ce6d14 | 656 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2f0babb7 | 657 | struct tw9910_priv *priv = to_tw9910(client); |
6a6c8786 GL |
658 | |
659 | a->c.left = 0; | |
660 | a->c.top = 0; | |
2f0babb7 | 661 | if (priv->norm & V4L2_STD_NTSC) { |
2ad90b71 GL |
662 | a->c.width = 640; |
663 | a->c.height = 480; | |
664 | } else { | |
665 | a->c.width = 768; | |
666 | a->c.height = 576; | |
667 | } | |
6a6c8786 GL |
668 | a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
669 | ||
670 | return 0; | |
671 | } | |
672 | ||
673 | static int tw9910_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a) | |
674 | { | |
2ad90b71 | 675 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2f0babb7 | 676 | struct tw9910_priv *priv = to_tw9910(client); |
2ad90b71 | 677 | |
6a6c8786 GL |
678 | a->bounds.left = 0; |
679 | a->bounds.top = 0; | |
2f0babb7 | 680 | if (priv->norm & V4L2_STD_NTSC) { |
2ad90b71 GL |
681 | a->bounds.width = 640; |
682 | a->bounds.height = 480; | |
683 | } else { | |
684 | a->bounds.width = 768; | |
685 | a->bounds.height = 576; | |
686 | } | |
687 | a->defrect = a->bounds; | |
6a6c8786 GL |
688 | a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
689 | a->pixelaspect.numerator = 1; | |
690 | a->pixelaspect.denominator = 1; | |
691 | ||
692 | return 0; | |
693 | } | |
694 | ||
760697be GL |
695 | static int tw9910_g_fmt(struct v4l2_subdev *sd, |
696 | struct v4l2_mbus_framefmt *mf) | |
6a6c8786 | 697 | { |
c4ce6d14 | 698 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
6a6c8786 | 699 | struct tw9910_priv *priv = to_tw9910(client); |
6a6c8786 GL |
700 | |
701 | if (!priv->scale) { | |
702 | int ret; | |
2ad90b71 GL |
703 | u32 width = 640, height = 480; |
704 | ret = tw9910_set_frame(sd, &width, &height); | |
6a6c8786 GL |
705 | if (ret < 0) |
706 | return ret; | |
707 | } | |
708 | ||
760697be GL |
709 | mf->width = priv->scale->width; |
710 | mf->height = priv->scale->height; | |
ace6e979 | 711 | mf->code = V4L2_MBUS_FMT_UYVY8_2X8; |
760697be | 712 | mf->colorspace = V4L2_COLORSPACE_JPEG; |
34cae30b | 713 | mf->field = V4L2_FIELD_INTERLACED_BT; |
6a6c8786 GL |
714 | |
715 | return 0; | |
716 | } | |
717 | ||
760697be GL |
718 | static int tw9910_s_fmt(struct v4l2_subdev *sd, |
719 | struct v4l2_mbus_framefmt *mf) | |
09e231b3 | 720 | { |
2ad90b71 | 721 | u32 width = mf->width, height = mf->height; |
760697be GL |
722 | int ret; |
723 | ||
724 | WARN_ON(mf->field != V4L2_FIELD_ANY && | |
34cae30b | 725 | mf->field != V4L2_FIELD_INTERLACED_BT); |
09e231b3 GL |
726 | |
727 | /* | |
728 | * check color format | |
729 | */ | |
ace6e979 | 730 | if (mf->code != V4L2_MBUS_FMT_UYVY8_2X8) |
09e231b3 GL |
731 | return -EINVAL; |
732 | ||
760697be GL |
733 | mf->colorspace = V4L2_COLORSPACE_JPEG; |
734 | ||
2ad90b71 | 735 | ret = tw9910_set_frame(sd, &width, &height); |
123ab622 | 736 | if (!ret) { |
2ad90b71 GL |
737 | mf->width = width; |
738 | mf->height = height; | |
123ab622 GL |
739 | } |
740 | return ret; | |
09e231b3 GL |
741 | } |
742 | ||
760697be GL |
743 | static int tw9910_try_fmt(struct v4l2_subdev *sd, |
744 | struct v4l2_mbus_framefmt *mf) | |
ed922a89 | 745 | { |
c4ce6d14 | 746 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2f0babb7 | 747 | struct tw9910_priv *priv = to_tw9910(client); |
ed922a89 KM |
748 | const struct tw9910_scale_ctrl *scale; |
749 | ||
760697be | 750 | if (V4L2_FIELD_ANY == mf->field) { |
34cae30b KM |
751 | mf->field = V4L2_FIELD_INTERLACED_BT; |
752 | } else if (V4L2_FIELD_INTERLACED_BT != mf->field) { | |
760697be | 753 | dev_err(&client->dev, "Field type %d invalid.\n", mf->field); |
ed922a89 KM |
754 | return -EINVAL; |
755 | } | |
756 | ||
ace6e979 | 757 | mf->code = V4L2_MBUS_FMT_UYVY8_2X8; |
760697be GL |
758 | mf->colorspace = V4L2_COLORSPACE_JPEG; |
759 | ||
ed922a89 KM |
760 | /* |
761 | * select suitable norm | |
762 | */ | |
2f0babb7 | 763 | scale = tw9910_select_norm(priv->norm, mf->width, mf->height); |
ed922a89 KM |
764 | if (!scale) |
765 | return -EINVAL; | |
766 | ||
760697be GL |
767 | mf->width = scale->width; |
768 | mf->height = scale->height; | |
ed922a89 KM |
769 | |
770 | return 0; | |
771 | } | |
772 | ||
2f0babb7 | 773 | static int tw9910_video_probe(struct i2c_client *client) |
ed922a89 | 774 | { |
979ea1dd | 775 | struct tw9910_priv *priv = to_tw9910(client); |
88a67c51 | 776 | s32 id; |
ed922a89 | 777 | |
ed922a89 KM |
778 | /* |
779 | * tw9910 only use 8 or 16 bit bus width | |
780 | */ | |
781 | if (SOCAM_DATAWIDTH_16 != priv->info->buswidth && | |
782 | SOCAM_DATAWIDTH_8 != priv->info->buswidth) { | |
85f8be68 | 783 | dev_err(&client->dev, "bus width error\n"); |
ed922a89 KM |
784 | return -ENODEV; |
785 | } | |
786 | ||
ed922a89 KM |
787 | /* |
788 | * check and show Product ID | |
4a4bc5e4 | 789 | * So far only revisions 0 and 1 have been seen |
ed922a89 | 790 | */ |
88a67c51 KM |
791 | id = i2c_smbus_read_byte_data(client, ID); |
792 | priv->revision = GET_REV(id); | |
793 | id = GET_ID(id); | |
40e2e092 | 794 | |
88a67c51 | 795 | if (0x0B != id || |
6d74e5f3 | 796 | 0x01 < priv->revision) { |
85f8be68 | 797 | dev_err(&client->dev, |
6d74e5f3 | 798 | "Product ID error %x:%x\n", |
88a67c51 | 799 | id, priv->revision); |
ed922a89 KM |
800 | return -ENODEV; |
801 | } | |
802 | ||
85f8be68 | 803 | dev_info(&client->dev, |
88a67c51 | 804 | "tw9910 Product ID %0x:%0x\n", id, priv->revision); |
ed922a89 | 805 | |
2f0babb7 | 806 | priv->norm = V4L2_STD_NTSC; |
ed922a89 | 807 | |
979ea1dd | 808 | return 0; |
ed922a89 KM |
809 | } |
810 | ||
979ea1dd GL |
811 | static struct v4l2_subdev_core_ops tw9910_subdev_core_ops = { |
812 | .g_chip_ident = tw9910_g_chip_ident, | |
813 | .s_std = tw9910_s_std, | |
2f0babb7 | 814 | .g_std = tw9910_g_std, |
ed922a89 | 815 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
979ea1dd GL |
816 | .g_register = tw9910_g_register, |
817 | .s_register = tw9910_s_register, | |
ed922a89 KM |
818 | #endif |
819 | }; | |
820 | ||
3805f201 | 821 | static int tw9910_enum_fmt(struct v4l2_subdev *sd, unsigned int index, |
760697be GL |
822 | enum v4l2_mbus_pixelcode *code) |
823 | { | |
824 | if (index) | |
825 | return -EINVAL; | |
826 | ||
ace6e979 | 827 | *code = V4L2_MBUS_FMT_UYVY8_2X8; |
760697be GL |
828 | return 0; |
829 | } | |
830 | ||
0d3263f9 GL |
831 | static int tw9910_g_mbus_config(struct v4l2_subdev *sd, |
832 | struct v4l2_mbus_config *cfg) | |
833 | { | |
834 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
14178aa5 | 835 | struct soc_camera_link *icl = soc_camera_i2c_to_link(client); |
0d3263f9 GL |
836 | |
837 | cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER | | |
838 | V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW | | |
839 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW | | |
840 | V4L2_MBUS_DATA_ACTIVE_HIGH; | |
841 | cfg->type = V4L2_MBUS_PARALLEL; | |
842 | cfg->flags = soc_camera_apply_board_flags(icl, cfg); | |
843 | ||
844 | return 0; | |
845 | } | |
846 | ||
847 | static int tw9910_s_mbus_config(struct v4l2_subdev *sd, | |
848 | const struct v4l2_mbus_config *cfg) | |
849 | { | |
850 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
14178aa5 | 851 | struct soc_camera_link *icl = soc_camera_i2c_to_link(client); |
0d3263f9 GL |
852 | u8 val = VSSL_VVALID | HSSL_DVALID; |
853 | unsigned long flags = soc_camera_apply_board_flags(icl, cfg); | |
854 | ||
855 | /* | |
856 | * set OUTCTR1 | |
857 | * | |
858 | * We use VVALID and DVALID signals to control VSYNC and HSYNC | |
859 | * outputs, in this mode their polarity is inverted. | |
860 | */ | |
861 | if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) | |
862 | val |= HSP_HI; | |
863 | ||
864 | if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) | |
865 | val |= VSP_HI; | |
866 | ||
867 | return i2c_smbus_write_byte_data(client, OUTCTR1, val); | |
868 | } | |
869 | ||
979ea1dd GL |
870 | static struct v4l2_subdev_video_ops tw9910_subdev_video_ops = { |
871 | .s_stream = tw9910_s_stream, | |
760697be GL |
872 | .g_mbus_fmt = tw9910_g_fmt, |
873 | .s_mbus_fmt = tw9910_s_fmt, | |
874 | .try_mbus_fmt = tw9910_try_fmt, | |
6a6c8786 GL |
875 | .cropcap = tw9910_cropcap, |
876 | .g_crop = tw9910_g_crop, | |
760697be | 877 | .enum_mbus_fmt = tw9910_enum_fmt, |
0d3263f9 GL |
878 | .g_mbus_config = tw9910_g_mbus_config, |
879 | .s_mbus_config = tw9910_s_mbus_config, | |
979ea1dd GL |
880 | }; |
881 | ||
882 | static struct v4l2_subdev_ops tw9910_subdev_ops = { | |
883 | .core = &tw9910_subdev_core_ops, | |
884 | .video = &tw9910_subdev_video_ops, | |
885 | }; | |
886 | ||
ed922a89 KM |
887 | /* |
888 | * i2c_driver function | |
889 | */ | |
890 | ||
891 | static int tw9910_probe(struct i2c_client *client, | |
892 | const struct i2c_device_id *did) | |
893 | ||
894 | { | |
14178aa5 GL |
895 | struct tw9910_priv *priv; |
896 | struct tw9910_video_info *info; | |
14178aa5 | 897 | struct i2c_adapter *adapter = |
40e2e092 | 898 | to_i2c_adapter(client->dev.parent); |
14178aa5 GL |
899 | struct soc_camera_link *icl = soc_camera_i2c_to_link(client); |
900 | int ret; | |
ed922a89 | 901 | |
14178aa5 GL |
902 | if (!icl || !icl->priv) { |
903 | dev_err(&client->dev, "TW9910: missing platform data!\n"); | |
ed922a89 | 904 | return -EINVAL; |
40e2e092 | 905 | } |
ed922a89 | 906 | |
0f448294 | 907 | info = icl->priv; |
40e2e092 GL |
908 | |
909 | if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { | |
ed922a89 KM |
910 | dev_err(&client->dev, |
911 | "I2C-Adapter doesn't support " | |
912 | "I2C_FUNC_SMBUS_BYTE_DATA\n"); | |
913 | return -EIO; | |
914 | } | |
915 | ||
916 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
917 | if (!priv) | |
918 | return -ENOMEM; | |
919 | ||
920 | priv->info = info; | |
979ea1dd GL |
921 | |
922 | v4l2_i2c_subdev_init(&priv->subdev, client, &tw9910_subdev_ops); | |
ed922a89 | 923 | |
2f0babb7 | 924 | ret = tw9910_video_probe(client); |
5476ea8d | 925 | if (ret) |
ed922a89 | 926 | kfree(priv); |
ed922a89 KM |
927 | |
928 | return ret; | |
929 | } | |
930 | ||
931 | static int tw9910_remove(struct i2c_client *client) | |
932 | { | |
979ea1dd | 933 | struct tw9910_priv *priv = to_tw9910(client); |
ed922a89 | 934 | |
ed922a89 KM |
935 | kfree(priv); |
936 | return 0; | |
937 | } | |
938 | ||
939 | static const struct i2c_device_id tw9910_id[] = { | |
940 | { "tw9910", 0 }, | |
941 | { } | |
942 | }; | |
943 | MODULE_DEVICE_TABLE(i2c, tw9910_id); | |
944 | ||
945 | static struct i2c_driver tw9910_i2c_driver = { | |
946 | .driver = { | |
947 | .name = "tw9910", | |
948 | }, | |
949 | .probe = tw9910_probe, | |
950 | .remove = tw9910_remove, | |
951 | .id_table = tw9910_id, | |
952 | }; | |
953 | ||
954 | /* | |
955 | * module function | |
956 | */ | |
957 | static int __init tw9910_module_init(void) | |
958 | { | |
959 | return i2c_add_driver(&tw9910_i2c_driver); | |
960 | } | |
961 | ||
962 | static void __exit tw9910_module_exit(void) | |
963 | { | |
964 | i2c_del_driver(&tw9910_i2c_driver); | |
965 | } | |
966 | ||
967 | module_init(tw9910_module_init); | |
968 | module_exit(tw9910_module_exit); | |
969 | ||
970 | MODULE_DESCRIPTION("SoC Camera driver for tw9910"); | |
971 | MODULE_AUTHOR("Kuninori Morimoto"); | |
972 | MODULE_LICENSE("GPL v2"); |