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7ec94453 A |
1 | /* |
2 | * EMIF driver | |
3 | * | |
4 | * Copyright (C) 2012 Texas Instruments, Inc. | |
5 | * | |
6 | * Aneesh V <aneesh@ti.com> | |
7 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/reboot.h> | |
15 | #include <linux/platform_data/emif_plat.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/device.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/seq_file.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/list.h> | |
a93de288 | 24 | #include <linux/spinlock.h> |
7ec94453 A |
25 | #include <memory/jedec_ddr.h> |
26 | #include "emif.h" | |
27 | ||
28 | /** | |
29 | * struct emif_data - Per device static data for driver's use | |
30 | * @duplicate: Whether the DDR devices attached to this EMIF | |
31 | * instance are exactly same as that on EMIF1. In | |
32 | * this case we can save some memory and processing | |
33 | * @temperature_level: Maximum temperature of LPDDR2 devices attached | |
34 | * to this EMIF - read from MR4 register. If there | |
35 | * are two devices attached to this EMIF, this | |
36 | * value is the maximum of the two temperature | |
37 | * levels. | |
38 | * @node: node in the device list | |
39 | * @base: base address of memory-mapped IO registers. | |
40 | * @dev: device pointer. | |
a93de288 A |
41 | * @addressing table with addressing information from the spec |
42 | * @regs_cache: An array of 'struct emif_regs' that stores | |
43 | * calculated register values for different | |
44 | * frequencies, to avoid re-calculating them on | |
45 | * each DVFS transition. | |
46 | * @curr_regs: The set of register values used in the last | |
47 | * frequency change (i.e. corresponding to the | |
48 | * frequency in effect at the moment) | |
7ec94453 A |
49 | * @plat_data: Pointer to saved platform data. |
50 | */ | |
51 | struct emif_data { | |
52 | u8 duplicate; | |
53 | u8 temperature_level; | |
a93de288 | 54 | u8 lpmode; |
7ec94453 | 55 | struct list_head node; |
a93de288 | 56 | unsigned long irq_state; |
7ec94453 A |
57 | void __iomem *base; |
58 | struct device *dev; | |
a93de288 A |
59 | const struct lpddr2_addressing *addressing; |
60 | struct emif_regs *regs_cache[EMIF_MAX_NUM_FREQUENCIES]; | |
61 | struct emif_regs *curr_regs; | |
7ec94453 A |
62 | struct emif_platform_data *plat_data; |
63 | }; | |
64 | ||
65 | static struct emif_data *emif1; | |
a93de288 A |
66 | static spinlock_t emif_lock; |
67 | static unsigned long irq_state; | |
68 | static u32 t_ck; /* DDR clock period in ps */ | |
7ec94453 A |
69 | static LIST_HEAD(device_list); |
70 | ||
a93de288 A |
71 | /* |
72 | * Calculate the period of DDR clock from frequency value | |
73 | */ | |
74 | static void set_ddr_clk_period(u32 freq) | |
75 | { | |
76 | /* Divide 10^12 by frequency to get period in ps */ | |
77 | t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq); | |
78 | } | |
79 | ||
98231c4f A |
80 | /* |
81 | * Get bus width used by EMIF. Note that this may be different from the | |
82 | * bus width of the DDR devices used. For instance two 16-bit DDR devices | |
83 | * may be connected to a given CS of EMIF. In this case bus width as far | |
84 | * as EMIF is concerned is 32, where as the DDR bus width is 16 bits. | |
85 | */ | |
86 | static u32 get_emif_bus_width(struct emif_data *emif) | |
87 | { | |
88 | u32 width; | |
89 | void __iomem *base = emif->base; | |
90 | ||
91 | width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK) | |
92 | >> NARROW_MODE_SHIFT; | |
93 | width = width == 0 ? 32 : 16; | |
94 | ||
95 | return width; | |
96 | } | |
97 | ||
a93de288 A |
98 | /* |
99 | * Get the CL from SDRAM_CONFIG register | |
100 | */ | |
101 | static u32 get_cl(struct emif_data *emif) | |
102 | { | |
103 | u32 cl; | |
104 | void __iomem *base = emif->base; | |
105 | ||
106 | cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT; | |
107 | ||
108 | return cl; | |
109 | } | |
110 | ||
111 | static void set_lpmode(struct emif_data *emif, u8 lpmode) | |
112 | { | |
113 | u32 temp; | |
114 | void __iomem *base = emif->base; | |
115 | ||
116 | temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL); | |
117 | temp &= ~LP_MODE_MASK; | |
118 | temp |= (lpmode << LP_MODE_SHIFT); | |
119 | writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL); | |
120 | } | |
121 | ||
122 | static void do_freq_update(void) | |
123 | { | |
124 | struct emif_data *emif; | |
125 | ||
126 | /* | |
127 | * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE | |
128 | * | |
129 | * i728 DESCRIPTION: | |
130 | * The EMIF automatically puts the SDRAM into self-refresh mode | |
131 | * after the EMIF has not performed accesses during | |
132 | * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles | |
133 | * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set | |
134 | * to 0x2. If during a small window the following three events | |
135 | * occur: | |
136 | * - The SR_TIMING counter expires | |
137 | * - And frequency change is requested | |
138 | * - And OCP access is requested | |
139 | * Then it causes instable clock on the DDR interface. | |
140 | * | |
141 | * WORKAROUND | |
142 | * To avoid the occurrence of the three events, the workaround | |
143 | * is to disable the self-refresh when requesting a frequency | |
144 | * change. Before requesting a frequency change the software must | |
145 | * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the | |
146 | * frequency change has been done, the software can reprogram | |
147 | * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2 | |
148 | */ | |
149 | list_for_each_entry(emif, &device_list, node) { | |
150 | if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) | |
151 | set_lpmode(emif, EMIF_LP_MODE_DISABLE); | |
152 | } | |
153 | ||
154 | /* | |
155 | * TODO: Do FREQ_UPDATE here when an API | |
156 | * is available for this as part of the new | |
157 | * clock framework | |
158 | */ | |
159 | ||
160 | list_for_each_entry(emif, &device_list, node) { | |
161 | if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) | |
162 | set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH); | |
163 | } | |
164 | } | |
165 | ||
166 | /* Find addressing table entry based on the device's type and density */ | |
167 | static const struct lpddr2_addressing *get_addressing_table( | |
168 | const struct ddr_device_info *device_info) | |
169 | { | |
170 | u32 index, type, density; | |
171 | ||
172 | type = device_info->type; | |
173 | density = device_info->density; | |
174 | ||
175 | switch (type) { | |
176 | case DDR_TYPE_LPDDR2_S4: | |
177 | index = density - 1; | |
178 | break; | |
179 | case DDR_TYPE_LPDDR2_S2: | |
180 | switch (density) { | |
181 | case DDR_DENSITY_1Gb: | |
182 | case DDR_DENSITY_2Gb: | |
183 | index = density + 3; | |
184 | break; | |
185 | default: | |
186 | index = density - 1; | |
187 | } | |
188 | break; | |
189 | default: | |
190 | return NULL; | |
191 | } | |
192 | ||
193 | return &lpddr2_jedec_addressing_table[index]; | |
194 | } | |
195 | ||
196 | /* | |
197 | * Find the the right timing table from the array of timing | |
198 | * tables of the device using DDR clock frequency | |
199 | */ | |
200 | static const struct lpddr2_timings *get_timings_table(struct emif_data *emif, | |
201 | u32 freq) | |
202 | { | |
203 | u32 i, min, max, freq_nearest; | |
204 | const struct lpddr2_timings *timings = NULL; | |
205 | const struct lpddr2_timings *timings_arr = emif->plat_data->timings; | |
206 | struct device *dev = emif->dev; | |
207 | ||
208 | /* Start with a very high frequency - 1GHz */ | |
209 | freq_nearest = 1000000000; | |
210 | ||
211 | /* | |
212 | * Find the timings table such that: | |
213 | * 1. the frequency range covers the required frequency(safe) AND | |
214 | * 2. the max_freq is closest to the required frequency(optimal) | |
215 | */ | |
216 | for (i = 0; i < emif->plat_data->timings_arr_size; i++) { | |
217 | max = timings_arr[i].max_freq; | |
218 | min = timings_arr[i].min_freq; | |
219 | if ((freq >= min) && (freq <= max) && (max < freq_nearest)) { | |
220 | freq_nearest = max; | |
221 | timings = &timings_arr[i]; | |
222 | } | |
223 | } | |
224 | ||
225 | if (!timings) | |
226 | dev_err(dev, "%s: couldn't find timings for - %dHz\n", | |
227 | __func__, freq); | |
228 | ||
229 | dev_dbg(dev, "%s: timings table: freq %d, speed bin freq %d\n", | |
230 | __func__, freq, freq_nearest); | |
231 | ||
232 | return timings; | |
233 | } | |
234 | ||
235 | static u32 get_sdram_ref_ctrl_shdw(u32 freq, | |
236 | const struct lpddr2_addressing *addressing) | |
237 | { | |
238 | u32 ref_ctrl_shdw = 0, val = 0, freq_khz, t_refi; | |
239 | ||
240 | /* Scale down frequency and t_refi to avoid overflow */ | |
241 | freq_khz = freq / 1000; | |
242 | t_refi = addressing->tREFI_ns / 100; | |
243 | ||
244 | /* | |
245 | * refresh rate to be set is 'tREFI(in us) * freq in MHz | |
246 | * division by 10000 to account for change in units | |
247 | */ | |
248 | val = t_refi * freq_khz / 10000; | |
249 | ref_ctrl_shdw |= val << REFRESH_RATE_SHIFT; | |
250 | ||
251 | return ref_ctrl_shdw; | |
252 | } | |
253 | ||
254 | static u32 get_sdram_tim_1_shdw(const struct lpddr2_timings *timings, | |
255 | const struct lpddr2_min_tck *min_tck, | |
256 | const struct lpddr2_addressing *addressing) | |
257 | { | |
258 | u32 tim1 = 0, val = 0; | |
259 | ||
260 | val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1; | |
261 | tim1 |= val << T_WTR_SHIFT; | |
262 | ||
263 | if (addressing->num_banks == B8) | |
264 | val = DIV_ROUND_UP(timings->tFAW, t_ck*4); | |
265 | else | |
266 | val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck)); | |
267 | tim1 |= (val - 1) << T_RRD_SHIFT; | |
268 | ||
269 | val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1; | |
270 | tim1 |= val << T_RC_SHIFT; | |
271 | ||
272 | val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck)); | |
273 | tim1 |= (val - 1) << T_RAS_SHIFT; | |
274 | ||
275 | val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1; | |
276 | tim1 |= val << T_WR_SHIFT; | |
277 | ||
278 | val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1; | |
279 | tim1 |= val << T_RCD_SHIFT; | |
280 | ||
281 | val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1; | |
282 | tim1 |= val << T_RP_SHIFT; | |
283 | ||
284 | return tim1; | |
285 | } | |
286 | ||
287 | static u32 get_sdram_tim_1_shdw_derated(const struct lpddr2_timings *timings, | |
288 | const struct lpddr2_min_tck *min_tck, | |
289 | const struct lpddr2_addressing *addressing) | |
290 | { | |
291 | u32 tim1 = 0, val = 0; | |
292 | ||
293 | val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1; | |
294 | tim1 = val << T_WTR_SHIFT; | |
295 | ||
296 | /* | |
297 | * tFAW is approximately 4 times tRRD. So add 1875*4 = 7500ps | |
298 | * to tFAW for de-rating | |
299 | */ | |
300 | if (addressing->num_banks == B8) { | |
301 | val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1; | |
302 | } else { | |
303 | val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck); | |
304 | val = max(min_tck->tRRD, val) - 1; | |
305 | } | |
306 | tim1 |= val << T_RRD_SHIFT; | |
307 | ||
308 | val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck); | |
309 | tim1 |= (val - 1) << T_RC_SHIFT; | |
310 | ||
311 | val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck); | |
312 | val = max(min_tck->tRASmin, val) - 1; | |
313 | tim1 |= val << T_RAS_SHIFT; | |
314 | ||
315 | val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1; | |
316 | tim1 |= val << T_WR_SHIFT; | |
317 | ||
318 | val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck)); | |
319 | tim1 |= (val - 1) << T_RCD_SHIFT; | |
320 | ||
321 | val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck)); | |
322 | tim1 |= (val - 1) << T_RP_SHIFT; | |
323 | ||
324 | return tim1; | |
325 | } | |
326 | ||
327 | static u32 get_sdram_tim_2_shdw(const struct lpddr2_timings *timings, | |
328 | const struct lpddr2_min_tck *min_tck, | |
329 | const struct lpddr2_addressing *addressing, | |
330 | u32 type) | |
331 | { | |
332 | u32 tim2 = 0, val = 0; | |
333 | ||
334 | val = min_tck->tCKE - 1; | |
335 | tim2 |= val << T_CKE_SHIFT; | |
336 | ||
337 | val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1; | |
338 | tim2 |= val << T_RTP_SHIFT; | |
339 | ||
340 | /* tXSNR = tRFCab_ps + 10 ns(tRFCab_ps for LPDDR2). */ | |
341 | val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1; | |
342 | tim2 |= val << T_XSNR_SHIFT; | |
343 | ||
344 | /* XSRD same as XSNR for LPDDR2 */ | |
345 | tim2 |= val << T_XSRD_SHIFT; | |
346 | ||
347 | val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1; | |
348 | tim2 |= val << T_XP_SHIFT; | |
349 | ||
350 | return tim2; | |
351 | } | |
352 | ||
353 | static u32 get_sdram_tim_3_shdw(const struct lpddr2_timings *timings, | |
354 | const struct lpddr2_min_tck *min_tck, | |
355 | const struct lpddr2_addressing *addressing, | |
356 | u32 type, u32 ip_rev, u32 derated) | |
357 | { | |
358 | u32 tim3 = 0, val = 0, t_dqsck; | |
359 | ||
360 | val = timings->tRAS_max_ns / addressing->tREFI_ns - 1; | |
361 | val = val > 0xF ? 0xF : val; | |
362 | tim3 |= val << T_RAS_MAX_SHIFT; | |
363 | ||
364 | val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1; | |
365 | tim3 |= val << T_RFC_SHIFT; | |
366 | ||
367 | t_dqsck = (derated == EMIF_DERATED_TIMINGS) ? | |
368 | timings->tDQSCK_max_derated : timings->tDQSCK_max; | |
369 | if (ip_rev == EMIF_4D5) | |
370 | val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1; | |
371 | else | |
372 | val = DIV_ROUND_UP(t_dqsck, t_ck) - 1; | |
373 | ||
374 | tim3 |= val << T_TDQSCKMAX_SHIFT; | |
375 | ||
376 | val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1; | |
377 | tim3 |= val << ZQ_ZQCS_SHIFT; | |
378 | ||
379 | val = DIV_ROUND_UP(timings->tCKESR, t_ck); | |
380 | val = max(min_tck->tCKESR, val) - 1; | |
381 | tim3 |= val << T_CKESR_SHIFT; | |
382 | ||
383 | if (ip_rev == EMIF_4D5) { | |
384 | tim3 |= (EMIF_T_CSTA - 1) << T_CSTA_SHIFT; | |
385 | ||
386 | val = DIV_ROUND_UP(EMIF_T_PDLL_UL, 128) - 1; | |
387 | tim3 |= val << T_PDLL_UL_SHIFT; | |
388 | } | |
389 | ||
390 | return tim3; | |
391 | } | |
392 | ||
98231c4f A |
393 | static u32 get_zq_config_reg(const struct lpddr2_addressing *addressing, |
394 | bool cs1_used, bool cal_resistors_per_cs) | |
395 | { | |
396 | u32 zq = 0, val = 0; | |
397 | ||
398 | val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns; | |
399 | zq |= val << ZQ_REFINTERVAL_SHIFT; | |
400 | ||
401 | val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1; | |
402 | zq |= val << ZQ_ZQCL_MULT_SHIFT; | |
403 | ||
404 | val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1; | |
405 | zq |= val << ZQ_ZQINIT_MULT_SHIFT; | |
406 | ||
407 | zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT; | |
408 | ||
409 | if (cal_resistors_per_cs) | |
410 | zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT; | |
411 | else | |
412 | zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT; | |
413 | ||
414 | zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */ | |
415 | ||
416 | val = cs1_used ? 1 : 0; | |
417 | zq |= val << ZQ_CS1EN_SHIFT; | |
418 | ||
419 | return zq; | |
420 | } | |
421 | ||
422 | static u32 get_temp_alert_config(const struct lpddr2_addressing *addressing, | |
423 | const struct emif_custom_configs *custom_configs, bool cs1_used, | |
424 | u32 sdram_io_width, u32 emif_bus_width) | |
425 | { | |
426 | u32 alert = 0, interval, devcnt; | |
427 | ||
428 | if (custom_configs && (custom_configs->mask & | |
429 | EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL)) | |
430 | interval = custom_configs->temp_alert_poll_interval_ms; | |
431 | else | |
432 | interval = TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS; | |
433 | ||
434 | interval *= 1000000; /* Convert to ns */ | |
435 | interval /= addressing->tREFI_ns; /* Convert to refresh cycles */ | |
436 | alert |= (interval << TA_REFINTERVAL_SHIFT); | |
437 | ||
438 | /* | |
439 | * sdram_io_width is in 'log2(x) - 1' form. Convert emif_bus_width | |
440 | * also to this form and subtract to get TA_DEVCNT, which is | |
441 | * in log2(x) form. | |
442 | */ | |
443 | emif_bus_width = __fls(emif_bus_width) - 1; | |
444 | devcnt = emif_bus_width - sdram_io_width; | |
445 | alert |= devcnt << TA_DEVCNT_SHIFT; | |
446 | ||
447 | /* DEVWDT is in 'log2(x) - 3' form */ | |
448 | alert |= (sdram_io_width - 2) << TA_DEVWDT_SHIFT; | |
449 | ||
450 | alert |= 1 << TA_SFEXITEN_SHIFT; | |
451 | alert |= 1 << TA_CS0EN_SHIFT; | |
452 | alert |= (cs1_used ? 1 : 0) << TA_CS1EN_SHIFT; | |
453 | ||
454 | return alert; | |
455 | } | |
456 | ||
a93de288 A |
457 | static u32 get_read_idle_ctrl_shdw(u8 volt_ramp) |
458 | { | |
459 | u32 idle = 0, val = 0; | |
460 | ||
461 | /* | |
462 | * Maximum value in normal conditions and increased frequency | |
463 | * when voltage is ramping | |
464 | */ | |
465 | if (volt_ramp) | |
466 | val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1; | |
467 | else | |
468 | val = 0x1FF; | |
469 | ||
470 | /* | |
471 | * READ_IDLE_CTRL register in EMIF4D has same offset and fields | |
472 | * as DLL_CALIB_CTRL in EMIF4D5, so use the same shifts | |
473 | */ | |
474 | idle |= val << DLL_CALIB_INTERVAL_SHIFT; | |
475 | idle |= EMIF_READ_IDLE_LEN_VAL << ACK_WAIT_SHIFT; | |
476 | ||
477 | return idle; | |
478 | } | |
479 | ||
480 | static u32 get_dll_calib_ctrl_shdw(u8 volt_ramp) | |
481 | { | |
482 | u32 calib = 0, val = 0; | |
483 | ||
484 | if (volt_ramp == DDR_VOLTAGE_RAMPING) | |
485 | val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1; | |
486 | else | |
487 | val = 0; /* Disabled when voltage is stable */ | |
488 | ||
489 | calib |= val << DLL_CALIB_INTERVAL_SHIFT; | |
490 | calib |= DLL_CALIB_ACK_WAIT_VAL << ACK_WAIT_SHIFT; | |
491 | ||
492 | return calib; | |
493 | } | |
494 | ||
495 | static u32 get_ddr_phy_ctrl_1_attilaphy_4d(const struct lpddr2_timings *timings, | |
496 | u32 freq, u8 RL) | |
497 | { | |
498 | u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY, val = 0; | |
499 | ||
500 | val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1; | |
501 | phy |= val << READ_LATENCY_SHIFT_4D; | |
502 | ||
503 | if (freq <= 100000000) | |
504 | val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY; | |
505 | else if (freq <= 200000000) | |
506 | val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY; | |
507 | else | |
508 | val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY; | |
509 | ||
510 | phy |= val << DLL_SLAVE_DLY_CTRL_SHIFT_4D; | |
511 | ||
512 | return phy; | |
513 | } | |
514 | ||
515 | static u32 get_phy_ctrl_1_intelliphy_4d5(u32 freq, u8 cl) | |
516 | { | |
517 | u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY, half_delay; | |
518 | ||
519 | /* | |
520 | * DLL operates at 266 MHz. If DDR frequency is near 266 MHz, | |
521 | * half-delay is not needed else set half-delay | |
522 | */ | |
523 | if (freq >= 265000000 && freq < 267000000) | |
524 | half_delay = 0; | |
525 | else | |
526 | half_delay = 1; | |
527 | ||
528 | phy |= half_delay << DLL_HALF_DELAY_SHIFT_4D5; | |
529 | phy |= ((cl + DIV_ROUND_UP(EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS, | |
530 | t_ck) - 1) << READ_LATENCY_SHIFT_4D5); | |
531 | ||
532 | return phy; | |
533 | } | |
534 | ||
535 | static u32 get_ext_phy_ctrl_2_intelliphy_4d5(void) | |
536 | { | |
537 | u32 fifo_we_slave_ratio; | |
538 | ||
539 | fifo_we_slave_ratio = DIV_ROUND_CLOSEST( | |
540 | EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck); | |
541 | ||
542 | return fifo_we_slave_ratio | fifo_we_slave_ratio << 11 | | |
543 | fifo_we_slave_ratio << 22; | |
544 | } | |
545 | ||
546 | static u32 get_ext_phy_ctrl_3_intelliphy_4d5(void) | |
547 | { | |
548 | u32 fifo_we_slave_ratio; | |
549 | ||
550 | fifo_we_slave_ratio = DIV_ROUND_CLOSEST( | |
551 | EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck); | |
552 | ||
553 | return fifo_we_slave_ratio >> 10 | fifo_we_slave_ratio << 1 | | |
554 | fifo_we_slave_ratio << 12 | fifo_we_slave_ratio << 23; | |
555 | } | |
556 | ||
557 | static u32 get_ext_phy_ctrl_4_intelliphy_4d5(void) | |
558 | { | |
559 | u32 fifo_we_slave_ratio; | |
560 | ||
561 | fifo_we_slave_ratio = DIV_ROUND_CLOSEST( | |
562 | EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck); | |
563 | ||
564 | return fifo_we_slave_ratio >> 9 | fifo_we_slave_ratio << 2 | | |
565 | fifo_we_slave_ratio << 13; | |
566 | } | |
567 | ||
568 | static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev) | |
569 | { | |
570 | u32 pwr_mgmt_ctrl = 0, timeout; | |
571 | u32 lpmode = EMIF_LP_MODE_SELF_REFRESH; | |
572 | u32 timeout_perf = EMIF_LP_MODE_TIMEOUT_PERFORMANCE; | |
573 | u32 timeout_pwr = EMIF_LP_MODE_TIMEOUT_POWER; | |
574 | u32 freq_threshold = EMIF_LP_MODE_FREQ_THRESHOLD; | |
575 | ||
576 | struct emif_custom_configs *cust_cfgs = emif->plat_data->custom_configs; | |
577 | ||
578 | if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) { | |
579 | lpmode = cust_cfgs->lpmode; | |
580 | timeout_perf = cust_cfgs->lpmode_timeout_performance; | |
581 | timeout_pwr = cust_cfgs->lpmode_timeout_power; | |
582 | freq_threshold = cust_cfgs->lpmode_freq_threshold; | |
583 | } | |
584 | ||
585 | /* Timeout based on DDR frequency */ | |
586 | timeout = freq >= freq_threshold ? timeout_perf : timeout_pwr; | |
587 | ||
588 | /* The value to be set in register is "log2(timeout) - 3" */ | |
589 | if (timeout < 16) { | |
590 | timeout = 0; | |
591 | } else { | |
592 | timeout = __fls(timeout) - 3; | |
593 | if (timeout & (timeout - 1)) | |
594 | timeout++; | |
595 | } | |
596 | ||
597 | switch (lpmode) { | |
598 | case EMIF_LP_MODE_CLOCK_STOP: | |
599 | pwr_mgmt_ctrl = (timeout << CS_TIM_SHIFT) | | |
600 | SR_TIM_MASK | PD_TIM_MASK; | |
601 | break; | |
602 | case EMIF_LP_MODE_SELF_REFRESH: | |
603 | /* Workaround for errata i735 */ | |
604 | if (timeout < 6) | |
605 | timeout = 6; | |
606 | ||
607 | pwr_mgmt_ctrl = (timeout << SR_TIM_SHIFT) | | |
608 | CS_TIM_MASK | PD_TIM_MASK; | |
609 | break; | |
610 | case EMIF_LP_MODE_PWR_DN: | |
611 | pwr_mgmt_ctrl = (timeout << PD_TIM_SHIFT) | | |
612 | CS_TIM_MASK | SR_TIM_MASK; | |
613 | break; | |
614 | case EMIF_LP_MODE_DISABLE: | |
615 | default: | |
616 | pwr_mgmt_ctrl = CS_TIM_MASK | | |
617 | PD_TIM_MASK | SR_TIM_MASK; | |
618 | } | |
619 | ||
620 | /* No CS_TIM in EMIF_4D5 */ | |
621 | if (ip_rev == EMIF_4D5) | |
622 | pwr_mgmt_ctrl &= ~CS_TIM_MASK; | |
623 | ||
624 | pwr_mgmt_ctrl |= lpmode << LP_MODE_SHIFT; | |
625 | ||
626 | return pwr_mgmt_ctrl; | |
627 | } | |
628 | ||
68b4aee3 A |
629 | /* |
630 | * Get the temperature level of the EMIF instance: | |
631 | * Reads the MR4 register of attached SDRAM parts to find out the temperature | |
632 | * level. If there are two parts attached(one on each CS), then the temperature | |
633 | * level for the EMIF instance is the higher of the two temperatures. | |
634 | */ | |
635 | static void get_temperature_level(struct emif_data *emif) | |
636 | { | |
637 | u32 temp, temperature_level; | |
638 | void __iomem *base; | |
639 | ||
640 | base = emif->base; | |
641 | ||
642 | /* Read mode register 4 */ | |
643 | writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG); | |
644 | temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA); | |
645 | temperature_level = (temperature_level & MR4_SDRAM_REF_RATE_MASK) >> | |
646 | MR4_SDRAM_REF_RATE_SHIFT; | |
647 | ||
648 | if (emif->plat_data->device_info->cs1_used) { | |
649 | writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG); | |
650 | temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA); | |
651 | temp = (temp & MR4_SDRAM_REF_RATE_MASK) | |
652 | >> MR4_SDRAM_REF_RATE_SHIFT; | |
653 | temperature_level = max(temp, temperature_level); | |
654 | } | |
655 | ||
656 | /* treat everything less than nominal(3) in MR4 as nominal */ | |
657 | if (unlikely(temperature_level < SDRAM_TEMP_NOMINAL)) | |
658 | temperature_level = SDRAM_TEMP_NOMINAL; | |
659 | ||
660 | /* if we get reserved value in MR4 persist with the existing value */ | |
661 | if (likely(temperature_level != SDRAM_TEMP_RESERVED_4)) | |
662 | emif->temperature_level = temperature_level; | |
663 | } | |
664 | ||
a93de288 A |
665 | /* |
666 | * Program EMIF shadow registers that are not dependent on temperature | |
667 | * or voltage | |
668 | */ | |
669 | static void setup_registers(struct emif_data *emif, struct emif_regs *regs) | |
670 | { | |
671 | void __iomem *base = emif->base; | |
672 | ||
673 | writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW); | |
674 | writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW); | |
675 | ||
676 | /* Settings specific for EMIF4D5 */ | |
677 | if (emif->plat_data->ip_rev != EMIF_4D5) | |
678 | return; | |
679 | writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW); | |
680 | writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW); | |
681 | writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW); | |
682 | } | |
683 | ||
684 | /* | |
685 | * When voltage ramps dll calibration and forced read idle should | |
686 | * happen more often | |
687 | */ | |
688 | static void setup_volt_sensitive_regs(struct emif_data *emif, | |
689 | struct emif_regs *regs, u32 volt_state) | |
690 | { | |
691 | u32 calib_ctrl; | |
692 | void __iomem *base = emif->base; | |
693 | ||
694 | /* | |
695 | * EMIF_READ_IDLE_CTRL in EMIF4D refers to the same register as | |
696 | * EMIF_DLL_CALIB_CTRL in EMIF4D5 and dll_calib_ctrl_shadow_* | |
697 | * is an alias of the respective read_idle_ctrl_shdw_* (members of | |
698 | * a union). So, the below code takes care of both cases | |
699 | */ | |
700 | if (volt_state == DDR_VOLTAGE_RAMPING) | |
701 | calib_ctrl = regs->dll_calib_ctrl_shdw_volt_ramp; | |
702 | else | |
703 | calib_ctrl = regs->dll_calib_ctrl_shdw_normal; | |
704 | ||
705 | writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW); | |
706 | } | |
707 | ||
708 | /* | |
709 | * setup_temperature_sensitive_regs() - set the timings for temperature | |
710 | * sensitive registers. This happens once at initialisation time based | |
711 | * on the temperature at boot time and subsequently based on the temperature | |
712 | * alert interrupt. Temperature alert can happen when the temperature | |
713 | * increases or drops. So this function can have the effect of either | |
714 | * derating the timings or going back to nominal values. | |
715 | */ | |
716 | static void setup_temperature_sensitive_regs(struct emif_data *emif, | |
717 | struct emif_regs *regs) | |
718 | { | |
719 | u32 tim1, tim3, ref_ctrl, type; | |
720 | void __iomem *base = emif->base; | |
721 | u32 temperature; | |
722 | ||
723 | type = emif->plat_data->device_info->type; | |
724 | ||
725 | tim1 = regs->sdram_tim1_shdw; | |
726 | tim3 = regs->sdram_tim3_shdw; | |
727 | ref_ctrl = regs->ref_ctrl_shdw; | |
728 | ||
729 | /* No de-rating for non-lpddr2 devices */ | |
730 | if (type != DDR_TYPE_LPDDR2_S2 && type != DDR_TYPE_LPDDR2_S4) | |
731 | goto out; | |
732 | ||
733 | temperature = emif->temperature_level; | |
734 | if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH) { | |
735 | ref_ctrl = regs->ref_ctrl_shdw_derated; | |
736 | } else if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS) { | |
737 | tim1 = regs->sdram_tim1_shdw_derated; | |
738 | tim3 = regs->sdram_tim3_shdw_derated; | |
739 | ref_ctrl = regs->ref_ctrl_shdw_derated; | |
740 | } | |
741 | ||
742 | out: | |
743 | writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW); | |
744 | writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW); | |
745 | writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW); | |
746 | } | |
747 | ||
68b4aee3 A |
748 | static irqreturn_t handle_temp_alert(void __iomem *base, struct emif_data *emif) |
749 | { | |
750 | u32 old_temp_level; | |
751 | irqreturn_t ret = IRQ_HANDLED; | |
752 | ||
753 | spin_lock_irqsave(&emif_lock, irq_state); | |
754 | old_temp_level = emif->temperature_level; | |
755 | get_temperature_level(emif); | |
756 | ||
757 | if (unlikely(emif->temperature_level == old_temp_level)) { | |
758 | goto out; | |
759 | } else if (!emif->curr_regs) { | |
760 | dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n"); | |
761 | goto out; | |
762 | } | |
763 | ||
764 | if (emif->temperature_level < old_temp_level || | |
765 | emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) { | |
766 | /* | |
767 | * Temperature coming down - defer handling to thread OR | |
768 | * Temperature far too high - do kernel_power_off() from | |
769 | * thread context | |
770 | */ | |
771 | ret = IRQ_WAKE_THREAD; | |
772 | } else { | |
773 | /* Temperature is going up - handle immediately */ | |
774 | setup_temperature_sensitive_regs(emif, emif->curr_regs); | |
775 | do_freq_update(); | |
776 | } | |
777 | ||
778 | out: | |
779 | spin_unlock_irqrestore(&emif_lock, irq_state); | |
780 | return ret; | |
781 | } | |
782 | ||
783 | static irqreturn_t emif_interrupt_handler(int irq, void *dev_id) | |
784 | { | |
785 | u32 interrupts; | |
786 | struct emif_data *emif = dev_id; | |
787 | void __iomem *base = emif->base; | |
788 | struct device *dev = emif->dev; | |
789 | irqreturn_t ret = IRQ_HANDLED; | |
790 | ||
791 | /* Save the status and clear it */ | |
792 | interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); | |
793 | writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); | |
794 | ||
795 | /* | |
796 | * Handle temperature alert | |
797 | * Temperature alert should be same for all ports | |
798 | * So, it's enough to process it only for one of the ports | |
799 | */ | |
800 | if (interrupts & TA_SYS_MASK) | |
801 | ret = handle_temp_alert(base, emif); | |
802 | ||
803 | if (interrupts & ERR_SYS_MASK) | |
804 | dev_err(dev, "Access error from SYS port - %x\n", interrupts); | |
805 | ||
806 | if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) { | |
807 | /* Save the status and clear it */ | |
808 | interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS); | |
809 | writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS); | |
810 | ||
811 | if (interrupts & ERR_LL_MASK) | |
812 | dev_err(dev, "Access error from LL port - %x\n", | |
813 | interrupts); | |
814 | } | |
815 | ||
816 | return ret; | |
817 | } | |
818 | ||
819 | static irqreturn_t emif_threaded_isr(int irq, void *dev_id) | |
820 | { | |
821 | struct emif_data *emif = dev_id; | |
822 | ||
823 | if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) { | |
824 | dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n"); | |
825 | kernel_power_off(); | |
826 | return IRQ_HANDLED; | |
827 | } | |
828 | ||
829 | spin_lock_irqsave(&emif_lock, irq_state); | |
830 | ||
831 | if (emif->curr_regs) { | |
832 | setup_temperature_sensitive_regs(emif, emif->curr_regs); | |
833 | do_freq_update(); | |
834 | } else { | |
835 | dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n"); | |
836 | } | |
837 | ||
838 | spin_unlock_irqrestore(&emif_lock, irq_state); | |
839 | ||
840 | return IRQ_HANDLED; | |
841 | } | |
842 | ||
843 | static void clear_all_interrupts(struct emif_data *emif) | |
844 | { | |
845 | void __iomem *base = emif->base; | |
846 | ||
847 | writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS), | |
848 | base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); | |
849 | if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) | |
850 | writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS), | |
851 | base + EMIF_LL_OCP_INTERRUPT_STATUS); | |
852 | } | |
853 | ||
854 | static void disable_and_clear_all_interrupts(struct emif_data *emif) | |
855 | { | |
856 | void __iomem *base = emif->base; | |
857 | ||
858 | /* Disable all interrupts */ | |
859 | writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET), | |
860 | base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR); | |
861 | if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) | |
862 | writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET), | |
863 | base + EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR); | |
864 | ||
865 | /* Clear all interrupts */ | |
866 | clear_all_interrupts(emif); | |
867 | } | |
868 | ||
869 | static int __init_or_module setup_interrupts(struct emif_data *emif, u32 irq) | |
870 | { | |
871 | u32 interrupts, type; | |
872 | void __iomem *base = emif->base; | |
873 | ||
874 | type = emif->plat_data->device_info->type; | |
875 | ||
876 | clear_all_interrupts(emif); | |
877 | ||
878 | /* Enable interrupts for SYS interface */ | |
879 | interrupts = EN_ERR_SYS_MASK; | |
880 | if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) | |
881 | interrupts |= EN_TA_SYS_MASK; | |
882 | writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET); | |
883 | ||
884 | /* Enable interrupts for LL interface */ | |
885 | if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) { | |
886 | /* TA need not be enabled for LL */ | |
887 | interrupts = EN_ERR_LL_MASK; | |
888 | writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET); | |
889 | } | |
890 | ||
891 | /* setup IRQ handlers */ | |
892 | return devm_request_threaded_irq(emif->dev, irq, | |
893 | emif_interrupt_handler, | |
894 | emif_threaded_isr, | |
895 | 0, dev_name(emif->dev), | |
896 | emif); | |
897 | ||
898 | } | |
899 | ||
98231c4f A |
900 | static void __init_or_module emif_onetime_settings(struct emif_data *emif) |
901 | { | |
902 | u32 pwr_mgmt_ctrl, zq, temp_alert_cfg; | |
903 | void __iomem *base = emif->base; | |
904 | const struct lpddr2_addressing *addressing; | |
905 | const struct ddr_device_info *device_info; | |
906 | ||
907 | device_info = emif->plat_data->device_info; | |
908 | addressing = get_addressing_table(device_info); | |
909 | ||
910 | /* | |
911 | * Init power management settings | |
912 | * We don't know the frequency yet. Use a high frequency | |
913 | * value for a conservative timeout setting | |
914 | */ | |
915 | pwr_mgmt_ctrl = get_pwr_mgmt_ctrl(1000000000, emif, | |
916 | emif->plat_data->ip_rev); | |
917 | emif->lpmode = (pwr_mgmt_ctrl & LP_MODE_MASK) >> LP_MODE_SHIFT; | |
918 | writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL); | |
919 | ||
920 | /* Init ZQ calibration settings */ | |
921 | zq = get_zq_config_reg(addressing, device_info->cs1_used, | |
922 | device_info->cal_resistors_per_cs); | |
923 | writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG); | |
924 | ||
925 | /* Check temperature level temperature level*/ | |
926 | get_temperature_level(emif); | |
927 | if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) | |
928 | dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n"); | |
929 | ||
930 | /* Init temperature polling */ | |
931 | temp_alert_cfg = get_temp_alert_config(addressing, | |
932 | emif->plat_data->custom_configs, device_info->cs1_used, | |
933 | device_info->io_width, get_emif_bus_width(emif)); | |
934 | writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG); | |
935 | ||
936 | /* | |
937 | * Program external PHY control registers that are not frequency | |
938 | * dependent | |
939 | */ | |
940 | if (emif->plat_data->phy_type != EMIF_PHY_TYPE_INTELLIPHY) | |
941 | return; | |
942 | writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW); | |
943 | writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW); | |
944 | writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW); | |
945 | writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW); | |
946 | writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW); | |
947 | writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW); | |
948 | writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW); | |
949 | writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW); | |
950 | writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW); | |
951 | writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW); | |
952 | writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW); | |
953 | writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW); | |
954 | writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW); | |
955 | writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW); | |
956 | writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW); | |
957 | writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW); | |
958 | writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW); | |
959 | writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW); | |
960 | writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW); | |
961 | writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW); | |
962 | writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW); | |
963 | } | |
964 | ||
7ec94453 A |
965 | static void get_default_timings(struct emif_data *emif) |
966 | { | |
967 | struct emif_platform_data *pd = emif->plat_data; | |
968 | ||
969 | pd->timings = lpddr2_jedec_timings; | |
970 | pd->timings_arr_size = ARRAY_SIZE(lpddr2_jedec_timings); | |
971 | ||
972 | dev_warn(emif->dev, "%s: using default timings\n", __func__); | |
973 | } | |
974 | ||
975 | static int is_dev_data_valid(u32 type, u32 density, u32 io_width, u32 phy_type, | |
976 | u32 ip_rev, struct device *dev) | |
977 | { | |
978 | int valid; | |
979 | ||
980 | valid = (type == DDR_TYPE_LPDDR2_S4 || | |
981 | type == DDR_TYPE_LPDDR2_S2) | |
982 | && (density >= DDR_DENSITY_64Mb | |
983 | && density <= DDR_DENSITY_8Gb) | |
984 | && (io_width >= DDR_IO_WIDTH_8 | |
985 | && io_width <= DDR_IO_WIDTH_32); | |
986 | ||
987 | /* Combinations of EMIF and PHY revisions that we support today */ | |
988 | switch (ip_rev) { | |
989 | case EMIF_4D: | |
990 | valid = valid && (phy_type == EMIF_PHY_TYPE_ATTILAPHY); | |
991 | break; | |
992 | case EMIF_4D5: | |
993 | valid = valid && (phy_type == EMIF_PHY_TYPE_INTELLIPHY); | |
994 | break; | |
995 | default: | |
996 | valid = 0; | |
997 | } | |
998 | ||
999 | if (!valid) | |
1000 | dev_err(dev, "%s: invalid DDR details\n", __func__); | |
1001 | return valid; | |
1002 | } | |
1003 | ||
1004 | static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs, | |
1005 | struct device *dev) | |
1006 | { | |
1007 | int valid = 1; | |
1008 | ||
1009 | if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) && | |
1010 | (cust_cfgs->lpmode != EMIF_LP_MODE_DISABLE)) | |
1011 | valid = cust_cfgs->lpmode_freq_threshold && | |
1012 | cust_cfgs->lpmode_timeout_performance && | |
1013 | cust_cfgs->lpmode_timeout_power; | |
1014 | ||
1015 | if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL) | |
1016 | valid = valid && cust_cfgs->temp_alert_poll_interval_ms; | |
1017 | ||
1018 | if (!valid) | |
1019 | dev_warn(dev, "%s: invalid custom configs\n", __func__); | |
1020 | ||
1021 | return valid; | |
1022 | } | |
1023 | ||
1024 | static struct emif_data *__init_or_module get_device_details( | |
1025 | struct platform_device *pdev) | |
1026 | { | |
1027 | u32 size; | |
1028 | struct emif_data *emif = NULL; | |
1029 | struct ddr_device_info *dev_info; | |
1030 | struct emif_custom_configs *cust_cfgs; | |
1031 | struct emif_platform_data *pd; | |
1032 | struct device *dev; | |
1033 | void *temp; | |
1034 | ||
1035 | pd = pdev->dev.platform_data; | |
1036 | dev = &pdev->dev; | |
1037 | ||
1038 | if (!(pd && pd->device_info && is_dev_data_valid(pd->device_info->type, | |
1039 | pd->device_info->density, pd->device_info->io_width, | |
1040 | pd->phy_type, pd->ip_rev, dev))) { | |
1041 | dev_err(dev, "%s: invalid device data\n", __func__); | |
1042 | goto error; | |
1043 | } | |
1044 | ||
1045 | emif = devm_kzalloc(dev, sizeof(*emif), GFP_KERNEL); | |
1046 | temp = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); | |
1047 | dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL); | |
1048 | ||
1049 | if (!emif || !pd || !dev_info) { | |
1050 | dev_err(dev, "%s:%d: allocation error\n", __func__, __LINE__); | |
1051 | goto error; | |
1052 | } | |
1053 | ||
1054 | memcpy(temp, pd, sizeof(*pd)); | |
1055 | pd = temp; | |
1056 | memcpy(dev_info, pd->device_info, sizeof(*dev_info)); | |
1057 | ||
1058 | pd->device_info = dev_info; | |
1059 | emif->plat_data = pd; | |
1060 | emif->dev = dev; | |
1061 | emif->temperature_level = SDRAM_TEMP_NOMINAL; | |
1062 | ||
1063 | /* | |
1064 | * For EMIF instances other than EMIF1 see if the devices connected | |
1065 | * are exactly same as on EMIF1(which is typically the case). If so, | |
1066 | * mark it as a duplicate of EMIF1 and skip copying timings data. | |
1067 | * This will save some memory and some computation later. | |
1068 | */ | |
1069 | emif->duplicate = emif1 && (memcmp(dev_info, | |
1070 | emif1->plat_data->device_info, | |
1071 | sizeof(struct ddr_device_info)) == 0); | |
1072 | ||
1073 | if (emif->duplicate) { | |
1074 | pd->timings = NULL; | |
1075 | pd->min_tck = NULL; | |
1076 | goto out; | |
1077 | } else if (emif1) { | |
1078 | dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n", | |
1079 | __func__); | |
1080 | } | |
1081 | ||
1082 | /* | |
1083 | * Copy custom configs - ignore allocation error, if any, as | |
1084 | * custom_configs is not very critical | |
1085 | */ | |
1086 | cust_cfgs = pd->custom_configs; | |
1087 | if (cust_cfgs && is_custom_config_valid(cust_cfgs, dev)) { | |
1088 | temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL); | |
1089 | if (temp) | |
1090 | memcpy(temp, cust_cfgs, sizeof(*cust_cfgs)); | |
1091 | else | |
1092 | dev_warn(dev, "%s:%d: allocation error\n", __func__, | |
1093 | __LINE__); | |
1094 | pd->custom_configs = temp; | |
1095 | } | |
1096 | ||
1097 | /* | |
1098 | * Copy timings and min-tck values from platform data. If it is not | |
1099 | * available or if memory allocation fails, use JEDEC defaults | |
1100 | */ | |
1101 | size = sizeof(struct lpddr2_timings) * pd->timings_arr_size; | |
1102 | if (pd->timings) { | |
1103 | temp = devm_kzalloc(dev, size, GFP_KERNEL); | |
1104 | if (temp) { | |
1105 | memcpy(temp, pd->timings, sizeof(*pd->timings)); | |
1106 | pd->timings = temp; | |
1107 | } else { | |
1108 | dev_warn(dev, "%s:%d: allocation error\n", __func__, | |
1109 | __LINE__); | |
1110 | get_default_timings(emif); | |
1111 | } | |
1112 | } else { | |
1113 | get_default_timings(emif); | |
1114 | } | |
1115 | ||
1116 | if (pd->min_tck) { | |
1117 | temp = devm_kzalloc(dev, sizeof(*pd->min_tck), GFP_KERNEL); | |
1118 | if (temp) { | |
1119 | memcpy(temp, pd->min_tck, sizeof(*pd->min_tck)); | |
1120 | pd->min_tck = temp; | |
1121 | } else { | |
1122 | dev_warn(dev, "%s:%d: allocation error\n", __func__, | |
1123 | __LINE__); | |
1124 | pd->min_tck = &lpddr2_jedec_min_tck; | |
1125 | } | |
1126 | } else { | |
1127 | pd->min_tck = &lpddr2_jedec_min_tck; | |
1128 | } | |
1129 | ||
1130 | out: | |
1131 | return emif; | |
1132 | ||
1133 | error: | |
1134 | return NULL; | |
1135 | } | |
1136 | ||
1137 | static int __init_or_module emif_probe(struct platform_device *pdev) | |
1138 | { | |
1139 | struct emif_data *emif; | |
1140 | struct resource *res; | |
68b4aee3 | 1141 | int irq; |
7ec94453 A |
1142 | |
1143 | emif = get_device_details(pdev); | |
1144 | if (!emif) { | |
1145 | pr_err("%s: error getting device data\n", __func__); | |
1146 | goto error; | |
1147 | } | |
1148 | ||
7ec94453 | 1149 | list_add(&emif->node, &device_list); |
a93de288 | 1150 | emif->addressing = get_addressing_table(emif->plat_data->device_info); |
7ec94453 A |
1151 | |
1152 | /* Save pointers to each other in emif and device structures */ | |
1153 | emif->dev = &pdev->dev; | |
1154 | platform_set_drvdata(pdev, emif); | |
1155 | ||
1156 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1157 | if (!res) { | |
1158 | dev_err(emif->dev, "%s: error getting memory resource\n", | |
1159 | __func__); | |
1160 | goto error; | |
1161 | } | |
1162 | ||
1163 | emif->base = devm_request_and_ioremap(emif->dev, res); | |
1164 | if (!emif->base) { | |
1165 | dev_err(emif->dev, "%s: devm_request_and_ioremap() failed\n", | |
1166 | __func__); | |
1167 | goto error; | |
1168 | } | |
1169 | ||
68b4aee3 A |
1170 | irq = platform_get_irq(pdev, 0); |
1171 | if (irq < 0) { | |
1172 | dev_err(emif->dev, "%s: error getting IRQ resource - %d\n", | |
1173 | __func__, irq); | |
1174 | goto error; | |
1175 | } | |
1176 | ||
98231c4f | 1177 | emif_onetime_settings(emif); |
68b4aee3 A |
1178 | disable_and_clear_all_interrupts(emif); |
1179 | setup_interrupts(emif, irq); | |
1180 | ||
a93de288 A |
1181 | /* One-time actions taken on probing the first device */ |
1182 | if (!emif1) { | |
1183 | emif1 = emif; | |
1184 | spin_lock_init(&emif_lock); | |
1185 | ||
1186 | /* | |
1187 | * TODO: register notifiers for frequency and voltage | |
1188 | * change here once the respective frameworks are | |
1189 | * available | |
1190 | */ | |
1191 | } | |
1192 | ||
68b4aee3 A |
1193 | dev_info(&pdev->dev, "%s: device configured with addr = %p and IRQ%d\n", |
1194 | __func__, emif->base, irq); | |
7ec94453 A |
1195 | |
1196 | return 0; | |
1197 | error: | |
1198 | return -ENODEV; | |
1199 | } | |
1200 | ||
68b4aee3 A |
1201 | static void emif_shutdown(struct platform_device *pdev) |
1202 | { | |
1203 | struct emif_data *emif = platform_get_drvdata(pdev); | |
1204 | ||
1205 | disable_and_clear_all_interrupts(emif); | |
1206 | } | |
1207 | ||
a93de288 A |
1208 | static int get_emif_reg_values(struct emif_data *emif, u32 freq, |
1209 | struct emif_regs *regs) | |
1210 | { | |
1211 | u32 cs1_used, ip_rev, phy_type; | |
1212 | u32 cl, type; | |
1213 | const struct lpddr2_timings *timings; | |
1214 | const struct lpddr2_min_tck *min_tck; | |
1215 | const struct ddr_device_info *device_info; | |
1216 | const struct lpddr2_addressing *addressing; | |
1217 | struct emif_data *emif_for_calc; | |
1218 | struct device *dev; | |
1219 | const struct emif_custom_configs *custom_configs; | |
1220 | ||
1221 | dev = emif->dev; | |
1222 | /* | |
1223 | * If the devices on this EMIF instance is duplicate of EMIF1, | |
1224 | * use EMIF1 details for the calculation | |
1225 | */ | |
1226 | emif_for_calc = emif->duplicate ? emif1 : emif; | |
1227 | timings = get_timings_table(emif_for_calc, freq); | |
1228 | addressing = emif_for_calc->addressing; | |
1229 | if (!timings || !addressing) { | |
1230 | dev_err(dev, "%s: not enough data available for %dHz", | |
1231 | __func__, freq); | |
1232 | return -1; | |
1233 | } | |
1234 | ||
1235 | device_info = emif_for_calc->plat_data->device_info; | |
1236 | type = device_info->type; | |
1237 | cs1_used = device_info->cs1_used; | |
1238 | ip_rev = emif_for_calc->plat_data->ip_rev; | |
1239 | phy_type = emif_for_calc->plat_data->phy_type; | |
1240 | ||
1241 | min_tck = emif_for_calc->plat_data->min_tck; | |
1242 | custom_configs = emif_for_calc->plat_data->custom_configs; | |
1243 | ||
1244 | set_ddr_clk_period(freq); | |
1245 | ||
1246 | regs->ref_ctrl_shdw = get_sdram_ref_ctrl_shdw(freq, addressing); | |
1247 | regs->sdram_tim1_shdw = get_sdram_tim_1_shdw(timings, min_tck, | |
1248 | addressing); | |
1249 | regs->sdram_tim2_shdw = get_sdram_tim_2_shdw(timings, min_tck, | |
1250 | addressing, type); | |
1251 | regs->sdram_tim3_shdw = get_sdram_tim_3_shdw(timings, min_tck, | |
1252 | addressing, type, ip_rev, EMIF_NORMAL_TIMINGS); | |
1253 | ||
1254 | cl = get_cl(emif); | |
1255 | ||
1256 | if (phy_type == EMIF_PHY_TYPE_ATTILAPHY && ip_rev == EMIF_4D) { | |
1257 | regs->phy_ctrl_1_shdw = get_ddr_phy_ctrl_1_attilaphy_4d( | |
1258 | timings, freq, cl); | |
1259 | } else if (phy_type == EMIF_PHY_TYPE_INTELLIPHY && ip_rev == EMIF_4D5) { | |
1260 | regs->phy_ctrl_1_shdw = get_phy_ctrl_1_intelliphy_4d5(freq, cl); | |
1261 | regs->ext_phy_ctrl_2_shdw = get_ext_phy_ctrl_2_intelliphy_4d5(); | |
1262 | regs->ext_phy_ctrl_3_shdw = get_ext_phy_ctrl_3_intelliphy_4d5(); | |
1263 | regs->ext_phy_ctrl_4_shdw = get_ext_phy_ctrl_4_intelliphy_4d5(); | |
1264 | } else { | |
1265 | return -1; | |
1266 | } | |
1267 | ||
1268 | /* Only timeout values in pwr_mgmt_ctrl_shdw register */ | |
1269 | regs->pwr_mgmt_ctrl_shdw = | |
1270 | get_pwr_mgmt_ctrl(freq, emif_for_calc, ip_rev) & | |
1271 | (CS_TIM_MASK | SR_TIM_MASK | PD_TIM_MASK); | |
1272 | ||
1273 | if (ip_rev & EMIF_4D) { | |
1274 | regs->read_idle_ctrl_shdw_normal = | |
1275 | get_read_idle_ctrl_shdw(DDR_VOLTAGE_STABLE); | |
1276 | ||
1277 | regs->read_idle_ctrl_shdw_volt_ramp = | |
1278 | get_read_idle_ctrl_shdw(DDR_VOLTAGE_RAMPING); | |
1279 | } else if (ip_rev & EMIF_4D5) { | |
1280 | regs->dll_calib_ctrl_shdw_normal = | |
1281 | get_dll_calib_ctrl_shdw(DDR_VOLTAGE_STABLE); | |
1282 | ||
1283 | regs->dll_calib_ctrl_shdw_volt_ramp = | |
1284 | get_dll_calib_ctrl_shdw(DDR_VOLTAGE_RAMPING); | |
1285 | } | |
1286 | ||
1287 | if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) { | |
1288 | regs->ref_ctrl_shdw_derated = get_sdram_ref_ctrl_shdw(freq / 4, | |
1289 | addressing); | |
1290 | ||
1291 | regs->sdram_tim1_shdw_derated = | |
1292 | get_sdram_tim_1_shdw_derated(timings, min_tck, | |
1293 | addressing); | |
1294 | ||
1295 | regs->sdram_tim3_shdw_derated = get_sdram_tim_3_shdw(timings, | |
1296 | min_tck, addressing, type, ip_rev, | |
1297 | EMIF_DERATED_TIMINGS); | |
1298 | } | |
1299 | ||
1300 | regs->freq = freq; | |
1301 | ||
1302 | return 0; | |
1303 | } | |
1304 | ||
1305 | /* | |
1306 | * get_regs() - gets the cached emif_regs structure for a given EMIF instance | |
1307 | * given frequency(freq): | |
1308 | * | |
1309 | * As an optimisation, every EMIF instance other than EMIF1 shares the | |
1310 | * register cache with EMIF1 if the devices connected on this instance | |
1311 | * are same as that on EMIF1(indicated by the duplicate flag) | |
1312 | * | |
1313 | * If we do not have an entry corresponding to the frequency given, we | |
1314 | * allocate a new entry and calculate the values | |
1315 | * | |
1316 | * Upon finding the right reg dump, save it in curr_regs. It can be | |
1317 | * directly used for thermal de-rating and voltage ramping changes. | |
1318 | */ | |
1319 | static struct emif_regs *get_regs(struct emif_data *emif, u32 freq) | |
1320 | { | |
1321 | int i; | |
1322 | struct emif_regs **regs_cache; | |
1323 | struct emif_regs *regs = NULL; | |
1324 | struct device *dev; | |
1325 | ||
1326 | dev = emif->dev; | |
1327 | if (emif->curr_regs && emif->curr_regs->freq == freq) { | |
1328 | dev_dbg(dev, "%s: using curr_regs - %u Hz", __func__, freq); | |
1329 | return emif->curr_regs; | |
1330 | } | |
1331 | ||
1332 | if (emif->duplicate) | |
1333 | regs_cache = emif1->regs_cache; | |
1334 | else | |
1335 | regs_cache = emif->regs_cache; | |
1336 | ||
1337 | for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) { | |
1338 | if (regs_cache[i]->freq == freq) { | |
1339 | regs = regs_cache[i]; | |
1340 | dev_dbg(dev, | |
1341 | "%s: reg dump found in reg cache for %u Hz\n", | |
1342 | __func__, freq); | |
1343 | break; | |
1344 | } | |
1345 | } | |
1346 | ||
1347 | /* | |
1348 | * If we don't have an entry for this frequency in the cache create one | |
1349 | * and calculate the values | |
1350 | */ | |
1351 | if (!regs) { | |
1352 | regs = devm_kzalloc(emif->dev, sizeof(*regs), GFP_ATOMIC); | |
1353 | if (!regs) | |
1354 | return NULL; | |
1355 | ||
1356 | if (get_emif_reg_values(emif, freq, regs)) { | |
1357 | devm_kfree(emif->dev, regs); | |
1358 | return NULL; | |
1359 | } | |
1360 | ||
1361 | /* | |
1362 | * Now look for an un-used entry in the cache and save the | |
1363 | * newly created struct. If there are no free entries | |
1364 | * over-write the last entry | |
1365 | */ | |
1366 | for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) | |
1367 | ; | |
1368 | ||
1369 | if (i >= EMIF_MAX_NUM_FREQUENCIES) { | |
1370 | dev_warn(dev, "%s: regs_cache full - reusing a slot!!\n", | |
1371 | __func__); | |
1372 | i = EMIF_MAX_NUM_FREQUENCIES - 1; | |
1373 | devm_kfree(emif->dev, regs_cache[i]); | |
1374 | } | |
1375 | regs_cache[i] = regs; | |
1376 | } | |
1377 | ||
1378 | return regs; | |
1379 | } | |
1380 | ||
1381 | static void do_volt_notify_handling(struct emif_data *emif, u32 volt_state) | |
1382 | { | |
1383 | dev_dbg(emif->dev, "%s: voltage notification : %d", __func__, | |
1384 | volt_state); | |
1385 | ||
1386 | if (!emif->curr_regs) { | |
1387 | dev_err(emif->dev, | |
1388 | "%s: volt-notify before registers are ready: %d\n", | |
1389 | __func__, volt_state); | |
1390 | return; | |
1391 | } | |
1392 | ||
1393 | setup_volt_sensitive_regs(emif, emif->curr_regs, volt_state); | |
1394 | } | |
1395 | ||
1396 | /* | |
1397 | * TODO: voltage notify handling should be hooked up to | |
1398 | * regulator framework as soon as the necessary support | |
1399 | * is available in mainline kernel. This function is un-used | |
1400 | * right now. | |
1401 | */ | |
1402 | static void __attribute__((unused)) volt_notify_handling(u32 volt_state) | |
1403 | { | |
1404 | struct emif_data *emif; | |
1405 | ||
1406 | spin_lock_irqsave(&emif_lock, irq_state); | |
1407 | ||
1408 | list_for_each_entry(emif, &device_list, node) | |
1409 | do_volt_notify_handling(emif, volt_state); | |
1410 | do_freq_update(); | |
1411 | ||
1412 | spin_unlock_irqrestore(&emif_lock, irq_state); | |
1413 | } | |
1414 | ||
1415 | static void do_freq_pre_notify_handling(struct emif_data *emif, u32 new_freq) | |
1416 | { | |
1417 | struct emif_regs *regs; | |
1418 | ||
1419 | regs = get_regs(emif, new_freq); | |
1420 | if (!regs) | |
1421 | return; | |
1422 | ||
1423 | emif->curr_regs = regs; | |
1424 | ||
1425 | /* | |
1426 | * Update the shadow registers: | |
1427 | * Temperature and voltage-ramp sensitive settings are also configured | |
1428 | * in terms of DDR cycles. So, we need to update them too when there | |
1429 | * is a freq change | |
1430 | */ | |
1431 | dev_dbg(emif->dev, "%s: setting up shadow registers for %uHz", | |
1432 | __func__, new_freq); | |
1433 | setup_registers(emif, regs); | |
1434 | setup_temperature_sensitive_regs(emif, regs); | |
1435 | setup_volt_sensitive_regs(emif, regs, DDR_VOLTAGE_STABLE); | |
1436 | ||
1437 | /* | |
1438 | * Part of workaround for errata i728. See do_freq_update() | |
1439 | * for more details | |
1440 | */ | |
1441 | if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) | |
1442 | set_lpmode(emif, EMIF_LP_MODE_DISABLE); | |
1443 | } | |
1444 | ||
1445 | /* | |
1446 | * TODO: frequency notify handling should be hooked up to | |
1447 | * clock framework as soon as the necessary support is | |
1448 | * available in mainline kernel. This function is un-used | |
1449 | * right now. | |
1450 | */ | |
1451 | static void __attribute__((unused)) freq_pre_notify_handling(u32 new_freq) | |
1452 | { | |
1453 | struct emif_data *emif; | |
1454 | ||
1455 | /* | |
1456 | * NOTE: we are taking the spin-lock here and releases it | |
1457 | * only in post-notifier. This doesn't look good and | |
1458 | * Sparse complains about it, but this seems to be | |
1459 | * un-avoidable. We need to lock a sequence of events | |
1460 | * that is split between EMIF and clock framework. | |
1461 | * | |
1462 | * 1. EMIF driver updates EMIF timings in shadow registers in the | |
1463 | * frequency pre-notify callback from clock framework | |
1464 | * 2. clock framework sets up the registers for the new frequency | |
1465 | * 3. clock framework initiates a hw-sequence that updates | |
1466 | * the frequency EMIF timings synchronously. | |
1467 | * | |
1468 | * All these 3 steps should be performed as an atomic operation | |
1469 | * vis-a-vis similar sequence in the EMIF interrupt handler | |
1470 | * for temperature events. Otherwise, there could be race | |
1471 | * conditions that could result in incorrect EMIF timings for | |
1472 | * a given frequency | |
1473 | */ | |
1474 | spin_lock_irqsave(&emif_lock, irq_state); | |
1475 | ||
1476 | list_for_each_entry(emif, &device_list, node) | |
1477 | do_freq_pre_notify_handling(emif, new_freq); | |
1478 | } | |
1479 | ||
1480 | static void do_freq_post_notify_handling(struct emif_data *emif) | |
1481 | { | |
1482 | /* | |
1483 | * Part of workaround for errata i728. See do_freq_update() | |
1484 | * for more details | |
1485 | */ | |
1486 | if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) | |
1487 | set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH); | |
1488 | } | |
1489 | ||
1490 | /* | |
1491 | * TODO: frequency notify handling should be hooked up to | |
1492 | * clock framework as soon as the necessary support is | |
1493 | * available in mainline kernel. This function is un-used | |
1494 | * right now. | |
1495 | */ | |
1496 | static void __attribute__((unused)) freq_post_notify_handling(void) | |
1497 | { | |
1498 | struct emif_data *emif; | |
1499 | ||
1500 | list_for_each_entry(emif, &device_list, node) | |
1501 | do_freq_post_notify_handling(emif); | |
1502 | ||
1503 | /* | |
1504 | * Lock is done in pre-notify handler. See freq_pre_notify_handling() | |
1505 | * for more details | |
1506 | */ | |
1507 | spin_unlock_irqrestore(&emif_lock, irq_state); | |
1508 | } | |
1509 | ||
7ec94453 | 1510 | static struct platform_driver emif_driver = { |
68b4aee3 | 1511 | .shutdown = emif_shutdown, |
7ec94453 A |
1512 | .driver = { |
1513 | .name = "emif", | |
1514 | }, | |
1515 | }; | |
1516 | ||
1517 | static int __init_or_module emif_register(void) | |
1518 | { | |
1519 | return platform_driver_probe(&emif_driver, emif_probe); | |
1520 | } | |
1521 | ||
1522 | static void __exit emif_unregister(void) | |
1523 | { | |
1524 | platform_driver_unregister(&emif_driver); | |
1525 | } | |
1526 | ||
1527 | module_init(emif_register); | |
1528 | module_exit(emif_unregister); | |
1529 | MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver"); | |
1530 | MODULE_LICENSE("GPL"); | |
1531 | MODULE_ALIAS("platform:emif"); | |
1532 | MODULE_AUTHOR("Texas Instruments Inc"); |