[mirror_ubuntu-bionic-kernel.git] / drivers / memory / fsl_ifc.c

/*
 * Copyright 2011 Freescale Semiconductor, Inc
 *
 * Freescale Integrated Flash Controller
 *
 * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/compiler.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/fsl_ifc.h>
#include <asm/prom.h>

struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
EXPORT_SYMBOL(fsl_ifc_ctrl_dev);

/*
 * convert_ifc_address - convert the base address
 * @addr_base:	base address of the memory bank
 */
unsigned int convert_ifc_address(phys_addr_t addr_base)
{
	return addr_base & CSPR_BA;
}
EXPORT_SYMBOL(convert_ifc_address);

/*
 * fsl_ifc_find - find IFC bank
 * @addr_base:	base address of the memory bank
 *
 * This function walks IFC banks comparing "Base address" field of the CSPR
 * registers with the supplied addr_base argument. When bases match this
 * function returns bank number (starting with 0), otherwise it returns
 * appropriate errno value.
 */
int fsl_ifc_find(phys_addr_t addr_base)
{
	int i = 0;

	if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
		return -ENODEV;

	for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
		u32 cspr = in_be32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr);
		if (cspr & CSPR_V && (cspr & CSPR_BA) ==
				convert_ifc_address(addr_base))
			return i;
	}

	return -ENOENT;
}
EXPORT_SYMBOL(fsl_ifc_find);

static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
{
	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;

	/*
	 * Clear all the common status and event registers
	 */
	if (in_be32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
		out_be32(&ifc->cm_evter_stat, IFC_CM_EVTER_STAT_CSER);

	/* enable all error and events */
	out_be32(&ifc->cm_evter_en, IFC_CM_EVTER_EN_CSEREN);

	/* enable all error and event interrupts */
	out_be32(&ifc->cm_evter_intr_en, IFC_CM_EVTER_INTR_EN_CSERIREN);
	out_be32(&ifc->cm_erattr0, 0x0);
	out_be32(&ifc->cm_erattr1, 0x0);

	return 0;
}

static int fsl_ifc_ctrl_remove(struct platform_device *dev)
{
	struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev);

	free_irq(ctrl->nand_irq, ctrl);
	free_irq(ctrl->irq, ctrl);

	irq_dispose_mapping(ctrl->nand_irq);
	irq_dispose_mapping(ctrl->irq);

	iounmap(ctrl->regs);

	dev_set_drvdata(&dev->dev, NULL);
	kfree(ctrl);

	return 0;
}

/*
 * NAND events are split between an operational interrupt which only
 * receives OPC, and an error interrupt that receives everything else,
 * including non-NAND errors.  Whichever interrupt gets to it first
 * records the status and wakes the wait queue.
 */
static DEFINE_SPINLOCK(nand_irq_lock);

static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
{
	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
	unsigned long flags;
	u32 stat;

	spin_lock_irqsave(&nand_irq_lock, flags);

	stat = in_be32(&ifc->ifc_nand.nand_evter_stat);
	if (stat) {
		out_be32(&ifc->ifc_nand.nand_evter_stat, stat);
		ctrl->nand_stat = stat;
		wake_up(&ctrl->nand_wait);
	}

	spin_unlock_irqrestore(&nand_irq_lock, flags);

	return stat;
}

static irqreturn_t fsl_ifc_nand_irq(int irqno, void *data)
{
	struct fsl_ifc_ctrl *ctrl = data;

	if (check_nand_stat(ctrl))
		return IRQ_HANDLED;

	return IRQ_NONE;
}

/*
 * NOTE: This interrupt is used to report ifc events of various kinds,
 * such as transaction errors on the chipselects.
 */
static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
{
	struct fsl_ifc_ctrl *ctrl = data;
	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
	u32 err_axiid, err_srcid, status, cs_err, err_addr;
	irqreturn_t ret = IRQ_NONE;

	/* read for chip select error */
	cs_err = in_be32(&ifc->cm_evter_stat);
	if (cs_err) {
		dev_err(ctrl->dev, "transaction sent to IFC is not mapped to"
				"any memory bank 0x%08X\n", cs_err);
		/* clear the chip select error */
		out_be32(&ifc->cm_evter_stat, IFC_CM_EVTER_STAT_CSER);

		/* read error attribute registers print the error information */
		status = in_be32(&ifc->cm_erattr0);
		err_addr = in_be32(&ifc->cm_erattr1);

		if (status & IFC_CM_ERATTR0_ERTYP_READ)
			dev_err(ctrl->dev, "Read transaction error"
				"CM_ERATTR0 0x%08X\n", status);
		else
			dev_err(ctrl->dev, "Write transaction error"
				"CM_ERATTR0 0x%08X\n", status);

		err_axiid = (status & IFC_CM_ERATTR0_ERAID) >>
					IFC_CM_ERATTR0_ERAID_SHIFT;
		dev_err(ctrl->dev, "AXI ID of the error"
					"transaction 0x%08X\n", err_axiid);

		err_srcid = (status & IFC_CM_ERATTR0_ESRCID) >>
					IFC_CM_ERATTR0_ESRCID_SHIFT;
		dev_err(ctrl->dev, "SRC ID of the error"
					"transaction 0x%08X\n", err_srcid);

		dev_err(ctrl->dev, "Transaction Address corresponding to error"
					"ERADDR 0x%08X\n", err_addr);

		ret = IRQ_HANDLED;
	}

	if (check_nand_stat(ctrl))
		ret = IRQ_HANDLED;

	return ret;
}

/*
 * fsl_ifc_ctrl_probe
 *
 * called by device layer when it finds a device matching
 * one our driver can handled. This code allocates all of
 * the resources needed for the controller only.  The
 * resources for the NAND banks themselves are allocated
 * in the chip probe function.
*/
static int fsl_ifc_ctrl_probe(struct platform_device *dev)
{
	int ret = 0;
	int version, banks;

	dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");

	fsl_ifc_ctrl_dev = kzalloc(sizeof(*fsl_ifc_ctrl_dev), GFP_KERNEL);
	if (!fsl_ifc_ctrl_dev)
		return -ENOMEM;

	dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev);

	/* IOMAP the entire IFC region */
	fsl_ifc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
	if (!fsl_ifc_ctrl_dev->regs) {
		dev_err(&dev->dev, "failed to get memory region\n");
		ret = -ENODEV;
		goto err;
	}

	version = ioread32be(&fsl_ifc_ctrl_dev->regs->ifc_rev) &
			FSL_IFC_VERSION_MASK;
	banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
	dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
		version >> 24, (version >> 16) & 0xf, banks);

	fsl_ifc_ctrl_dev->version = version;
	fsl_ifc_ctrl_dev->banks = banks;

	/* get the Controller level irq */
	fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
	if (fsl_ifc_ctrl_dev->irq == NO_IRQ) {
		dev_err(&dev->dev, "failed to get irq resource "
							"for IFC\n");
		ret = -ENODEV;
		goto err;
	}

	/* get the nand machine irq */
	fsl_ifc_ctrl_dev->nand_irq =
			irq_of_parse_and_map(dev->dev.of_node, 1);

	fsl_ifc_ctrl_dev->dev = &dev->dev;

	ret = fsl_ifc_ctrl_init(fsl_ifc_ctrl_dev);
	if (ret < 0)
		goto err;

	init_waitqueue_head(&fsl_ifc_ctrl_dev->nand_wait);

	ret = request_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_irq, IRQF_SHARED,
			  "fsl-ifc", fsl_ifc_ctrl_dev);
	if (ret != 0) {
		dev_err(&dev->dev, "failed to install irq (%d)\n",
			fsl_ifc_ctrl_dev->irq);
		goto err_irq;
	}

	if (fsl_ifc_ctrl_dev->nand_irq) {
		ret = request_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_nand_irq,
				0, "fsl-ifc-nand", fsl_ifc_ctrl_dev);
		if (ret != 0) {
			dev_err(&dev->dev, "failed to install irq (%d)\n",
				fsl_ifc_ctrl_dev->nand_irq);
			goto err_nandirq;
		}
	}

	return 0;

err_nandirq:
	free_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_ctrl_dev);
	irq_dispose_mapping(fsl_ifc_ctrl_dev->nand_irq);
err_irq:
	free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev);
	irq_dispose_mapping(fsl_ifc_ctrl_dev->irq);
err:
	return ret;
}

static const struct of_device_id fsl_ifc_match[] = {
	{
		.compatible = "fsl,ifc",
	},
	{},
};

static struct platform_driver fsl_ifc_ctrl_driver = {
	.driver = {
		.name	= "fsl-ifc",
		.of_match_table = fsl_ifc_match,
	},
	.probe       = fsl_ifc_ctrl_probe,
	.remove      = fsl_ifc_ctrl_remove,
};

static int __init fsl_ifc_init(void)
{
	return platform_driver_register(&fsl_ifc_ctrl_driver);
}
subsys_initcall(fsl_ifc_init);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Freescale Semiconductor");
MODULE_DESCRIPTION("Freescale Integrated Flash Controller driver");
Commit	Line	Data
a20cbdef PK	1	/*
	2	* Copyright 2011 Freescale Semiconductor, Inc
	3	*
	4	* Freescale Integrated Flash Controller
	5	*
	6	* Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
a20cbdef PK	22	#include <linux/module.h>
	23	#include <linux/kernel.h>
	24	#include <linux/compiler.h>
	25	#include <linux/spinlock.h>
	26	#include <linux/types.h>
	27	#include <linux/slab.h>
	28	#include <linux/io.h>
	29	#include <linux/of.h>
	30	#include <linux/of_device.h>
	31	#include <linux/platform_device.h>
d2ae2e20	32	#include <linux/fsl_ifc.h>
a20cbdef	33	#include <asm/prom.h>
a20cbdef PK	34
	35	struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
	36	EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
	37
	38	/*
	39	* convert_ifc_address - convert the base address
	40	* @addr_base: base address of the memory bank
	41	*/
	42	unsigned int convert_ifc_address(phys_addr_t addr_base)
	43	{
	44	return addr_base & CSPR_BA;
	45	}
	46	EXPORT_SYMBOL(convert_ifc_address);
	47
	48	/*
	49	* fsl_ifc_find - find IFC bank
	50	* @addr_base: base address of the memory bank
	51	*
	52	* This function walks IFC banks comparing "Base address" field of the CSPR
	53	* registers with the supplied addr_base argument. When bases match this
	54	* function returns bank number (starting with 0), otherwise it returns
	55	* appropriate errno value.
	56	*/
	57	int fsl_ifc_find(phys_addr_t addr_base)
	58	{
	59	int i = 0;
	60
	61	if (!fsl_ifc_ctrl_dev \|\| !fsl_ifc_ctrl_dev->regs)
	62	return -ENODEV;
	63
09691661	64	for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
8998a030	65	u32 cspr = in_be32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr);
a20cbdef PK	66	if (cspr & CSPR_V && (cspr & CSPR_BA) ==
	67	convert_ifc_address(addr_base))
	68	return i;
	69	}
	70
	71	return -ENOENT;
	72	}
	73	EXPORT_SYMBOL(fsl_ifc_find);
	74
cad5cef6	75	static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
a20cbdef PK	76	{
	77	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
	78
	79	/*
	80	* Clear all the common status and event registers
	81	*/
	82	if (in_be32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
	83	out_be32(&ifc->cm_evter_stat, IFC_CM_EVTER_STAT_CSER);
	84
	85	/* enable all error and events */
	86	out_be32(&ifc->cm_evter_en, IFC_CM_EVTER_EN_CSEREN);
	87
	88	/* enable all error and event interrupts */
	89	out_be32(&ifc->cm_evter_intr_en, IFC_CM_EVTER_INTR_EN_CSERIREN);
	90	out_be32(&ifc->cm_erattr0, 0x0);
	91	out_be32(&ifc->cm_erattr1, 0x0);
	92
	93	return 0;
	94	}
	95
	96	static int fsl_ifc_ctrl_remove(struct platform_device *dev)
	97	{
	98	struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev);
	99
	100	free_irq(ctrl->nand_irq, ctrl);
	101	free_irq(ctrl->irq, ctrl);
	102
	103	irq_dispose_mapping(ctrl->nand_irq);
	104	irq_dispose_mapping(ctrl->irq);
	105
	106	iounmap(ctrl->regs);
	107
	108	dev_set_drvdata(&dev->dev, NULL);
	109	kfree(ctrl);
	110
	111	return 0;
	112	}
	113
	114	/*
	115	* NAND events are split between an operational interrupt which only
	116	* receives OPC, and an error interrupt that receives everything else,
	117	* including non-NAND errors. Whichever interrupt gets to it first
	118	* records the status and wakes the wait queue.
	119	*/
	120	static DEFINE_SPINLOCK(nand_irq_lock);
	121
	122	static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
	123	{
	124	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
	125	unsigned long flags;
	126	u32 stat;
	127
	128	spin_lock_irqsave(&nand_irq_lock, flags);
	129
	130	stat = in_be32(&ifc->ifc_nand.nand_evter_stat);
	131	if (stat) {
	132	out_be32(&ifc->ifc_nand.nand_evter_stat, stat);
	133	ctrl->nand_stat = stat;
	134	wake_up(&ctrl->nand_wait);
	135	}
	136
	137	spin_unlock_irqrestore(&nand_irq_lock, flags);
	138
	139	return stat;
140	}
141
142	static irqreturn_t fsl_ifc_nand_irq(int irqno, void *data)
143	{
144	struct fsl_ifc_ctrl *ctrl = data;
145
146	if (check_nand_stat(ctrl))
147	return IRQ_HANDLED;
148
149	return IRQ_NONE;
150	}
151
152	/*
153	* NOTE: This interrupt is used to report ifc events of various kinds,
154	* such as transaction errors on the chipselects.
155	*/
156	static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
157	{
158	struct fsl_ifc_ctrl *ctrl = data;
159	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
160	u32 err_axiid, err_srcid, status, cs_err, err_addr;
161	irqreturn_t ret = IRQ_NONE;
162
163	/* read for chip select error */
164	cs_err = in_be32(&ifc->cm_evter_stat);
165	if (cs_err) {
166	dev_err(ctrl->dev, "transaction sent to IFC is not mapped to"
167	"any memory bank 0x%08X\n", cs_err);
168	/* clear the chip select error */
169	out_be32(&ifc->cm_evter_stat, IFC_CM_EVTER_STAT_CSER);
170
171	/* read error attribute registers print the error information */
172	status = in_be32(&ifc->cm_erattr0);
173	err_addr = in_be32(&ifc->cm_erattr1);
174
175	if (status & IFC_CM_ERATTR0_ERTYP_READ)
176	dev_err(ctrl->dev, "Read transaction error"
177	"CM_ERATTR0 0x%08X\n", status);
178	else
179	dev_err(ctrl->dev, "Write transaction error"
180	"CM_ERATTR0 0x%08X\n", status);
181
182	err_axiid = (status & IFC_CM_ERATTR0_ERAID) >>
183	IFC_CM_ERATTR0_ERAID_SHIFT;
184	dev_err(ctrl->dev, "AXI ID of the error"
185	"transaction 0x%08X\n", err_axiid);
186
187	err_srcid = (status & IFC_CM_ERATTR0_ESRCID) >>
188	IFC_CM_ERATTR0_ESRCID_SHIFT;
189	dev_err(ctrl->dev, "SRC ID of the error"
190	"transaction 0x%08X\n", err_srcid);
191
192	dev_err(ctrl->dev, "Transaction Address corresponding to error"
193	"ERADDR 0x%08X\n", err_addr);
194
195	ret = IRQ_HANDLED;
196	}
197
198	if (check_nand_stat(ctrl))
199	ret = IRQ_HANDLED;
200
201	return ret;
202	}
203
204	/*
205	* fsl_ifc_ctrl_probe
206	*
207	* called by device layer when it finds a device matching
208	* one our driver can handled. This code allocates all of
209	* the resources needed for the controller only. The
210	* resources for the NAND banks themselves are allocated
211	* in the chip probe function.
212	*/
cad5cef6	213	static int fsl_ifc_ctrl_probe(struct platform_device *dev)
a20cbdef PK	214	{
a20cbdef PK	215	int ret = 0;
09691661	216	int version, banks;
a20cbdef PK	217
	218	dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");
	219
	220	fsl_ifc_ctrl_dev = kzalloc(sizeof(*fsl_ifc_ctrl_dev), GFP_KERNEL);
	221	if (!fsl_ifc_ctrl_dev)
	222	return -ENOMEM;
	223
	224	dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev);
	225
	226	/* IOMAP the entire IFC region */
	227	fsl_ifc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
	228	if (!fsl_ifc_ctrl_dev->regs) {
	229	dev_err(&dev->dev, "failed to get memory region\n");
	230	ret = -ENODEV;
	231	goto err;
	232	}
	233
09691661 AS	234	version = ioread32be(&fsl_ifc_ctrl_dev->regs->ifc_rev) &
	235	FSL_IFC_VERSION_MASK;
	236	banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
	237	dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
	238	version >> 24, (version >> 16) & 0xf, banks);
	239
	240	fsl_ifc_ctrl_dev->version = version;
	241	fsl_ifc_ctrl_dev->banks = banks;
	242
a20cbdef PK	243	/* get the Controller level irq */
	244	fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
	245	if (fsl_ifc_ctrl_dev->irq == NO_IRQ) {
	246	dev_err(&dev->dev, "failed to get irq resource "
	247	"for IFC\n");
	248	ret = -ENODEV;
	249	goto err;
	250	}
	251
	252	/* get the nand machine irq */
	253	fsl_ifc_ctrl_dev->nand_irq =
	254	irq_of_parse_and_map(dev->dev.of_node, 1);
a20cbdef PK	255
	256	fsl_ifc_ctrl_dev->dev = &dev->dev;
	257
	258	ret = fsl_ifc_ctrl_init(fsl_ifc_ctrl_dev);
	259	if (ret < 0)
	260	goto err;
	261
	262	init_waitqueue_head(&fsl_ifc_ctrl_dev->nand_wait);
	263
	264	ret = request_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_irq, IRQF_SHARED,
	265	"fsl-ifc", fsl_ifc_ctrl_dev);
	266	if (ret != 0) {
	267	dev_err(&dev->dev, "failed to install irq (%d)\n",
	268	fsl_ifc_ctrl_dev->irq);
	269	goto err_irq;
	270	}
	271
721c0705 PK	272	if (fsl_ifc_ctrl_dev->nand_irq) {
	273	ret = request_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_nand_irq,
	274	0, "fsl-ifc-nand", fsl_ifc_ctrl_dev);
	275	if (ret != 0) {
	276	dev_err(&dev->dev, "failed to install irq (%d)\n",
	277	fsl_ifc_ctrl_dev->nand_irq);
	278	goto err_nandirq;
	279	}
a20cbdef PK	280	}
	281
	282	return 0;
	283
	284	err_nandirq:
	285	free_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_ctrl_dev);
	286	irq_dispose_mapping(fsl_ifc_ctrl_dev->nand_irq);
	287	err_irq:
	288	free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev);
	289	irq_dispose_mapping(fsl_ifc_ctrl_dev->irq);
	290	err:
	291	return ret;
	292	}
	293
	294	static const struct of_device_id fsl_ifc_match[] = {
	295	{
	296	.compatible = "fsl,ifc",
	297	},
	298	{},
	299	};
	300
	301	static struct platform_driver fsl_ifc_ctrl_driver = {
	302	.driver = {
	303	.name = "fsl-ifc",
	304	.of_match_table = fsl_ifc_match,
	305	},
	306	.probe = fsl_ifc_ctrl_probe,
	307	.remove = fsl_ifc_ctrl_remove,
	308	};
	309
d2ae2e20 PK	310	static int __init fsl_ifc_init(void)
	311	{
	312	return platform_driver_register(&fsl_ifc_ctrl_driver);
	313	}
	314	subsys_initcall(fsl_ifc_init);
a20cbdef PK	315
	316	MODULE_LICENSE("GPL");
	317	MODULE_AUTHOR("Freescale Semiconductor");
	318	MODULE_DESCRIPTION("Freescale Integrated Flash Controller driver");