[mirror_ubuntu-focal-kernel.git] / drivers / memory / fsl_ifc.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2011 Freescale Semiconductor, Inc
 *
 * Freescale Integrated Flash Controller
 *
 * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/compiler.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/fsl_ifc.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
EXPORT_SYMBOL(fsl_ifc_ctrl_dev);

/*
 * convert_ifc_address - convert the base address
 * @addr_base:	base address of the memory bank
 */
unsigned int convert_ifc_address(phys_addr_t addr_base)
{
	return addr_base & CSPR_BA;
}
EXPORT_SYMBOL(convert_ifc_address);

/*
 * fsl_ifc_find - find IFC bank
 * @addr_base:	base address of the memory bank
 *
 * This function walks IFC banks comparing "Base address" field of the CSPR
 * registers with the supplied addr_base argument. When bases match this
 * function returns bank number (starting with 0), otherwise it returns
 * appropriate errno value.
 */
int fsl_ifc_find(phys_addr_t addr_base)
{
	int i = 0;

	if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->gregs)
		return -ENODEV;

	for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
		u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->gregs->cspr_cs[i].cspr);
		if (cspr & CSPR_V && (cspr & CSPR_BA) ==
				convert_ifc_address(addr_base))
			return i;
	}

	return -ENOENT;
}
EXPORT_SYMBOL(fsl_ifc_find);

static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
{
	struct fsl_ifc_global __iomem *ifc = ctrl->gregs;

	/*
	 * Clear all the common status and event registers
	 */
	if (ifc_in32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
		ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);

	/* enable all error and events */
	ifc_out32(IFC_CM_EVTER_EN_CSEREN, &ifc->cm_evter_en);

	/* enable all error and event interrupts */
	ifc_out32(IFC_CM_EVTER_INTR_EN_CSERIREN, &ifc->cm_evter_intr_en);
	ifc_out32(0x0, &ifc->cm_erattr0);
	ifc_out32(0x0, &ifc->cm_erattr1);

	return 0;
}

static int fsl_ifc_ctrl_remove(struct platform_device *dev)
{
	struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev);

	free_irq(ctrl->nand_irq, ctrl);
	free_irq(ctrl->irq, ctrl);

	irq_dispose_mapping(ctrl->nand_irq);
	irq_dispose_mapping(ctrl->irq);

	iounmap(ctrl->gregs);

	dev_set_drvdata(&dev->dev, NULL);

	return 0;
}

/*
 * NAND events are split between an operational interrupt which only
 * receives OPC, and an error interrupt that receives everything else,
 * including non-NAND errors.  Whichever interrupt gets to it first
 * records the status and wakes the wait queue.
 */
static DEFINE_SPINLOCK(nand_irq_lock);

static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
{
	struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
	unsigned long flags;
	u32 stat;

	spin_lock_irqsave(&nand_irq_lock, flags);

	stat = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
	if (stat) {
		ifc_out32(stat, &ifc->ifc_nand.nand_evter_stat);
		ctrl->nand_stat = stat;
		wake_up(&ctrl->nand_wait);
	}

	spin_unlock_irqrestore(&nand_irq_lock, flags);

	return stat;
}

static irqreturn_t fsl_ifc_nand_irq(int irqno, void *data)
{
	struct fsl_ifc_ctrl *ctrl = data;

	if (check_nand_stat(ctrl))
		return IRQ_HANDLED;

	return IRQ_NONE;
}

/*
 * NOTE: This interrupt is used to report ifc events of various kinds,
 * such as transaction errors on the chipselects.
 */
static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
{
	struct fsl_ifc_ctrl *ctrl = data;
	struct fsl_ifc_global __iomem *ifc = ctrl->gregs;
	u32 err_axiid, err_srcid, status, cs_err, err_addr;
	irqreturn_t ret = IRQ_NONE;

	/* read for chip select error */
	cs_err = ifc_in32(&ifc->cm_evter_stat);
	if (cs_err) {
		dev_err(ctrl->dev, "transaction sent to IFC is not mapped to"
				"any memory bank 0x%08X\n", cs_err);
		/* clear the chip select error */
		ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);

		/* read error attribute registers print the error information */
		status = ifc_in32(&ifc->cm_erattr0);
		err_addr = ifc_in32(&ifc->cm_erattr1);

		if (status & IFC_CM_ERATTR0_ERTYP_READ)
			dev_err(ctrl->dev, "Read transaction error"
				"CM_ERATTR0 0x%08X\n", status);
		else
			dev_err(ctrl->dev, "Write transaction error"
				"CM_ERATTR0 0x%08X\n", status);

		err_axiid = (status & IFC_CM_ERATTR0_ERAID) >>
					IFC_CM_ERATTR0_ERAID_SHIFT;
		dev_err(ctrl->dev, "AXI ID of the error"
					"transaction 0x%08X\n", err_axiid);

		err_srcid = (status & IFC_CM_ERATTR0_ESRCID) >>
					IFC_CM_ERATTR0_ESRCID_SHIFT;
		dev_err(ctrl->dev, "SRC ID of the error"
					"transaction 0x%08X\n", err_srcid);

		dev_err(ctrl->dev, "Transaction Address corresponding to error"
					"ERADDR 0x%08X\n", err_addr);

		ret = IRQ_HANDLED;
	}

	if (check_nand_stat(ctrl))
		ret = IRQ_HANDLED;

	return ret;
}

/*
 * fsl_ifc_ctrl_probe
 *
 * called by device layer when it finds a device matching
 * one our driver can handled. This code allocates all of
 * the resources needed for the controller only.  The
 * resources for the NAND banks themselves are allocated
 * in the chip probe function.
*/
static int fsl_ifc_ctrl_probe(struct platform_device *dev)
{
	int ret = 0;
	int version, banks;
	void __iomem *addr;

	dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");

	fsl_ifc_ctrl_dev = devm_kzalloc(&dev->dev, sizeof(*fsl_ifc_ctrl_dev),
					GFP_KERNEL);
	if (!fsl_ifc_ctrl_dev)
		return -ENOMEM;

	dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev);

	/* IOMAP the entire IFC region */
	fsl_ifc_ctrl_dev->gregs = of_iomap(dev->dev.of_node, 0);
	if (!fsl_ifc_ctrl_dev->gregs) {
		dev_err(&dev->dev, "failed to get memory region\n");
		return -ENODEV;
	}

	if (of_property_read_bool(dev->dev.of_node, "little-endian")) {
		fsl_ifc_ctrl_dev->little_endian = true;
		dev_dbg(&dev->dev, "IFC REGISTERS are LITTLE endian\n");
	} else {
		fsl_ifc_ctrl_dev->little_endian = false;
		dev_dbg(&dev->dev, "IFC REGISTERS are BIG endian\n");
	}

	version = ifc_in32(&fsl_ifc_ctrl_dev->gregs->ifc_rev) &
			FSL_IFC_VERSION_MASK;

	banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
	dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
		version >> 24, (version >> 16) & 0xf, banks);

	fsl_ifc_ctrl_dev->version = version;
	fsl_ifc_ctrl_dev->banks = banks;

	addr = fsl_ifc_ctrl_dev->gregs;
	if (version >= FSL_IFC_VERSION_2_0_0)
		addr += PGOFFSET_64K;
	else
		addr += PGOFFSET_4K;
	fsl_ifc_ctrl_dev->rregs = addr;

	/* get the Controller level irq */
	fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
	if (fsl_ifc_ctrl_dev->irq == 0) {
		dev_err(&dev->dev, "failed to get irq resource "
							"for IFC\n");
		ret = -ENODEV;
		goto err;
	}

	/* get the nand machine irq */
	fsl_ifc_ctrl_dev->nand_irq =
			irq_of_parse_and_map(dev->dev.of_node, 1);

	fsl_ifc_ctrl_dev->dev = &dev->dev;

	ret = fsl_ifc_ctrl_init(fsl_ifc_ctrl_dev);
	if (ret < 0)
		goto err_unmap_nandirq;

	init_waitqueue_head(&fsl_ifc_ctrl_dev->nand_wait);

	ret = request_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_irq, IRQF_SHARED,
			  "fsl-ifc", fsl_ifc_ctrl_dev);
	if (ret != 0) {
		dev_err(&dev->dev, "failed to install irq (%d)\n",
			fsl_ifc_ctrl_dev->irq);
		goto err_unmap_nandirq;
	}

	if (fsl_ifc_ctrl_dev->nand_irq) {
		ret = request_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_nand_irq,
				0, "fsl-ifc-nand", fsl_ifc_ctrl_dev);
		if (ret != 0) {
			dev_err(&dev->dev, "failed to install irq (%d)\n",
				fsl_ifc_ctrl_dev->nand_irq);
			goto err_free_irq;
		}
	}

	return 0;

err_free_irq:
	free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev);
err_unmap_nandirq:
	irq_dispose_mapping(fsl_ifc_ctrl_dev->nand_irq);
	irq_dispose_mapping(fsl_ifc_ctrl_dev->irq);
err:
	iounmap(fsl_ifc_ctrl_dev->gregs);
	return ret;
}

static const struct of_device_id fsl_ifc_match[] = {
	{
		.compatible = "fsl,ifc",
	},
	{},
};

static struct platform_driver fsl_ifc_ctrl_driver = {
	.driver = {
		.name	= "fsl-ifc",
		.of_match_table = fsl_ifc_match,
	},
	.probe       = fsl_ifc_ctrl_probe,
	.remove      = fsl_ifc_ctrl_remove,
};

static int __init fsl_ifc_init(void)
{
	return platform_driver_register(&fsl_ifc_ctrl_driver);
}
subsys_initcall(fsl_ifc_init);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Freescale Semiconductor");
MODULE_DESCRIPTION("Freescale Integrated Flash Controller driver");
Commit	Line	Data
74ba9207	1	// SPDX-License-Identifier: GPL-2.0-or-later
a20cbdef PK	2	/*
	3	* Copyright 2011 Freescale Semiconductor, Inc
	4	*
	5	* Freescale Integrated Flash Controller
	6	*
	7	* Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
a20cbdef	8	*/
a20cbdef PK	9	#include <linux/module.h>
	10	#include <linux/kernel.h>
	11	#include <linux/compiler.h>
c4aa1937	12	#include <linux/sched.h>
a20cbdef PK	13	#include <linux/spinlock.h>
	14	#include <linux/types.h>
	15	#include <linux/slab.h>
	16	#include <linux/io.h>
	17	#include <linux/of.h>
	18	#include <linux/of_device.h>
	19	#include <linux/platform_device.h>
d2ae2e20	20	#include <linux/fsl_ifc.h>
8ea126bc RD	21	#include <linux/irqdomain.h>
	22	#include <linux/of_address.h>
	23	#include <linux/of_irq.h>
a20cbdef PK	24
	25	struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
	26	EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
	27
	28	/*
	29	* convert_ifc_address - convert the base address
	30	* @addr_base: base address of the memory bank
	31	*/
	32	unsigned int convert_ifc_address(phys_addr_t addr_base)
	33	{
	34	return addr_base & CSPR_BA;
	35	}
	36	EXPORT_SYMBOL(convert_ifc_address);
	37
	38	/*
	39	* fsl_ifc_find - find IFC bank
	40	* @addr_base: base address of the memory bank
	41	*
	42	* This function walks IFC banks comparing "Base address" field of the CSPR
	43	* registers with the supplied addr_base argument. When bases match this
	44	* function returns bank number (starting with 0), otherwise it returns
	45	* appropriate errno value.
	46	*/
	47	int fsl_ifc_find(phys_addr_t addr_base)
	48	{
	49	int i = 0;
	50
7a654172	51	if (!fsl_ifc_ctrl_dev \|\| !fsl_ifc_ctrl_dev->gregs)
a20cbdef PK	52	return -ENODEV;
a20cbdef PK	53
09691661	54	for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
7a654172	55	u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->gregs->cspr_cs[i].cspr);
a20cbdef PK	56	if (cspr & CSPR_V && (cspr & CSPR_BA) ==
	57	convert_ifc_address(addr_base))
	58	return i;
	59	}
	60
	61	return -ENOENT;
	62	}
	63	EXPORT_SYMBOL(fsl_ifc_find);
	64
cad5cef6	65	static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
a20cbdef	66	{
7a654172	67	struct fsl_ifc_global __iomem *ifc = ctrl->gregs;
a20cbdef PK	68
	69	/*
	70	* Clear all the common status and event registers
	71	*/
cf184dc2 JS	72	if (ifc_in32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
cf184dc2 JS	73	ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
a20cbdef PK	74
a20cbdef PK	75	/* enable all error and events */
cf184dc2	76	ifc_out32(IFC_CM_EVTER_EN_CSEREN, &ifc->cm_evter_en);
a20cbdef PK	77
a20cbdef PK	78	/* enable all error and event interrupts */
cf184dc2 JS	79	ifc_out32(IFC_CM_EVTER_INTR_EN_CSERIREN, &ifc->cm_evter_intr_en);
	80	ifc_out32(0x0, &ifc->cm_erattr0);
	81	ifc_out32(0x0, &ifc->cm_erattr1);
a20cbdef PK	82
	83	return 0;
	84	}
	85
	86	static int fsl_ifc_ctrl_remove(struct platform_device *dev)
	87	{
	88	struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev);
	89
	90	free_irq(ctrl->nand_irq, ctrl);
	91	free_irq(ctrl->irq, ctrl);
	92
	93	irq_dispose_mapping(ctrl->nand_irq);
	94	irq_dispose_mapping(ctrl->irq);
	95
7a654172	96	iounmap(ctrl->gregs);
a20cbdef PK	97
a20cbdef PK	98	dev_set_drvdata(&dev->dev, NULL);
a20cbdef PK	99
	100	return 0;
	101	}
	102
	103	/*
	104	* NAND events are split between an operational interrupt which only
	105	* receives OPC, and an error interrupt that receives everything else,
	106	* including non-NAND errors. Whichever interrupt gets to it first
	107	* records the status and wakes the wait queue.
	108	*/
	109	static DEFINE_SPINLOCK(nand_irq_lock);
	110
	111	static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
	112	{
7a654172	113	struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
a20cbdef PK	114	unsigned long flags;
	115	u32 stat;
	116
	117	spin_lock_irqsave(&nand_irq_lock, flags);
	118
cf184dc2	119	stat = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
a20cbdef	120	if (stat) {
cf184dc2	121	ifc_out32(stat, &ifc->ifc_nand.nand_evter_stat);
a20cbdef PK	122	ctrl->nand_stat = stat;
	123	wake_up(&ctrl->nand_wait);
	124	}
	125
	126	spin_unlock_irqrestore(&nand_irq_lock, flags);
	127
	128	return stat;
	129	}
	130
	131	static irqreturn_t fsl_ifc_nand_irq(int irqno, void *data)
	132	{
	133	struct fsl_ifc_ctrl *ctrl = data;
	134
	135	if (check_nand_stat(ctrl))
	136	return IRQ_HANDLED;
	137
	138	return IRQ_NONE;
	139	}
	140
	141	/*
	142	* NOTE: This interrupt is used to report ifc events of various kinds,
	143	* such as transaction errors on the chipselects.
	144	*/
	145	static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
	146	{
	147	struct fsl_ifc_ctrl *ctrl = data;
7a654172	148	struct fsl_ifc_global __iomem *ifc = ctrl->gregs;
a20cbdef PK	149	u32 err_axiid, err_srcid, status, cs_err, err_addr;
	150	irqreturn_t ret = IRQ_NONE;
	151
	152	/* read for chip select error */
cf184dc2	153	cs_err = ifc_in32(&ifc->cm_evter_stat);
a20cbdef PK	154	if (cs_err) {
	155	dev_err(ctrl->dev, "transaction sent to IFC is not mapped to"
	156	"any memory bank 0x%08X\n", cs_err);
	157	/* clear the chip select error */
cf184dc2	158	ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
a20cbdef PK	159
a20cbdef PK	160	/* read error attribute registers print the error information */
cf184dc2 JS	161	status = ifc_in32(&ifc->cm_erattr0);
cf184dc2 JS	162	err_addr = ifc_in32(&ifc->cm_erattr1);
a20cbdef PK	163
	164	if (status & IFC_CM_ERATTR0_ERTYP_READ)
	165	dev_err(ctrl->dev, "Read transaction error"
	166	"CM_ERATTR0 0x%08X\n", status);
	167	else
	168	dev_err(ctrl->dev, "Write transaction error"
	169	"CM_ERATTR0 0x%08X\n", status);
	170
	171	err_axiid = (status & IFC_CM_ERATTR0_ERAID) >>
	172	IFC_CM_ERATTR0_ERAID_SHIFT;
	173	dev_err(ctrl->dev, "AXI ID of the error"
	174	"transaction 0x%08X\n", err_axiid);
	175
	176	err_srcid = (status & IFC_CM_ERATTR0_ESRCID) >>
	177	IFC_CM_ERATTR0_ESRCID_SHIFT;
	178	dev_err(ctrl->dev, "SRC ID of the error"
	179	"transaction 0x%08X\n", err_srcid);
	180
	181	dev_err(ctrl->dev, "Transaction Address corresponding to error"
	182	"ERADDR 0x%08X\n", err_addr);
	183
	184	ret = IRQ_HANDLED;
	185	}
	186
	187	if (check_nand_stat(ctrl))
	188	ret = IRQ_HANDLED;
	189
	190	return ret;
	191	}
	192
	193	/*
	194	* fsl_ifc_ctrl_probe
	195	*
	196	* called by device layer when it finds a device matching
	197	* one our driver can handled. This code allocates all of
	198	* the resources needed for the controller only. The
	199	* resources for the NAND banks themselves are allocated
	200	* in the chip probe function.
	201	*/
cad5cef6	202	static int fsl_ifc_ctrl_probe(struct platform_device *dev)
a20cbdef PK	203	{
a20cbdef PK	204	int ret = 0;
09691661	205	int version, banks;
7a654172	206	void __iomem *addr;
a20cbdef PK	207
	208	dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");
	209
7adfd713 KK	210	fsl_ifc_ctrl_dev = devm_kzalloc(&dev->dev, sizeof(*fsl_ifc_ctrl_dev),
7adfd713 KK	211	GFP_KERNEL);
a20cbdef PK	212	if (!fsl_ifc_ctrl_dev)
	213	return -ENOMEM;
	214
	215	dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev);
	216
	217	/* IOMAP the entire IFC region */
7a654172 RD	218	fsl_ifc_ctrl_dev->gregs = of_iomap(dev->dev.of_node, 0);
7a654172 RD	219	if (!fsl_ifc_ctrl_dev->gregs) {
a20cbdef	220	dev_err(&dev->dev, "failed to get memory region\n");
4ad0aa22	221	return -ENODEV;
a20cbdef PK	222	}
a20cbdef PK	223
cf184dc2 JS	224	if (of_property_read_bool(dev->dev.of_node, "little-endian")) {
	225	fsl_ifc_ctrl_dev->little_endian = true;
	226	dev_dbg(&dev->dev, "IFC REGISTERS are LITTLE endian\n");
	227	} else {
	228	fsl_ifc_ctrl_dev->little_endian = false;
	229	dev_dbg(&dev->dev, "IFC REGISTERS are BIG endian\n");
	230	}
	231
7a654172	232	version = ifc_in32(&fsl_ifc_ctrl_dev->gregs->ifc_rev) &
09691661	233	FSL_IFC_VERSION_MASK;
7a654172	234
09691661 AS	235	banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
	236	dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
	237	version >> 24, (version >> 16) & 0xf, banks);
	238
	239	fsl_ifc_ctrl_dev->version = version;
	240	fsl_ifc_ctrl_dev->banks = banks;
	241
7a654172 RD	242	addr = fsl_ifc_ctrl_dev->gregs;
	243	if (version >= FSL_IFC_VERSION_2_0_0)
	244	addr += PGOFFSET_64K;
	245	else
	246	addr += PGOFFSET_4K;
	247	fsl_ifc_ctrl_dev->rregs = addr;
	248
a20cbdef PK	249	/* get the Controller level irq */
a20cbdef PK	250	fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
ed4eeba7	251	if (fsl_ifc_ctrl_dev->irq == 0) {
a20cbdef PK	252	dev_err(&dev->dev, "failed to get irq resource "
	253	"for IFC\n");
	254	ret = -ENODEV;
	255	goto err;
	256	}
	257
	258	/* get the nand machine irq */
	259	fsl_ifc_ctrl_dev->nand_irq =
	260	irq_of_parse_and_map(dev->dev.of_node, 1);
a20cbdef PK	261
	262	fsl_ifc_ctrl_dev->dev = &dev->dev;
	263
	264	ret = fsl_ifc_ctrl_init(fsl_ifc_ctrl_dev);
	265	if (ret < 0)
fcaa5040	266	goto err_unmap_nandirq;
a20cbdef PK	267
	268	init_waitqueue_head(&fsl_ifc_ctrl_dev->nand_wait);
	269
	270	ret = request_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_irq, IRQF_SHARED,
	271	"fsl-ifc", fsl_ifc_ctrl_dev);
	272	if (ret != 0) {
	273	dev_err(&dev->dev, "failed to install irq (%d)\n",
	274	fsl_ifc_ctrl_dev->irq);
fcaa5040	275	goto err_unmap_nandirq;
a20cbdef PK	276	}
a20cbdef PK	277
721c0705 PK	278	if (fsl_ifc_ctrl_dev->nand_irq) {
	279	ret = request_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_nand_irq,
	280	0, "fsl-ifc-nand", fsl_ifc_ctrl_dev);
	281	if (ret != 0) {
	282	dev_err(&dev->dev, "failed to install irq (%d)\n",
	283	fsl_ifc_ctrl_dev->nand_irq);
fcaa5040	284	goto err_free_irq;
721c0705	285	}
a20cbdef PK	286	}
	287
	288	return 0;
	289
fcaa5040	290	err_free_irq:
a20cbdef	291	free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev);
fcaa5040 DM	292	err_unmap_nandirq:
fcaa5040 DM	293	irq_dispose_mapping(fsl_ifc_ctrl_dev->nand_irq);
a20cbdef PK	294	irq_dispose_mapping(fsl_ifc_ctrl_dev->irq);
a20cbdef PK	295	err:
4ad0aa22	296	iounmap(fsl_ifc_ctrl_dev->gregs);
a20cbdef PK	297	return ret;
	298	}
	299
	300	static const struct of_device_id fsl_ifc_match[] = {
	301	{
	302	.compatible = "fsl,ifc",
	303	},
	304	{},
	305	};
	306
	307	static struct platform_driver fsl_ifc_ctrl_driver = {
	308	.driver = {
	309	.name = "fsl-ifc",
	310	.of_match_table = fsl_ifc_match,
	311	},
	312	.probe = fsl_ifc_ctrl_probe,
	313	.remove = fsl_ifc_ctrl_remove,
	314	};
	315
d2ae2e20 PK	316	static int __init fsl_ifc_init(void)
	317	{
	318	return platform_driver_register(&fsl_ifc_ctrl_driver);
	319	}
	320	subsys_initcall(fsl_ifc_init);
a20cbdef PK	321
	322	MODULE_LICENSE("GPL");
	323	MODULE_AUTHOR("Freescale Semiconductor");
	324	MODULE_DESCRIPTION("Freescale Integrated Flash Controller driver");