[mirror_ubuntu-bionic-kernel.git] / drivers / memory / mtk-smi.c

/*
 * Copyright (c) 2015-2016 MediaTek Inc.
 * Author: Yong Wu <yong.wu@mediatek.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/clk.h>
#include <linux/component.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <soc/mediatek/smi.h>
#include <dt-bindings/memory/mt2701-larb-port.h>

/* mt8173 */
#define SMI_LARB_MMU_EN		0xf00

/* mt2701 */
#define REG_SMI_SECUR_CON_BASE		0x5c0

/* every register control 8 port, register offset 0x4 */
#define REG_SMI_SECUR_CON_OFFSET(id)	(((id) >> 3) << 2)
#define REG_SMI_SECUR_CON_ADDR(id)	\
	(REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))

/*
 * every port have 4 bit to control, bit[port + 3] control virtual or physical,
 * bit[port + 2 : port + 1] control the domain, bit[port] control the security
 * or non-security.
 */
#define SMI_SECUR_CON_VAL_MSK(id)	(~(0xf << (((id) & 0x7) << 2)))
#define SMI_SECUR_CON_VAL_VIRT(id)	BIT((((id) & 0x7) << 2) + 3)
/* mt2701 domain should be set to 3 */
#define SMI_SECUR_CON_VAL_DOMAIN(id)	(0x3 << ((((id) & 0x7) << 2) + 1))

/* mt2712 */
#define SMI_LARB_NONSEC_CON(id)	(0x380 + ((id) * 4))
#define F_MMU_EN		BIT(0)

struct mtk_smi_larb_gen {
	bool need_larbid;
	int port_in_larb[MTK_LARB_NR_MAX + 1];
	void (*config_port)(struct device *);
};

struct mtk_smi {
	struct device			*dev;
	struct clk			*clk_apb, *clk_smi;
	struct clk			*clk_async; /*only needed by mt2701*/
	void __iomem			*smi_ao_base;
};

struct mtk_smi_larb { /* larb: local arbiter */
	struct mtk_smi			smi;
	void __iomem			*base;
	struct device			*smi_common_dev;
	const struct mtk_smi_larb_gen	*larb_gen;
	int				larbid;
	u32				*mmu;
};

enum mtk_smi_gen {
	MTK_SMI_GEN1,
	MTK_SMI_GEN2
};

static int mtk_smi_enable(const struct mtk_smi *smi)
{
	int ret;

	ret = pm_runtime_get_sync(smi->dev);
	if (ret < 0)
		return ret;

	ret = clk_prepare_enable(smi->clk_apb);
	if (ret)
		goto err_put_pm;

	ret = clk_prepare_enable(smi->clk_smi);
	if (ret)
		goto err_disable_apb;

	return 0;

err_disable_apb:
	clk_disable_unprepare(smi->clk_apb);
err_put_pm:
	pm_runtime_put_sync(smi->dev);
	return ret;
}

static void mtk_smi_disable(const struct mtk_smi *smi)
{
	clk_disable_unprepare(smi->clk_smi);
	clk_disable_unprepare(smi->clk_apb);
	pm_runtime_put_sync(smi->dev);
}

int mtk_smi_larb_get(struct device *larbdev)
{
	struct mtk_smi_larb *larb = dev_get_drvdata(larbdev);
	const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
	struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
	int ret;

	/* Enable the smi-common's power and clocks */
	ret = mtk_smi_enable(common);
	if (ret)
		return ret;

	/* Enable the larb's power and clocks */
	ret = mtk_smi_enable(&larb->smi);
	if (ret) {
		mtk_smi_disable(common);
		return ret;
	}

	/* Configure the iommu info for this larb */
	larb_gen->config_port(larbdev);

	return 0;
}
EXPORT_SYMBOL_GPL(mtk_smi_larb_get);

void mtk_smi_larb_put(struct device *larbdev)
{
	struct mtk_smi_larb *larb = dev_get_drvdata(larbdev);
	struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);

	/*
	 * Don't de-configure the iommu info for this larb since there may be
	 * several modules in this larb.
	 * The iommu info will be reset after power off.
	 */

	mtk_smi_disable(&larb->smi);
	mtk_smi_disable(common);
}
EXPORT_SYMBOL_GPL(mtk_smi_larb_put);

static int
mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
{
	struct mtk_smi_larb *larb = dev_get_drvdata(dev);
	struct mtk_smi_iommu *smi_iommu = data;
	unsigned int         i;

	if (larb->larb_gen->need_larbid) {
		larb->mmu = &smi_iommu->larb_imu[larb->larbid].mmu;
		return 0;
	}

	/*
	 * If there is no larbid property, Loop to find the corresponding
	 * iommu information.
	 */
	for (i = 0; i < smi_iommu->larb_nr; i++) {
		if (dev == smi_iommu->larb_imu[i].dev) {
			/* The 'mmu' may be updated in iommu-attach/detach. */
			larb->mmu = &smi_iommu->larb_imu[i].mmu;
			return 0;
		}
	}
	return -ENODEV;
}

static void mtk_smi_larb_config_port_mt2712(struct device *dev)
{
	struct mtk_smi_larb *larb = dev_get_drvdata(dev);
	u32 reg;
	int i;

	/*
	 * larb 8/9 is the bdpsys larb, the iommu_en is enabled defaultly.
	 * Don't need to set it again.
	 */
	if (larb->larbid == 8 || larb->larbid == 9)
		return;

	for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
		reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
		reg |= F_MMU_EN;
		writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
	}
}

static void mtk_smi_larb_config_port_mt8173(struct device *dev)
{
	struct mtk_smi_larb *larb = dev_get_drvdata(dev);

	writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN);
}

static void mtk_smi_larb_config_port_gen1(struct device *dev)
{
	struct mtk_smi_larb *larb = dev_get_drvdata(dev);
	const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
	struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
	int i, m4u_port_id, larb_port_num;
	u32 sec_con_val, reg_val;

	m4u_port_id = larb_gen->port_in_larb[larb->larbid];
	larb_port_num = larb_gen->port_in_larb[larb->larbid + 1]
			- larb_gen->port_in_larb[larb->larbid];

	for (i = 0; i < larb_port_num; i++, m4u_port_id++) {
		if (*larb->mmu & BIT(i)) {
			/* bit[port + 3] controls the virtual or physical */
			sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id);
		} else {
			/* do not need to enable m4u for this port */
			continue;
		}
		reg_val = readl(common->smi_ao_base
			+ REG_SMI_SECUR_CON_ADDR(m4u_port_id));
		reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
		reg_val |= sec_con_val;
		reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
		writel(reg_val,
			common->smi_ao_base
			+ REG_SMI_SECUR_CON_ADDR(m4u_port_id));
	}
}

static void
mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
{
	/* Do nothing as the iommu is always enabled. */
}

static const struct component_ops mtk_smi_larb_component_ops = {
	.bind = mtk_smi_larb_bind,
	.unbind = mtk_smi_larb_unbind,
};

static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
	/* mt8173 do not need the port in larb */
	.config_port = mtk_smi_larb_config_port_mt8173,
};

static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
	.need_larbid = true,
	.port_in_larb = {
		LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
		LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
	},
	.config_port = mtk_smi_larb_config_port_gen1,
};

static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
	.need_larbid = true,
	.config_port = mtk_smi_larb_config_port_mt2712,
};

static const struct of_device_id mtk_smi_larb_of_ids[] = {
	{
		.compatible = "mediatek,mt8173-smi-larb",
		.data = &mtk_smi_larb_mt8173
	},
	{
		.compatible = "mediatek,mt2701-smi-larb",
		.data = &mtk_smi_larb_mt2701
	},
	{
		.compatible = "mediatek,mt2712-smi-larb",
		.data = &mtk_smi_larb_mt2712
	},
	{}
};

static int mtk_smi_larb_probe(struct platform_device *pdev)
{
	struct mtk_smi_larb *larb;
	struct resource *res;
	struct device *dev = &pdev->dev;
	struct device_node *smi_node;
	struct platform_device *smi_pdev;
	int err;

	larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
	if (!larb)
		return -ENOMEM;

	larb->larb_gen = of_device_get_match_data(dev);
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	larb->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(larb->base))
		return PTR_ERR(larb->base);

	larb->smi.clk_apb = devm_clk_get(dev, "apb");
	if (IS_ERR(larb->smi.clk_apb))
		return PTR_ERR(larb->smi.clk_apb);

	larb->smi.clk_smi = devm_clk_get(dev, "smi");
	if (IS_ERR(larb->smi.clk_smi))
		return PTR_ERR(larb->smi.clk_smi);
	larb->smi.dev = dev;

	if (larb->larb_gen->need_larbid) {
		err = of_property_read_u32(dev->of_node, "mediatek,larb-id",
					   &larb->larbid);
		if (err) {
			dev_err(dev, "missing larbid property\n");
			return err;
		}
	}

	smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
	if (!smi_node)
		return -EINVAL;

	smi_pdev = of_find_device_by_node(smi_node);
	of_node_put(smi_node);
	if (smi_pdev) {
		if (!platform_get_drvdata(smi_pdev))
			return -EPROBE_DEFER;
		larb->smi_common_dev = &smi_pdev->dev;
	} else {
		dev_err(dev, "Failed to get the smi_common device\n");
		return -EINVAL;
	}

	pm_runtime_enable(dev);
	platform_set_drvdata(pdev, larb);
	return component_add(dev, &mtk_smi_larb_component_ops);
}

static int mtk_smi_larb_remove(struct platform_device *pdev)
{
	pm_runtime_disable(&pdev->dev);
	component_del(&pdev->dev, &mtk_smi_larb_component_ops);
	return 0;
}

static struct platform_driver mtk_smi_larb_driver = {
	.probe	= mtk_smi_larb_probe,
	.remove	= mtk_smi_larb_remove,
	.driver	= {
		.name = "mtk-smi-larb",
		.of_match_table = mtk_smi_larb_of_ids,
	}
};

static const struct of_device_id mtk_smi_common_of_ids[] = {
	{
		.compatible = "mediatek,mt8173-smi-common",
		.data = (void *)MTK_SMI_GEN2
	},
	{
		.compatible = "mediatek,mt2701-smi-common",
		.data = (void *)MTK_SMI_GEN1
	},
	{
		.compatible = "mediatek,mt2712-smi-common",
		.data = (void *)MTK_SMI_GEN2
	},
	{}
};

static int mtk_smi_common_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct mtk_smi *common;
	struct resource *res;
	enum mtk_smi_gen smi_gen;
	int ret;

	common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
	if (!common)
		return -ENOMEM;
	common->dev = dev;

	common->clk_apb = devm_clk_get(dev, "apb");
	if (IS_ERR(common->clk_apb))
		return PTR_ERR(common->clk_apb);

	common->clk_smi = devm_clk_get(dev, "smi");
	if (IS_ERR(common->clk_smi))
		return PTR_ERR(common->clk_smi);

	/*
	 * for mtk smi gen 1, we need to get the ao(always on) base to config
	 * m4u port, and we need to enable the aync clock for transform the smi
	 * clock into emi clock domain, but for mtk smi gen2, there's no smi ao
	 * base.
	 */
	smi_gen = (enum mtk_smi_gen)of_device_get_match_data(dev);
	if (smi_gen == MTK_SMI_GEN1) {
		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		common->smi_ao_base = devm_ioremap_resource(dev, res);
		if (IS_ERR(common->smi_ao_base))
			return PTR_ERR(common->smi_ao_base);

		common->clk_async = devm_clk_get(dev, "async");
		if (IS_ERR(common->clk_async))
			return PTR_ERR(common->clk_async);

		ret = clk_prepare_enable(common->clk_async);
		if (ret)
			return ret;
	}
	pm_runtime_enable(dev);
	platform_set_drvdata(pdev, common);
	return 0;
}

static int mtk_smi_common_remove(struct platform_device *pdev)
{
	pm_runtime_disable(&pdev->dev);
	return 0;
}

static struct platform_driver mtk_smi_common_driver = {
	.probe	= mtk_smi_common_probe,
	.remove = mtk_smi_common_remove,
	.driver	= {
		.name = "mtk-smi-common",
		.of_match_table = mtk_smi_common_of_ids,
	}
};

static int __init mtk_smi_init(void)
{
	int ret;

	ret = platform_driver_register(&mtk_smi_common_driver);
	if (ret != 0) {
		pr_err("Failed to register SMI driver\n");
		return ret;
	}

	ret = platform_driver_register(&mtk_smi_larb_driver);
	if (ret != 0) {
		pr_err("Failed to register SMI-LARB driver\n");
		goto err_unreg_smi;
	}
	return ret;

err_unreg_smi:
	platform_driver_unregister(&mtk_smi_common_driver);
	return ret;
}

module_init(mtk_smi_init);
Commit	Line	Data
cc8bbe1a YW	1	/*
	2	* Copyright (c) 2015-2016 MediaTek Inc.
	3	* Author: Yong Wu <yong.wu@mediatek.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14	#include <linux/clk.h>
	15	#include <linux/component.h>
	16	#include <linux/device.h>
	17	#include <linux/err.h>
	18	#include <linux/io.h>
4f608d38	19	#include <linux/module.h>
cc8bbe1a YW	20	#include <linux/of.h>
	21	#include <linux/of_platform.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/pm_runtime.h>
	24	#include <soc/mediatek/smi.h>
3c8f4ad8	25	#include <dt-bindings/memory/mt2701-larb-port.h>
cc8bbe1a	26
e6dec923	27	/* mt8173 */
cc8bbe1a	28	#define SMI_LARB_MMU_EN 0xf00
e6dec923 YW	29
e6dec923 YW	30	/* mt2701 */
3c8f4ad8 HZ	31	#define REG_SMI_SECUR_CON_BASE 0x5c0
	32
	33	/* every register control 8 port, register offset 0x4 */
	34	#define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2)
	35	#define REG_SMI_SECUR_CON_ADDR(id) \
	36	(REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))
	37
	38	/*
	39	* every port have 4 bit to control, bit[port + 3] control virtual or physical,
	40	* bit[port + 2 : port + 1] control the domain, bit[port] control the security
	41	* or non-security.
	42	*/
	43	#define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2)))
	44	#define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3)
	45	/* mt2701 domain should be set to 3 */
	46	#define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1))
	47
e6dec923 YW	48	/* mt2712 */
	49	#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
	50	#define F_MMU_EN BIT(0)
	51
3c8f4ad8	52	struct mtk_smi_larb_gen {
363932cd	53	bool need_larbid;
3c8f4ad8 HZ	54	int port_in_larb[MTK_LARB_NR_MAX + 1];
	55	void (config_port)(struct device );
	56	};
cc8bbe1a YW	57
cc8bbe1a YW	58	struct mtk_smi {
3c8f4ad8 HZ	59	struct device *dev;
	60	struct clk clk_apb, clk_smi;
	61	struct clk clk_async; /only needed by mt2701*/
	62	void __iomem *smi_ao_base;
cc8bbe1a YW	63	};
	64
	65	struct mtk_smi_larb { /* larb: local arbiter */
3c8f4ad8 HZ	66	struct mtk_smi smi;
	67	void __iomem *base;
	68	struct device *smi_common_dev;
	69	const struct mtk_smi_larb_gen *larb_gen;
	70	int larbid;
	71	u32 *mmu;
	72	};
	73
	74	enum mtk_smi_gen {
	75	MTK_SMI_GEN1,
	76	MTK_SMI_GEN2
cc8bbe1a YW	77	};
	78
	79	static int mtk_smi_enable(const struct mtk_smi *smi)
	80	{
	81	int ret;
	82
	83	ret = pm_runtime_get_sync(smi->dev);
	84	if (ret < 0)
	85	return ret;
	86
	87	ret = clk_prepare_enable(smi->clk_apb);
	88	if (ret)
	89	goto err_put_pm;
	90
	91	ret = clk_prepare_enable(smi->clk_smi);
	92	if (ret)
	93	goto err_disable_apb;
	94
	95	return 0;
	96
	97	err_disable_apb:
	98	clk_disable_unprepare(smi->clk_apb);
	99	err_put_pm:
	100	pm_runtime_put_sync(smi->dev);
	101	return ret;
	102	}
	103
	104	static void mtk_smi_disable(const struct mtk_smi *smi)
	105	{
	106	clk_disable_unprepare(smi->clk_smi);
	107	clk_disable_unprepare(smi->clk_apb);
	108	pm_runtime_put_sync(smi->dev);
	109	}
	110
	111	int mtk_smi_larb_get(struct device *larbdev)
	112	{
	113	struct mtk_smi_larb *larb = dev_get_drvdata(larbdev);
3c8f4ad8	114	const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
cc8bbe1a YW	115	struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
	116	int ret;
	117
	118	/* Enable the smi-common's power and clocks */
	119	ret = mtk_smi_enable(common);
	120	if (ret)
	121	return ret;
	122
	123	/* Enable the larb's power and clocks */
	124	ret = mtk_smi_enable(&larb->smi);
	125	if (ret) {
	126	mtk_smi_disable(common);
	127	return ret;
	128	}
	129
	130	/* Configure the iommu info for this larb */
3c8f4ad8	131	larb_gen->config_port(larbdev);
cc8bbe1a YW	132
	133	return 0;
	134	}
cb1b5dff	135	EXPORT_SYMBOL_GPL(mtk_smi_larb_get);
cc8bbe1a YW	136
	137	void mtk_smi_larb_put(struct device *larbdev)
	138	{
	139	struct mtk_smi_larb *larb = dev_get_drvdata(larbdev);
	140	struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
	141
	142	/*
	143	* Don't de-configure the iommu info for this larb since there may be
	144	* several modules in this larb.
	145	* The iommu info will be reset after power off.
	146	*/
	147
	148	mtk_smi_disable(&larb->smi);
	149	mtk_smi_disable(common);
	150	}
cb1b5dff	151	EXPORT_SYMBOL_GPL(mtk_smi_larb_put);
cc8bbe1a YW	152
	153	static int
	154	mtk_smi_larb_bind(struct device dev, struct device master, void *data)
	155	{
	156	struct mtk_smi_larb *larb = dev_get_drvdata(dev);
	157	struct mtk_smi_iommu *smi_iommu = data;
	158	unsigned int i;
	159
e6dec923 YW	160	if (larb->larb_gen->need_larbid) {
	161	larb->mmu = &smi_iommu->larb_imu[larb->larbid].mmu;
	162	return 0;
	163	}
	164
	165	/*
	166	* If there is no larbid property, Loop to find the corresponding
	167	* iommu information.
	168	*/
cc8bbe1a YW	169	for (i = 0; i < smi_iommu->larb_nr; i++) {
	170	if (dev == smi_iommu->larb_imu[i].dev) {
	171	/* The 'mmu' may be updated in iommu-attach/detach. */
	172	larb->mmu = &smi_iommu->larb_imu[i].mmu;
	173	return 0;
	174	}
	175	}
	176	return -ENODEV;
	177	}
	178
e6dec923	179	static void mtk_smi_larb_config_port_mt2712(struct device *dev)
3c8f4ad8 HZ	180	{
3c8f4ad8 HZ	181	struct mtk_smi_larb *larb = dev_get_drvdata(dev);
e6dec923 YW	182	u32 reg;
e6dec923 YW	183	int i;
3c8f4ad8	184
e6dec923 YW	185	/*
	186	* larb 8/9 is the bdpsys larb, the iommu_en is enabled defaultly.
	187	* Don't need to set it again.
	188	*/
	189	if (larb->larbid == 8 \|\| larb->larbid == 9)
	190	return;
	191
	192	for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
	193	reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
	194	reg \|= F_MMU_EN;
	195	writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
	196	}
3c8f4ad8 HZ	197	}
3c8f4ad8 HZ	198
e6dec923 YW	199	static void mtk_smi_larb_config_port_mt8173(struct device *dev)
	200	{
	201	struct mtk_smi_larb *larb = dev_get_drvdata(dev);
	202
	203	writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN);
	204	}
3c8f4ad8 HZ	205
	206	static void mtk_smi_larb_config_port_gen1(struct device *dev)
	207	{
	208	struct mtk_smi_larb *larb = dev_get_drvdata(dev);
	209	const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
	210	struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
	211	int i, m4u_port_id, larb_port_num;
	212	u32 sec_con_val, reg_val;
	213
	214	m4u_port_id = larb_gen->port_in_larb[larb->larbid];
	215	larb_port_num = larb_gen->port_in_larb[larb->larbid + 1]
	216	- larb_gen->port_in_larb[larb->larbid];
	217
	218	for (i = 0; i < larb_port_num; i++, m4u_port_id++) {
	219	if (*larb->mmu & BIT(i)) {
	220	/* bit[port + 3] controls the virtual or physical */
	221	sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id);
	222	} else {
	223	/* do not need to enable m4u for this port */
	224	continue;
	225	}
	226	reg_val = readl(common->smi_ao_base
	227	+ REG_SMI_SECUR_CON_ADDR(m4u_port_id));
	228	reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
	229	reg_val \|= sec_con_val;
	230	reg_val \|= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
	231	writel(reg_val,
	232	common->smi_ao_base
	233	+ REG_SMI_SECUR_CON_ADDR(m4u_port_id));
	234	}
	235	}
	236
cc8bbe1a YW	237	static void
	238	mtk_smi_larb_unbind(struct device dev, struct device master, void *data)
	239	{
	240	/* Do nothing as the iommu is always enabled. */
	241	}
	242
	243	static const struct component_ops mtk_smi_larb_component_ops = {
	244	.bind = mtk_smi_larb_bind,
	245	.unbind = mtk_smi_larb_unbind,
	246	};
	247
3c8f4ad8 HZ	248	static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
3c8f4ad8 HZ	249	/* mt8173 do not need the port in larb */
e6dec923	250	.config_port = mtk_smi_larb_config_port_mt8173,
3c8f4ad8 HZ	251	};
	252
	253	static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
363932cd	254	.need_larbid = true,
3c8f4ad8 HZ	255	.port_in_larb = {
	256	LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
	257	LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
	258	},
	259	.config_port = mtk_smi_larb_config_port_gen1,
	260	};
	261
e6dec923 YW	262	static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
	263	.need_larbid = true,
	264	.config_port = mtk_smi_larb_config_port_mt2712,
	265	};
	266
3c8f4ad8 HZ	267	static const struct of_device_id mtk_smi_larb_of_ids[] = {
	268	{
	269	.compatible = "mediatek,mt8173-smi-larb",
	270	.data = &mtk_smi_larb_mt8173
	271	},
	272	{
	273	.compatible = "mediatek,mt2701-smi-larb",
	274	.data = &mtk_smi_larb_mt2701
	275	},
e6dec923 YW	276	{
	277	.compatible = "mediatek,mt2712-smi-larb",
	278	.data = &mtk_smi_larb_mt2712
	279	},
3c8f4ad8 HZ	280	{}
	281	};
	282
cc8bbe1a YW	283	static int mtk_smi_larb_probe(struct platform_device *pdev)
	284	{
	285	struct mtk_smi_larb *larb;
	286	struct resource *res;
	287	struct device *dev = &pdev->dev;
	288	struct device_node *smi_node;
	289	struct platform_device *smi_pdev;
363932cd	290	int err;
cc8bbe1a	291
cc8bbe1a YW	292	larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
	293	if (!larb)
	294	return -ENOMEM;
	295
75487860	296	larb->larb_gen = of_device_get_match_data(dev);
cc8bbe1a YW	297	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	298	larb->base = devm_ioremap_resource(dev, res);
	299	if (IS_ERR(larb->base))
	300	return PTR_ERR(larb->base);
	301
	302	larb->smi.clk_apb = devm_clk_get(dev, "apb");
	303	if (IS_ERR(larb->smi.clk_apb))
	304	return PTR_ERR(larb->smi.clk_apb);
	305
	306	larb->smi.clk_smi = devm_clk_get(dev, "smi");
	307	if (IS_ERR(larb->smi.clk_smi))
	308	return PTR_ERR(larb->smi.clk_smi);
	309	larb->smi.dev = dev;
	310
363932cd HZ	311	if (larb->larb_gen->need_larbid) {
	312	err = of_property_read_u32(dev->of_node, "mediatek,larb-id",
	313	&larb->larbid);
	314	if (err) {
	315	dev_err(dev, "missing larbid property\n");
	316	return err;
	317	}
	318	}
	319
cc8bbe1a YW	320	smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
	321	if (!smi_node)
	322	return -EINVAL;
	323
	324	smi_pdev = of_find_device_by_node(smi_node);
	325	of_node_put(smi_node);
	326	if (smi_pdev) {
4f608d38 YW	327	if (!platform_get_drvdata(smi_pdev))
4f608d38 YW	328	return -EPROBE_DEFER;
cc8bbe1a YW	329	larb->smi_common_dev = &smi_pdev->dev;
	330	} else {
	331	dev_err(dev, "Failed to get the smi_common device\n");
	332	return -EINVAL;
	333	}
	334
	335	pm_runtime_enable(dev);
	336	platform_set_drvdata(pdev, larb);
	337	return component_add(dev, &mtk_smi_larb_component_ops);
	338	}
	339
	340	static int mtk_smi_larb_remove(struct platform_device *pdev)
	341	{
	342	pm_runtime_disable(&pdev->dev);
	343	component_del(&pdev->dev, &mtk_smi_larb_component_ops);
	344	return 0;
	345	}
	346
cc8bbe1a YW	347	static struct platform_driver mtk_smi_larb_driver = {
cc8bbe1a YW	348	.probe = mtk_smi_larb_probe,
3c8f4ad8	349	.remove = mtk_smi_larb_remove,
cc8bbe1a YW	350	.driver = {
	351	.name = "mtk-smi-larb",
	352	.of_match_table = mtk_smi_larb_of_ids,
	353	}
	354	};
	355
3c8f4ad8 HZ	356	static const struct of_device_id mtk_smi_common_of_ids[] = {
	357	{
	358	.compatible = "mediatek,mt8173-smi-common",
	359	.data = (void *)MTK_SMI_GEN2
	360	},
	361	{
	362	.compatible = "mediatek,mt2701-smi-common",
	363	.data = (void *)MTK_SMI_GEN1
	364	},
e6dec923 YW	365	{
	366	.compatible = "mediatek,mt2712-smi-common",
	367	.data = (void *)MTK_SMI_GEN2
	368	},
3c8f4ad8 HZ	369	{}
	370	};
	371
cc8bbe1a YW	372	static int mtk_smi_common_probe(struct platform_device *pdev)
	373	{
	374	struct device *dev = &pdev->dev;
	375	struct mtk_smi *common;
3c8f4ad8	376	struct resource *res;
3c8f4ad8	377	enum mtk_smi_gen smi_gen;
46cc815d	378	int ret;
cc8bbe1a	379
cc8bbe1a YW	380	common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
	381	if (!common)
	382	return -ENOMEM;
	383	common->dev = dev;
	384
	385	common->clk_apb = devm_clk_get(dev, "apb");
	386	if (IS_ERR(common->clk_apb))
	387	return PTR_ERR(common->clk_apb);
	388
	389	common->clk_smi = devm_clk_get(dev, "smi");
	390	if (IS_ERR(common->clk_smi))
	391	return PTR_ERR(common->clk_smi);
	392
3c8f4ad8 HZ	393	/*
	394	* for mtk smi gen 1, we need to get the ao(always on) base to config
	395	* m4u port, and we need to enable the aync clock for transform the smi
	396	* clock into emi clock domain, but for mtk smi gen2, there's no smi ao
	397	* base.
	398	*/
75487860	399	smi_gen = (enum mtk_smi_gen)of_device_get_match_data(dev);
3c8f4ad8 HZ	400	if (smi_gen == MTK_SMI_GEN1) {
	401	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	402	common->smi_ao_base = devm_ioremap_resource(dev, res);
	403	if (IS_ERR(common->smi_ao_base))
	404	return PTR_ERR(common->smi_ao_base);
	405
	406	common->clk_async = devm_clk_get(dev, "async");
	407	if (IS_ERR(common->clk_async))
	408	return PTR_ERR(common->clk_async);
	409
46cc815d AY	410	ret = clk_prepare_enable(common->clk_async);
	411	if (ret)
	412	return ret;
3c8f4ad8	413	}
cc8bbe1a YW	414	pm_runtime_enable(dev);
	415	platform_set_drvdata(pdev, common);
	416	return 0;
	417	}
	418
	419	static int mtk_smi_common_remove(struct platform_device *pdev)
	420	{
	421	pm_runtime_disable(&pdev->dev);
	422	return 0;
	423	}
	424
cc8bbe1a YW	425	static struct platform_driver mtk_smi_common_driver = {
	426	.probe = mtk_smi_common_probe,
	427	.remove = mtk_smi_common_remove,
	428	.driver = {
	429	.name = "mtk-smi-common",
	430	.of_match_table = mtk_smi_common_of_ids,
	431	}
	432	};
	433
	434	static int __init mtk_smi_init(void)
	435	{
	436	int ret;
	437
	438	ret = platform_driver_register(&mtk_smi_common_driver);
	439	if (ret != 0) {
	440	pr_err("Failed to register SMI driver\n");
	441	return ret;
	442	}
	443
	444	ret = platform_driver_register(&mtk_smi_larb_driver);
	445	if (ret != 0) {
	446	pr_err("Failed to register SMI-LARB driver\n");
	447	goto err_unreg_smi;
	448	}
	449	return ret;
	450
	451	err_unreg_smi:
	452	platform_driver_unregister(&mtk_smi_common_driver);
	453	return ret;
	454	}
3c8f4ad8	455
4f608d38	456	module_init(mtk_smi_init);