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memory: omap-gpmc: use WARN() instead of BUG() on wrong free
[mirror_ubuntu-hirsute-kernel.git] / drivers / memory / omap-gpmc.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
4bbbc1ad
JY		 2/*
3 * GPMC support functions
4 *
5 * Copyright (C) 2005-2006 Nokia Corporation
6 *
7 * Author: Juha Yrjola
8 *
44169075
SS		 9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
4bbbc1ad 11 */
db97eb7d 12#include <linux/irq.h>
4bbbc1ad
JY		 13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/clk.h>
f37e4580
ID		 17#include <linux/ioport.h>
18#include <linux/spinlock.h>
fced80c7 19#include <linux/io.h>
d2d00862 20#include <linux/gpio/driver.h>
a0752e9c 21#include <linux/gpio/consumer.h> /* GPIO descriptor enum */
5923ea6c 22#include <linux/gpio/machine.h>
db97eb7d 23#include <linux/interrupt.h>
384258f2 24#include <linux/irqdomain.h>
da496873 25#include <linux/platform_device.h>
bc6b1e7b 26#include <linux/of.h>
cdd6928c 27#include <linux/of_address.h>
bc6b1e7b 28#include <linux/of_device.h>
b1dc1ca9 29#include <linux/of_platform.h>
e639cd5b 30#include <linux/omap-gpmc.h>
b3f5525c 31#include <linux/pm_runtime.h>
07852c3f 32#include <linux/sizes.h>
4bbbc1ad 33
bc3668ea 34#include <linux/platform_data/mtd-nand-omap2.h>
4bbbc1ad 35
4be48fd5
AM		 36#define DEVICE_NAME "omap-gpmc"
37
fd1dc87d 38/* GPMC register offsets */
4bbbc1ad
JY		 39#define GPMC_REVISION 0x00
40#define GPMC_SYSCONFIG 0x10
41#define GPMC_SYSSTATUS 0x14
42#define GPMC_IRQSTATUS 0x18
43#define GPMC_IRQENABLE 0x1c
44#define GPMC_TIMEOUT_CONTROL 0x40
45#define GPMC_ERR_ADDRESS 0x44
46#define GPMC_ERR_TYPE 0x48
47#define GPMC_CONFIG 0x50
48#define GPMC_STATUS 0x54
49#define GPMC_PREFETCH_CONFIG1 0x1e0
50#define GPMC_PREFETCH_CONFIG2 0x1e4
15e02a3b 51#define GPMC_PREFETCH_CONTROL 0x1ec
4bbbc1ad
JY		 52#define GPMC_PREFETCH_STATUS 0x1f0
53#define GPMC_ECC_CONFIG 0x1f4
54#define GPMC_ECC_CONTROL 0x1f8
55#define GPMC_ECC_SIZE_CONFIG 0x1fc
948d38e7 56#define GPMC_ECC1_RESULT 0x200
8d602cf5 57#define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
2fdf0c98
AM		 58#define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
59#define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
60#define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
27c9fd60 61#define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
62#define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
63#define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
4bbbc1ad 64
2c65e744
YY		 65/* GPMC ECC control settings */
66#define GPMC_ECC_CTRL_ECCCLEAR 0x100
67#define GPMC_ECC_CTRL_ECCDISABLE 0x000
68#define GPMC_ECC_CTRL_ECCREG1 0x001
69#define GPMC_ECC_CTRL_ECCREG2 0x002
70#define GPMC_ECC_CTRL_ECCREG3 0x003
71#define GPMC_ECC_CTRL_ECCREG4 0x004
72#define GPMC_ECC_CTRL_ECCREG5 0x005
73#define GPMC_ECC_CTRL_ECCREG6 0x006
74#define GPMC_ECC_CTRL_ECCREG7 0x007
75#define GPMC_ECC_CTRL_ECCREG8 0x008
76#define GPMC_ECC_CTRL_ECCREG9 0x009
77
e378d22b
RQ		 78#define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
79
512d73d1
RQ		 80#define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0)
81
559d94b0
AM		 82#define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
83#define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
84#define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
85#define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
86#define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
87#define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
88
948d38e7 89#define GPMC_CS0_OFFSET 0x60
4bbbc1ad 90#define GPMC_CS_SIZE 0x30
2fdf0c98 91#define GPMC_BCH_SIZE 0x10
4bbbc1ad 92
bdd7e033
RQ		 93/*
94 * The first 1MB of GPMC address space is typically mapped to
95 * the internal ROM. Never allocate the first page, to
96 * facilitate bug detection; even if we didn't boot from ROM.
97 * As GPMC minimum partition size is 16MB we can only start from
98 * there.
99 */
100#define GPMC_MEM_START 0x1000000
f37e4580 101#define GPMC_MEM_END 0x3FFFFFFF
f37e4580
ID		 102
103#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
104#define GPMC_SECTION_SHIFT 28 /* 128 MB */
105
59e9c5ae 106#define CS_NUM_SHIFT 24
107#define ENABLE_PREFETCH (0x1 << 7)
108#define DMA_MPU_MODE 2
109
98397f1c
KK		 110#define GPMC_REVISION_MAJOR(l) (((l) >> 4) & 0xf)
111#define GPMC_REVISION_MINOR(l) ((l) & 0xf)
da496873
AM		 112
113#define GPMC_HAS_WR_ACCESS 0x1
114#define GPMC_HAS_WR_DATA_MUX_BUS 0x2
aa8d4767 115#define GPMC_HAS_MUX_AAD 0x4
da496873 116
9f833156
JH		 117#define GPMC_NR_WAITPINS 4
118
e639cd5b
TL		 119#define GPMC_CS_CONFIG1 0x00
120#define GPMC_CS_CONFIG2 0x04
121#define GPMC_CS_CONFIG3 0x08
122#define GPMC_CS_CONFIG4 0x0c
123#define GPMC_CS_CONFIG5 0x10
124#define GPMC_CS_CONFIG6 0x14
125#define GPMC_CS_CONFIG7 0x18
126#define GPMC_CS_NAND_COMMAND 0x1c
127#define GPMC_CS_NAND_ADDRESS 0x20
128#define GPMC_CS_NAND_DATA 0x24
129
130/* Control Commands */
131#define GPMC_CONFIG_RDY_BSY 0x00000001
132#define GPMC_CONFIG_DEV_SIZE 0x00000002
133#define GPMC_CONFIG_DEV_TYPE 0x00000003
e639cd5b
TL		 134
135#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
136#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
137#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
138#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
139#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
140#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
141#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
98397f1c 142#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
4b613e9b
RA		 143/** CLKACTIVATIONTIME Max Ticks */
144#define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
98397f1c 145#define GPMC_CONFIG1_PAGE_LEN(val) (((val) & 3) << 23)
4b613e9b
RA		 146/** ATTACHEDDEVICEPAGELENGTH Max Value */
147#define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
e639cd5b
TL		 148#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
149#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
98397f1c 150#define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
2e676901
RA		 151/** WAITMONITORINGTIME Max Ticks */
152#define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
98397f1c
KK		 153#define GPMC_CONFIG1_WAIT_PIN_SEL(val) (((val) & 3) << 16)
154#define GPMC_CONFIG1_DEVICESIZE(val) (((val) & 3) << 12)
e639cd5b 155#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
4b613e9b
RA		 156/** DEVICESIZE Max Value */
157#define GPMC_CONFIG1_DEVICESIZE_MAX 1
98397f1c 158#define GPMC_CONFIG1_DEVICETYPE(val) (((val) & 3) << 10)
e639cd5b 159#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
98397f1c 160#define GPMC_CONFIG1_MUXTYPE(val) (((val) & 3) << 8)
e639cd5b 161#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
98397f1c 162#define GPMC_CONFIG1_FCLK_DIV(val) ((val) & 3)
e639cd5b
TL		 163#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
164#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
165#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
166#define GPMC_CONFIG7_CSVALID (1 << 6)
167
9c4f757e
SP		 168#define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
169#define GPMC_CONFIG7_CSVALID_MASK BIT(6)
170#define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
171#define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
172/* All CONFIG7 bits except reserved bits */
173#define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
174 GPMC_CONFIG7_CSVALID_MASK | \
175 GPMC_CONFIG7_MASKADDRESS_MASK)
176
e639cd5b
TL		 177#define GPMC_DEVICETYPE_NOR 0
178#define GPMC_DEVICETYPE_NAND 2
179#define GPMC_CONFIG_WRITEPROTECT 0x00000010
180#define WR_RD_PIN_MONITORING 0x00600000
181
e639cd5b
TL		 182/* ECC commands */
183#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
184#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
185#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
186
b2bac25a 187#define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */
6b6c32fc 188
7f2e8c58
RA		 189enum gpmc_clk_domain {
190 GPMC_CD_FCLK,
191 GPMC_CD_CLK
192};
193
9ed7a776
TL		 194struct gpmc_cs_data {
195 const char *name;
196
197#define GPMC_CS_RESERVED (1 << 0)
198 u32 flags;
199
200 struct resource mem;
201};
202
a2d3e7ba
RN		 203/* Structure to save gpmc cs context */
204struct gpmc_cs_config {
205 u32 config1;
206 u32 config2;
207 u32 config3;
208 u32 config4;
209 u32 config5;
210 u32 config6;
211 u32 config7;
212 int is_valid;
213};
214
215/*
216 * Structure to save/restore gpmc context
217 * to support core off on OMAP3
218 */
219struct omap3_gpmc_regs {
220 u32 sysconfig;
221 u32 irqenable;
222 u32 timeout_ctrl;
223 u32 config;
224 u32 prefetch_config1;
225 u32 prefetch_config2;
226 u32 prefetch_control;
227 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
228};
229
384258f2
RQ		 230struct gpmc_device {
231 struct device *dev;
232 int irq;
233 struct irq_chip irq_chip;
d2d00862 234 struct gpio_chip gpio_chip;
b2bac25a 235 int nirqs;
384258f2
RQ		 236};
237
238static struct irq_domain *gpmc_irq_domain;
6b6c32fc 239
f37e4580 240static struct resource gpmc_mem_root;
9ed7a776 241static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
87b247c4 242static DEFINE_SPINLOCK(gpmc_mem_lock);
6797b4fe 243/* Define chip-selects as reserved by default until probe completes */
f34f3716 244static unsigned int gpmc_cs_num = GPMC_CS_NUM;
9f833156 245static unsigned int gpmc_nr_waitpins;
1cd53458 246static unsigned int gpmc_capability;
fd1dc87d 247static void __iomem *gpmc_base;
4bbbc1ad 248
fd1dc87d 249static struct clk *gpmc_l3_clk;
4bbbc1ad 250
db97eb7d
SG		 251static irqreturn_t gpmc_handle_irq(int irq, void *dev);
252
4bbbc1ad
JY		 253static void gpmc_write_reg(int idx, u32 val)
254{
edfaf05c 255 writel_relaxed(val, gpmc_base + idx);
4bbbc1ad
JY		 256}
257
258static u32 gpmc_read_reg(int idx)
259{
edfaf05c 260 return readl_relaxed(gpmc_base + idx);
4bbbc1ad
JY		 261}
262
263void gpmc_cs_write_reg(int cs, int idx, u32 val)
264{
265 void __iomem *reg_addr;
266
948d38e7 267 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
edfaf05c 268 writel_relaxed(val, reg_addr);
4bbbc1ad
JY		 269}
270
3fc089e7 271static u32 gpmc_cs_read_reg(int cs, int idx)
4bbbc1ad 272{
fd1dc87d
PW		 273 void __iomem *reg_addr;
274
948d38e7 275 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
edfaf05c 276 return readl_relaxed(reg_addr);
4bbbc1ad
JY		 277}
278
fd1dc87d 279/* TODO: Add support for gpmc_fck to clock framework and use it */
3fc089e7 280static unsigned long gpmc_get_fclk_period(void)
4bbbc1ad 281{
fd1dc87d
PW		 282 unsigned long rate = clk_get_rate(gpmc_l3_clk);
283
fd1dc87d
PW		 284 rate /= 1000;
285 rate = 1000000000 / rate; /* In picoseconds */
286
287 return rate;
4bbbc1ad
JY		 288}
289
7f2e8c58
RA		 290/**
291 * gpmc_get_clk_period - get period of selected clock domain in ps
80c4f5a8
KK		 292 * @cs: Chip Select Region.
293 * @cd: Clock Domain.
7f2e8c58
RA		 294 *
295 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
296 * prior to calling this function with GPMC_CD_CLK.
297 */
298static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
299{
7f2e8c58
RA		 300 unsigned long tick_ps = gpmc_get_fclk_period();
301 u32 l;
302 int div;
303
304 switch (cd) {
305 case GPMC_CD_CLK:
306 /* get current clk divider */
307 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
308 div = (l & 0x03) + 1;
309 /* get GPMC_CLK period */
310 tick_ps *= div;
311 break;
312 case GPMC_CD_FCLK:
313 /* FALL-THROUGH */
314 default:
315 break;
316 }
317
318 return tick_ps;
7f2e8c58
RA		 319}
320
321static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
322 enum gpmc_clk_domain cd)
4bbbc1ad
JY		 323{
324 unsigned long tick_ps;
325
326 /* Calculate in picosecs to yield more exact results */
7f2e8c58 327 tick_ps = gpmc_get_clk_period(cs, cd);
4bbbc1ad
JY		 328
329 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
330}
331
7f2e8c58
RA		 332static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
333{
334 return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
335}
336
3fc089e7 337static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
a3551f5b
AH		 338{
339 unsigned long tick_ps;
340
341 /* Calculate in picosecs to yield more exact results */
342 tick_ps = gpmc_get_fclk_period();
343
344 return (time_ps + tick_ps - 1) / tick_ps;
345}
346
3950fffd
BX		 347static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
348 enum gpmc_clk_domain cd)
7f2e8c58
RA		 349{
350 return ticks * gpmc_get_clk_period(cs, cd) / 1000;
351}
352
fd1dc87d
PW		 353unsigned int gpmc_ticks_to_ns(unsigned int ticks)
354{
7f2e8c58 355 return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
fd1dc87d
PW		 356}
357
246da26d
AM		 358static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
359{
360 return ticks * gpmc_get_fclk_period();
361}
362
363static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
364{
365 unsigned long ticks = gpmc_ps_to_ticks(time_ps);
366
367 return ticks * gpmc_get_fclk_period();
368}
369
559d94b0
AM		 370static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
371{
372 u32 l;
373
374 l = gpmc_cs_read_reg(cs, reg);
375 if (value)
376 l |= mask;
377 else
378 l &= ~mask;
379 gpmc_cs_write_reg(cs, reg, l);
380}
381
382static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
383{
384 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
385 GPMC_CONFIG1_TIME_PARA_GRAN,
386 p->time_para_granularity);
387 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
388 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
389 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
390 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
391 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
392 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
393 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
8f50b8e5 394 GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
559d94b0
AM		 395 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
396 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
397 p->cycle2cyclesamecsen);
398 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
399 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
400 p->cycle2cyclediffcsen);
401}
402
63aa945b 403#ifdef CONFIG_OMAP_GPMC_DEBUG
563dbb26
RA		 404/**
405 * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
406 * @cs: Chip Select Region
407 * @reg: GPMC_CS_CONFIGn register offset.
408 * @st_bit: Start Bit
409 * @end_bit: End Bit. Must be >= @st_bit.
80c4f5a8 410 * @max: Maximum parameter value (before optional @shift).
4b613e9b 411 * If 0, maximum is as high as @st_bit and @end_bit allow.
563dbb26 412 * @name: DTS node name, w/o "gpmc,"
7f2e8c58
RA		 413 * @cd: Clock Domain of timing parameter.
414 * @shift: Parameter value left shifts @shift, which is then printed instead of value.
563dbb26
RA		 415 * @raw: Raw Format Option.
416 * raw format: gpmc,name = <value>
417 * tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
418 * Where x ns -- y ns result in the same tick value.
4b613e9b 419 * When @max is exceeded, "invalid" is printed inside comment.
563dbb26 420 * @noval: Parameter values equal to 0 are not printed.
563dbb26
RA		 421 * @return: Specified timing parameter (after optional @shift).
422 *
423 */
7f2e8c58
RA		 424static int get_gpmc_timing_reg(
425 /* timing specifiers */
4b613e9b 426 int cs, int reg, int st_bit, int end_bit, int max,
7f2e8c58
RA		 427 const char *name, const enum gpmc_clk_domain cd,
428 /* value transform */
429 int shift,
430 /* format specifiers */
431 bool raw, bool noval)
35ac051e
TL		 432{
433 u32 l;
563dbb26
RA		 434 int nr_bits;
435 int mask;
4b613e9b 436 bool invalid;
35ac051e
TL		 437
438 l = gpmc_cs_read_reg(cs, reg);
439 nr_bits = end_bit - st_bit + 1;
563dbb26
RA		 440 mask = (1 << nr_bits) - 1;
441 l = (l >> st_bit) & mask;
4b613e9b
RA		 442 if (!max)
443 max = mask;
444 invalid = l > max;
35ac051e
TL		 445 if (shift)
446 l = (shift << l);
447 if (noval && (l == 0))
448 return 0;
449 if (!raw) {
563dbb26
RA		 450 /* DTS tick format for timings in ns */
451 unsigned int time_ns;
452 unsigned int time_ns_min = 0;
35ac051e 453
563dbb26 454 if (l)
7f2e8c58
RA		 455 time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
456 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
95c278b2 457 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
4b613e9b
RA		 458 name, time_ns, time_ns_min, time_ns, l,
459 invalid ? "; invalid " : " ");
35ac051e 460 } else {
563dbb26 461 /* raw format */
95c278b2 462 pr_info("gpmc,%s = <%u>;%s\n", name, l,
4b613e9b 463 invalid ? " /* invalid */" : "");
35ac051e
TL		 464 }
465
466 return l;
467}
468
469#define GPMC_PRINT_CONFIG(cs, config) \
470 pr_info("cs%i %s: 0x%08x\n", cs, #config, \
471 gpmc_cs_read_reg(cs, config))
472#define GPMC_GET_RAW(reg, st, end, field) \
4b613e9b
RA		 473 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
474#define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
475 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
35ac051e 476#define GPMC_GET_RAW_BOOL(reg, st, end, field) \
4b613e9b
RA		 477 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
478#define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
479 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
35ac051e 480#define GPMC_GET_TICKS(reg, st, end, field) \
4b613e9b 481 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
7f2e8c58 482#define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
4b613e9b
RA		 483 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
484#define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
485 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
35ac051e
TL		 486
487static void gpmc_show_regs(int cs, const char *desc)
488{
489 pr_info("gpmc cs%i %s:\n", cs, desc);
490 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
491 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
492 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
493 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
494 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
495 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
496}
497
498/*
499 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
500 * see commit c9fb809.
501 */
502static void gpmc_cs_show_timings(int cs, const char *desc)
503{
504 gpmc_show_regs(cs, desc);
505
506 pr_info("gpmc cs%i access configuration:\n", cs);
507 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
508 GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
aff523fb 509 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
cdd1aeae 510 GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
35ac051e
TL		 511 GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
512 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
513 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
4b613e9b
RA		 514 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
515 GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
516 "burst-length");
35ac051e
TL		 517 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
518 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
519 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
520 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
521 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
522
523 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay");
524
525 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay");
526
527 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
528 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay");
529
530 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen");
531 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen");
532
533 pr_info("gpmc cs%i timings configuration:\n", cs);
534 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns");
535 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns");
536 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
537
538 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns");
539 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns");
540 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
2c92c04b
NA		 541 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
542 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
543 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
544 "adv-aad-mux-rd-off-ns");
545 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
546 "adv-aad-mux-wr-off-ns");
547 }
35ac051e
TL		 548
549 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns");
550 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns");
2c92c04b
NA		 551 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
552 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns");
553 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
554 }
35ac051e
TL		 555 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
556 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
557
558 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns");
559 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns");
560 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
561
562 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
563
564 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
565 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
566
4b613e9b
RA		 567 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
568 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
569 "wait-monitoring-ns", GPMC_CD_CLK);
570 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
571 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
572 "clk-activation-ns", GPMC_CD_FCLK);
35ac051e
TL		 573
574 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
575 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
576}
4bbbc1ad 577#else
35ac051e
TL		 578static inline void gpmc_cs_show_timings(int cs, const char *desc)
579{
580}
4bbbc1ad 581#endif
35ac051e 582
7f2e8c58
RA		 583/**
584 * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
585 * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
586 * prior to calling this function with @cd equal to GPMC_CD_CLK.
587 *
588 * @cs: Chip Select Region.
589 * @reg: GPMC_CS_CONFIGn register offset.
590 * @st_bit: Start Bit
591 * @end_bit: End Bit. Must be >= @st_bit.
4b613e9b
RA		 592 * @max: Maximum parameter value.
593 * If 0, maximum is as high as @st_bit and @end_bit allow.
7f2e8c58
RA		 594 * @time: Timing parameter in ns.
595 * @cd: Timing parameter clock domain.
596 * @name: Timing parameter name.
597 * @return: 0 on success, -1 on error.
598 */
4b613e9b 599static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
7f2e8c58 600 int time, enum gpmc_clk_domain cd, const char *name)
4bbbc1ad
JY		 601{
602 u32 l;
603 int ticks, mask, nr_bits;
604
605 if (time == 0)
606 ticks = 0;
607 else
7f2e8c58 608 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
4bbbc1ad 609 nr_bits = end_bit - st_bit + 1;
80323742
RQ		 610 mask = (1 << nr_bits) - 1;
611
4b613e9b
RA		 612 if (!max)
613 max = mask;
614
615 if (ticks > max) {
7f2e8c58 616 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
4b613e9b 617 __func__, cs, name, time, ticks, max);
80323742 618
4bbbc1ad 619 return -1;
1c22cc13 620 }
4bbbc1ad 621
4bbbc1ad 622 l = gpmc_cs_read_reg(cs, reg);
63aa945b 623#ifdef CONFIG_OMAP_GPMC_DEBUG
cdd1aeae
KK		 624 pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
625 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
1c22cc13 626 (l >> st_bit) & mask, time);
4bbbc1ad
JY		 627#endif
628 l &= ~(mask << st_bit);
629 l |= ticks << st_bit;
630 gpmc_cs_write_reg(cs, reg, l);
631
632 return 0;
633}
634
2e676901
RA		 635/**
636 * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
637 * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
638 * read --> don't sample bus too early
639 * write --> data is longer on bus
640 *
641 * Formula:
642 * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
643 * / waitmonitoring_ticks)
644 * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
645 * div <= 0 check.
646 *
647 * @wait_monitoring: WAITMONITORINGTIME in ns.
648 * @return: -1 on failure to scale, else proper divider > 0.
649 */
650static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
651{
2e676901
RA		 652 int div = gpmc_ns_to_ticks(wait_monitoring);
653
654 div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
655 div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
656
657 if (div > 4)
658 return -1;
659 if (div <= 0)
660 div = 1;
661
662 return div;
2e676901
RA		 663}
664
665/**
666 * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
667 * @sync_clk: GPMC_CLK period in ps.
668 * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
669 * Else, returns -1.
670 */
1b47ca1a 671int gpmc_calc_divider(unsigned int sync_clk)
4bbbc1ad 672{
2e676901 673 int div = gpmc_ps_to_ticks(sync_clk);
4bbbc1ad 674
4bbbc1ad
JY		 675 if (div > 4)
676 return -1;
1c22cc13 677 if (div <= 0)
4bbbc1ad
JY		 678 div = 1;
679
680 return div;
681}
682
2e676901
RA		 683/**
684 * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
685 * @cs: Chip Select Region.
686 * @t: GPMC timing parameters.
687 * @s: GPMC timing settings.
688 * @return: 0 on success, -1 on error.
689 */
690int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
691 const struct gpmc_settings *s)
4bbbc1ad 692{
1724f1b6 693 int div, ret;
4bbbc1ad
JY		 694 u32 l;
695
1b47ca1a 696 div = gpmc_calc_divider(t->sync_clk);
4bbbc1ad 697 if (div < 0)
d25112aa 698 return -EINVAL;
4bbbc1ad 699
2e676901
RA		 700 /*
701 * See if we need to change the divider for waitmonitoringtime.
702 *
703 * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
704 * pure asynchronous accesses, i.e. both read and write asynchronous.
705 * However, only do so if WAITMONITORINGTIME is actually used, i.e.
706 * either WAITREADMONITORING or WAITWRITEMONITORING is set.
707 *
708 * This statement must not change div to scale async WAITMONITORINGTIME
709 * to protect mixed synchronous and asynchronous accesses.
710 *
711 * We raise an error later if WAITMONITORINGTIME does not fit.
712 */
713 if (!s->sync_read && !s->sync_write &&
714 (s->wait_on_read || s->wait_on_write)
715 ) {
2e676901
RA		 716 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
717 if (div < 0) {
718 pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
719 __func__,
720 t->wait_monitoring
721 );
d25112aa 722 return -ENXIO;
2e676901
RA		 723 }
724 }
725
1724f1b6
KK		 726 ret = 0;
727 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 0, 3, 0, t->cs_on,
728 GPMC_CD_FCLK, "cs_on");
729 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 8, 12, 0, t->cs_rd_off,
730 GPMC_CD_FCLK, "cs_rd_off");
731 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 16, 20, 0, t->cs_wr_off,
732 GPMC_CD_FCLK, "cs_wr_off");
733 if (ret)
734 return -ENXIO;
735
736 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 0, 3, 0, t->adv_on,
737 GPMC_CD_FCLK, "adv_on");
738 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 8, 12, 0, t->adv_rd_off,
739 GPMC_CD_FCLK, "adv_rd_off");
740 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 16, 20, 0, t->adv_wr_off,
741 GPMC_CD_FCLK, "adv_wr_off");
742 if (ret)
743 return -ENXIO;
4bbbc1ad 744
2c92c04b 745 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
1724f1b6
KK		 746 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 4, 6, 0,
747 t->adv_aad_mux_on, GPMC_CD_FCLK,
748 "adv_aad_mux_on");
749 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 24, 26, 0,
750 t->adv_aad_mux_rd_off, GPMC_CD_FCLK,
751 "adv_aad_mux_rd_off");
752 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 28, 30, 0,
753 t->adv_aad_mux_wr_off, GPMC_CD_FCLK,
754 "adv_aad_mux_wr_off");
755 if (ret)
756 return -ENXIO;
2c92c04b 757 }
4bbbc1ad 758
1724f1b6
KK		 759 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 0, 3, 0, t->oe_on,
760 GPMC_CD_FCLK, "oe_on");
761 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 8, 12, 0, t->oe_off,
762 GPMC_CD_FCLK, "oe_off");
2c92c04b 763 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
1724f1b6
KK		 764 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 4, 6, 0,
765 t->oe_aad_mux_on, GPMC_CD_FCLK,
766 "oe_aad_mux_on");
767 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 13, 15, 0,
768 t->oe_aad_mux_off, GPMC_CD_FCLK,
769 "oe_aad_mux_off");
770 }
771 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 16, 19, 0, t->we_on,
772 GPMC_CD_FCLK, "we_on");
773 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 24, 28, 0, t->we_off,
774 GPMC_CD_FCLK, "we_off");
775 if (ret)
776 return -ENXIO;
777
778 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 0, 4, 0, t->rd_cycle,
779 GPMC_CD_FCLK, "rd_cycle");
780 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 8, 12, 0, t->wr_cycle,
781 GPMC_CD_FCLK, "wr_cycle");
782 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 16, 20, 0, t->access,
783 GPMC_CD_FCLK, "access");
784 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 24, 27, 0,
785 t->page_burst_access, GPMC_CD_FCLK,
786 "page_burst_access");
787 if (ret)
788 return -ENXIO;
789
790 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 0, 3, 0,
791 t->bus_turnaround, GPMC_CD_FCLK,
792 "bus_turnaround");
793 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 8, 11, 0,
794 t->cycle2cycle_delay, GPMC_CD_FCLK,
795 "cycle2cycle_delay");
796 if (ret)
797 return -ENXIO;
798
799 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) {
800 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 16, 19, 0,
801 t->wr_data_mux_bus, GPMC_CD_FCLK,
802 "wr_data_mux_bus");
803 if (ret)
804 return -ENXIO;
805 }
806 if (gpmc_capability & GPMC_HAS_WR_ACCESS) {
807 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 24, 28, 0,
808 t->wr_access, GPMC_CD_FCLK,
809 "wr_access");
810 if (ret)
811 return -ENXIO;
2c92c04b 812 }
cc26b3b0 813
1c22cc13 814 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
7f2e8c58
RA		 815 l &= ~0x03;
816 l |= (div - 1);
817 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
818
1724f1b6
KK		 819 ret = 0;
820 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 18, 19,
821 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
822 t->wait_monitoring, GPMC_CD_CLK,
823 "wait_monitoring");
824 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 25, 26,
825 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
826 t->clk_activation, GPMC_CD_FCLK,
827 "clk_activation");
828 if (ret)
829 return -ENXIO;
7f2e8c58 830
63aa945b 831#ifdef CONFIG_OMAP_GPMC_DEBUG
f585070b
RA		 832 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
833 cs, (div * gpmc_get_fclk_period()) / 1000, div);
4bbbc1ad 834#endif
4bbbc1ad 835
559d94b0 836 gpmc_cs_bool_timings(cs, &t->bool_timings);
35ac051e 837 gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
559d94b0 838
4bbbc1ad
JY		 839 return 0;
840}
841
4cf27d2e 842static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
f37e4580
ID		 843{
844 u32 l;
845 u32 mask;
846
c71f8e9b
JH		 847 /*
848 * Ensure that base address is aligned on a
849 * boundary equal to or greater than size.
850 */
851 if (base & (size - 1))
852 return -EINVAL;
853
9c4f757e 854 base >>= GPMC_CHUNK_SHIFT;
f37e4580 855 mask = (1 << GPMC_SECTION_SHIFT) - size;
9c4f757e
SP		 856 mask >>= GPMC_CHUNK_SHIFT;
857 mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
858
f37e4580 859 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
9c4f757e
SP		 860 l &= ~GPMC_CONFIG7_MASK;
861 l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
862 l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
a2d3e7ba 863 l |= GPMC_CONFIG7_CSVALID;
f37e4580 864 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
c71f8e9b
JH		 865
866 return 0;
f37e4580
ID		 867}
868
4cf27d2e
RQ		 869static void gpmc_cs_enable_mem(int cs)
870{
871 u32 l;
872
873 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
874 l |= GPMC_CONFIG7_CSVALID;
875 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
876}
877
f37e4580
ID		 878static void gpmc_cs_disable_mem(int cs)
879{
880 u32 l;
881
882 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
a2d3e7ba 883 l &= ~GPMC_CONFIG7_CSVALID;
f37e4580
ID		 884 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
885}
886
887static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
888{
889 u32 l;
890 u32 mask;
891
892 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
893 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
894 mask = (l >> 8) & 0x0f;
895 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
896}
897
898static int gpmc_cs_mem_enabled(int cs)
899{
900 u32 l;
901
902 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
a2d3e7ba 903 return l & GPMC_CONFIG7_CSVALID;
f37e4580
ID		 904}
905
f5d8edaf 906static void gpmc_cs_set_reserved(int cs, int reserved)
4bbbc1ad 907{
9ed7a776
TL		 908 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
909
910 gpmc->flags |= GPMC_CS_RESERVED;
f37e4580
ID		 911}
912
ae9d908a 913static bool gpmc_cs_reserved(int cs)
f37e4580 914{
9ed7a776
TL		 915 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
916
917 return gpmc->flags & GPMC_CS_RESERVED;
918}
919
920static void gpmc_cs_set_name(int cs, const char *name)
921{
922 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
923
924 gpmc->name = name;
925}
926
2e25b0ec 927static const char *gpmc_cs_get_name(int cs)
9ed7a776
TL		 928{
929 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
930
931 return gpmc->name;
f37e4580
ID		 932}
933
934static unsigned long gpmc_mem_align(unsigned long size)
935{
936 int order;
937
938 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
939 order = GPMC_CHUNK_SHIFT - 1;
940 do {
941 size >>= 1;
942 order++;
943 } while (size);
944 size = 1 << order;
945 return size;
946}
947
948static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
949{
9ed7a776
TL		 950 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
951 struct resource *res = &gpmc->mem;
f37e4580
ID		 952 int r;
953
954 size = gpmc_mem_align(size);
955 spin_lock(&gpmc_mem_lock);
956 res->start = base;
957 res->end = base + size - 1;
958 r = request_resource(&gpmc_mem_root, res);
959 spin_unlock(&gpmc_mem_lock);
960
961 return r;
962}
963
da496873
AM		 964static int gpmc_cs_delete_mem(int cs)
965{
9ed7a776
TL		 966 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
967 struct resource *res = &gpmc->mem;
da496873
AM		 968 int r;
969
970 spin_lock(&gpmc_mem_lock);
efe80723 971 r = release_resource(res);
da496873
AM		 972 res->start = 0;
973 res->end = 0;
974 spin_unlock(&gpmc_mem_lock);
975
976 return r;
977}
978
cdd6928c
JH		 979/**
980 * gpmc_cs_remap - remaps a chip-select physical base address
981 * @cs: chip-select to remap
982 * @base: physical base address to re-map chip-select to
983 *
984 * Re-maps a chip-select to a new physical base address specified by
985 * "base". Returns 0 on success and appropriate negative error code
986 * on failure.
987 */
988static int gpmc_cs_remap(int cs, u32 base)
989{
990 int ret;
991 u32 old_base, size;
992
f34f3716
GP		 993 if (cs > gpmc_cs_num) {
994 pr_err("%s: requested chip-select is disabled\n", __func__);
cdd6928c 995 return -ENODEV;
f34f3716 996 }
fb677ef7
TL		 997
998 /*
999 * Make sure we ignore any device offsets from the GPMC partition
1000 * allocated for the chip select and that the new base confirms
1001 * to the GPMC 16MB minimum granularity.
1a1e7580 1002 */
fb677ef7
TL		 1003 base &= ~(SZ_16M - 1);
1004
cdd6928c
JH		 1005 gpmc_cs_get_memconf(cs, &old_base, &size);
1006 if (base == old_base)
1007 return 0;
4cf27d2e 1008
cdd6928c
JH		 1009 ret = gpmc_cs_delete_mem(cs);
1010 if (ret < 0)
1011 return ret;
4cf27d2e 1012
cdd6928c 1013 ret = gpmc_cs_insert_mem(cs, base, size);
c71f8e9b
JH		 1014 if (ret < 0)
1015 return ret;
cdd6928c 1016
4cf27d2e
RQ		 1017 ret = gpmc_cs_set_memconf(cs, base, size);
1018
1019 return ret;
cdd6928c
JH		 1020}
1021
f37e4580
ID		 1022int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
1023{
9ed7a776
TL		 1024 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1025 struct resource *res = &gpmc->mem;
f37e4580
ID		 1026 int r = -1;
1027
f34f3716
GP		 1028 if (cs > gpmc_cs_num) {
1029 pr_err("%s: requested chip-select is disabled\n", __func__);
f37e4580 1030 return -ENODEV;
f34f3716 1031 }
f37e4580
ID		 1032 size = gpmc_mem_align(size);
1033 if (size > (1 << GPMC_SECTION_SHIFT))
1034 return -ENOMEM;
1035
1036 spin_lock(&gpmc_mem_lock);
1037 if (gpmc_cs_reserved(cs)) {
1038 r = -EBUSY;
1039 goto out;
1040 }
1041 if (gpmc_cs_mem_enabled(cs))
1042 r = adjust_resource(res, res->start & ~(size - 1), size);
1043 if (r < 0)
1044 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
1045 size, NULL, NULL);
1046 if (r < 0)
1047 goto out;
1048
4cf27d2e
RQ		 1049 /* Disable CS while changing base address and size mask */
1050 gpmc_cs_disable_mem(cs);
1051
1052 r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
c71f8e9b
JH		 1053 if (r < 0) {
1054 release_resource(res);
1055 goto out;
1056 }
1057
4cf27d2e
RQ		 1058 /* Enable CS */
1059 gpmc_cs_enable_mem(cs);
f37e4580
ID		 1060 *base = res->start;
1061 gpmc_cs_set_reserved(cs, 1);
1062out:
1063 spin_unlock(&gpmc_mem_lock);
1064 return r;
1065}
fd1dc87d 1066EXPORT_SYMBOL(gpmc_cs_request);
f37e4580
ID		 1067
1068void gpmc_cs_free(int cs)
1069{
9ed7a776
TL		 1070 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1071 struct resource *res = &gpmc->mem;
efe80723 1072
f37e4580 1073 spin_lock(&gpmc_mem_lock);
f34f3716 1074 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
07b6cc45 1075 WARN(1, "Trying to free non-reserved GPMC CS%d\n", cs);
f37e4580
ID		 1076 spin_unlock(&gpmc_mem_lock);
1077 return;
1078 }
1079 gpmc_cs_disable_mem(cs);
efe80723
TL		 1080 if (res->flags)
1081 release_resource(res);
f37e4580
ID		 1082 gpmc_cs_set_reserved(cs, 0);
1083 spin_unlock(&gpmc_mem_lock);
1084}
fd1dc87d 1085EXPORT_SYMBOL(gpmc_cs_free);
f37e4580 1086
948d38e7 1087/**
3a544354 1088 * gpmc_configure - write request to configure gpmc
948d38e7
SG		 1089 * @cmd: command type
1090 * @wval: value to write
1091 * @return status of the operation
1092 */
3a544354 1093int gpmc_configure(int cmd, int wval)
948d38e7 1094{
3a544354 1095 u32 regval;
948d38e7
SG		 1096
1097 switch (cmd) {
948d38e7
SG		 1098 case GPMC_CONFIG_WP:
1099 regval = gpmc_read_reg(GPMC_CONFIG);
1100 if (wval)
1101 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1102 else
1103 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
1104 gpmc_write_reg(GPMC_CONFIG, regval);
1105 break;
1106
948d38e7 1107 default:
3a544354
JH		 1108 pr_err("%s: command not supported\n", __func__);
1109 return -EINVAL;
948d38e7
SG		 1110 }
1111
3a544354 1112 return 0;
948d38e7 1113}
3a544354 1114EXPORT_SYMBOL(gpmc_configure);
948d38e7 1115
a622c641
LM		 1116static bool gpmc_nand_writebuffer_empty(void)
1117{
1118 if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1119 return true;
1120
1121 return false;
1122}
1123
1124static struct gpmc_nand_ops nand_ops = {
1125 .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1126};
1127
1128/**
1129 * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
80c4f5a8 1130 * @reg: the GPMC NAND register map exclusive for NAND use.
a622c641
LM		 1131 * @cs: GPMC chip select number on which the NAND sits. The
1132 * register map returned will be specific to this chip select.
1133 *
1134 * Returns NULL on error e.g. invalid cs.
1135 */
1136struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
52bd138d 1137{
2fdf0c98
AM		 1138 int i;
1139
a622c641
LM		 1140 if (cs >= gpmc_cs_num)
1141 return NULL;
1142
52bd138d
AM		 1143 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1144 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1145 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1146 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1147 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1148 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1149 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1150 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1151 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1152 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1153 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1154 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1155 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1156 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
2fdf0c98
AM		 1157
1158 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1159 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1160 GPMC_BCH_SIZE * i;
1161 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1162 GPMC_BCH_SIZE * i;
1163 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1164 GPMC_BCH_SIZE * i;
1165 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1166 GPMC_BCH_SIZE * i;
27c9fd60 1167 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1168 i * GPMC_BCH_SIZE;
1169 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1170 i * GPMC_BCH_SIZE;
1171 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1172 i * GPMC_BCH_SIZE;
2fdf0c98 1173 }
f47fcad6
RQ		 1174
1175 return &nand_ops;
1176}
1177EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1178
a758f50f
LM		 1179static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
1180 struct gpmc_settings *s,
1181 int freq, int latency)
1182{
1183 struct gpmc_device_timings dev_t;
1184 const int t_cer = 15;
1185 const int t_avdp = 12;
1186 const int t_cez = 20; /* max of t_cez, t_oez */
1187 const int t_wpl = 40;
1188 const int t_wph = 30;
1189 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
1190
1191 switch (freq) {
1192 case 104:
1193 min_gpmc_clk_period = 9600; /* 104 MHz */
1194 t_ces = 3;
1195 t_avds = 4;
1196 t_avdh = 2;
1197 t_ach = 3;
1198 t_aavdh = 6;
1199 t_rdyo = 6;
1200 break;
1201 case 83:
1202 min_gpmc_clk_period = 12000; /* 83 MHz */
1203 t_ces = 5;
1204 t_avds = 4;
1205 t_avdh = 2;
1206 t_ach = 6;
1207 t_aavdh = 6;
1208 t_rdyo = 9;
1209 break;
1210 case 66:
1211 min_gpmc_clk_period = 15000; /* 66 MHz */
1212 t_ces = 6;
1213 t_avds = 5;
1214 t_avdh = 2;
1215 t_ach = 6;
1216 t_aavdh = 6;
1217 t_rdyo = 11;
1218 break;
1219 default:
1220 min_gpmc_clk_period = 18500; /* 54 MHz */
1221 t_ces = 7;
1222 t_avds = 7;
1223 t_avdh = 7;
1224 t_ach = 9;
1225 t_aavdh = 7;
1226 t_rdyo = 15;
1227 break;
1228 }
1229
1230 /* Set synchronous read timings */
1231 memset(&dev_t, 0, sizeof(dev_t));
1232
1233 if (!s->sync_write) {
1234 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
1235 dev_t.t_wpl = t_wpl * 1000;
1236 dev_t.t_wph = t_wph * 1000;
1237 dev_t.t_aavdh = t_aavdh * 1000;
1238 }
1239 dev_t.ce_xdelay = true;
1240 dev_t.avd_xdelay = true;
1241 dev_t.oe_xdelay = true;
1242 dev_t.we_xdelay = true;
1243 dev_t.clk = min_gpmc_clk_period;
1244 dev_t.t_bacc = dev_t.clk;
1245 dev_t.t_ces = t_ces * 1000;
1246 dev_t.t_avds = t_avds * 1000;
1247 dev_t.t_avdh = t_avdh * 1000;
1248 dev_t.t_ach = t_ach * 1000;
1249 dev_t.cyc_iaa = (latency + 1);
1250 dev_t.t_cez_r = t_cez * 1000;
1251 dev_t.t_cez_w = dev_t.t_cez_r;
1252 dev_t.cyc_aavdh_oe = 1;
1253 dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
1254
1255 gpmc_calc_timings(t, s, &dev_t);
1256}
1257
1258int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
1259 int latency,
1260 struct gpmc_onenand_info *info)
1261{
1262 int ret;
1263 struct gpmc_timings gpmc_t;
1264 struct gpmc_settings gpmc_s;
1265
1266 gpmc_read_settings_dt(dev->of_node, &gpmc_s);
1267
1268 info->sync_read = gpmc_s.sync_read;
1269 info->sync_write = gpmc_s.sync_write;
1270 info->burst_len = gpmc_s.burst_len;
1271
1272 if (!gpmc_s.sync_read && !gpmc_s.sync_write)
1273 return 0;
1274
1275 gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
1276
1277 ret = gpmc_cs_program_settings(cs, &gpmc_s);
1278 if (ret < 0)
1279 return ret;
1280
1281 return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1282}
1283EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
1284
1cd53458 1285int gpmc_get_client_irq(unsigned int irq_config)
6b6c32fc 1286{
384258f2
RQ		 1287 if (!gpmc_irq_domain) {
1288 pr_warn("%s called before GPMC IRQ domain available\n",
1289 __func__);
6b6c32fc 1290 return 0;
384258f2 1291 }
6b6c32fc 1292
b2bac25a
RQ		 1293 /* we restrict this to NAND IRQs only */
1294 if (irq_config >= GPMC_NR_NAND_IRQS)
384258f2 1295 return 0;
6b6c32fc 1296
384258f2 1297 return irq_create_mapping(gpmc_irq_domain, irq_config);
6b6c32fc
AM		 1298}
1299
384258f2 1300static int gpmc_irq_endis(unsigned long hwirq, bool endis)
6b6c32fc 1301{
6b6c32fc
AM		 1302 u32 regval;
1303
b2bac25a
RQ		 1304 /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
1305 if (hwirq >= GPMC_NR_NAND_IRQS)
1306 hwirq += 8 - GPMC_NR_NAND_IRQS;
1307
384258f2
RQ		 1308 regval = gpmc_read_reg(GPMC_IRQENABLE);
1309 if (endis)
1310 regval |= BIT(hwirq);
1311 else
1312 regval &= ~BIT(hwirq);
1313 gpmc_write_reg(GPMC_IRQENABLE, regval);
6b6c32fc
AM		 1314
1315 return 0;
1316}
1317
1318static void gpmc_irq_disable(struct irq_data *p)
1319{
384258f2 1320 gpmc_irq_endis(p->hwirq, false);
6b6c32fc
AM		 1321}
1322
1323static void gpmc_irq_enable(struct irq_data *p)
1324{
384258f2 1325 gpmc_irq_endis(p->hwirq, true);
6b6c32fc
AM		 1326}
1327
b2bac25a
RQ		 1328static void gpmc_irq_mask(struct irq_data *d)
1329{
1330 gpmc_irq_endis(d->hwirq, false);
1331}
1332
1333static void gpmc_irq_unmask(struct irq_data *d)
1334{
1335 gpmc_irq_endis(d->hwirq, true);
1336}
1337
1338static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
1339{
1340 u32 regval;
1341
1342 /* NAND IRQs polarity is not configurable */
1343 if (hwirq < GPMC_NR_NAND_IRQS)
1344 return;
1345
1346 /* WAITPIN starts at BIT 8 */
1347 hwirq += 8 - GPMC_NR_NAND_IRQS;
1348
1349 regval = gpmc_read_reg(GPMC_CONFIG);
1350 if (rising_edge)
1351 regval &= ~BIT(hwirq);
1352 else
1353 regval |= BIT(hwirq);
1354
1355 gpmc_write_reg(GPMC_CONFIG, regval);
1356}
1357
1358static void gpmc_irq_ack(struct irq_data *d)
1359{
1360 unsigned int hwirq = d->hwirq;
1361
1362 /* skip reserved bits */
1363 if (hwirq >= GPMC_NR_NAND_IRQS)
1364 hwirq += 8 - GPMC_NR_NAND_IRQS;
1365
1366 /* Setting bit to 1 clears (or Acks) the interrupt */
1367 gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
1368}
1369
1370static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
1371{
1372 /* can't set type for NAND IRQs */
1373 if (d->hwirq < GPMC_NR_NAND_IRQS)
1374 return -EINVAL;
1375
1376 /* We can support either rising or falling edge at a time */
1377 if (trigger == IRQ_TYPE_EDGE_FALLING)
1378 gpmc_irq_edge_config(d->hwirq, false);
1379 else if (trigger == IRQ_TYPE_EDGE_RISING)
1380 gpmc_irq_edge_config(d->hwirq, true);
1381 else
1382 return -EINVAL;
6b6c32fc 1383
b2bac25a
RQ		 1384 return 0;
1385}
6b6c32fc 1386
384258f2
RQ		 1387static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1388 irq_hw_number_t hw)
6b6c32fc 1389{
384258f2
RQ		 1390 struct gpmc_device *gpmc = d->host_data;
1391
1392 irq_set_chip_data(virq, gpmc);
b2bac25a
RQ		 1393 if (hw < GPMC_NR_NAND_IRQS) {
1394 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1395 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1396 handle_simple_irq);
1397 } else {
1398 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1399 handle_edge_irq);
1400 }
384258f2
RQ		 1401
1402 return 0;
1403}
1404
1405static const struct irq_domain_ops gpmc_irq_domain_ops = {
1406 .map = gpmc_irq_map,
1407 .xlate = irq_domain_xlate_twocell,
1408};
1409
1410static irqreturn_t gpmc_handle_irq(int irq, void *data)
1411{
1412 int hwirq, virq;
b2bac25a 1413 u32 regval, regvalx;
384258f2 1414 struct gpmc_device *gpmc = data;
6b6c32fc 1415
384258f2 1416 regval = gpmc_read_reg(GPMC_IRQSTATUS);
b2bac25a 1417 regvalx = regval;
6b6c32fc 1418
384258f2
RQ		 1419 if (!regval)
1420 return IRQ_NONE;
6b6c32fc 1421
b2bac25a
RQ		 1422 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
1423 /* skip reserved status bits */
1424 if (hwirq == GPMC_NR_NAND_IRQS)
1425 regvalx >>= 8 - GPMC_NR_NAND_IRQS;
1426
1427 if (regvalx & BIT(hwirq)) {
384258f2
RQ		 1428 virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1429 if (!virq) {
1430 dev_warn(gpmc->dev,
1431 "spurious irq detected hwirq %d, virq %d\n",
1432 hwirq, virq);
1433 }
1434
1435 generic_handle_irq(virq);
1436 }
6b6c32fc
AM		 1437 }
1438
384258f2
RQ		 1439 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1440
1441 return IRQ_HANDLED;
1442}
1443
1444static int gpmc_setup_irq(struct gpmc_device *gpmc)
1445{
1446 u32 regval;
1447 int rc;
1448
6b6c32fc
AM		 1449 /* Disable interrupts */
1450 gpmc_write_reg(GPMC_IRQENABLE, 0);
1451
1452 /* clear interrupts */
1453 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1454 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1455
384258f2 1456 gpmc->irq_chip.name = "gpmc";
384258f2
RQ		 1457 gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1458 gpmc->irq_chip.irq_disable = gpmc_irq_disable;
b2bac25a
RQ		 1459 gpmc->irq_chip.irq_ack = gpmc_irq_ack;
1460 gpmc->irq_chip.irq_mask = gpmc_irq_mask;
1461 gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
1462 gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
384258f2
RQ		 1463
1464 gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
b2bac25a 1465 gpmc->nirqs,
384258f2
RQ		 1466 &gpmc_irq_domain_ops,
1467 gpmc);
1468 if (!gpmc_irq_domain) {
1469 dev_err(gpmc->dev, "IRQ domain add failed\n");
1470 return -ENODEV;
1471 }
1472
1473 rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1474 if (rc) {
1475 dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1476 gpmc->irq, rc);
1477 irq_domain_remove(gpmc_irq_domain);
1478 gpmc_irq_domain = NULL;
1479 }
1480
1481 return rc;
6b6c32fc
AM		 1482}
1483
384258f2 1484static int gpmc_free_irq(struct gpmc_device *gpmc)
da496873 1485{
384258f2 1486 int hwirq;
da496873 1487
384258f2 1488 free_irq(gpmc->irq, gpmc);
da496873 1489
b2bac25a 1490 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
384258f2 1491 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
da496873 1492
384258f2
RQ		 1493 irq_domain_remove(gpmc_irq_domain);
1494 gpmc_irq_domain = NULL;
da496873
AM		 1495
1496 return 0;
1497}
1498
351a102d 1499static void gpmc_mem_exit(void)
da496873
AM		 1500{
1501 int cs;
1502
f34f3716 1503 for (cs = 0; cs < gpmc_cs_num; cs++) {
da496873
AM		 1504 if (!gpmc_cs_mem_enabled(cs))
1505 continue;
1506 gpmc_cs_delete_mem(cs);
1507 }
da496873
AM		 1508}
1509
84b00f0e 1510static void gpmc_mem_init(void)
f37e4580 1511{
84b00f0e 1512 int cs;
f37e4580 1513
bdd7e033 1514 gpmc_mem_root.start = GPMC_MEM_START;
f37e4580
ID		 1515 gpmc_mem_root.end = GPMC_MEM_END;
1516
1517 /* Reserve all regions that has been set up by bootloader */
f34f3716 1518 for (cs = 0; cs < gpmc_cs_num; cs++) {
f37e4580
ID		 1519 u32 base, size;
1520
1521 if (!gpmc_cs_mem_enabled(cs))
1522 continue;
1523 gpmc_cs_get_memconf(cs, &base, &size);
84b00f0e
JH		 1524 if (gpmc_cs_insert_mem(cs, base, size)) {
1525 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1526 __func__, cs, base, base + size);
1527 gpmc_cs_disable_mem(cs);
8119024e 1528 }
f37e4580 1529 }
4bbbc1ad
JY		 1530}
1531
246da26d
AM		 1532static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1533{
1534 u32 temp;
1535 int div;
1536
1537 div = gpmc_calc_divider(sync_clk);
1538 temp = gpmc_ps_to_ticks(time_ps);
1539 temp = (temp + div - 1) / div;
1540 return gpmc_ticks_to_ps(temp * div);
1541}
1542
1543/* XXX: can the cycles be avoided ? */
1544static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1545 struct gpmc_device_timings *dev_t,
1546 bool mux)
246da26d 1547{
246da26d
AM		 1548 u32 temp;
1549
1550 /* adv_rd_off */
1551 temp = dev_t->t_avdp_r;
1552 /* XXX: mux check required ? */
1553 if (mux) {
1554 /* XXX: t_avdp not to be required for sync, only added for tusb
1555 * this indirectly necessitates requirement of t_avdp_r and
1556 * t_avdp_w instead of having a single t_avdp
1557 */
1558 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1559 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1560 }
1561 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1562
1563 /* oe_on */
1564 temp = dev_t->t_oeasu; /* XXX: remove this ? */
1565 if (mux) {
1566 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1567 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1568 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1569 }
1570 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1571
1572 /* access */
1573 /* XXX: any scope for improvement ?, by combining oe_on
1574 * and clk_activation, need to check whether
1575 * access = clk_activation + round to sync clk ?
1576 */
1577 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1578 temp += gpmc_t->clk_activation;
1579 if (dev_t->cyc_oe)
1580 temp = max_t(u32, temp, gpmc_t->oe_on +
1581 gpmc_ticks_to_ps(dev_t->cyc_oe));
1582 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1583
1584 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1585 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1586
1587 /* rd_cycle */
1588 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1589 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1590 gpmc_t->access;
1591 /* XXX: barter t_ce_rdyz with t_cez_r ? */
1592 if (dev_t->t_ce_rdyz)
1593 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1594 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1595
1596 return 0;
1597}
1598
1599static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1600 struct gpmc_device_timings *dev_t,
1601 bool mux)
246da26d 1602{
246da26d
AM		 1603 u32 temp;
1604
1605 /* adv_wr_off */
1606 temp = dev_t->t_avdp_w;
1607 if (mux) {
1608 temp = max_t(u32, temp,
1609 gpmc_t->clk_activation + dev_t->t_avdh);
1610 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1611 }
1612 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1613
1614 /* wr_data_mux_bus */
1615 temp = max_t(u32, dev_t->t_weasu,
1616 gpmc_t->clk_activation + dev_t->t_rdyo);
1617 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1618 * and in that case remember to handle we_on properly
1619 */
1620 if (mux) {
1621 temp = max_t(u32, temp,
1622 gpmc_t->adv_wr_off + dev_t->t_aavdh);
1623 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1624 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1625 }
1626 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1627
1628 /* we_on */
1629 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1630 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1631 else
1632 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1633
1634 /* wr_access */
1635 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1636 gpmc_t->wr_access = gpmc_t->access;
1637
1638 /* we_off */
1639 temp = gpmc_t->we_on + dev_t->t_wpl;
1640 temp = max_t(u32, temp,
1641 gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1642 temp = max_t(u32, temp,
1643 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1644 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1645
1646 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1647 dev_t->t_wph);
1648
1649 /* wr_cycle */
1650 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1651 temp += gpmc_t->wr_access;
1652 /* XXX: barter t_ce_rdyz with t_cez_w ? */
1653 if (dev_t->t_ce_rdyz)
1654 temp = max_t(u32, temp,
1655 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1656 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1657
1658 return 0;
1659}
1660
1661static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1662 struct gpmc_device_timings *dev_t,
1663 bool mux)
246da26d 1664{
246da26d
AM		 1665 u32 temp;
1666
1667 /* adv_rd_off */
1668 temp = dev_t->t_avdp_r;
1669 if (mux)
1670 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1671 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1672
1673 /* oe_on */
1674 temp = dev_t->t_oeasu;
1675 if (mux)
cdd1aeae 1676 temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh);
246da26d
AM		 1677 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1678
1679 /* access */
1680 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
cdd1aeae
KK		 1681 gpmc_t->oe_on + dev_t->t_oe);
1682 temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce);
1683 temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa);
246da26d
AM		 1684 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1685
1686 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1687 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1688
1689 /* rd_cycle */
1690 temp = max_t(u32, dev_t->t_rd_cycle,
1691 gpmc_t->cs_rd_off + dev_t->t_cez_r);
1692 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1693 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1694
1695 return 0;
1696}
1697
1698static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1699 struct gpmc_device_timings *dev_t,
1700 bool mux)
246da26d 1701{
246da26d
AM		 1702 u32 temp;
1703
1704 /* adv_wr_off */
1705 temp = dev_t->t_avdp_w;
1706 if (mux)
1707 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1708 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1709
1710 /* wr_data_mux_bus */
1711 temp = dev_t->t_weasu;
1712 if (mux) {
1713 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1714 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1715 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1716 }
1717 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1718
1719 /* we_on */
1720 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1721 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1722 else
1723 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1724
1725 /* we_off */
1726 temp = gpmc_t->we_on + dev_t->t_wpl;
1727 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1728
1729 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1730 dev_t->t_wph);
1731
1732 /* wr_cycle */
1733 temp = max_t(u32, dev_t->t_wr_cycle,
1734 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1735 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1736
1737 return 0;
1738}
1739
1740static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1741 struct gpmc_device_timings *dev_t)
1742{
1743 u32 temp;
1744
1745 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1746 gpmc_get_fclk_period();
1747
1748 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1749 dev_t->t_bacc,
1750 gpmc_t->sync_clk);
1751
1752 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1753 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1754
1755 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1756 return 0;
1757
1758 if (dev_t->ce_xdelay)
1759 gpmc_t->bool_timings.cs_extra_delay = true;
1760 if (dev_t->avd_xdelay)
1761 gpmc_t->bool_timings.adv_extra_delay = true;
1762 if (dev_t->oe_xdelay)
1763 gpmc_t->bool_timings.oe_extra_delay = true;
1764 if (dev_t->we_xdelay)
1765 gpmc_t->bool_timings.we_extra_delay = true;
1766
1767 return 0;
1768}
1769
1770static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1771 struct gpmc_device_timings *dev_t,
1772 bool sync)
246da26d
AM		 1773{
1774 u32 temp;
1775
1776 /* cs_on */
1777 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1778
1779 /* adv_on */
1780 temp = dev_t->t_avdasu;
1781 if (dev_t->t_ce_avd)
1782 temp = max_t(u32, temp,
1783 gpmc_t->cs_on + dev_t->t_ce_avd);
1784 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1785
c3be5b45 1786 if (sync)
246da26d
AM		 1787 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1788
1789 return 0;
1790}
1791
1a1e7580
KK		 1792/*
1793 * TODO: remove this function once all peripherals are confirmed to
246da26d
AM		 1794 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1795 * has to be modified to handle timings in ps instead of ns
1a1e7580 1796 */
246da26d
AM		 1797static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1798{
1799 t->cs_on /= 1000;
1800 t->cs_rd_off /= 1000;
1801 t->cs_wr_off /= 1000;
1802 t->adv_on /= 1000;
1803 t->adv_rd_off /= 1000;
1804 t->adv_wr_off /= 1000;
1805 t->we_on /= 1000;
1806 t->we_off /= 1000;
1807 t->oe_on /= 1000;
1808 t->oe_off /= 1000;
1809 t->page_burst_access /= 1000;
1810 t->access /= 1000;
1811 t->rd_cycle /= 1000;
1812 t->wr_cycle /= 1000;
1813 t->bus_turnaround /= 1000;
1814 t->cycle2cycle_delay /= 1000;
1815 t->wait_monitoring /= 1000;
1816 t->clk_activation /= 1000;
1817 t->wr_access /= 1000;
1818 t->wr_data_mux_bus /= 1000;
1819}
1820
1821int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1822 struct gpmc_settings *gpmc_s,
1823 struct gpmc_device_timings *dev_t)
246da26d 1824{
c3be5b45
JH		 1825 bool mux = false, sync = false;
1826
1827 if (gpmc_s) {
1828 mux = gpmc_s->mux_add_data ? true : false;
1829 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1830 }
1831
246da26d
AM		 1832 memset(gpmc_t, 0, sizeof(*gpmc_t));
1833
c3be5b45 1834 gpmc_calc_common_timings(gpmc_t, dev_t, sync);
246da26d 1835
c3be5b45
JH		 1836 if (gpmc_s && gpmc_s->sync_read)
1837 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
246da26d 1838 else
c3be5b45 1839 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
246da26d 1840
c3be5b45
JH		 1841 if (gpmc_s && gpmc_s->sync_write)
1842 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
246da26d 1843 else
c3be5b45 1844 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
246da26d
AM		 1845
1846 /* TODO: remove, see function definition */
1847 gpmc_convert_ps_to_ns(gpmc_t);
1848
1849 return 0;
1850}
1851
aa8d4767
JH		 1852/**
1853 * gpmc_cs_program_settings - programs non-timing related settings
1854 * @cs: GPMC chip-select to program
1855 * @p: pointer to GPMC settings structure
1856 *
1857 * Programs non-timing related settings for a GPMC chip-select, such as
1858 * bus-width, burst configuration, etc. Function should be called once
1859 * for each chip-select that is being used and must be called before
1860 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1861 * register will be initialised to zero by this function. Returns 0 on
1862 * success and appropriate negative error code on failure.
1863 */
1864int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1865{
1866 u32 config1;
1867
1868 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1869 pr_err("%s: invalid width %d!", __func__, p->device_width);
1870 return -EINVAL;
1871 }
1872
1873 /* Address-data multiplexing not supported for NAND devices */
1874 if (p->device_nand && p->mux_add_data) {
1875 pr_err("%s: invalid configuration!\n", __func__);
1876 return -EINVAL;
1877 }
1878
1879 if ((p->mux_add_data > GPMC_MUX_AD) ||
1880 ((p->mux_add_data == GPMC_MUX_AAD) &&
1881 !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1882 pr_err("%s: invalid multiplex configuration!\n", __func__);
1883 return -EINVAL;
1884 }
1885
1886 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1887 if (p->burst_read || p->burst_write) {
1888 switch (p->burst_len) {
1889 case GPMC_BURST_4:
1890 case GPMC_BURST_8:
1891 case GPMC_BURST_16:
1892 break;
1893 default:
1894 pr_err("%s: invalid page/burst-length (%d)\n",
1895 __func__, p->burst_len);
1896 return -EINVAL;
1897 }
1898 }
1899
2b54057c 1900 if (p->wait_pin > gpmc_nr_waitpins) {
aa8d4767
JH		 1901 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1902 return -EINVAL;
1903 }
1904
1905 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1906
1907 if (p->sync_read)
1908 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1909 if (p->sync_write)
1910 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1911 if (p->wait_on_read)
1912 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1913 if (p->wait_on_write)
1914 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1915 if (p->wait_on_read || p->wait_on_write)
1916 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1917 if (p->device_nand)
1918 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1919 if (p->mux_add_data)
1920 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1921 if (p->burst_read)
1922 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1923 if (p->burst_write)
1924 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1925 if (p->burst_read || p->burst_write) {
1926 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1927 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1928 }
1929
1930 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1931
1932 return 0;
1933}
1934
bc6b1e7b 1935#ifdef CONFIG_OF
31957609 1936static const struct of_device_id gpmc_dt_ids[] = {
bc6b1e7b
DM		 1937 { .compatible = "ti,omap2420-gpmc" },
1938 { .compatible = "ti,omap2430-gpmc" },
1939 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1940 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1941 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
1942 { }
1943};
bc6b1e7b 1944
8c8a7771
JH		 1945/**
1946 * gpmc_read_settings_dt - read gpmc settings from device-tree
1947 * @np: pointer to device-tree node for a gpmc child device
1948 * @p: pointer to gpmc settings structure
1949 *
1950 * Reads the GPMC settings for a GPMC child device from device-tree and
1951 * stores them in the GPMC settings structure passed. The GPMC settings
1952 * structure is initialised to zero by this function and so any
1953 * previously stored settings will be cleared.
1954 */
1955void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1956{
1957 memset(p, 0, sizeof(struct gpmc_settings));
1958
1959 p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1960 p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
8c8a7771
JH		 1961 of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1962 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1963
1964 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1965 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1966 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1967 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1968 if (!p->burst_read && !p->burst_write)
1969 pr_warn("%s: page/burst-length set but not used!\n",
1970 __func__);
1971 }
1972
1973 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1974 p->wait_on_read = of_property_read_bool(np,
1975 "gpmc,wait-on-read");
1976 p->wait_on_write = of_property_read_bool(np,
1977 "gpmc,wait-on-write");
1978 if (!p->wait_on_read && !p->wait_on_write)
2b54057c
RQ		 1979 pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1980 __func__);
8c8a7771
JH		 1981 }
1982}
1983
bc6b1e7b
DM		 1984static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1985 struct gpmc_timings *gpmc_t)
1986{
d36b4cd4
JH		 1987 struct gpmc_bool_timings *p;
1988
1989 if (!np || !gpmc_t)
1990 return;
bc6b1e7b
DM		 1991
1992 memset(gpmc_t, 0, sizeof(*gpmc_t));
1993
1994 /* minimum clock period for syncronous mode */
d36b4cd4 1995 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
bc6b1e7b
DM		 1996
1997 /* chip select timtings */
d36b4cd4
JH		 1998 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1999 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
2000 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
bc6b1e7b
DM		 2001
2002 /* ADV signal timings */
d36b4cd4
JH		 2003 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
2004 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
2005 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
2c92c04b
NA		 2006 of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
2007 &gpmc_t->adv_aad_mux_on);
2008 of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
2009 &gpmc_t->adv_aad_mux_rd_off);
2010 of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
2011 &gpmc_t->adv_aad_mux_wr_off);
bc6b1e7b
DM		 2012
2013 /* WE signal timings */
d36b4cd4
JH		 2014 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
2015 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
bc6b1e7b
DM		 2016
2017 /* OE signal timings */
d36b4cd4
JH		 2018 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
2019 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
2c92c04b
NA		 2020 of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
2021 &gpmc_t->oe_aad_mux_on);
2022 of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
2023 &gpmc_t->oe_aad_mux_off);
bc6b1e7b
DM		 2024
2025 /* access and cycle timings */
d36b4cd4
JH		 2026 of_property_read_u32(np, "gpmc,page-burst-access-ns",
2027 &gpmc_t->page_burst_access);
2028 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
2029 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
2030 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
2031 of_property_read_u32(np, "gpmc,bus-turnaround-ns",
2032 &gpmc_t->bus_turnaround);
2033 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
2034 &gpmc_t->cycle2cycle_delay);
2035 of_property_read_u32(np, "gpmc,wait-monitoring-ns",
2036 &gpmc_t->wait_monitoring);
2037 of_property_read_u32(np, "gpmc,clk-activation-ns",
2038 &gpmc_t->clk_activation);
2039
2040 /* only applicable to OMAP3+ */
2041 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
2042 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
2043 &gpmc_t->wr_data_mux_bus);
2044
2045 /* bool timing parameters */
2046 p = &gpmc_t->bool_timings;
2047
2048 p->cycle2cyclediffcsen =
2049 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
2050 p->cycle2cyclesamecsen =
2051 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
2052 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
2053 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
2054 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
2055 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
2056 p->time_para_granularity =
2057 of_property_read_bool(np, "gpmc,time-para-granularity");
bc6b1e7b
DM		 2058}
2059
cdd6928c 2060/**
3af91cf7 2061 * gpmc_probe_generic_child - configures the gpmc for a child device
cdd6928c 2062 * @pdev: pointer to gpmc platform device
3af91cf7 2063 * @child: pointer to device-tree node for child device
cdd6928c 2064 *
3af91cf7 2065 * Allocates and configures a GPMC chip-select for a child device.
cdd6928c
JH		 2066 * Returns 0 on success and appropriate negative error code on failure.
2067 */
3af91cf7 2068static int gpmc_probe_generic_child(struct platform_device *pdev,
cdd6928c
JH		 2069 struct device_node *child)
2070{
2071 struct gpmc_settings gpmc_s;
2072 struct gpmc_timings gpmc_t;
2073 struct resource res;
2074 unsigned long base;
9ed7a776 2075 const char *name;
cdd6928c 2076 int ret, cs;
e378d22b 2077 u32 val;
210325f0
RQ		 2078 struct gpio_desc *waitpin_desc = NULL;
2079 struct gpmc_device *gpmc = platform_get_drvdata(pdev);
cdd6928c
JH		 2080
2081 if (of_property_read_u32(child, "reg", &cs) < 0) {
db749d17
RH		 2082 dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
2083 child);
cdd6928c
JH		 2084 return -ENODEV;
2085 }
2086
2087 if (of_address_to_resource(child, 0, &res) < 0) {
db749d17
RH		 2088 dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
2089 child);
cdd6928c
JH		 2090 return -ENODEV;
2091 }
2092
9ed7a776
TL		 2093 /*
2094 * Check if we have multiple instances of the same device
2095 * on a single chip select. If so, use the already initialized
2096 * timings.
2097 */
2098 name = gpmc_cs_get_name(cs);
c2ade654 2099 if (name && of_node_name_eq(child, name))
d507178f 2100 goto no_timings;
9ed7a776 2101
cdd6928c
JH		 2102 ret = gpmc_cs_request(cs, resource_size(&res), &base);
2103 if (ret < 0) {
2104 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
2105 return ret;
2106 }
c2ade654 2107 gpmc_cs_set_name(cs, child->full_name);
cdd6928c 2108
35ac051e
TL		 2109 gpmc_read_settings_dt(child, &gpmc_s);
2110 gpmc_read_timings_dt(child, &gpmc_t);
cdd6928c 2111
fd4446f2
TL		 2112 /*
2113 * For some GPMC devices we still need to rely on the bootloader
35ac051e
TL		 2114 * timings because the devices can be connected via FPGA.
2115 * REVISIT: Add timing support from slls644g.pdf.
fd4446f2 2116 */
35ac051e
TL		 2117 if (!gpmc_t.cs_rd_off) {
2118 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2119 cs);
2120 gpmc_cs_show_timings(cs,
2121 "please add GPMC bootloader timings to .dts");
fd4446f2
TL		 2122 goto no_timings;
2123 }
2124
4cf27d2e
RQ		 2125 /* CS must be disabled while making changes to gpmc configuration */
2126 gpmc_cs_disable_mem(cs);
2127
cdd6928c 2128 /*
858432c7 2129 * FIXME: gpmc_cs_request() will map the CS to an arbitrary
cdd6928c
JH		 2130 * location in the gpmc address space. When booting with
2131 * device-tree we want the NOR flash to be mapped to the
2132 * location specified in the device-tree blob. So remap the
2133 * CS to this location. Once DT migration is complete should
2134 * just make gpmc_cs_request() map a specific address.
2135 */
2136 ret = gpmc_cs_remap(cs, res.start);
2137 if (ret < 0) {
f70bf2a3
FE		 2138 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2139 cs, &res.start);
bdd7e033
RQ		 2140 if (res.start < GPMC_MEM_START) {
2141 dev_info(&pdev->dev,
2142 "GPMC CS %d start cannot be lesser than 0x%x\n",
2143 cs, GPMC_MEM_START);
2144 } else if (res.end > GPMC_MEM_END) {
2145 dev_info(&pdev->dev,
2146 "GPMC CS %d end cannot be greater than 0x%x\n",
2147 cs, GPMC_MEM_END);
2148 }
cdd6928c
JH		 2149 goto err;
2150 }
2151
c2ade654 2152 if (of_node_name_eq(child, "nand")) {
c9711ec5
RQ		 2153 /* Warn about older DT blobs with no compatible property */
2154 if (!of_property_read_bool(child, "compatible")) {
2155 dev_warn(&pdev->dev,
2156 "Incompatible NAND node: missing compatible");
2157 ret = -EINVAL;
2158 goto err;
2159 }
2160 }
2161
c2ade654 2162 if (of_node_name_eq(child, "onenand")) {
a758f50f
LM		 2163 /* Warn about older DT blobs with no compatible property */
2164 if (!of_property_read_bool(child, "compatible")) {
2165 dev_warn(&pdev->dev,
2166 "Incompatible OneNAND node: missing compatible");
2167 ret = -EINVAL;
2168 goto err;
2169 }
2170 }
2171
c9711ec5
RQ		 2172 if (of_device_is_compatible(child, "ti,omap2-nand")) {
2173 /* NAND specific setup */
f679888f
BB		 2174 val = 8;
2175 of_property_read_u32(child, "nand-bus-width", &val);
c9711ec5
RQ		 2176 switch (val) {
2177 case 8:
2178 gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2179 break;
2180 case 16:
2181 gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2182 break;
2183 default:
c86f9854
RH		 2184 dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n",
2185 child);
c9711ec5
RQ		 2186 ret = -EINVAL;
2187 goto err;
2188 }
2189
2190 /* disable write protect */
2191 gpmc_configure(GPMC_CONFIG_WP, 0);
2192 gpmc_s.device_nand = true;
2193 } else {
2194 ret = of_property_read_u32(child, "bank-width",
2195 &gpmc_s.device_width);
c18a7ac3
LM		 2196 if (ret < 0 && !gpmc_s.device_width) {
2197 dev_err(&pdev->dev,
2198 "%pOF has no 'gpmc,device-width' property\n",
db749d17 2199 child);
c9711ec5 2200 goto err;
c9eabf40 2201 }
c9711ec5 2202 }
cdd6928c 2203
210325f0
RQ		 2204 /* Reserve wait pin if it is required and valid */
2205 if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
2206 unsigned int wait_pin = gpmc_s.wait_pin;
2207
2208 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
21abf103 2209 wait_pin, "WAITPIN",
5923ea6c
LW		 2210 GPIO_ACTIVE_HIGH,
2211 GPIOD_IN);
210325f0
RQ		 2212 if (IS_ERR(waitpin_desc)) {
2213 dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
2214 ret = PTR_ERR(waitpin_desc);
2215 goto err;
2216 }
2217 }
2218
fd820a1e 2219 gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
210325f0 2220
cdd6928c
JH		 2221 ret = gpmc_cs_program_settings(cs, &gpmc_s);
2222 if (ret < 0)
210325f0 2223 goto err_cs;
cdd6928c 2224
2e676901 2225 ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
7604baf3 2226 if (ret) {
c86f9854
RH		 2227 dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n",
2228 child);
210325f0 2229 goto err_cs;
7604baf3 2230 }
cdd6928c 2231
e378d22b
RQ		 2232 /* Clear limited address i.e. enable A26-A11 */
2233 val = gpmc_read_reg(GPMC_CONFIG);
2234 val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2235 gpmc_write_reg(GPMC_CONFIG, val);
2236
4cf27d2e
RQ		 2237 /* Enable CS region */
2238 gpmc_cs_enable_mem(cs);
cdd6928c 2239
fd4446f2 2240no_timings:
b1dc1ca9
RA		 2241
2242 /* create platform device, NULL on error or when disabled */
2243 if (!of_platform_device_create(child, NULL, &pdev->dev))
2244 goto err_child_fail;
2245
2246 /* is child a common bus? */
2247 if (of_match_node(of_default_bus_match_table, child))
2248 /* create children and other common bus children */
9f2c519c 2249 if (of_platform_default_populate(child, NULL, &pdev->dev))
b1dc1ca9
RA		 2250 goto err_child_fail;
2251
2252 return 0;
2253
2254err_child_fail:
cdd6928c 2255
c86f9854 2256 dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child);
e8ffd6fd 2257 ret = -ENODEV;
cdd6928c 2258
210325f0 2259err_cs:
3f41a3c4 2260 gpiochip_free_own_desc(waitpin_desc);
cdd6928c
JH		 2261err:
2262 gpmc_cs_free(cs);
2263
2264 return ret;
2265}
2266
bc6b1e7b
DM		 2267static int gpmc_probe_dt(struct platform_device *pdev)
2268{
2269 int ret;
bc6b1e7b
DM		 2270 const struct of_device_id *of_id =
2271 of_match_device(gpmc_dt_ids, &pdev->dev);
2272
2273 if (!of_id)
2274 return 0;
2275
f34f3716
GP		 2276 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2277 &gpmc_cs_num);
2278 if (ret < 0) {
2279 pr_err("%s: number of chip-selects not defined\n", __func__);
2280 return ret;
2281 } else if (gpmc_cs_num < 1) {
2282 pr_err("%s: all chip-selects are disabled\n", __func__);
2283 return -EINVAL;
2284 } else if (gpmc_cs_num > GPMC_CS_NUM) {
2285 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2286 __func__, GPMC_CS_NUM);
2287 return -EINVAL;
2288 }
2289
9f833156
JH		 2290 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2291 &gpmc_nr_waitpins);
2292 if (ret < 0) {
2293 pr_err("%s: number of wait pins not found!\n", __func__);
2294 return ret;
2295 }
2296
d2d00862
RQ		 2297 return 0;
2298}
2299
23540d6e 2300static void gpmc_probe_dt_children(struct platform_device *pdev)
d2d00862
RQ		 2301{
2302 int ret;
2303 struct device_node *child;
2304
68e2eb53 2305 for_each_available_child_of_node(pdev->dev.of_node, child) {
a758f50f 2306 ret = gpmc_probe_generic_child(pdev, child);
23540d6e 2307 if (ret) {
c86f9854
RH		 2308 dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n",
2309 child, ret);
23540d6e 2310 }
5330dc16 2311 }
bc6b1e7b
DM		 2312}
2313#else
2314static int gpmc_probe_dt(struct platform_device *pdev)
2315{
2316 return 0;
2317}
d2d00862 2318
23540d6e 2319static void gpmc_probe_dt_children(struct platform_device *pdev)
d2d00862 2320{
d2d00862 2321}
32dd625a
RQ		 2322#endif /* CONFIG_OF */
2323
2324static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
2325{
2326 return 1; /* we're input only */
2327}
2328
2329static int gpmc_gpio_direction_input(struct gpio_chip *chip,
2330 unsigned int offset)
2331{
2332 return 0; /* we're input only */
2333}
2334
2335static int gpmc_gpio_direction_output(struct gpio_chip *chip,
2336 unsigned int offset, int value)
2337{
2338 return -EINVAL; /* we're input only */
2339}
2340
2341static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
2342 int value)
2343{
2344}
2345
2346static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
2347{
2348 u32 reg;
2349
2350 offset += 8;
2351
2352 reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
2353
2354 return !!reg;
2355}
2356
2357static int gpmc_gpio_init(struct gpmc_device *gpmc)
2358{
2359 int ret;
2360
2361 gpmc->gpio_chip.parent = gpmc->dev;
2362 gpmc->gpio_chip.owner = THIS_MODULE;
2363 gpmc->gpio_chip.label = DEVICE_NAME;
2364 gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
2365 gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
2366 gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
2367 gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
2368 gpmc->gpio_chip.set = gpmc_gpio_set;
2369 gpmc->gpio_chip.get = gpmc_gpio_get;
2370 gpmc->gpio_chip.base = -1;
2371
525fe43f 2372 ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
32dd625a
RQ		 2373 if (ret < 0) {
2374 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
2375 return ret;
2376 }
2377
2378 return 0;
2379}
2380
351a102d 2381static int gpmc_probe(struct platform_device *pdev)
4bbbc1ad 2382{
8119024e 2383 int rc;
6b6c32fc 2384 u32 l;
da496873 2385 struct resource *res;
384258f2
RQ		 2386 struct gpmc_device *gpmc;
2387
2388 gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2389 if (!gpmc)
2390 return -ENOMEM;
2391
2392 gpmc->dev = &pdev->dev;
2393 platform_set_drvdata(pdev, gpmc);
4bbbc1ad 2394
da496873
AM		 2395 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2396 if (res == NULL)
2397 return -ENOENT;
8d08436d 2398
5857bd98
TR		 2399 gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2400 if (IS_ERR(gpmc_base))
2401 return PTR_ERR(gpmc_base);
da496873
AM		 2402
2403 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
384258f2
RQ		 2404 if (!res) {
2405 dev_err(&pdev->dev, "Failed to get resource: irq\n");
2406 return -ENOENT;
2407 }
2408
2409 gpmc->irq = res->start;
da496873 2410
8bf9be56 2411 gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
da496873 2412 if (IS_ERR(gpmc_l3_clk)) {
8bf9be56 2413 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
da496873 2414 return PTR_ERR(gpmc_l3_clk);
fd1dc87d
PW		 2415 }
2416
8bf9be56
RQ		 2417 if (!clk_get_rate(gpmc_l3_clk)) {
2418 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2419 return -EINVAL;
2420 }
2421
d2d00862
RQ		 2422 if (pdev->dev.of_node) {
2423 rc = gpmc_probe_dt(pdev);
2424 if (rc)
2425 return rc;
2426 } else {
2427 gpmc_cs_num = GPMC_CS_NUM;
2428 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2429 }
2430
b3f5525c 2431 pm_runtime_enable(&pdev->dev);
2432 pm_runtime_get_sync(&pdev->dev);
1daa8c1d 2433
4bbbc1ad 2434 l = gpmc_read_reg(GPMC_REVISION);
aa8d4767
JH		 2435
2436 /*
2437 * FIXME: Once device-tree migration is complete the below flags
2438 * should be populated based upon the device-tree compatible
2439 * string. For now just use the IP revision. OMAP3+ devices have
2440 * the wr_access and wr_data_mux_bus register fields. OMAP4+
2441 * devices support the addr-addr-data multiplex protocol.
2442 *
2443 * GPMC IP revisions:
2444 * - OMAP24xx = 2.0
2445 * - OMAP3xxx = 5.0
2446 * - OMAP44xx/54xx/AM335x = 6.0
2447 */
da496873
AM		 2448 if (GPMC_REVISION_MAJOR(l) > 0x4)
2449 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
aa8d4767
JH		 2450 if (GPMC_REVISION_MAJOR(l) > 0x5)
2451 gpmc_capability |= GPMC_HAS_MUX_AAD;
384258f2 2452 dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
da496873
AM		 2453 GPMC_REVISION_MINOR(l));
2454
84b00f0e 2455 gpmc_mem_init();
d2d00862
RQ		 2456 rc = gpmc_gpio_init(gpmc);
2457 if (rc)
2458 goto gpio_init_failed;
db97eb7d 2459
b2bac25a 2460 gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
384258f2
RQ		 2461 rc = gpmc_setup_irq(gpmc);
2462 if (rc) {
2463 dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
525fe43f 2464 goto gpio_init_failed;
384258f2 2465 }
da496873 2466
23540d6e 2467 gpmc_probe_dt_children(pdev);
bc6b1e7b 2468
da496873 2469 return 0;
384258f2 2470
d2d00862
RQ		 2471gpio_init_failed:
2472 gpmc_mem_exit();
384258f2 2473 pm_runtime_put_sync(&pdev->dev);
d2d00862
RQ		 2474 pm_runtime_disable(&pdev->dev);
2475
384258f2 2476 return rc;
da496873
AM		 2477}
2478
351a102d 2479static int gpmc_remove(struct platform_device *pdev)
da496873 2480{
384258f2
RQ		 2481 struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2482
2483 gpmc_free_irq(gpmc);
da496873 2484 gpmc_mem_exit();
b3f5525c 2485 pm_runtime_put_sync(&pdev->dev);
2486 pm_runtime_disable(&pdev->dev);
384258f2 2487
da496873
AM		 2488 return 0;
2489}
2490
b536dd41 2491#ifdef CONFIG_PM_SLEEP
2492static int gpmc_suspend(struct device *dev)
2493{
2494 omap3_gpmc_save_context();
2495 pm_runtime_put_sync(dev);
2496 return 0;
2497}
2498
2499static int gpmc_resume(struct device *dev)
2500{
2501 pm_runtime_get_sync(dev);
2502 omap3_gpmc_restore_context();
2503 return 0;
2504}
2505#endif
2506
2507static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2508
da496873
AM		 2509static struct platform_driver gpmc_driver = {
2510 .probe = gpmc_probe,
351a102d 2511 .remove = gpmc_remove,
da496873
AM		 2512 .driver = {
2513 .name = DEVICE_NAME,
bc6b1e7b 2514 .of_match_table = of_match_ptr(gpmc_dt_ids),
b536dd41 2515 .pm = &gpmc_pm_ops,
da496873
AM		 2516 },
2517};
2518
2519static __init int gpmc_init(void)
2520{
2521 return platform_driver_register(&gpmc_driver);
2522}
a8612809 2523postcore_initcall(gpmc_init);
db97eb7d 2524
a2d3e7ba
RN		 2525static struct omap3_gpmc_regs gpmc_context;
2526
b2fa3b7c 2527void omap3_gpmc_save_context(void)
a2d3e7ba
RN		 2528{
2529 int i;
b2fa3b7c 2530
e984a179
TV		 2531 if (!gpmc_base)
2532 return;
2533
a2d3e7ba
RN		 2534 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2535 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2536 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2537 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2538 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2539 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2540 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
f34f3716 2541 for (i = 0; i < gpmc_cs_num; i++) {
a2d3e7ba
RN		 2542 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2543 if (gpmc_context.cs_context[i].is_valid) {
2544 gpmc_context.cs_context[i].config1 =
2545 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2546 gpmc_context.cs_context[i].config2 =
2547 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2548 gpmc_context.cs_context[i].config3 =
2549 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2550 gpmc_context.cs_context[i].config4 =
2551 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2552 gpmc_context.cs_context[i].config5 =
2553 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2554 gpmc_context.cs_context[i].config6 =
2555 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2556 gpmc_context.cs_context[i].config7 =
2557 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2558 }
2559 }
2560}
2561
b2fa3b7c 2562void omap3_gpmc_restore_context(void)
a2d3e7ba
RN		 2563{
2564 int i;
b2fa3b7c 2565
e984a179
TV		 2566 if (!gpmc_base)
2567 return;
2568
a2d3e7ba
RN		 2569 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2570 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2571 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2572 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2573 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2574 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2575 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
f34f3716 2576 for (i = 0; i < gpmc_cs_num; i++) {
a2d3e7ba
RN		 2577 if (gpmc_context.cs_context[i].is_valid) {
2578 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2579 gpmc_context.cs_context[i].config1);
2580 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2581 gpmc_context.cs_context[i].config2);
2582 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2583 gpmc_context.cs_context[i].config3);
2584 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2585 gpmc_context.cs_context[i].config4);
2586 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2587 gpmc_context.cs_context[i].config5);
2588 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2589 gpmc_context.cs_context[i].config6);
2590 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2591 gpmc_context.cs_context[i].config7);
2592 }
2593 }
2594}
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