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Commit | Line | Data |
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4bbbc1ad JY |
1 | /* |
2 | * GPMC support functions | |
3 | * | |
4 | * Copyright (C) 2005-2006 Nokia Corporation | |
5 | * | |
6 | * Author: Juha Yrjola | |
7 | * | |
44169075 SS |
8 | * Copyright (C) 2009 Texas Instruments |
9 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
10 | * | |
4bbbc1ad JY |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
fd1dc87d PW |
15 | #undef DEBUG |
16 | ||
db97eb7d | 17 | #include <linux/irq.h> |
4bbbc1ad JY |
18 | #include <linux/kernel.h> |
19 | #include <linux/init.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/clk.h> | |
f37e4580 ID |
22 | #include <linux/ioport.h> |
23 | #include <linux/spinlock.h> | |
fced80c7 | 24 | #include <linux/io.h> |
fd1dc87d | 25 | #include <linux/module.h> |
db97eb7d | 26 | #include <linux/interrupt.h> |
da496873 | 27 | #include <linux/platform_device.h> |
bc6b1e7b | 28 | #include <linux/of.h> |
cdd6928c | 29 | #include <linux/of_address.h> |
bc6b1e7b DM |
30 | #include <linux/of_mtd.h> |
31 | #include <linux/of_device.h> | |
e639cd5b | 32 | #include <linux/omap-gpmc.h> |
bc6b1e7b | 33 | #include <linux/mtd/nand.h> |
b3f5525c | 34 | #include <linux/pm_runtime.h> |
4bbbc1ad | 35 | |
bc3668ea | 36 | #include <linux/platform_data/mtd-nand-omap2.h> |
e639cd5b | 37 | #include <linux/platform_data/mtd-onenand-omap2.h> |
4bbbc1ad | 38 | |
7f245162 | 39 | #include <asm/mach-types.h> |
72d0f1c3 | 40 | |
4be48fd5 AM |
41 | #define DEVICE_NAME "omap-gpmc" |
42 | ||
fd1dc87d | 43 | /* GPMC register offsets */ |
4bbbc1ad JY |
44 | #define GPMC_REVISION 0x00 |
45 | #define GPMC_SYSCONFIG 0x10 | |
46 | #define GPMC_SYSSTATUS 0x14 | |
47 | #define GPMC_IRQSTATUS 0x18 | |
48 | #define GPMC_IRQENABLE 0x1c | |
49 | #define GPMC_TIMEOUT_CONTROL 0x40 | |
50 | #define GPMC_ERR_ADDRESS 0x44 | |
51 | #define GPMC_ERR_TYPE 0x48 | |
52 | #define GPMC_CONFIG 0x50 | |
53 | #define GPMC_STATUS 0x54 | |
54 | #define GPMC_PREFETCH_CONFIG1 0x1e0 | |
55 | #define GPMC_PREFETCH_CONFIG2 0x1e4 | |
15e02a3b | 56 | #define GPMC_PREFETCH_CONTROL 0x1ec |
4bbbc1ad JY |
57 | #define GPMC_PREFETCH_STATUS 0x1f0 |
58 | #define GPMC_ECC_CONFIG 0x1f4 | |
59 | #define GPMC_ECC_CONTROL 0x1f8 | |
60 | #define GPMC_ECC_SIZE_CONFIG 0x1fc | |
948d38e7 | 61 | #define GPMC_ECC1_RESULT 0x200 |
8d602cf5 | 62 | #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */ |
2fdf0c98 AM |
63 | #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */ |
64 | #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */ | |
65 | #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */ | |
27c9fd60 | 66 | #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */ |
67 | #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */ | |
68 | #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */ | |
4bbbc1ad | 69 | |
2c65e744 YY |
70 | /* GPMC ECC control settings */ |
71 | #define GPMC_ECC_CTRL_ECCCLEAR 0x100 | |
72 | #define GPMC_ECC_CTRL_ECCDISABLE 0x000 | |
73 | #define GPMC_ECC_CTRL_ECCREG1 0x001 | |
74 | #define GPMC_ECC_CTRL_ECCREG2 0x002 | |
75 | #define GPMC_ECC_CTRL_ECCREG3 0x003 | |
76 | #define GPMC_ECC_CTRL_ECCREG4 0x004 | |
77 | #define GPMC_ECC_CTRL_ECCREG5 0x005 | |
78 | #define GPMC_ECC_CTRL_ECCREG6 0x006 | |
79 | #define GPMC_ECC_CTRL_ECCREG7 0x007 | |
80 | #define GPMC_ECC_CTRL_ECCREG8 0x008 | |
81 | #define GPMC_ECC_CTRL_ECCREG9 0x009 | |
82 | ||
e378d22b RQ |
83 | #define GPMC_CONFIG_LIMITEDADDRESS BIT(1) |
84 | ||
559d94b0 AM |
85 | #define GPMC_CONFIG2_CSEXTRADELAY BIT(7) |
86 | #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7) | |
87 | #define GPMC_CONFIG4_OEEXTRADELAY BIT(7) | |
88 | #define GPMC_CONFIG4_WEEXTRADELAY BIT(23) | |
89 | #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6) | |
90 | #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7) | |
91 | ||
948d38e7 | 92 | #define GPMC_CS0_OFFSET 0x60 |
4bbbc1ad | 93 | #define GPMC_CS_SIZE 0x30 |
2fdf0c98 | 94 | #define GPMC_BCH_SIZE 0x10 |
4bbbc1ad | 95 | |
f37e4580 | 96 | #define GPMC_MEM_END 0x3FFFFFFF |
f37e4580 ID |
97 | |
98 | #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ | |
99 | #define GPMC_SECTION_SHIFT 28 /* 128 MB */ | |
100 | ||
59e9c5ae | 101 | #define CS_NUM_SHIFT 24 |
102 | #define ENABLE_PREFETCH (0x1 << 7) | |
103 | #define DMA_MPU_MODE 2 | |
104 | ||
da496873 AM |
105 | #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf) |
106 | #define GPMC_REVISION_MINOR(l) (l & 0xf) | |
107 | ||
108 | #define GPMC_HAS_WR_ACCESS 0x1 | |
109 | #define GPMC_HAS_WR_DATA_MUX_BUS 0x2 | |
aa8d4767 | 110 | #define GPMC_HAS_MUX_AAD 0x4 |
da496873 | 111 | |
9f833156 JH |
112 | #define GPMC_NR_WAITPINS 4 |
113 | ||
e639cd5b TL |
114 | #define GPMC_CS_CONFIG1 0x00 |
115 | #define GPMC_CS_CONFIG2 0x04 | |
116 | #define GPMC_CS_CONFIG3 0x08 | |
117 | #define GPMC_CS_CONFIG4 0x0c | |
118 | #define GPMC_CS_CONFIG5 0x10 | |
119 | #define GPMC_CS_CONFIG6 0x14 | |
120 | #define GPMC_CS_CONFIG7 0x18 | |
121 | #define GPMC_CS_NAND_COMMAND 0x1c | |
122 | #define GPMC_CS_NAND_ADDRESS 0x20 | |
123 | #define GPMC_CS_NAND_DATA 0x24 | |
124 | ||
125 | /* Control Commands */ | |
126 | #define GPMC_CONFIG_RDY_BSY 0x00000001 | |
127 | #define GPMC_CONFIG_DEV_SIZE 0x00000002 | |
128 | #define GPMC_CONFIG_DEV_TYPE 0x00000003 | |
129 | #define GPMC_SET_IRQ_STATUS 0x00000004 | |
130 | ||
131 | #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) | |
132 | #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) | |
133 | #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) | |
134 | #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29) | |
135 | #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28) | |
136 | #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) | |
137 | #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) | |
138 | #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25) | |
139 | #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23) | |
140 | #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22) | |
141 | #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21) | |
142 | #define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18) | |
143 | #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16) | |
144 | #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12) | |
145 | #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) | |
146 | #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) | |
147 | #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) | |
148 | #define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8) | |
149 | #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) | |
150 | #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) | |
151 | #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) | |
152 | #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) | |
153 | #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) | |
154 | #define GPMC_CONFIG7_CSVALID (1 << 6) | |
155 | ||
9c4f757e SP |
156 | #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f |
157 | #define GPMC_CONFIG7_CSVALID_MASK BIT(6) | |
158 | #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8 | |
159 | #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET) | |
160 | /* All CONFIG7 bits except reserved bits */ | |
161 | #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \ | |
162 | GPMC_CONFIG7_CSVALID_MASK | \ | |
163 | GPMC_CONFIG7_MASKADDRESS_MASK) | |
164 | ||
e639cd5b TL |
165 | #define GPMC_DEVICETYPE_NOR 0 |
166 | #define GPMC_DEVICETYPE_NAND 2 | |
167 | #define GPMC_CONFIG_WRITEPROTECT 0x00000010 | |
168 | #define WR_RD_PIN_MONITORING 0x00600000 | |
169 | ||
170 | #define GPMC_ENABLE_IRQ 0x0000000d | |
171 | ||
172 | /* ECC commands */ | |
173 | #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ | |
174 | #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ | |
175 | #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */ | |
176 | ||
6b6c32fc AM |
177 | /* XXX: Only NAND irq has been considered,currently these are the only ones used |
178 | */ | |
179 | #define GPMC_NR_IRQ 2 | |
180 | ||
9ed7a776 TL |
181 | struct gpmc_cs_data { |
182 | const char *name; | |
183 | ||
184 | #define GPMC_CS_RESERVED (1 << 0) | |
185 | u32 flags; | |
186 | ||
187 | struct resource mem; | |
188 | }; | |
189 | ||
6b6c32fc AM |
190 | struct gpmc_client_irq { |
191 | unsigned irq; | |
192 | u32 bitmask; | |
193 | }; | |
194 | ||
a2d3e7ba RN |
195 | /* Structure to save gpmc cs context */ |
196 | struct gpmc_cs_config { | |
197 | u32 config1; | |
198 | u32 config2; | |
199 | u32 config3; | |
200 | u32 config4; | |
201 | u32 config5; | |
202 | u32 config6; | |
203 | u32 config7; | |
204 | int is_valid; | |
205 | }; | |
206 | ||
207 | /* | |
208 | * Structure to save/restore gpmc context | |
209 | * to support core off on OMAP3 | |
210 | */ | |
211 | struct omap3_gpmc_regs { | |
212 | u32 sysconfig; | |
213 | u32 irqenable; | |
214 | u32 timeout_ctrl; | |
215 | u32 config; | |
216 | u32 prefetch_config1; | |
217 | u32 prefetch_config2; | |
218 | u32 prefetch_control; | |
219 | struct gpmc_cs_config cs_context[GPMC_CS_NUM]; | |
220 | }; | |
221 | ||
6b6c32fc AM |
222 | static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ]; |
223 | static struct irq_chip gpmc_irq_chip; | |
af072196 | 224 | static int gpmc_irq_start; |
6b6c32fc | 225 | |
f37e4580 | 226 | static struct resource gpmc_mem_root; |
9ed7a776 | 227 | static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM]; |
87b247c4 | 228 | static DEFINE_SPINLOCK(gpmc_mem_lock); |
6797b4fe | 229 | /* Define chip-selects as reserved by default until probe completes */ |
f34f3716 | 230 | static unsigned int gpmc_cs_num = GPMC_CS_NUM; |
9f833156 | 231 | static unsigned int gpmc_nr_waitpins; |
da496873 AM |
232 | static struct device *gpmc_dev; |
233 | static int gpmc_irq; | |
234 | static resource_size_t phys_base, mem_size; | |
235 | static unsigned gpmc_capability; | |
fd1dc87d | 236 | static void __iomem *gpmc_base; |
4bbbc1ad | 237 | |
fd1dc87d | 238 | static struct clk *gpmc_l3_clk; |
4bbbc1ad | 239 | |
db97eb7d SG |
240 | static irqreturn_t gpmc_handle_irq(int irq, void *dev); |
241 | ||
4bbbc1ad JY |
242 | static void gpmc_write_reg(int idx, u32 val) |
243 | { | |
edfaf05c | 244 | writel_relaxed(val, gpmc_base + idx); |
4bbbc1ad JY |
245 | } |
246 | ||
247 | static u32 gpmc_read_reg(int idx) | |
248 | { | |
edfaf05c | 249 | return readl_relaxed(gpmc_base + idx); |
4bbbc1ad JY |
250 | } |
251 | ||
252 | void gpmc_cs_write_reg(int cs, int idx, u32 val) | |
253 | { | |
254 | void __iomem *reg_addr; | |
255 | ||
948d38e7 | 256 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
edfaf05c | 257 | writel_relaxed(val, reg_addr); |
4bbbc1ad JY |
258 | } |
259 | ||
3fc089e7 | 260 | static u32 gpmc_cs_read_reg(int cs, int idx) |
4bbbc1ad | 261 | { |
fd1dc87d PW |
262 | void __iomem *reg_addr; |
263 | ||
948d38e7 | 264 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
edfaf05c | 265 | return readl_relaxed(reg_addr); |
4bbbc1ad JY |
266 | } |
267 | ||
fd1dc87d | 268 | /* TODO: Add support for gpmc_fck to clock framework and use it */ |
3fc089e7 | 269 | static unsigned long gpmc_get_fclk_period(void) |
4bbbc1ad | 270 | { |
fd1dc87d PW |
271 | unsigned long rate = clk_get_rate(gpmc_l3_clk); |
272 | ||
fd1dc87d PW |
273 | rate /= 1000; |
274 | rate = 1000000000 / rate; /* In picoseconds */ | |
275 | ||
276 | return rate; | |
4bbbc1ad JY |
277 | } |
278 | ||
3fc089e7 | 279 | static unsigned int gpmc_ns_to_ticks(unsigned int time_ns) |
4bbbc1ad JY |
280 | { |
281 | unsigned long tick_ps; | |
282 | ||
283 | /* Calculate in picosecs to yield more exact results */ | |
284 | tick_ps = gpmc_get_fclk_period(); | |
285 | ||
286 | return (time_ns * 1000 + tick_ps - 1) / tick_ps; | |
287 | } | |
288 | ||
3fc089e7 | 289 | static unsigned int gpmc_ps_to_ticks(unsigned int time_ps) |
a3551f5b AH |
290 | { |
291 | unsigned long tick_ps; | |
292 | ||
293 | /* Calculate in picosecs to yield more exact results */ | |
294 | tick_ps = gpmc_get_fclk_period(); | |
295 | ||
296 | return (time_ps + tick_ps - 1) / tick_ps; | |
297 | } | |
298 | ||
fd1dc87d PW |
299 | unsigned int gpmc_ticks_to_ns(unsigned int ticks) |
300 | { | |
301 | return ticks * gpmc_get_fclk_period() / 1000; | |
302 | } | |
303 | ||
246da26d AM |
304 | static unsigned int gpmc_ticks_to_ps(unsigned int ticks) |
305 | { | |
306 | return ticks * gpmc_get_fclk_period(); | |
307 | } | |
308 | ||
309 | static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps) | |
310 | { | |
311 | unsigned long ticks = gpmc_ps_to_ticks(time_ps); | |
312 | ||
313 | return ticks * gpmc_get_fclk_period(); | |
314 | } | |
315 | ||
559d94b0 AM |
316 | static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value) |
317 | { | |
318 | u32 l; | |
319 | ||
320 | l = gpmc_cs_read_reg(cs, reg); | |
321 | if (value) | |
322 | l |= mask; | |
323 | else | |
324 | l &= ~mask; | |
325 | gpmc_cs_write_reg(cs, reg, l); | |
326 | } | |
327 | ||
328 | static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) | |
329 | { | |
330 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1, | |
331 | GPMC_CONFIG1_TIME_PARA_GRAN, | |
332 | p->time_para_granularity); | |
333 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2, | |
334 | GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay); | |
335 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3, | |
336 | GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay); | |
337 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, | |
338 | GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay); | |
339 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, | |
340 | GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay); | |
341 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, | |
342 | GPMC_CONFIG6_CYCLE2CYCLESAMECSEN, | |
343 | p->cycle2cyclesamecsen); | |
344 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, | |
345 | GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN, | |
346 | p->cycle2cyclediffcsen); | |
347 | } | |
348 | ||
4bbbc1ad | 349 | #ifdef DEBUG |
35ac051e TL |
350 | static int get_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, |
351 | bool raw, bool noval, int shift, | |
352 | const char *name) | |
353 | { | |
354 | u32 l; | |
355 | int nr_bits, max_value, mask; | |
356 | ||
357 | l = gpmc_cs_read_reg(cs, reg); | |
358 | nr_bits = end_bit - st_bit + 1; | |
359 | max_value = (1 << nr_bits) - 1; | |
360 | mask = max_value << st_bit; | |
361 | l = (l & mask) >> st_bit; | |
362 | if (shift) | |
363 | l = (shift << l); | |
364 | if (noval && (l == 0)) | |
365 | return 0; | |
366 | if (!raw) { | |
367 | unsigned int time_ns_min, time_ns, time_ns_max; | |
368 | ||
369 | time_ns_min = gpmc_ticks_to_ns(l ? l - 1 : 0); | |
370 | time_ns = gpmc_ticks_to_ns(l); | |
371 | time_ns_max = gpmc_ticks_to_ns(l + 1 > max_value ? | |
372 | max_value : l + 1); | |
373 | pr_info("gpmc,%s = <%u> (%u - %u ns, %i ticks)\n", | |
374 | name, time_ns, time_ns_min, time_ns_max, l); | |
375 | } else { | |
376 | pr_info("gpmc,%s = <%u>\n", name, l); | |
377 | } | |
378 | ||
379 | return l; | |
380 | } | |
381 | ||
382 | #define GPMC_PRINT_CONFIG(cs, config) \ | |
383 | pr_info("cs%i %s: 0x%08x\n", cs, #config, \ | |
384 | gpmc_cs_read_reg(cs, config)) | |
385 | #define GPMC_GET_RAW(reg, st, end, field) \ | |
386 | get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 0, 0, field) | |
387 | #define GPMC_GET_RAW_BOOL(reg, st, end, field) \ | |
388 | get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, 0, field) | |
389 | #define GPMC_GET_RAW_SHIFT(reg, st, end, shift, field) \ | |
390 | get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, (shift), field) | |
391 | #define GPMC_GET_TICKS(reg, st, end, field) \ | |
392 | get_gpmc_timing_reg(cs, (reg), (st), (end), 0, 0, 0, field) | |
393 | ||
394 | static void gpmc_show_regs(int cs, const char *desc) | |
395 | { | |
396 | pr_info("gpmc cs%i %s:\n", cs, desc); | |
397 | GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1); | |
398 | GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2); | |
399 | GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3); | |
400 | GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4); | |
401 | GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5); | |
402 | GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6); | |
403 | } | |
404 | ||
405 | /* | |
406 | * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available, | |
407 | * see commit c9fb809. | |
408 | */ | |
409 | static void gpmc_cs_show_timings(int cs, const char *desc) | |
410 | { | |
411 | gpmc_show_regs(cs, desc); | |
412 | ||
413 | pr_info("gpmc cs%i access configuration:\n", cs); | |
414 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity"); | |
415 | GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data"); | |
416 | GPMC_GET_RAW(GPMC_CS_CONFIG1, 12, 13, "device-width"); | |
417 | GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin"); | |
418 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write"); | |
419 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read"); | |
420 | GPMC_GET_RAW_SHIFT(GPMC_CS_CONFIG1, 23, 24, 4, "burst-length"); | |
421 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write"); | |
422 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write"); | |
423 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read"); | |
424 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read"); | |
425 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap"); | |
426 | ||
427 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay"); | |
428 | ||
429 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay"); | |
430 | ||
431 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay"); | |
432 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay"); | |
433 | ||
434 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen"); | |
435 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen"); | |
436 | ||
437 | pr_info("gpmc cs%i timings configuration:\n", cs); | |
438 | GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns"); | |
439 | GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns"); | |
440 | GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns"); | |
441 | ||
442 | GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns"); | |
443 | GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns"); | |
444 | GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns"); | |
445 | ||
446 | GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns"); | |
447 | GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns"); | |
448 | GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns"); | |
449 | GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns"); | |
450 | ||
451 | GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns"); | |
452 | GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns"); | |
453 | GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns"); | |
454 | ||
455 | GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns"); | |
456 | ||
457 | GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns"); | |
458 | GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns"); | |
459 | ||
460 | GPMC_GET_TICKS(GPMC_CS_CONFIG1, 18, 19, "wait-monitoring-ns"); | |
461 | GPMC_GET_TICKS(GPMC_CS_CONFIG1, 25, 26, "clk-activation-ns"); | |
462 | ||
463 | GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns"); | |
464 | GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns"); | |
465 | } | |
4bbbc1ad | 466 | #else |
35ac051e TL |
467 | static inline void gpmc_cs_show_timings(int cs, const char *desc) |
468 | { | |
469 | } | |
4bbbc1ad | 470 | #endif |
35ac051e | 471 | |
4bbbc1ad | 472 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, |
2aab6468 | 473 | int time, const char *name) |
4bbbc1ad JY |
474 | { |
475 | u32 l; | |
476 | int ticks, mask, nr_bits; | |
477 | ||
478 | if (time == 0) | |
479 | ticks = 0; | |
480 | else | |
481 | ticks = gpmc_ns_to_ticks(time); | |
482 | nr_bits = end_bit - st_bit + 1; | |
80323742 RQ |
483 | mask = (1 << nr_bits) - 1; |
484 | ||
485 | if (ticks > mask) { | |
486 | pr_err("%s: GPMC error! CS%d: %s: %d ns, %d ticks > %d\n", | |
487 | __func__, cs, name, time, ticks, mask); | |
488 | ||
4bbbc1ad | 489 | return -1; |
1c22cc13 | 490 | } |
4bbbc1ad | 491 | |
4bbbc1ad JY |
492 | l = gpmc_cs_read_reg(cs, reg); |
493 | #ifdef DEBUG | |
1c22cc13 DB |
494 | printk(KERN_INFO |
495 | "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", | |
2aab6468 | 496 | cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000, |
1c22cc13 | 497 | (l >> st_bit) & mask, time); |
4bbbc1ad JY |
498 | #endif |
499 | l &= ~(mask << st_bit); | |
500 | l |= ticks << st_bit; | |
501 | gpmc_cs_write_reg(cs, reg, l); | |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
4bbbc1ad JY |
506 | #define GPMC_SET_ONE(reg, st, end, field) \ |
507 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), \ | |
508 | t->field, #field) < 0) \ | |
509 | return -1 | |
4bbbc1ad | 510 | |
1b47ca1a | 511 | int gpmc_calc_divider(unsigned int sync_clk) |
4bbbc1ad JY |
512 | { |
513 | int div; | |
514 | u32 l; | |
515 | ||
a3551f5b | 516 | l = sync_clk + (gpmc_get_fclk_period() - 1); |
4bbbc1ad JY |
517 | div = l / gpmc_get_fclk_period(); |
518 | if (div > 4) | |
519 | return -1; | |
1c22cc13 | 520 | if (div <= 0) |
4bbbc1ad JY |
521 | div = 1; |
522 | ||
523 | return div; | |
524 | } | |
525 | ||
526 | int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) | |
527 | { | |
528 | int div; | |
529 | u32 l; | |
530 | ||
35ac051e | 531 | gpmc_cs_show_timings(cs, "before gpmc_cs_set_timings"); |
1b47ca1a | 532 | div = gpmc_calc_divider(t->sync_clk); |
4bbbc1ad | 533 | if (div < 0) |
a032d33b | 534 | return div; |
4bbbc1ad JY |
535 | |
536 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on); | |
537 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off); | |
538 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off); | |
539 | ||
540 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on); | |
541 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off); | |
542 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off); | |
543 | ||
544 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on); | |
545 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off); | |
546 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on); | |
547 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off); | |
548 | ||
549 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle); | |
550 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle); | |
551 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access); | |
552 | ||
553 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); | |
554 | ||
559d94b0 AM |
555 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround); |
556 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay); | |
557 | ||
558 | GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring); | |
559 | GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation); | |
560 | ||
da496873 | 561 | if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) |
cc26b3b0 | 562 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus); |
da496873 | 563 | if (gpmc_capability & GPMC_HAS_WR_ACCESS) |
cc26b3b0 | 564 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access); |
cc26b3b0 | 565 | |
1c22cc13 DB |
566 | /* caller is expected to have initialized CONFIG1 to cover |
567 | * at least sync vs async | |
568 | */ | |
569 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
570 | if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) { | |
4bbbc1ad | 571 | #ifdef DEBUG |
1c22cc13 DB |
572 | printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n", |
573 | cs, (div * gpmc_get_fclk_period()) / 1000, div); | |
4bbbc1ad | 574 | #endif |
1c22cc13 DB |
575 | l &= ~0x03; |
576 | l |= (div - 1); | |
577 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l); | |
578 | } | |
4bbbc1ad | 579 | |
559d94b0 | 580 | gpmc_cs_bool_timings(cs, &t->bool_timings); |
35ac051e | 581 | gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings"); |
559d94b0 | 582 | |
4bbbc1ad JY |
583 | return 0; |
584 | } | |
585 | ||
4cf27d2e | 586 | static int gpmc_cs_set_memconf(int cs, u32 base, u32 size) |
f37e4580 ID |
587 | { |
588 | u32 l; | |
589 | u32 mask; | |
590 | ||
c71f8e9b JH |
591 | /* |
592 | * Ensure that base address is aligned on a | |
593 | * boundary equal to or greater than size. | |
594 | */ | |
595 | if (base & (size - 1)) | |
596 | return -EINVAL; | |
597 | ||
9c4f757e | 598 | base >>= GPMC_CHUNK_SHIFT; |
f37e4580 | 599 | mask = (1 << GPMC_SECTION_SHIFT) - size; |
9c4f757e SP |
600 | mask >>= GPMC_CHUNK_SHIFT; |
601 | mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET; | |
602 | ||
f37e4580 | 603 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); |
9c4f757e SP |
604 | l &= ~GPMC_CONFIG7_MASK; |
605 | l |= base & GPMC_CONFIG7_BASEADDRESS_MASK; | |
606 | l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK; | |
a2d3e7ba | 607 | l |= GPMC_CONFIG7_CSVALID; |
f37e4580 | 608 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
c71f8e9b JH |
609 | |
610 | return 0; | |
f37e4580 ID |
611 | } |
612 | ||
4cf27d2e RQ |
613 | static void gpmc_cs_enable_mem(int cs) |
614 | { | |
615 | u32 l; | |
616 | ||
617 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
618 | l |= GPMC_CONFIG7_CSVALID; | |
619 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); | |
620 | } | |
621 | ||
f37e4580 ID |
622 | static void gpmc_cs_disable_mem(int cs) |
623 | { | |
624 | u32 l; | |
625 | ||
626 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 627 | l &= ~GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
628 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
629 | } | |
630 | ||
631 | static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) | |
632 | { | |
633 | u32 l; | |
634 | u32 mask; | |
635 | ||
636 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
637 | *base = (l & 0x3f) << GPMC_CHUNK_SHIFT; | |
638 | mask = (l >> 8) & 0x0f; | |
639 | *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT); | |
640 | } | |
641 | ||
642 | static int gpmc_cs_mem_enabled(int cs) | |
643 | { | |
644 | u32 l; | |
645 | ||
646 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 647 | return l & GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
648 | } |
649 | ||
f5d8edaf | 650 | static void gpmc_cs_set_reserved(int cs, int reserved) |
4bbbc1ad | 651 | { |
9ed7a776 TL |
652 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; |
653 | ||
654 | gpmc->flags |= GPMC_CS_RESERVED; | |
f37e4580 ID |
655 | } |
656 | ||
ae9d908a | 657 | static bool gpmc_cs_reserved(int cs) |
f37e4580 | 658 | { |
9ed7a776 TL |
659 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; |
660 | ||
661 | return gpmc->flags & GPMC_CS_RESERVED; | |
662 | } | |
663 | ||
664 | static void gpmc_cs_set_name(int cs, const char *name) | |
665 | { | |
666 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; | |
667 | ||
668 | gpmc->name = name; | |
669 | } | |
670 | ||
671 | const char *gpmc_cs_get_name(int cs) | |
672 | { | |
673 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; | |
674 | ||
675 | return gpmc->name; | |
f37e4580 ID |
676 | } |
677 | ||
678 | static unsigned long gpmc_mem_align(unsigned long size) | |
679 | { | |
680 | int order; | |
681 | ||
682 | size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1); | |
683 | order = GPMC_CHUNK_SHIFT - 1; | |
684 | do { | |
685 | size >>= 1; | |
686 | order++; | |
687 | } while (size); | |
688 | size = 1 << order; | |
689 | return size; | |
690 | } | |
691 | ||
692 | static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) | |
693 | { | |
9ed7a776 TL |
694 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; |
695 | struct resource *res = &gpmc->mem; | |
f37e4580 ID |
696 | int r; |
697 | ||
698 | size = gpmc_mem_align(size); | |
699 | spin_lock(&gpmc_mem_lock); | |
700 | res->start = base; | |
701 | res->end = base + size - 1; | |
702 | r = request_resource(&gpmc_mem_root, res); | |
703 | spin_unlock(&gpmc_mem_lock); | |
704 | ||
705 | return r; | |
706 | } | |
707 | ||
da496873 AM |
708 | static int gpmc_cs_delete_mem(int cs) |
709 | { | |
9ed7a776 TL |
710 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; |
711 | struct resource *res = &gpmc->mem; | |
da496873 AM |
712 | int r; |
713 | ||
714 | spin_lock(&gpmc_mem_lock); | |
efe80723 | 715 | r = release_resource(res); |
da496873 AM |
716 | res->start = 0; |
717 | res->end = 0; | |
718 | spin_unlock(&gpmc_mem_lock); | |
719 | ||
720 | return r; | |
721 | } | |
722 | ||
cdd6928c JH |
723 | /** |
724 | * gpmc_cs_remap - remaps a chip-select physical base address | |
725 | * @cs: chip-select to remap | |
726 | * @base: physical base address to re-map chip-select to | |
727 | * | |
728 | * Re-maps a chip-select to a new physical base address specified by | |
729 | * "base". Returns 0 on success and appropriate negative error code | |
730 | * on failure. | |
731 | */ | |
732 | static int gpmc_cs_remap(int cs, u32 base) | |
733 | { | |
734 | int ret; | |
735 | u32 old_base, size; | |
736 | ||
f34f3716 GP |
737 | if (cs > gpmc_cs_num) { |
738 | pr_err("%s: requested chip-select is disabled\n", __func__); | |
cdd6928c | 739 | return -ENODEV; |
f34f3716 | 740 | } |
fb677ef7 TL |
741 | |
742 | /* | |
743 | * Make sure we ignore any device offsets from the GPMC partition | |
744 | * allocated for the chip select and that the new base confirms | |
745 | * to the GPMC 16MB minimum granularity. | |
746 | */ | |
747 | base &= ~(SZ_16M - 1); | |
748 | ||
cdd6928c JH |
749 | gpmc_cs_get_memconf(cs, &old_base, &size); |
750 | if (base == old_base) | |
751 | return 0; | |
4cf27d2e | 752 | |
cdd6928c JH |
753 | ret = gpmc_cs_delete_mem(cs); |
754 | if (ret < 0) | |
755 | return ret; | |
4cf27d2e | 756 | |
cdd6928c | 757 | ret = gpmc_cs_insert_mem(cs, base, size); |
c71f8e9b JH |
758 | if (ret < 0) |
759 | return ret; | |
cdd6928c | 760 | |
4cf27d2e RQ |
761 | ret = gpmc_cs_set_memconf(cs, base, size); |
762 | ||
763 | return ret; | |
cdd6928c JH |
764 | } |
765 | ||
f37e4580 ID |
766 | int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) |
767 | { | |
9ed7a776 TL |
768 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; |
769 | struct resource *res = &gpmc->mem; | |
f37e4580 ID |
770 | int r = -1; |
771 | ||
f34f3716 GP |
772 | if (cs > gpmc_cs_num) { |
773 | pr_err("%s: requested chip-select is disabled\n", __func__); | |
f37e4580 | 774 | return -ENODEV; |
f34f3716 | 775 | } |
f37e4580 ID |
776 | size = gpmc_mem_align(size); |
777 | if (size > (1 << GPMC_SECTION_SHIFT)) | |
778 | return -ENOMEM; | |
779 | ||
780 | spin_lock(&gpmc_mem_lock); | |
781 | if (gpmc_cs_reserved(cs)) { | |
782 | r = -EBUSY; | |
783 | goto out; | |
784 | } | |
785 | if (gpmc_cs_mem_enabled(cs)) | |
786 | r = adjust_resource(res, res->start & ~(size - 1), size); | |
787 | if (r < 0) | |
788 | r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0, | |
789 | size, NULL, NULL); | |
790 | if (r < 0) | |
791 | goto out; | |
792 | ||
4cf27d2e RQ |
793 | /* Disable CS while changing base address and size mask */ |
794 | gpmc_cs_disable_mem(cs); | |
795 | ||
796 | r = gpmc_cs_set_memconf(cs, res->start, resource_size(res)); | |
c71f8e9b JH |
797 | if (r < 0) { |
798 | release_resource(res); | |
799 | goto out; | |
800 | } | |
801 | ||
4cf27d2e RQ |
802 | /* Enable CS */ |
803 | gpmc_cs_enable_mem(cs); | |
f37e4580 ID |
804 | *base = res->start; |
805 | gpmc_cs_set_reserved(cs, 1); | |
806 | out: | |
807 | spin_unlock(&gpmc_mem_lock); | |
808 | return r; | |
809 | } | |
fd1dc87d | 810 | EXPORT_SYMBOL(gpmc_cs_request); |
f37e4580 ID |
811 | |
812 | void gpmc_cs_free(int cs) | |
813 | { | |
9ed7a776 TL |
814 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; |
815 | struct resource *res = &gpmc->mem; | |
efe80723 | 816 | |
f37e4580 | 817 | spin_lock(&gpmc_mem_lock); |
f34f3716 | 818 | if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) { |
f37e4580 ID |
819 | printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); |
820 | BUG(); | |
821 | spin_unlock(&gpmc_mem_lock); | |
822 | return; | |
823 | } | |
824 | gpmc_cs_disable_mem(cs); | |
efe80723 TL |
825 | if (res->flags) |
826 | release_resource(res); | |
f37e4580 ID |
827 | gpmc_cs_set_reserved(cs, 0); |
828 | spin_unlock(&gpmc_mem_lock); | |
829 | } | |
fd1dc87d | 830 | EXPORT_SYMBOL(gpmc_cs_free); |
f37e4580 | 831 | |
948d38e7 | 832 | /** |
3a544354 | 833 | * gpmc_configure - write request to configure gpmc |
948d38e7 SG |
834 | * @cmd: command type |
835 | * @wval: value to write | |
836 | * @return status of the operation | |
837 | */ | |
3a544354 | 838 | int gpmc_configure(int cmd, int wval) |
948d38e7 | 839 | { |
3a544354 | 840 | u32 regval; |
948d38e7 SG |
841 | |
842 | switch (cmd) { | |
db97eb7d SG |
843 | case GPMC_ENABLE_IRQ: |
844 | gpmc_write_reg(GPMC_IRQENABLE, wval); | |
845 | break; | |
846 | ||
948d38e7 SG |
847 | case GPMC_SET_IRQ_STATUS: |
848 | gpmc_write_reg(GPMC_IRQSTATUS, wval); | |
849 | break; | |
850 | ||
851 | case GPMC_CONFIG_WP: | |
852 | regval = gpmc_read_reg(GPMC_CONFIG); | |
853 | if (wval) | |
854 | regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ | |
855 | else | |
856 | regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ | |
857 | gpmc_write_reg(GPMC_CONFIG, regval); | |
858 | break; | |
859 | ||
948d38e7 | 860 | default: |
3a544354 JH |
861 | pr_err("%s: command not supported\n", __func__); |
862 | return -EINVAL; | |
948d38e7 SG |
863 | } |
864 | ||
3a544354 | 865 | return 0; |
948d38e7 | 866 | } |
3a544354 | 867 | EXPORT_SYMBOL(gpmc_configure); |
948d38e7 | 868 | |
52bd138d AM |
869 | void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) |
870 | { | |
2fdf0c98 AM |
871 | int i; |
872 | ||
52bd138d AM |
873 | reg->gpmc_status = gpmc_base + GPMC_STATUS; |
874 | reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + | |
875 | GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; | |
876 | reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET + | |
877 | GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs; | |
878 | reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET + | |
879 | GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs; | |
880 | reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1; | |
881 | reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2; | |
882 | reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL; | |
883 | reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS; | |
884 | reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG; | |
885 | reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; | |
886 | reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; | |
887 | reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; | |
2fdf0c98 AM |
888 | |
889 | for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) { | |
890 | reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 + | |
891 | GPMC_BCH_SIZE * i; | |
892 | reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 + | |
893 | GPMC_BCH_SIZE * i; | |
894 | reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 + | |
895 | GPMC_BCH_SIZE * i; | |
896 | reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 + | |
897 | GPMC_BCH_SIZE * i; | |
27c9fd60 | 898 | reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 + |
899 | i * GPMC_BCH_SIZE; | |
900 | reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 + | |
901 | i * GPMC_BCH_SIZE; | |
902 | reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 + | |
903 | i * GPMC_BCH_SIZE; | |
2fdf0c98 | 904 | } |
52bd138d AM |
905 | } |
906 | ||
6b6c32fc AM |
907 | int gpmc_get_client_irq(unsigned irq_config) |
908 | { | |
909 | int i; | |
910 | ||
911 | if (hweight32(irq_config) > 1) | |
912 | return 0; | |
913 | ||
914 | for (i = 0; i < GPMC_NR_IRQ; i++) | |
915 | if (gpmc_client_irq[i].bitmask & irq_config) | |
916 | return gpmc_client_irq[i].irq; | |
917 | ||
918 | return 0; | |
919 | } | |
920 | ||
921 | static int gpmc_irq_endis(unsigned irq, bool endis) | |
922 | { | |
923 | int i; | |
924 | u32 regval; | |
925 | ||
926 | for (i = 0; i < GPMC_NR_IRQ; i++) | |
927 | if (irq == gpmc_client_irq[i].irq) { | |
928 | regval = gpmc_read_reg(GPMC_IRQENABLE); | |
929 | if (endis) | |
930 | regval |= gpmc_client_irq[i].bitmask; | |
931 | else | |
932 | regval &= ~gpmc_client_irq[i].bitmask; | |
933 | gpmc_write_reg(GPMC_IRQENABLE, regval); | |
934 | break; | |
935 | } | |
936 | ||
937 | return 0; | |
938 | } | |
939 | ||
940 | static void gpmc_irq_disable(struct irq_data *p) | |
941 | { | |
942 | gpmc_irq_endis(p->irq, false); | |
943 | } | |
944 | ||
945 | static void gpmc_irq_enable(struct irq_data *p) | |
946 | { | |
947 | gpmc_irq_endis(p->irq, true); | |
948 | } | |
949 | ||
950 | static void gpmc_irq_noop(struct irq_data *data) { } | |
951 | ||
952 | static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; } | |
953 | ||
da496873 | 954 | static int gpmc_setup_irq(void) |
6b6c32fc AM |
955 | { |
956 | int i; | |
957 | u32 regval; | |
958 | ||
959 | if (!gpmc_irq) | |
960 | return -EINVAL; | |
961 | ||
962 | gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0); | |
71856843 | 963 | if (gpmc_irq_start < 0) { |
6b6c32fc AM |
964 | pr_err("irq_alloc_descs failed\n"); |
965 | return gpmc_irq_start; | |
966 | } | |
967 | ||
968 | gpmc_irq_chip.name = "gpmc"; | |
969 | gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret; | |
970 | gpmc_irq_chip.irq_enable = gpmc_irq_enable; | |
971 | gpmc_irq_chip.irq_disable = gpmc_irq_disable; | |
972 | gpmc_irq_chip.irq_shutdown = gpmc_irq_noop; | |
973 | gpmc_irq_chip.irq_ack = gpmc_irq_noop; | |
974 | gpmc_irq_chip.irq_mask = gpmc_irq_noop; | |
975 | gpmc_irq_chip.irq_unmask = gpmc_irq_noop; | |
976 | ||
977 | gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE; | |
978 | gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT; | |
979 | ||
980 | for (i = 0; i < GPMC_NR_IRQ; i++) { | |
981 | gpmc_client_irq[i].irq = gpmc_irq_start + i; | |
982 | irq_set_chip_and_handler(gpmc_client_irq[i].irq, | |
983 | &gpmc_irq_chip, handle_simple_irq); | |
984 | set_irq_flags(gpmc_client_irq[i].irq, | |
985 | IRQF_VALID | IRQF_NOAUTOEN); | |
986 | } | |
987 | ||
988 | /* Disable interrupts */ | |
989 | gpmc_write_reg(GPMC_IRQENABLE, 0); | |
990 | ||
991 | /* clear interrupts */ | |
992 | regval = gpmc_read_reg(GPMC_IRQSTATUS); | |
993 | gpmc_write_reg(GPMC_IRQSTATUS, regval); | |
994 | ||
995 | return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL); | |
996 | } | |
997 | ||
351a102d | 998 | static int gpmc_free_irq(void) |
da496873 AM |
999 | { |
1000 | int i; | |
1001 | ||
1002 | if (gpmc_irq) | |
1003 | free_irq(gpmc_irq, NULL); | |
1004 | ||
1005 | for (i = 0; i < GPMC_NR_IRQ; i++) { | |
1006 | irq_set_handler(gpmc_client_irq[i].irq, NULL); | |
1007 | irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip); | |
1008 | irq_modify_status(gpmc_client_irq[i].irq, 0, 0); | |
1009 | } | |
1010 | ||
1011 | irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ); | |
1012 | ||
1013 | return 0; | |
1014 | } | |
1015 | ||
351a102d | 1016 | static void gpmc_mem_exit(void) |
da496873 AM |
1017 | { |
1018 | int cs; | |
1019 | ||
f34f3716 | 1020 | for (cs = 0; cs < gpmc_cs_num; cs++) { |
da496873 AM |
1021 | if (!gpmc_cs_mem_enabled(cs)) |
1022 | continue; | |
1023 | gpmc_cs_delete_mem(cs); | |
1024 | } | |
1025 | ||
1026 | } | |
1027 | ||
84b00f0e | 1028 | static void gpmc_mem_init(void) |
f37e4580 | 1029 | { |
84b00f0e | 1030 | int cs; |
f37e4580 | 1031 | |
bf234397 JH |
1032 | /* |
1033 | * The first 1MB of GPMC address space is typically mapped to | |
1034 | * the internal ROM. Never allocate the first page, to | |
1035 | * facilitate bug detection; even if we didn't boot from ROM. | |
7f245162 | 1036 | */ |
bf234397 | 1037 | gpmc_mem_root.start = SZ_1M; |
f37e4580 ID |
1038 | gpmc_mem_root.end = GPMC_MEM_END; |
1039 | ||
1040 | /* Reserve all regions that has been set up by bootloader */ | |
f34f3716 | 1041 | for (cs = 0; cs < gpmc_cs_num; cs++) { |
f37e4580 ID |
1042 | u32 base, size; |
1043 | ||
1044 | if (!gpmc_cs_mem_enabled(cs)) | |
1045 | continue; | |
1046 | gpmc_cs_get_memconf(cs, &base, &size); | |
84b00f0e JH |
1047 | if (gpmc_cs_insert_mem(cs, base, size)) { |
1048 | pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n", | |
1049 | __func__, cs, base, base + size); | |
1050 | gpmc_cs_disable_mem(cs); | |
8119024e | 1051 | } |
f37e4580 | 1052 | } |
4bbbc1ad JY |
1053 | } |
1054 | ||
246da26d AM |
1055 | static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk) |
1056 | { | |
1057 | u32 temp; | |
1058 | int div; | |
1059 | ||
1060 | div = gpmc_calc_divider(sync_clk); | |
1061 | temp = gpmc_ps_to_ticks(time_ps); | |
1062 | temp = (temp + div - 1) / div; | |
1063 | return gpmc_ticks_to_ps(temp * div); | |
1064 | } | |
1065 | ||
1066 | /* XXX: can the cycles be avoided ? */ | |
1067 | static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1068 | struct gpmc_device_timings *dev_t, |
1069 | bool mux) | |
246da26d | 1070 | { |
246da26d AM |
1071 | u32 temp; |
1072 | ||
1073 | /* adv_rd_off */ | |
1074 | temp = dev_t->t_avdp_r; | |
1075 | /* XXX: mux check required ? */ | |
1076 | if (mux) { | |
1077 | /* XXX: t_avdp not to be required for sync, only added for tusb | |
1078 | * this indirectly necessitates requirement of t_avdp_r and | |
1079 | * t_avdp_w instead of having a single t_avdp | |
1080 | */ | |
1081 | temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh); | |
1082 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
1083 | } | |
1084 | gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); | |
1085 | ||
1086 | /* oe_on */ | |
1087 | temp = dev_t->t_oeasu; /* XXX: remove this ? */ | |
1088 | if (mux) { | |
1089 | temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach); | |
1090 | temp = max_t(u32, temp, gpmc_t->adv_rd_off + | |
1091 | gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe)); | |
1092 | } | |
1093 | gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); | |
1094 | ||
1095 | /* access */ | |
1096 | /* XXX: any scope for improvement ?, by combining oe_on | |
1097 | * and clk_activation, need to check whether | |
1098 | * access = clk_activation + round to sync clk ? | |
1099 | */ | |
1100 | temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk); | |
1101 | temp += gpmc_t->clk_activation; | |
1102 | if (dev_t->cyc_oe) | |
1103 | temp = max_t(u32, temp, gpmc_t->oe_on + | |
1104 | gpmc_ticks_to_ps(dev_t->cyc_oe)); | |
1105 | gpmc_t->access = gpmc_round_ps_to_ticks(temp); | |
1106 | ||
1107 | gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); | |
1108 | gpmc_t->cs_rd_off = gpmc_t->oe_off; | |
1109 | ||
1110 | /* rd_cycle */ | |
1111 | temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez); | |
1112 | temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) + | |
1113 | gpmc_t->access; | |
1114 | /* XXX: barter t_ce_rdyz with t_cez_r ? */ | |
1115 | if (dev_t->t_ce_rdyz) | |
1116 | temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz); | |
1117 | gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); | |
1118 | ||
1119 | return 0; | |
1120 | } | |
1121 | ||
1122 | static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1123 | struct gpmc_device_timings *dev_t, |
1124 | bool mux) | |
246da26d | 1125 | { |
246da26d AM |
1126 | u32 temp; |
1127 | ||
1128 | /* adv_wr_off */ | |
1129 | temp = dev_t->t_avdp_w; | |
1130 | if (mux) { | |
1131 | temp = max_t(u32, temp, | |
1132 | gpmc_t->clk_activation + dev_t->t_avdh); | |
1133 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
1134 | } | |
1135 | gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); | |
1136 | ||
1137 | /* wr_data_mux_bus */ | |
1138 | temp = max_t(u32, dev_t->t_weasu, | |
1139 | gpmc_t->clk_activation + dev_t->t_rdyo); | |
1140 | /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?, | |
1141 | * and in that case remember to handle we_on properly | |
1142 | */ | |
1143 | if (mux) { | |
1144 | temp = max_t(u32, temp, | |
1145 | gpmc_t->adv_wr_off + dev_t->t_aavdh); | |
1146 | temp = max_t(u32, temp, gpmc_t->adv_wr_off + | |
1147 | gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); | |
1148 | } | |
1149 | gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); | |
1150 | ||
1151 | /* we_on */ | |
1152 | if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) | |
1153 | gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); | |
1154 | else | |
1155 | gpmc_t->we_on = gpmc_t->wr_data_mux_bus; | |
1156 | ||
1157 | /* wr_access */ | |
1158 | /* XXX: gpmc_capability check reqd ? , even if not, will not harm */ | |
1159 | gpmc_t->wr_access = gpmc_t->access; | |
1160 | ||
1161 | /* we_off */ | |
1162 | temp = gpmc_t->we_on + dev_t->t_wpl; | |
1163 | temp = max_t(u32, temp, | |
1164 | gpmc_t->wr_access + gpmc_ticks_to_ps(1)); | |
1165 | temp = max_t(u32, temp, | |
1166 | gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl)); | |
1167 | gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); | |
1168 | ||
1169 | gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + | |
1170 | dev_t->t_wph); | |
1171 | ||
1172 | /* wr_cycle */ | |
1173 | temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk); | |
1174 | temp += gpmc_t->wr_access; | |
1175 | /* XXX: barter t_ce_rdyz with t_cez_w ? */ | |
1176 | if (dev_t->t_ce_rdyz) | |
1177 | temp = max_t(u32, temp, | |
1178 | gpmc_t->cs_wr_off + dev_t->t_ce_rdyz); | |
1179 | gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); | |
1180 | ||
1181 | return 0; | |
1182 | } | |
1183 | ||
1184 | static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1185 | struct gpmc_device_timings *dev_t, |
1186 | bool mux) | |
246da26d | 1187 | { |
246da26d AM |
1188 | u32 temp; |
1189 | ||
1190 | /* adv_rd_off */ | |
1191 | temp = dev_t->t_avdp_r; | |
1192 | if (mux) | |
1193 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
1194 | gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); | |
1195 | ||
1196 | /* oe_on */ | |
1197 | temp = dev_t->t_oeasu; | |
1198 | if (mux) | |
1199 | temp = max_t(u32, temp, | |
1200 | gpmc_t->adv_rd_off + dev_t->t_aavdh); | |
1201 | gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); | |
1202 | ||
1203 | /* access */ | |
1204 | temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */ | |
1205 | gpmc_t->oe_on + dev_t->t_oe); | |
1206 | temp = max_t(u32, temp, | |
1207 | gpmc_t->cs_on + dev_t->t_ce); | |
1208 | temp = max_t(u32, temp, | |
1209 | gpmc_t->adv_on + dev_t->t_aa); | |
1210 | gpmc_t->access = gpmc_round_ps_to_ticks(temp); | |
1211 | ||
1212 | gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); | |
1213 | gpmc_t->cs_rd_off = gpmc_t->oe_off; | |
1214 | ||
1215 | /* rd_cycle */ | |
1216 | temp = max_t(u32, dev_t->t_rd_cycle, | |
1217 | gpmc_t->cs_rd_off + dev_t->t_cez_r); | |
1218 | temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez); | |
1219 | gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); | |
1220 | ||
1221 | return 0; | |
1222 | } | |
1223 | ||
1224 | static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1225 | struct gpmc_device_timings *dev_t, |
1226 | bool mux) | |
246da26d | 1227 | { |
246da26d AM |
1228 | u32 temp; |
1229 | ||
1230 | /* adv_wr_off */ | |
1231 | temp = dev_t->t_avdp_w; | |
1232 | if (mux) | |
1233 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
1234 | gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); | |
1235 | ||
1236 | /* wr_data_mux_bus */ | |
1237 | temp = dev_t->t_weasu; | |
1238 | if (mux) { | |
1239 | temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh); | |
1240 | temp = max_t(u32, temp, gpmc_t->adv_wr_off + | |
1241 | gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); | |
1242 | } | |
1243 | gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); | |
1244 | ||
1245 | /* we_on */ | |
1246 | if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) | |
1247 | gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); | |
1248 | else | |
1249 | gpmc_t->we_on = gpmc_t->wr_data_mux_bus; | |
1250 | ||
1251 | /* we_off */ | |
1252 | temp = gpmc_t->we_on + dev_t->t_wpl; | |
1253 | gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); | |
1254 | ||
1255 | gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + | |
1256 | dev_t->t_wph); | |
1257 | ||
1258 | /* wr_cycle */ | |
1259 | temp = max_t(u32, dev_t->t_wr_cycle, | |
1260 | gpmc_t->cs_wr_off + dev_t->t_cez_w); | |
1261 | gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); | |
1262 | ||
1263 | return 0; | |
1264 | } | |
1265 | ||
1266 | static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t, | |
1267 | struct gpmc_device_timings *dev_t) | |
1268 | { | |
1269 | u32 temp; | |
1270 | ||
1271 | gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) * | |
1272 | gpmc_get_fclk_period(); | |
1273 | ||
1274 | gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk( | |
1275 | dev_t->t_bacc, | |
1276 | gpmc_t->sync_clk); | |
1277 | ||
1278 | temp = max_t(u32, dev_t->t_ces, dev_t->t_avds); | |
1279 | gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp); | |
1280 | ||
1281 | if (gpmc_calc_divider(gpmc_t->sync_clk) != 1) | |
1282 | return 0; | |
1283 | ||
1284 | if (dev_t->ce_xdelay) | |
1285 | gpmc_t->bool_timings.cs_extra_delay = true; | |
1286 | if (dev_t->avd_xdelay) | |
1287 | gpmc_t->bool_timings.adv_extra_delay = true; | |
1288 | if (dev_t->oe_xdelay) | |
1289 | gpmc_t->bool_timings.oe_extra_delay = true; | |
1290 | if (dev_t->we_xdelay) | |
1291 | gpmc_t->bool_timings.we_extra_delay = true; | |
1292 | ||
1293 | return 0; | |
1294 | } | |
1295 | ||
1296 | static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1297 | struct gpmc_device_timings *dev_t, |
1298 | bool sync) | |
246da26d AM |
1299 | { |
1300 | u32 temp; | |
1301 | ||
1302 | /* cs_on */ | |
1303 | gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu); | |
1304 | ||
1305 | /* adv_on */ | |
1306 | temp = dev_t->t_avdasu; | |
1307 | if (dev_t->t_ce_avd) | |
1308 | temp = max_t(u32, temp, | |
1309 | gpmc_t->cs_on + dev_t->t_ce_avd); | |
1310 | gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp); | |
1311 | ||
c3be5b45 | 1312 | if (sync) |
246da26d AM |
1313 | gpmc_calc_sync_common_timings(gpmc_t, dev_t); |
1314 | ||
1315 | return 0; | |
1316 | } | |
1317 | ||
1318 | /* TODO: remove this function once all peripherals are confirmed to | |
1319 | * work with generic timing. Simultaneously gpmc_cs_set_timings() | |
1320 | * has to be modified to handle timings in ps instead of ns | |
1321 | */ | |
1322 | static void gpmc_convert_ps_to_ns(struct gpmc_timings *t) | |
1323 | { | |
1324 | t->cs_on /= 1000; | |
1325 | t->cs_rd_off /= 1000; | |
1326 | t->cs_wr_off /= 1000; | |
1327 | t->adv_on /= 1000; | |
1328 | t->adv_rd_off /= 1000; | |
1329 | t->adv_wr_off /= 1000; | |
1330 | t->we_on /= 1000; | |
1331 | t->we_off /= 1000; | |
1332 | t->oe_on /= 1000; | |
1333 | t->oe_off /= 1000; | |
1334 | t->page_burst_access /= 1000; | |
1335 | t->access /= 1000; | |
1336 | t->rd_cycle /= 1000; | |
1337 | t->wr_cycle /= 1000; | |
1338 | t->bus_turnaround /= 1000; | |
1339 | t->cycle2cycle_delay /= 1000; | |
1340 | t->wait_monitoring /= 1000; | |
1341 | t->clk_activation /= 1000; | |
1342 | t->wr_access /= 1000; | |
1343 | t->wr_data_mux_bus /= 1000; | |
1344 | } | |
1345 | ||
1346 | int gpmc_calc_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1347 | struct gpmc_settings *gpmc_s, |
1348 | struct gpmc_device_timings *dev_t) | |
246da26d | 1349 | { |
c3be5b45 JH |
1350 | bool mux = false, sync = false; |
1351 | ||
1352 | if (gpmc_s) { | |
1353 | mux = gpmc_s->mux_add_data ? true : false; | |
1354 | sync = (gpmc_s->sync_read || gpmc_s->sync_write); | |
1355 | } | |
1356 | ||
246da26d AM |
1357 | memset(gpmc_t, 0, sizeof(*gpmc_t)); |
1358 | ||
c3be5b45 | 1359 | gpmc_calc_common_timings(gpmc_t, dev_t, sync); |
246da26d | 1360 | |
c3be5b45 JH |
1361 | if (gpmc_s && gpmc_s->sync_read) |
1362 | gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux); | |
246da26d | 1363 | else |
c3be5b45 | 1364 | gpmc_calc_async_read_timings(gpmc_t, dev_t, mux); |
246da26d | 1365 | |
c3be5b45 JH |
1366 | if (gpmc_s && gpmc_s->sync_write) |
1367 | gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux); | |
246da26d | 1368 | else |
c3be5b45 | 1369 | gpmc_calc_async_write_timings(gpmc_t, dev_t, mux); |
246da26d AM |
1370 | |
1371 | /* TODO: remove, see function definition */ | |
1372 | gpmc_convert_ps_to_ns(gpmc_t); | |
1373 | ||
1374 | return 0; | |
1375 | } | |
1376 | ||
aa8d4767 JH |
1377 | /** |
1378 | * gpmc_cs_program_settings - programs non-timing related settings | |
1379 | * @cs: GPMC chip-select to program | |
1380 | * @p: pointer to GPMC settings structure | |
1381 | * | |
1382 | * Programs non-timing related settings for a GPMC chip-select, such as | |
1383 | * bus-width, burst configuration, etc. Function should be called once | |
1384 | * for each chip-select that is being used and must be called before | |
1385 | * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1 | |
1386 | * register will be initialised to zero by this function. Returns 0 on | |
1387 | * success and appropriate negative error code on failure. | |
1388 | */ | |
1389 | int gpmc_cs_program_settings(int cs, struct gpmc_settings *p) | |
1390 | { | |
1391 | u32 config1; | |
1392 | ||
1393 | if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) { | |
1394 | pr_err("%s: invalid width %d!", __func__, p->device_width); | |
1395 | return -EINVAL; | |
1396 | } | |
1397 | ||
1398 | /* Address-data multiplexing not supported for NAND devices */ | |
1399 | if (p->device_nand && p->mux_add_data) { | |
1400 | pr_err("%s: invalid configuration!\n", __func__); | |
1401 | return -EINVAL; | |
1402 | } | |
1403 | ||
1404 | if ((p->mux_add_data > GPMC_MUX_AD) || | |
1405 | ((p->mux_add_data == GPMC_MUX_AAD) && | |
1406 | !(gpmc_capability & GPMC_HAS_MUX_AAD))) { | |
1407 | pr_err("%s: invalid multiplex configuration!\n", __func__); | |
1408 | return -EINVAL; | |
1409 | } | |
1410 | ||
1411 | /* Page/burst mode supports lengths of 4, 8 and 16 bytes */ | |
1412 | if (p->burst_read || p->burst_write) { | |
1413 | switch (p->burst_len) { | |
1414 | case GPMC_BURST_4: | |
1415 | case GPMC_BURST_8: | |
1416 | case GPMC_BURST_16: | |
1417 | break; | |
1418 | default: | |
1419 | pr_err("%s: invalid page/burst-length (%d)\n", | |
1420 | __func__, p->burst_len); | |
1421 | return -EINVAL; | |
1422 | } | |
1423 | } | |
1424 | ||
2b54057c | 1425 | if (p->wait_pin > gpmc_nr_waitpins) { |
aa8d4767 JH |
1426 | pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin); |
1427 | return -EINVAL; | |
1428 | } | |
1429 | ||
1430 | config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1)); | |
1431 | ||
1432 | if (p->sync_read) | |
1433 | config1 |= GPMC_CONFIG1_READTYPE_SYNC; | |
1434 | if (p->sync_write) | |
1435 | config1 |= GPMC_CONFIG1_WRITETYPE_SYNC; | |
1436 | if (p->wait_on_read) | |
1437 | config1 |= GPMC_CONFIG1_WAIT_READ_MON; | |
1438 | if (p->wait_on_write) | |
1439 | config1 |= GPMC_CONFIG1_WAIT_WRITE_MON; | |
1440 | if (p->wait_on_read || p->wait_on_write) | |
1441 | config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin); | |
1442 | if (p->device_nand) | |
1443 | config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND); | |
1444 | if (p->mux_add_data) | |
1445 | config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data); | |
1446 | if (p->burst_read) | |
1447 | config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP; | |
1448 | if (p->burst_write) | |
1449 | config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP; | |
1450 | if (p->burst_read || p->burst_write) { | |
1451 | config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3); | |
1452 | config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0; | |
1453 | } | |
1454 | ||
1455 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1); | |
1456 | ||
1457 | return 0; | |
1458 | } | |
1459 | ||
bc6b1e7b | 1460 | #ifdef CONFIG_OF |
31957609 | 1461 | static const struct of_device_id gpmc_dt_ids[] = { |
bc6b1e7b DM |
1462 | { .compatible = "ti,omap2420-gpmc" }, |
1463 | { .compatible = "ti,omap2430-gpmc" }, | |
1464 | { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */ | |
1465 | { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */ | |
1466 | { .compatible = "ti,am3352-gpmc" }, /* am335x devices */ | |
1467 | { } | |
1468 | }; | |
1469 | MODULE_DEVICE_TABLE(of, gpmc_dt_ids); | |
1470 | ||
8c8a7771 JH |
1471 | /** |
1472 | * gpmc_read_settings_dt - read gpmc settings from device-tree | |
1473 | * @np: pointer to device-tree node for a gpmc child device | |
1474 | * @p: pointer to gpmc settings structure | |
1475 | * | |
1476 | * Reads the GPMC settings for a GPMC child device from device-tree and | |
1477 | * stores them in the GPMC settings structure passed. The GPMC settings | |
1478 | * structure is initialised to zero by this function and so any | |
1479 | * previously stored settings will be cleared. | |
1480 | */ | |
1481 | void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p) | |
1482 | { | |
1483 | memset(p, 0, sizeof(struct gpmc_settings)); | |
1484 | ||
1485 | p->sync_read = of_property_read_bool(np, "gpmc,sync-read"); | |
1486 | p->sync_write = of_property_read_bool(np, "gpmc,sync-write"); | |
8c8a7771 JH |
1487 | of_property_read_u32(np, "gpmc,device-width", &p->device_width); |
1488 | of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data); | |
1489 | ||
1490 | if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) { | |
1491 | p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap"); | |
1492 | p->burst_read = of_property_read_bool(np, "gpmc,burst-read"); | |
1493 | p->burst_write = of_property_read_bool(np, "gpmc,burst-write"); | |
1494 | if (!p->burst_read && !p->burst_write) | |
1495 | pr_warn("%s: page/burst-length set but not used!\n", | |
1496 | __func__); | |
1497 | } | |
1498 | ||
1499 | if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) { | |
1500 | p->wait_on_read = of_property_read_bool(np, | |
1501 | "gpmc,wait-on-read"); | |
1502 | p->wait_on_write = of_property_read_bool(np, | |
1503 | "gpmc,wait-on-write"); | |
1504 | if (!p->wait_on_read && !p->wait_on_write) | |
2b54057c RQ |
1505 | pr_debug("%s: rd/wr wait monitoring not enabled!\n", |
1506 | __func__); | |
8c8a7771 JH |
1507 | } |
1508 | } | |
1509 | ||
bc6b1e7b DM |
1510 | static void __maybe_unused gpmc_read_timings_dt(struct device_node *np, |
1511 | struct gpmc_timings *gpmc_t) | |
1512 | { | |
d36b4cd4 JH |
1513 | struct gpmc_bool_timings *p; |
1514 | ||
1515 | if (!np || !gpmc_t) | |
1516 | return; | |
bc6b1e7b DM |
1517 | |
1518 | memset(gpmc_t, 0, sizeof(*gpmc_t)); | |
1519 | ||
1520 | /* minimum clock period for syncronous mode */ | |
d36b4cd4 | 1521 | of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk); |
bc6b1e7b DM |
1522 | |
1523 | /* chip select timtings */ | |
d36b4cd4 JH |
1524 | of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on); |
1525 | of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off); | |
1526 | of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off); | |
bc6b1e7b DM |
1527 | |
1528 | /* ADV signal timings */ | |
d36b4cd4 JH |
1529 | of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on); |
1530 | of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off); | |
1531 | of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off); | |
bc6b1e7b DM |
1532 | |
1533 | /* WE signal timings */ | |
d36b4cd4 JH |
1534 | of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on); |
1535 | of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off); | |
bc6b1e7b DM |
1536 | |
1537 | /* OE signal timings */ | |
d36b4cd4 JH |
1538 | of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on); |
1539 | of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off); | |
bc6b1e7b DM |
1540 | |
1541 | /* access and cycle timings */ | |
d36b4cd4 JH |
1542 | of_property_read_u32(np, "gpmc,page-burst-access-ns", |
1543 | &gpmc_t->page_burst_access); | |
1544 | of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access); | |
1545 | of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle); | |
1546 | of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle); | |
1547 | of_property_read_u32(np, "gpmc,bus-turnaround-ns", | |
1548 | &gpmc_t->bus_turnaround); | |
1549 | of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns", | |
1550 | &gpmc_t->cycle2cycle_delay); | |
1551 | of_property_read_u32(np, "gpmc,wait-monitoring-ns", | |
1552 | &gpmc_t->wait_monitoring); | |
1553 | of_property_read_u32(np, "gpmc,clk-activation-ns", | |
1554 | &gpmc_t->clk_activation); | |
1555 | ||
1556 | /* only applicable to OMAP3+ */ | |
1557 | of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access); | |
1558 | of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns", | |
1559 | &gpmc_t->wr_data_mux_bus); | |
1560 | ||
1561 | /* bool timing parameters */ | |
1562 | p = &gpmc_t->bool_timings; | |
1563 | ||
1564 | p->cycle2cyclediffcsen = | |
1565 | of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen"); | |
1566 | p->cycle2cyclesamecsen = | |
1567 | of_property_read_bool(np, "gpmc,cycle2cycle-samecsen"); | |
1568 | p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay"); | |
1569 | p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay"); | |
1570 | p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay"); | |
1571 | p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay"); | |
1572 | p->time_para_granularity = | |
1573 | of_property_read_bool(np, "gpmc,time-para-granularity"); | |
bc6b1e7b DM |
1574 | } |
1575 | ||
6b187b21 | 1576 | #if IS_ENABLED(CONFIG_MTD_NAND) |
bc6b1e7b | 1577 | |
496c8a0b MJ |
1578 | static const char * const nand_xfer_types[] = { |
1579 | [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled", | |
1580 | [NAND_OMAP_POLLED] = "polled", | |
1581 | [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma", | |
1582 | [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq", | |
1583 | }; | |
1584 | ||
bc6b1e7b DM |
1585 | static int gpmc_probe_nand_child(struct platform_device *pdev, |
1586 | struct device_node *child) | |
1587 | { | |
1588 | u32 val; | |
1589 | const char *s; | |
1590 | struct gpmc_timings gpmc_t; | |
1591 | struct omap_nand_platform_data *gpmc_nand_data; | |
1592 | ||
1593 | if (of_property_read_u32(child, "reg", &val) < 0) { | |
1594 | dev_err(&pdev->dev, "%s has no 'reg' property\n", | |
1595 | child->full_name); | |
1596 | return -ENODEV; | |
1597 | } | |
1598 | ||
1599 | gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data), | |
1600 | GFP_KERNEL); | |
1601 | if (!gpmc_nand_data) | |
1602 | return -ENOMEM; | |
1603 | ||
1604 | gpmc_nand_data->cs = val; | |
1605 | gpmc_nand_data->of_node = child; | |
1606 | ||
ac65caf5 PG |
1607 | /* Detect availability of ELM module */ |
1608 | gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0); | |
1609 | if (gpmc_nand_data->elm_of_node == NULL) | |
1610 | gpmc_nand_data->elm_of_node = | |
1611 | of_parse_phandle(child, "elm_id", 0); | |
ac65caf5 PG |
1612 | |
1613 | /* select ecc-scheme for NAND */ | |
1614 | if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) { | |
1615 | pr_err("%s: ti,nand-ecc-opt not found\n", __func__); | |
1616 | return -ENODEV; | |
1617 | } | |
a3e83f05 RQ |
1618 | |
1619 | if (!strcmp(s, "sw")) | |
1620 | gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW; | |
1621 | else if (!strcmp(s, "ham1") || | |
1622 | !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) | |
ac65caf5 PG |
1623 | gpmc_nand_data->ecc_opt = |
1624 | OMAP_ECC_HAM1_CODE_HW; | |
1625 | else if (!strcmp(s, "bch4")) | |
1626 | if (gpmc_nand_data->elm_of_node) | |
1627 | gpmc_nand_data->ecc_opt = | |
1628 | OMAP_ECC_BCH4_CODE_HW; | |
1629 | else | |
1630 | gpmc_nand_data->ecc_opt = | |
1631 | OMAP_ECC_BCH4_CODE_HW_DETECTION_SW; | |
1632 | else if (!strcmp(s, "bch8")) | |
1633 | if (gpmc_nand_data->elm_of_node) | |
1634 | gpmc_nand_data->ecc_opt = | |
1635 | OMAP_ECC_BCH8_CODE_HW; | |
1636 | else | |
1637 | gpmc_nand_data->ecc_opt = | |
1638 | OMAP_ECC_BCH8_CODE_HW_DETECTION_SW; | |
27c9fd60 | 1639 | else if (!strcmp(s, "bch16")) |
1640 | if (gpmc_nand_data->elm_of_node) | |
1641 | gpmc_nand_data->ecc_opt = | |
1642 | OMAP_ECC_BCH16_CODE_HW; | |
1643 | else | |
1644 | pr_err("%s: BCH16 requires ELM support\n", __func__); | |
ac65caf5 PG |
1645 | else |
1646 | pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__); | |
bc6b1e7b | 1647 | |
ac65caf5 | 1648 | /* select data transfer mode for NAND controller */ |
496c8a0b MJ |
1649 | if (!of_property_read_string(child, "ti,nand-xfer-type", &s)) |
1650 | for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++) | |
1651 | if (!strcasecmp(s, nand_xfer_types[val])) { | |
1652 | gpmc_nand_data->xfer_type = val; | |
1653 | break; | |
1654 | } | |
1655 | ||
fef775ca EG |
1656 | gpmc_nand_data->flash_bbt = of_get_nand_on_flash_bbt(child); |
1657 | ||
bc6b1e7b DM |
1658 | val = of_get_nand_bus_width(child); |
1659 | if (val == 16) | |
1660 | gpmc_nand_data->devsize = NAND_BUSWIDTH_16; | |
1661 | ||
1662 | gpmc_read_timings_dt(child, &gpmc_t); | |
1663 | gpmc_nand_init(gpmc_nand_data, &gpmc_t); | |
1664 | ||
1665 | return 0; | |
1666 | } | |
1667 | #else | |
1668 | static int gpmc_probe_nand_child(struct platform_device *pdev, | |
1669 | struct device_node *child) | |
1670 | { | |
1671 | return 0; | |
1672 | } | |
1673 | #endif | |
1674 | ||
980386d2 | 1675 | #if IS_ENABLED(CONFIG_MTD_ONENAND) |
75d3625e EG |
1676 | static int gpmc_probe_onenand_child(struct platform_device *pdev, |
1677 | struct device_node *child) | |
1678 | { | |
1679 | u32 val; | |
1680 | struct omap_onenand_platform_data *gpmc_onenand_data; | |
1681 | ||
1682 | if (of_property_read_u32(child, "reg", &val) < 0) { | |
1683 | dev_err(&pdev->dev, "%s has no 'reg' property\n", | |
1684 | child->full_name); | |
1685 | return -ENODEV; | |
1686 | } | |
1687 | ||
1688 | gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data), | |
1689 | GFP_KERNEL); | |
1690 | if (!gpmc_onenand_data) | |
1691 | return -ENOMEM; | |
1692 | ||
1693 | gpmc_onenand_data->cs = val; | |
1694 | gpmc_onenand_data->of_node = child; | |
1695 | gpmc_onenand_data->dma_channel = -1; | |
1696 | ||
1697 | if (!of_property_read_u32(child, "dma-channel", &val)) | |
1698 | gpmc_onenand_data->dma_channel = val; | |
1699 | ||
1700 | gpmc_onenand_init(gpmc_onenand_data); | |
1701 | ||
1702 | return 0; | |
1703 | } | |
1704 | #else | |
1705 | static int gpmc_probe_onenand_child(struct platform_device *pdev, | |
1706 | struct device_node *child) | |
1707 | { | |
1708 | return 0; | |
1709 | } | |
1710 | #endif | |
1711 | ||
cdd6928c | 1712 | /** |
3af91cf7 | 1713 | * gpmc_probe_generic_child - configures the gpmc for a child device |
cdd6928c | 1714 | * @pdev: pointer to gpmc platform device |
3af91cf7 | 1715 | * @child: pointer to device-tree node for child device |
cdd6928c | 1716 | * |
3af91cf7 | 1717 | * Allocates and configures a GPMC chip-select for a child device. |
cdd6928c JH |
1718 | * Returns 0 on success and appropriate negative error code on failure. |
1719 | */ | |
3af91cf7 | 1720 | static int gpmc_probe_generic_child(struct platform_device *pdev, |
cdd6928c JH |
1721 | struct device_node *child) |
1722 | { | |
1723 | struct gpmc_settings gpmc_s; | |
1724 | struct gpmc_timings gpmc_t; | |
1725 | struct resource res; | |
1726 | unsigned long base; | |
9ed7a776 | 1727 | const char *name; |
cdd6928c | 1728 | int ret, cs; |
e378d22b | 1729 | u32 val; |
cdd6928c JH |
1730 | |
1731 | if (of_property_read_u32(child, "reg", &cs) < 0) { | |
1732 | dev_err(&pdev->dev, "%s has no 'reg' property\n", | |
1733 | child->full_name); | |
1734 | return -ENODEV; | |
1735 | } | |
1736 | ||
1737 | if (of_address_to_resource(child, 0, &res) < 0) { | |
1738 | dev_err(&pdev->dev, "%s has malformed 'reg' property\n", | |
1739 | child->full_name); | |
1740 | return -ENODEV; | |
1741 | } | |
1742 | ||
9ed7a776 TL |
1743 | /* |
1744 | * Check if we have multiple instances of the same device | |
1745 | * on a single chip select. If so, use the already initialized | |
1746 | * timings. | |
1747 | */ | |
1748 | name = gpmc_cs_get_name(cs); | |
1749 | if (name && child->name && of_node_cmp(child->name, name) == 0) | |
1750 | goto no_timings; | |
1751 | ||
cdd6928c JH |
1752 | ret = gpmc_cs_request(cs, resource_size(&res), &base); |
1753 | if (ret < 0) { | |
1754 | dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs); | |
1755 | return ret; | |
1756 | } | |
9ed7a776 | 1757 | gpmc_cs_set_name(cs, child->name); |
cdd6928c | 1758 | |
35ac051e TL |
1759 | gpmc_read_settings_dt(child, &gpmc_s); |
1760 | gpmc_read_timings_dt(child, &gpmc_t); | |
cdd6928c | 1761 | |
fd4446f2 TL |
1762 | /* |
1763 | * For some GPMC devices we still need to rely on the bootloader | |
35ac051e TL |
1764 | * timings because the devices can be connected via FPGA. |
1765 | * REVISIT: Add timing support from slls644g.pdf. | |
fd4446f2 | 1766 | */ |
35ac051e TL |
1767 | if (!gpmc_t.cs_rd_off) { |
1768 | WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n", | |
1769 | cs); | |
1770 | gpmc_cs_show_timings(cs, | |
1771 | "please add GPMC bootloader timings to .dts"); | |
fd4446f2 TL |
1772 | goto no_timings; |
1773 | } | |
1774 | ||
4cf27d2e RQ |
1775 | /* CS must be disabled while making changes to gpmc configuration */ |
1776 | gpmc_cs_disable_mem(cs); | |
1777 | ||
cdd6928c JH |
1778 | /* |
1779 | * FIXME: gpmc_cs_request() will map the CS to an arbitary | |
1780 | * location in the gpmc address space. When booting with | |
1781 | * device-tree we want the NOR flash to be mapped to the | |
1782 | * location specified in the device-tree blob. So remap the | |
1783 | * CS to this location. Once DT migration is complete should | |
1784 | * just make gpmc_cs_request() map a specific address. | |
1785 | */ | |
1786 | ret = gpmc_cs_remap(cs, res.start); | |
1787 | if (ret < 0) { | |
f70bf2a3 FE |
1788 | dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n", |
1789 | cs, &res.start); | |
cdd6928c JH |
1790 | goto err; |
1791 | } | |
1792 | ||
cdd6928c JH |
1793 | ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width); |
1794 | if (ret < 0) | |
1795 | goto err; | |
1796 | ||
1797 | ret = gpmc_cs_program_settings(cs, &gpmc_s); | |
1798 | if (ret < 0) | |
1799 | goto err; | |
1800 | ||
7604baf3 RQ |
1801 | ret = gpmc_cs_set_timings(cs, &gpmc_t); |
1802 | if (ret) { | |
1803 | dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n", | |
1804 | child->name); | |
1805 | goto err; | |
1806 | } | |
cdd6928c | 1807 | |
e378d22b RQ |
1808 | /* Clear limited address i.e. enable A26-A11 */ |
1809 | val = gpmc_read_reg(GPMC_CONFIG); | |
1810 | val &= ~GPMC_CONFIG_LIMITEDADDRESS; | |
1811 | gpmc_write_reg(GPMC_CONFIG, val); | |
1812 | ||
4cf27d2e RQ |
1813 | /* Enable CS region */ |
1814 | gpmc_cs_enable_mem(cs); | |
cdd6928c | 1815 | |
fd4446f2 | 1816 | no_timings: |
cdd6928c JH |
1817 | if (of_platform_device_create(child, NULL, &pdev->dev)) |
1818 | return 0; | |
1819 | ||
1820 | dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name); | |
e8ffd6fd | 1821 | ret = -ENODEV; |
cdd6928c JH |
1822 | |
1823 | err: | |
1824 | gpmc_cs_free(cs); | |
1825 | ||
1826 | return ret; | |
1827 | } | |
1828 | ||
bc6b1e7b DM |
1829 | static int gpmc_probe_dt(struct platform_device *pdev) |
1830 | { | |
1831 | int ret; | |
1832 | struct device_node *child; | |
1833 | const struct of_device_id *of_id = | |
1834 | of_match_device(gpmc_dt_ids, &pdev->dev); | |
1835 | ||
1836 | if (!of_id) | |
1837 | return 0; | |
1838 | ||
f34f3716 GP |
1839 | ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs", |
1840 | &gpmc_cs_num); | |
1841 | if (ret < 0) { | |
1842 | pr_err("%s: number of chip-selects not defined\n", __func__); | |
1843 | return ret; | |
1844 | } else if (gpmc_cs_num < 1) { | |
1845 | pr_err("%s: all chip-selects are disabled\n", __func__); | |
1846 | return -EINVAL; | |
1847 | } else if (gpmc_cs_num > GPMC_CS_NUM) { | |
1848 | pr_err("%s: number of supported chip-selects cannot be > %d\n", | |
1849 | __func__, GPMC_CS_NUM); | |
1850 | return -EINVAL; | |
1851 | } | |
1852 | ||
9f833156 JH |
1853 | ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins", |
1854 | &gpmc_nr_waitpins); | |
1855 | if (ret < 0) { | |
1856 | pr_err("%s: number of wait pins not found!\n", __func__); | |
1857 | return ret; | |
1858 | } | |
1859 | ||
68e2eb53 | 1860 | for_each_available_child_of_node(pdev->dev.of_node, child) { |
bc6b1e7b | 1861 | |
f2b09f67 JMC |
1862 | if (!child->name) |
1863 | continue; | |
cdd6928c | 1864 | |
f2b09f67 JMC |
1865 | if (of_node_cmp(child->name, "nand") == 0) |
1866 | ret = gpmc_probe_nand_child(pdev, child); | |
1867 | else if (of_node_cmp(child->name, "onenand") == 0) | |
1868 | ret = gpmc_probe_onenand_child(pdev, child); | |
1869 | else if (of_node_cmp(child->name, "ethernet") == 0 || | |
fd4446f2 TL |
1870 | of_node_cmp(child->name, "nor") == 0 || |
1871 | of_node_cmp(child->name, "uart") == 0) | |
f2b09f67 | 1872 | ret = gpmc_probe_generic_child(pdev, child); |
cdd6928c | 1873 | |
b327b362 JMC |
1874 | if (WARN(ret < 0, "%s: probing gpmc child %s failed\n", |
1875 | __func__, child->full_name)) | |
5330dc16 | 1876 | of_node_put(child); |
5330dc16 JMC |
1877 | } |
1878 | ||
bc6b1e7b DM |
1879 | return 0; |
1880 | } | |
1881 | #else | |
1882 | static int gpmc_probe_dt(struct platform_device *pdev) | |
1883 | { | |
1884 | return 0; | |
1885 | } | |
1886 | #endif | |
1887 | ||
351a102d | 1888 | static int gpmc_probe(struct platform_device *pdev) |
4bbbc1ad | 1889 | { |
8119024e | 1890 | int rc; |
6b6c32fc | 1891 | u32 l; |
da496873 | 1892 | struct resource *res; |
4bbbc1ad | 1893 | |
da496873 AM |
1894 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1895 | if (res == NULL) | |
1896 | return -ENOENT; | |
8d08436d | 1897 | |
da496873 AM |
1898 | phys_base = res->start; |
1899 | mem_size = resource_size(res); | |
fd1dc87d | 1900 | |
5857bd98 TR |
1901 | gpmc_base = devm_ioremap_resource(&pdev->dev, res); |
1902 | if (IS_ERR(gpmc_base)) | |
1903 | return PTR_ERR(gpmc_base); | |
da496873 AM |
1904 | |
1905 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1906 | if (res == NULL) | |
1907 | dev_warn(&pdev->dev, "Failed to get resource: irq\n"); | |
1908 | else | |
1909 | gpmc_irq = res->start; | |
1910 | ||
8bf9be56 | 1911 | gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck"); |
da496873 | 1912 | if (IS_ERR(gpmc_l3_clk)) { |
8bf9be56 | 1913 | dev_err(&pdev->dev, "Failed to get GPMC fck\n"); |
da496873 AM |
1914 | gpmc_irq = 0; |
1915 | return PTR_ERR(gpmc_l3_clk); | |
fd1dc87d PW |
1916 | } |
1917 | ||
8bf9be56 RQ |
1918 | if (!clk_get_rate(gpmc_l3_clk)) { |
1919 | dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n"); | |
1920 | return -EINVAL; | |
1921 | } | |
1922 | ||
b3f5525c | 1923 | pm_runtime_enable(&pdev->dev); |
1924 | pm_runtime_get_sync(&pdev->dev); | |
1daa8c1d | 1925 | |
da496873 AM |
1926 | gpmc_dev = &pdev->dev; |
1927 | ||
4bbbc1ad | 1928 | l = gpmc_read_reg(GPMC_REVISION); |
aa8d4767 JH |
1929 | |
1930 | /* | |
1931 | * FIXME: Once device-tree migration is complete the below flags | |
1932 | * should be populated based upon the device-tree compatible | |
1933 | * string. For now just use the IP revision. OMAP3+ devices have | |
1934 | * the wr_access and wr_data_mux_bus register fields. OMAP4+ | |
1935 | * devices support the addr-addr-data multiplex protocol. | |
1936 | * | |
1937 | * GPMC IP revisions: | |
1938 | * - OMAP24xx = 2.0 | |
1939 | * - OMAP3xxx = 5.0 | |
1940 | * - OMAP44xx/54xx/AM335x = 6.0 | |
1941 | */ | |
da496873 AM |
1942 | if (GPMC_REVISION_MAJOR(l) > 0x4) |
1943 | gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS; | |
aa8d4767 JH |
1944 | if (GPMC_REVISION_MAJOR(l) > 0x5) |
1945 | gpmc_capability |= GPMC_HAS_MUX_AAD; | |
da496873 AM |
1946 | dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l), |
1947 | GPMC_REVISION_MINOR(l)); | |
1948 | ||
84b00f0e | 1949 | gpmc_mem_init(); |
db97eb7d | 1950 | |
71856843 | 1951 | if (gpmc_setup_irq() < 0) |
da496873 AM |
1952 | dev_warn(gpmc_dev, "gpmc_setup_irq failed\n"); |
1953 | ||
f34f3716 GP |
1954 | if (!pdev->dev.of_node) { |
1955 | gpmc_cs_num = GPMC_CS_NUM; | |
9f833156 | 1956 | gpmc_nr_waitpins = GPMC_NR_WAITPINS; |
f34f3716 | 1957 | } |
9f833156 | 1958 | |
bc6b1e7b DM |
1959 | rc = gpmc_probe_dt(pdev); |
1960 | if (rc < 0) { | |
b3f5525c | 1961 | pm_runtime_put_sync(&pdev->dev); |
bc6b1e7b DM |
1962 | dev_err(gpmc_dev, "failed to probe DT parameters\n"); |
1963 | return rc; | |
1964 | } | |
1965 | ||
da496873 AM |
1966 | return 0; |
1967 | } | |
1968 | ||
351a102d | 1969 | static int gpmc_remove(struct platform_device *pdev) |
da496873 AM |
1970 | { |
1971 | gpmc_free_irq(); | |
1972 | gpmc_mem_exit(); | |
b3f5525c | 1973 | pm_runtime_put_sync(&pdev->dev); |
1974 | pm_runtime_disable(&pdev->dev); | |
da496873 AM |
1975 | gpmc_dev = NULL; |
1976 | return 0; | |
1977 | } | |
1978 | ||
b536dd41 | 1979 | #ifdef CONFIG_PM_SLEEP |
1980 | static int gpmc_suspend(struct device *dev) | |
1981 | { | |
1982 | omap3_gpmc_save_context(); | |
1983 | pm_runtime_put_sync(dev); | |
1984 | return 0; | |
1985 | } | |
1986 | ||
1987 | static int gpmc_resume(struct device *dev) | |
1988 | { | |
1989 | pm_runtime_get_sync(dev); | |
1990 | omap3_gpmc_restore_context(); | |
1991 | return 0; | |
1992 | } | |
1993 | #endif | |
1994 | ||
1995 | static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume); | |
1996 | ||
da496873 AM |
1997 | static struct platform_driver gpmc_driver = { |
1998 | .probe = gpmc_probe, | |
351a102d | 1999 | .remove = gpmc_remove, |
da496873 AM |
2000 | .driver = { |
2001 | .name = DEVICE_NAME, | |
bc6b1e7b | 2002 | .of_match_table = of_match_ptr(gpmc_dt_ids), |
b536dd41 | 2003 | .pm = &gpmc_pm_ops, |
da496873 AM |
2004 | }, |
2005 | }; | |
2006 | ||
2007 | static __init int gpmc_init(void) | |
2008 | { | |
2009 | return platform_driver_register(&gpmc_driver); | |
2010 | } | |
2011 | ||
2012 | static __exit void gpmc_exit(void) | |
2013 | { | |
2014 | platform_driver_unregister(&gpmc_driver); | |
2015 | ||
db97eb7d | 2016 | } |
da496873 | 2017 | |
a8612809 | 2018 | postcore_initcall(gpmc_init); |
da496873 | 2019 | module_exit(gpmc_exit); |
db97eb7d SG |
2020 | |
2021 | static irqreturn_t gpmc_handle_irq(int irq, void *dev) | |
2022 | { | |
6b6c32fc AM |
2023 | int i; |
2024 | u32 regval; | |
2025 | ||
2026 | regval = gpmc_read_reg(GPMC_IRQSTATUS); | |
2027 | ||
2028 | if (!regval) | |
2029 | return IRQ_NONE; | |
2030 | ||
2031 | for (i = 0; i < GPMC_NR_IRQ; i++) | |
2032 | if (regval & gpmc_client_irq[i].bitmask) | |
2033 | generic_handle_irq(gpmc_client_irq[i].irq); | |
db97eb7d | 2034 | |
6b6c32fc | 2035 | gpmc_write_reg(GPMC_IRQSTATUS, regval); |
db97eb7d SG |
2036 | |
2037 | return IRQ_HANDLED; | |
4bbbc1ad | 2038 | } |
a2d3e7ba | 2039 | |
a2d3e7ba RN |
2040 | static struct omap3_gpmc_regs gpmc_context; |
2041 | ||
b2fa3b7c | 2042 | void omap3_gpmc_save_context(void) |
a2d3e7ba RN |
2043 | { |
2044 | int i; | |
b2fa3b7c | 2045 | |
a2d3e7ba RN |
2046 | gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); |
2047 | gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE); | |
2048 | gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); | |
2049 | gpmc_context.config = gpmc_read_reg(GPMC_CONFIG); | |
2050 | gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); | |
2051 | gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); | |
2052 | gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); | |
f34f3716 | 2053 | for (i = 0; i < gpmc_cs_num; i++) { |
a2d3e7ba RN |
2054 | gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i); |
2055 | if (gpmc_context.cs_context[i].is_valid) { | |
2056 | gpmc_context.cs_context[i].config1 = | |
2057 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG1); | |
2058 | gpmc_context.cs_context[i].config2 = | |
2059 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG2); | |
2060 | gpmc_context.cs_context[i].config3 = | |
2061 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG3); | |
2062 | gpmc_context.cs_context[i].config4 = | |
2063 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG4); | |
2064 | gpmc_context.cs_context[i].config5 = | |
2065 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG5); | |
2066 | gpmc_context.cs_context[i].config6 = | |
2067 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG6); | |
2068 | gpmc_context.cs_context[i].config7 = | |
2069 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG7); | |
2070 | } | |
2071 | } | |
2072 | } | |
2073 | ||
b2fa3b7c | 2074 | void omap3_gpmc_restore_context(void) |
a2d3e7ba RN |
2075 | { |
2076 | int i; | |
b2fa3b7c | 2077 | |
a2d3e7ba RN |
2078 | gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig); |
2079 | gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable); | |
2080 | gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl); | |
2081 | gpmc_write_reg(GPMC_CONFIG, gpmc_context.config); | |
2082 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1); | |
2083 | gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2); | |
2084 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control); | |
f34f3716 | 2085 | for (i = 0; i < gpmc_cs_num; i++) { |
a2d3e7ba RN |
2086 | if (gpmc_context.cs_context[i].is_valid) { |
2087 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, | |
2088 | gpmc_context.cs_context[i].config1); | |
2089 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG2, | |
2090 | gpmc_context.cs_context[i].config2); | |
2091 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG3, | |
2092 | gpmc_context.cs_context[i].config3); | |
2093 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG4, | |
2094 | gpmc_context.cs_context[i].config4); | |
2095 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG5, | |
2096 | gpmc_context.cs_context[i].config5); | |
2097 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG6, | |
2098 | gpmc_context.cs_context[i].config6); | |
2099 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, | |
2100 | gpmc_context.cs_context[i].config7); | |
2101 | } | |
2102 | } | |
2103 | } |