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memory: omap-gpmc: Correct white space issues
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d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
4bbbc1ad
JY		 2/*
3 * GPMC support functions
4 *
5 * Copyright (C) 2005-2006 Nokia Corporation
6 *
7 * Author: Juha Yrjola
8 *
44169075
SS		 9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
4bbbc1ad 11 */
db97eb7d 12#include <linux/irq.h>
4bbbc1ad
JY		 13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/clk.h>
f37e4580
ID		 17#include <linux/ioport.h>
18#include <linux/spinlock.h>
fced80c7 19#include <linux/io.h>
d2d00862 20#include <linux/gpio/driver.h>
a0752e9c 21#include <linux/gpio/consumer.h> /* GPIO descriptor enum */
5923ea6c 22#include <linux/gpio/machine.h>
db97eb7d 23#include <linux/interrupt.h>
384258f2 24#include <linux/irqdomain.h>
da496873 25#include <linux/platform_device.h>
bc6b1e7b 26#include <linux/of.h>
cdd6928c 27#include <linux/of_address.h>
bc6b1e7b 28#include <linux/of_device.h>
b1dc1ca9 29#include <linux/of_platform.h>
e639cd5b 30#include <linux/omap-gpmc.h>
b3f5525c 31#include <linux/pm_runtime.h>
07852c3f 32#include <linux/sizes.h>
4bbbc1ad 33
bc3668ea 34#include <linux/platform_data/mtd-nand-omap2.h>
4bbbc1ad 35
7f245162 36#include <asm/mach-types.h>
72d0f1c3 37
4be48fd5
AM		 38#define DEVICE_NAME "omap-gpmc"
39
fd1dc87d 40/* GPMC register offsets */
4bbbc1ad
JY		 41#define GPMC_REVISION 0x00
42#define GPMC_SYSCONFIG 0x10
43#define GPMC_SYSSTATUS 0x14
44#define GPMC_IRQSTATUS 0x18
45#define GPMC_IRQENABLE 0x1c
46#define GPMC_TIMEOUT_CONTROL 0x40
47#define GPMC_ERR_ADDRESS 0x44
48#define GPMC_ERR_TYPE 0x48
49#define GPMC_CONFIG 0x50
50#define GPMC_STATUS 0x54
51#define GPMC_PREFETCH_CONFIG1 0x1e0
52#define GPMC_PREFETCH_CONFIG2 0x1e4
15e02a3b 53#define GPMC_PREFETCH_CONTROL 0x1ec
4bbbc1ad
JY		 54#define GPMC_PREFETCH_STATUS 0x1f0
55#define GPMC_ECC_CONFIG 0x1f4
56#define GPMC_ECC_CONTROL 0x1f8
57#define GPMC_ECC_SIZE_CONFIG 0x1fc
948d38e7 58#define GPMC_ECC1_RESULT 0x200
8d602cf5 59#define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
2fdf0c98
AM		 60#define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
61#define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
62#define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
27c9fd60 63#define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
64#define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
65#define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
4bbbc1ad 66
2c65e744
YY		 67/* GPMC ECC control settings */
68#define GPMC_ECC_CTRL_ECCCLEAR 0x100
69#define GPMC_ECC_CTRL_ECCDISABLE 0x000
70#define GPMC_ECC_CTRL_ECCREG1 0x001
71#define GPMC_ECC_CTRL_ECCREG2 0x002
72#define GPMC_ECC_CTRL_ECCREG3 0x003
73#define GPMC_ECC_CTRL_ECCREG4 0x004
74#define GPMC_ECC_CTRL_ECCREG5 0x005
75#define GPMC_ECC_CTRL_ECCREG6 0x006
76#define GPMC_ECC_CTRL_ECCREG7 0x007
77#define GPMC_ECC_CTRL_ECCREG8 0x008
78#define GPMC_ECC_CTRL_ECCREG9 0x009
79
e378d22b
RQ		 80#define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
81
512d73d1
RQ		 82#define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0)
83
559d94b0
AM		 84#define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
85#define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
86#define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
87#define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
88#define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
89#define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
90
948d38e7 91#define GPMC_CS0_OFFSET 0x60
4bbbc1ad 92#define GPMC_CS_SIZE 0x30
2fdf0c98 93#define GPMC_BCH_SIZE 0x10
4bbbc1ad 94
bdd7e033
RQ		 95/*
96 * The first 1MB of GPMC address space is typically mapped to
97 * the internal ROM. Never allocate the first page, to
98 * facilitate bug detection; even if we didn't boot from ROM.
99 * As GPMC minimum partition size is 16MB we can only start from
100 * there.
101 */
102#define GPMC_MEM_START 0x1000000
f37e4580 103#define GPMC_MEM_END 0x3FFFFFFF
f37e4580
ID		 104
105#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
106#define GPMC_SECTION_SHIFT 28 /* 128 MB */
107
59e9c5ae 108#define CS_NUM_SHIFT 24
109#define ENABLE_PREFETCH (0x1 << 7)
110#define DMA_MPU_MODE 2
111
98397f1c
KK		 112#define GPMC_REVISION_MAJOR(l) (((l) >> 4) & 0xf)
113#define GPMC_REVISION_MINOR(l) ((l) & 0xf)
da496873
AM		 114
115#define GPMC_HAS_WR_ACCESS 0x1
116#define GPMC_HAS_WR_DATA_MUX_BUS 0x2
aa8d4767 117#define GPMC_HAS_MUX_AAD 0x4
da496873 118
9f833156
JH		 119#define GPMC_NR_WAITPINS 4
120
e639cd5b
TL		 121#define GPMC_CS_CONFIG1 0x00
122#define GPMC_CS_CONFIG2 0x04
123#define GPMC_CS_CONFIG3 0x08
124#define GPMC_CS_CONFIG4 0x0c
125#define GPMC_CS_CONFIG5 0x10
126#define GPMC_CS_CONFIG6 0x14
127#define GPMC_CS_CONFIG7 0x18
128#define GPMC_CS_NAND_COMMAND 0x1c
129#define GPMC_CS_NAND_ADDRESS 0x20
130#define GPMC_CS_NAND_DATA 0x24
131
132/* Control Commands */
133#define GPMC_CONFIG_RDY_BSY 0x00000001
134#define GPMC_CONFIG_DEV_SIZE 0x00000002
135#define GPMC_CONFIG_DEV_TYPE 0x00000003
e639cd5b
TL		 136
137#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
138#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
139#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
140#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
141#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
142#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
143#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
98397f1c 144#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
4b613e9b
RA		 145/** CLKACTIVATIONTIME Max Ticks */
146#define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
98397f1c 147#define GPMC_CONFIG1_PAGE_LEN(val) (((val) & 3) << 23)
4b613e9b
RA		 148/** ATTACHEDDEVICEPAGELENGTH Max Value */
149#define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
e639cd5b
TL		 150#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
151#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
98397f1c 152#define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
2e676901
RA		 153/** WAITMONITORINGTIME Max Ticks */
154#define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
98397f1c
KK		 155#define GPMC_CONFIG1_WAIT_PIN_SEL(val) (((val) & 3) << 16)
156#define GPMC_CONFIG1_DEVICESIZE(val) (((val) & 3) << 12)
e639cd5b 157#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
4b613e9b
RA		 158/** DEVICESIZE Max Value */
159#define GPMC_CONFIG1_DEVICESIZE_MAX 1
98397f1c 160#define GPMC_CONFIG1_DEVICETYPE(val) (((val) & 3) << 10)
e639cd5b 161#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
98397f1c 162#define GPMC_CONFIG1_MUXTYPE(val) (((val) & 3) << 8)
e639cd5b 163#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
98397f1c 164#define GPMC_CONFIG1_FCLK_DIV(val) ((val) & 3)
e639cd5b
TL		 165#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
166#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
167#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
168#define GPMC_CONFIG7_CSVALID (1 << 6)
169
9c4f757e
SP		 170#define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
171#define GPMC_CONFIG7_CSVALID_MASK BIT(6)
172#define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
173#define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
174/* All CONFIG7 bits except reserved bits */
175#define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
176 GPMC_CONFIG7_CSVALID_MASK | \
177 GPMC_CONFIG7_MASKADDRESS_MASK)
178
e639cd5b
TL		 179#define GPMC_DEVICETYPE_NOR 0
180#define GPMC_DEVICETYPE_NAND 2
181#define GPMC_CONFIG_WRITEPROTECT 0x00000010
182#define WR_RD_PIN_MONITORING 0x00600000
183
e639cd5b
TL		 184/* ECC commands */
185#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
186#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
187#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
188
b2bac25a 189#define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */
6b6c32fc 190
7f2e8c58
RA		 191enum gpmc_clk_domain {
192 GPMC_CD_FCLK,
193 GPMC_CD_CLK
194};
195
9ed7a776
TL		 196struct gpmc_cs_data {
197 const char *name;
198
199#define GPMC_CS_RESERVED (1 << 0)
200 u32 flags;
201
202 struct resource mem;
203};
204
a2d3e7ba
RN		 205/* Structure to save gpmc cs context */
206struct gpmc_cs_config {
207 u32 config1;
208 u32 config2;
209 u32 config3;
210 u32 config4;
211 u32 config5;
212 u32 config6;
213 u32 config7;
214 int is_valid;
215};
216
217/*
218 * Structure to save/restore gpmc context
219 * to support core off on OMAP3
220 */
221struct omap3_gpmc_regs {
222 u32 sysconfig;
223 u32 irqenable;
224 u32 timeout_ctrl;
225 u32 config;
226 u32 prefetch_config1;
227 u32 prefetch_config2;
228 u32 prefetch_control;
229 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
230};
231
384258f2
RQ		 232struct gpmc_device {
233 struct device *dev;
234 int irq;
235 struct irq_chip irq_chip;
d2d00862 236 struct gpio_chip gpio_chip;
b2bac25a 237 int nirqs;
384258f2
RQ		 238};
239
240static struct irq_domain *gpmc_irq_domain;
6b6c32fc 241
f37e4580 242static struct resource gpmc_mem_root;
9ed7a776 243static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
87b247c4 244static DEFINE_SPINLOCK(gpmc_mem_lock);
6797b4fe 245/* Define chip-selects as reserved by default until probe completes */
f34f3716 246static unsigned int gpmc_cs_num = GPMC_CS_NUM;
9f833156 247static unsigned int gpmc_nr_waitpins;
da496873 248static resource_size_t phys_base, mem_size;
1cd53458 249static unsigned int gpmc_capability;
fd1dc87d 250static void __iomem *gpmc_base;
4bbbc1ad 251
fd1dc87d 252static struct clk *gpmc_l3_clk;
4bbbc1ad 253
db97eb7d
SG		 254static irqreturn_t gpmc_handle_irq(int irq, void *dev);
255
4bbbc1ad
JY		 256static void gpmc_write_reg(int idx, u32 val)
257{
edfaf05c 258 writel_relaxed(val, gpmc_base + idx);
4bbbc1ad
JY		 259}
260
261static u32 gpmc_read_reg(int idx)
262{
edfaf05c 263 return readl_relaxed(gpmc_base + idx);
4bbbc1ad
JY		 264}
265
266void gpmc_cs_write_reg(int cs, int idx, u32 val)
267{
268 void __iomem *reg_addr;
269
948d38e7 270 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
edfaf05c 271 writel_relaxed(val, reg_addr);
4bbbc1ad
JY		 272}
273
3fc089e7 274static u32 gpmc_cs_read_reg(int cs, int idx)
4bbbc1ad 275{
fd1dc87d
PW		 276 void __iomem *reg_addr;
277
948d38e7 278 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
edfaf05c 279 return readl_relaxed(reg_addr);
4bbbc1ad
JY		 280}
281
fd1dc87d 282/* TODO: Add support for gpmc_fck to clock framework and use it */
3fc089e7 283static unsigned long gpmc_get_fclk_period(void)
4bbbc1ad 284{
fd1dc87d
PW		 285 unsigned long rate = clk_get_rate(gpmc_l3_clk);
286
fd1dc87d
PW		 287 rate /= 1000;
288 rate = 1000000000 / rate; /* In picoseconds */
289
290 return rate;
4bbbc1ad
JY		 291}
292
7f2e8c58
RA		 293/**
294 * gpmc_get_clk_period - get period of selected clock domain in ps
80c4f5a8
KK		 295 * @cs: Chip Select Region.
296 * @cd: Clock Domain.
7f2e8c58
RA		 297 *
298 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
299 * prior to calling this function with GPMC_CD_CLK.
300 */
301static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
302{
7f2e8c58
RA		 303 unsigned long tick_ps = gpmc_get_fclk_period();
304 u32 l;
305 int div;
306
307 switch (cd) {
308 case GPMC_CD_CLK:
309 /* get current clk divider */
310 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
311 div = (l & 0x03) + 1;
312 /* get GPMC_CLK period */
313 tick_ps *= div;
314 break;
315 case GPMC_CD_FCLK:
316 /* FALL-THROUGH */
317 default:
318 break;
319 }
320
321 return tick_ps;
7f2e8c58
RA		 322}
323
324static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
325 enum gpmc_clk_domain cd)
4bbbc1ad
JY		 326{
327 unsigned long tick_ps;
328
329 /* Calculate in picosecs to yield more exact results */
7f2e8c58 330 tick_ps = gpmc_get_clk_period(cs, cd);
4bbbc1ad
JY		 331
332 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
333}
334
7f2e8c58
RA		 335static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
336{
337 return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
338}
339
3fc089e7 340static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
a3551f5b
AH		 341{
342 unsigned long tick_ps;
343
344 /* Calculate in picosecs to yield more exact results */
345 tick_ps = gpmc_get_fclk_period();
346
347 return (time_ps + tick_ps - 1) / tick_ps;
348}
349
3950fffd
BX		 350static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
351 enum gpmc_clk_domain cd)
7f2e8c58
RA		 352{
353 return ticks * gpmc_get_clk_period(cs, cd) / 1000;
354}
355
fd1dc87d
PW		 356unsigned int gpmc_ticks_to_ns(unsigned int ticks)
357{
7f2e8c58 358 return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
fd1dc87d
PW		 359}
360
246da26d
AM		 361static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
362{
363 return ticks * gpmc_get_fclk_period();
364}
365
366static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
367{
368 unsigned long ticks = gpmc_ps_to_ticks(time_ps);
369
370 return ticks * gpmc_get_fclk_period();
371}
372
559d94b0
AM		 373static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
374{
375 u32 l;
376
377 l = gpmc_cs_read_reg(cs, reg);
378 if (value)
379 l |= mask;
380 else
381 l &= ~mask;
382 gpmc_cs_write_reg(cs, reg, l);
383}
384
385static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
386{
387 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
388 GPMC_CONFIG1_TIME_PARA_GRAN,
389 p->time_para_granularity);
390 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
391 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
392 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
393 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
394 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
395 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
396 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
8f50b8e5 397 GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
559d94b0
AM		 398 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
399 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
400 p->cycle2cyclesamecsen);
401 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
402 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
403 p->cycle2cyclediffcsen);
404}
405
63aa945b 406#ifdef CONFIG_OMAP_GPMC_DEBUG
563dbb26
RA		 407/**
408 * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
409 * @cs: Chip Select Region
410 * @reg: GPMC_CS_CONFIGn register offset.
411 * @st_bit: Start Bit
412 * @end_bit: End Bit. Must be >= @st_bit.
80c4f5a8 413 * @max: Maximum parameter value (before optional @shift).
4b613e9b 414 * If 0, maximum is as high as @st_bit and @end_bit allow.
563dbb26 415 * @name: DTS node name, w/o "gpmc,"
7f2e8c58
RA		 416 * @cd: Clock Domain of timing parameter.
417 * @shift: Parameter value left shifts @shift, which is then printed instead of value.
563dbb26
RA		 418 * @raw: Raw Format Option.
419 * raw format: gpmc,name = <value>
420 * tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
421 * Where x ns -- y ns result in the same tick value.
4b613e9b 422 * When @max is exceeded, "invalid" is printed inside comment.
563dbb26 423 * @noval: Parameter values equal to 0 are not printed.
563dbb26
RA		 424 * @return: Specified timing parameter (after optional @shift).
425 *
426 */
7f2e8c58
RA		 427static int get_gpmc_timing_reg(
428 /* timing specifiers */
4b613e9b 429 int cs, int reg, int st_bit, int end_bit, int max,
7f2e8c58
RA		 430 const char *name, const enum gpmc_clk_domain cd,
431 /* value transform */
432 int shift,
433 /* format specifiers */
434 bool raw, bool noval)
35ac051e
TL		 435{
436 u32 l;
563dbb26
RA		 437 int nr_bits;
438 int mask;
4b613e9b 439 bool invalid;
35ac051e
TL		 440
441 l = gpmc_cs_read_reg(cs, reg);
442 nr_bits = end_bit - st_bit + 1;
563dbb26
RA		 443 mask = (1 << nr_bits) - 1;
444 l = (l >> st_bit) & mask;
4b613e9b
RA		 445 if (!max)
446 max = mask;
447 invalid = l > max;
35ac051e
TL		 448 if (shift)
449 l = (shift << l);
450 if (noval && (l == 0))
451 return 0;
452 if (!raw) {
563dbb26
RA		 453 /* DTS tick format for timings in ns */
454 unsigned int time_ns;
455 unsigned int time_ns_min = 0;
35ac051e 456
563dbb26 457 if (l)
7f2e8c58
RA		 458 time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
459 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
95c278b2 460 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
4b613e9b
RA		 461 name, time_ns, time_ns_min, time_ns, l,
462 invalid ? "; invalid " : " ");
35ac051e 463 } else {
563dbb26 464 /* raw format */
95c278b2 465 pr_info("gpmc,%s = <%u>;%s\n", name, l,
4b613e9b 466 invalid ? " /* invalid */" : "");
35ac051e
TL		 467 }
468
469 return l;
470}
471
472#define GPMC_PRINT_CONFIG(cs, config) \
473 pr_info("cs%i %s: 0x%08x\n", cs, #config, \
474 gpmc_cs_read_reg(cs, config))
475#define GPMC_GET_RAW(reg, st, end, field) \
4b613e9b
RA		 476 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
477#define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
478 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
35ac051e 479#define GPMC_GET_RAW_BOOL(reg, st, end, field) \
4b613e9b
RA		 480 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
481#define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
482 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
35ac051e 483#define GPMC_GET_TICKS(reg, st, end, field) \
4b613e9b 484 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
7f2e8c58 485#define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
4b613e9b
RA		 486 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
487#define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
488 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
35ac051e
TL		 489
490static void gpmc_show_regs(int cs, const char *desc)
491{
492 pr_info("gpmc cs%i %s:\n", cs, desc);
493 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
494 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
495 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
496 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
497 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
498 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
499}
500
501/*
502 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
503 * see commit c9fb809.
504 */
505static void gpmc_cs_show_timings(int cs, const char *desc)
506{
507 gpmc_show_regs(cs, desc);
508
509 pr_info("gpmc cs%i access configuration:\n", cs);
510 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
511 GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
aff523fb 512 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
cdd1aeae 513 GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
35ac051e
TL		 514 GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
515 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
516 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
4b613e9b
RA		 517 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
518 GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
519 "burst-length");
35ac051e
TL		 520 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
521 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
522 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
523 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
524 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
525
526 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay");
527
528 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay");
529
530 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
531 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay");
532
533 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen");
534 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen");
535
536 pr_info("gpmc cs%i timings configuration:\n", cs);
537 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns");
538 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns");
539 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
540
541 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns");
542 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns");
543 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
2c92c04b
NA		 544 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
545 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
546 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
547 "adv-aad-mux-rd-off-ns");
548 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
549 "adv-aad-mux-wr-off-ns");
550 }
35ac051e
TL		 551
552 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns");
553 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns");
2c92c04b
NA		 554 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
555 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns");
556 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
557 }
35ac051e
TL		 558 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
559 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
560
561 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns");
562 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns");
563 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
564
565 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
566
567 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
568 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
569
4b613e9b
RA		 570 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
571 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
572 "wait-monitoring-ns", GPMC_CD_CLK);
573 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
574 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
575 "clk-activation-ns", GPMC_CD_FCLK);
35ac051e
TL		 576
577 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
578 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
579}
4bbbc1ad 580#else
35ac051e
TL		 581static inline void gpmc_cs_show_timings(int cs, const char *desc)
582{
583}
4bbbc1ad 584#endif
35ac051e 585
7f2e8c58
RA		 586/**
587 * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
588 * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
589 * prior to calling this function with @cd equal to GPMC_CD_CLK.
590 *
591 * @cs: Chip Select Region.
592 * @reg: GPMC_CS_CONFIGn register offset.
593 * @st_bit: Start Bit
594 * @end_bit: End Bit. Must be >= @st_bit.
4b613e9b
RA		 595 * @max: Maximum parameter value.
596 * If 0, maximum is as high as @st_bit and @end_bit allow.
7f2e8c58
RA		 597 * @time: Timing parameter in ns.
598 * @cd: Timing parameter clock domain.
599 * @name: Timing parameter name.
600 * @return: 0 on success, -1 on error.
601 */
4b613e9b 602static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
7f2e8c58 603 int time, enum gpmc_clk_domain cd, const char *name)
4bbbc1ad
JY		 604{
605 u32 l;
606 int ticks, mask, nr_bits;
607
608 if (time == 0)
609 ticks = 0;
610 else
7f2e8c58 611 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
4bbbc1ad 612 nr_bits = end_bit - st_bit + 1;
80323742
RQ		 613 mask = (1 << nr_bits) - 1;
614
4b613e9b
RA		 615 if (!max)
616 max = mask;
617
618 if (ticks > max) {
7f2e8c58 619 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
4b613e9b 620 __func__, cs, name, time, ticks, max);
80323742 621
4bbbc1ad 622 return -1;
1c22cc13 623 }
4bbbc1ad 624
4bbbc1ad 625 l = gpmc_cs_read_reg(cs, reg);
63aa945b 626#ifdef CONFIG_OMAP_GPMC_DEBUG
cdd1aeae
KK		 627 pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
628 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
1c22cc13 629 (l >> st_bit) & mask, time);
4bbbc1ad
JY		 630#endif
631 l &= ~(mask << st_bit);
632 l |= ticks << st_bit;
633 gpmc_cs_write_reg(cs, reg, l);
634
635 return 0;
636}
637
4b613e9b
RA		 638#define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd) \
639 if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
640 t->field, (cd), #field) < 0) \
4bbbc1ad 641 return -1
4bbbc1ad 642
7f2e8c58 643#define GPMC_SET_ONE(reg, st, end, field) \
4b613e9b 644 GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
7f2e8c58 645
2e676901
RA		 646/**
647 * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
648 * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
649 * read --> don't sample bus too early
650 * write --> data is longer on bus
651 *
652 * Formula:
653 * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
654 * / waitmonitoring_ticks)
655 * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
656 * div <= 0 check.
657 *
658 * @wait_monitoring: WAITMONITORINGTIME in ns.
659 * @return: -1 on failure to scale, else proper divider > 0.
660 */
661static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
662{
2e676901
RA		 663 int div = gpmc_ns_to_ticks(wait_monitoring);
664
665 div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
666 div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
667
668 if (div > 4)
669 return -1;
670 if (div <= 0)
671 div = 1;
672
673 return div;
2e676901
RA		 674}
675
676/**
677 * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
678 * @sync_clk: GPMC_CLK period in ps.
679 * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
680 * Else, returns -1.
681 */
1b47ca1a 682int gpmc_calc_divider(unsigned int sync_clk)
4bbbc1ad 683{
2e676901 684 int div = gpmc_ps_to_ticks(sync_clk);
4bbbc1ad 685
4bbbc1ad
JY		 686 if (div > 4)
687 return -1;
1c22cc13 688 if (div <= 0)
4bbbc1ad
JY		 689 div = 1;
690
691 return div;
692}
693
2e676901
RA		 694/**
695 * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
696 * @cs: Chip Select Region.
697 * @t: GPMC timing parameters.
698 * @s: GPMC timing settings.
699 * @return: 0 on success, -1 on error.
700 */
701int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
702 const struct gpmc_settings *s)
4bbbc1ad
JY		 703{
704 int div;
705 u32 l;
706
1b47ca1a 707 div = gpmc_calc_divider(t->sync_clk);
4bbbc1ad 708 if (div < 0)
a032d33b 709 return div;
4bbbc1ad 710
2e676901
RA		 711 /*
712 * See if we need to change the divider for waitmonitoringtime.
713 *
714 * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
715 * pure asynchronous accesses, i.e. both read and write asynchronous.
716 * However, only do so if WAITMONITORINGTIME is actually used, i.e.
717 * either WAITREADMONITORING or WAITWRITEMONITORING is set.
718 *
719 * This statement must not change div to scale async WAITMONITORINGTIME
720 * to protect mixed synchronous and asynchronous accesses.
721 *
722 * We raise an error later if WAITMONITORINGTIME does not fit.
723 */
724 if (!s->sync_read && !s->sync_write &&
725 (s->wait_on_read || s->wait_on_write)
726 ) {
2e676901
RA		 727 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
728 if (div < 0) {
729 pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
730 __func__,
731 t->wait_monitoring
732 );
733 return -1;
734 }
735 }
736
4bbbc1ad
JY		 737 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
738 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
739 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
740
741 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
742 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
743 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
2c92c04b
NA		 744 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
745 GPMC_SET_ONE(GPMC_CS_CONFIG3, 4, 6, adv_aad_mux_on);
746 GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off);
747 GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off);
748 }
4bbbc1ad
JY		 749
750 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
751 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
2c92c04b
NA		 752 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
753 GPMC_SET_ONE(GPMC_CS_CONFIG4, 4, 6, oe_aad_mux_on);
754 GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off);
755 }
4bbbc1ad
JY		 756 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
757 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
758
759 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
760 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
761 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
762
763 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
764
559d94b0
AM		 765 GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
766 GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
767
da496873 768 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
cc26b3b0 769 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
da496873 770 if (gpmc_capability & GPMC_HAS_WR_ACCESS)
cc26b3b0 771 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
cc26b3b0 772
1c22cc13 773 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
7f2e8c58
RA		 774 l &= ~0x03;
775 l |= (div - 1);
776 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
777
4b613e9b
RA		 778 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
779 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
780 wait_monitoring, GPMC_CD_CLK);
781 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
782 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
783 clk_activation, GPMC_CD_FCLK);
7f2e8c58 784
63aa945b 785#ifdef CONFIG_OMAP_GPMC_DEBUG
f585070b
RA		 786 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
787 cs, (div * gpmc_get_fclk_period()) / 1000, div);
4bbbc1ad 788#endif
4bbbc1ad 789
559d94b0 790 gpmc_cs_bool_timings(cs, &t->bool_timings);
35ac051e 791 gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
559d94b0 792
4bbbc1ad
JY		 793 return 0;
794}
795
4cf27d2e 796static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
f37e4580
ID		 797{
798 u32 l;
799 u32 mask;
800
c71f8e9b
JH		 801 /*
802 * Ensure that base address is aligned on a
803 * boundary equal to or greater than size.
804 */
805 if (base & (size - 1))
806 return -EINVAL;
807
9c4f757e 808 base >>= GPMC_CHUNK_SHIFT;
f37e4580 809 mask = (1 << GPMC_SECTION_SHIFT) - size;
9c4f757e
SP		 810 mask >>= GPMC_CHUNK_SHIFT;
811 mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
812
f37e4580 813 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
9c4f757e
SP		 814 l &= ~GPMC_CONFIG7_MASK;
815 l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
816 l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
a2d3e7ba 817 l |= GPMC_CONFIG7_CSVALID;
f37e4580 818 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
c71f8e9b
JH		 819
820 return 0;
f37e4580
ID		 821}
822
4cf27d2e
RQ		 823static void gpmc_cs_enable_mem(int cs)
824{
825 u32 l;
826
827 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
828 l |= GPMC_CONFIG7_CSVALID;
829 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
830}
831
f37e4580
ID		 832static void gpmc_cs_disable_mem(int cs)
833{
834 u32 l;
835
836 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
a2d3e7ba 837 l &= ~GPMC_CONFIG7_CSVALID;
f37e4580
ID		 838 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
839}
840
841static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
842{
843 u32 l;
844 u32 mask;
845
846 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
847 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
848 mask = (l >> 8) & 0x0f;
849 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
850}
851
852static int gpmc_cs_mem_enabled(int cs)
853{
854 u32 l;
855
856 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
a2d3e7ba 857 return l & GPMC_CONFIG7_CSVALID;
f37e4580
ID		 858}
859
f5d8edaf 860static void gpmc_cs_set_reserved(int cs, int reserved)
4bbbc1ad 861{
9ed7a776
TL		 862 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
863
864 gpmc->flags |= GPMC_CS_RESERVED;
f37e4580
ID		 865}
866
ae9d908a 867static bool gpmc_cs_reserved(int cs)
f37e4580 868{
9ed7a776
TL		 869 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
870
871 return gpmc->flags & GPMC_CS_RESERVED;
872}
873
874static void gpmc_cs_set_name(int cs, const char *name)
875{
876 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
877
878 gpmc->name = name;
879}
880
2e25b0ec 881static const char *gpmc_cs_get_name(int cs)
9ed7a776
TL		 882{
883 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
884
885 return gpmc->name;
f37e4580
ID		 886}
887
888static unsigned long gpmc_mem_align(unsigned long size)
889{
890 int order;
891
892 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
893 order = GPMC_CHUNK_SHIFT - 1;
894 do {
895 size >>= 1;
896 order++;
897 } while (size);
898 size = 1 << order;
899 return size;
900}
901
902static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
903{
9ed7a776
TL		 904 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
905 struct resource *res = &gpmc->mem;
f37e4580
ID		 906 int r;
907
908 size = gpmc_mem_align(size);
909 spin_lock(&gpmc_mem_lock);
910 res->start = base;
911 res->end = base + size - 1;
912 r = request_resource(&gpmc_mem_root, res);
913 spin_unlock(&gpmc_mem_lock);
914
915 return r;
916}
917
da496873
AM		 918static int gpmc_cs_delete_mem(int cs)
919{
9ed7a776
TL		 920 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
921 struct resource *res = &gpmc->mem;
da496873
AM		 922 int r;
923
924 spin_lock(&gpmc_mem_lock);
efe80723 925 r = release_resource(res);
da496873
AM		 926 res->start = 0;
927 res->end = 0;
928 spin_unlock(&gpmc_mem_lock);
929
930 return r;
931}
932
cdd6928c
JH		 933/**
934 * gpmc_cs_remap - remaps a chip-select physical base address
935 * @cs: chip-select to remap
936 * @base: physical base address to re-map chip-select to
937 *
938 * Re-maps a chip-select to a new physical base address specified by
939 * "base". Returns 0 on success and appropriate negative error code
940 * on failure.
941 */
942static int gpmc_cs_remap(int cs, u32 base)
943{
944 int ret;
945 u32 old_base, size;
946
f34f3716
GP		 947 if (cs > gpmc_cs_num) {
948 pr_err("%s: requested chip-select is disabled\n", __func__);
cdd6928c 949 return -ENODEV;
f34f3716 950 }
fb677ef7
TL		 951
952 /*
953 * Make sure we ignore any device offsets from the GPMC partition
954 * allocated for the chip select and that the new base confirms
955 * to the GPMC 16MB minimum granularity.
1a1e7580 956 */
fb677ef7
TL		 957 base &= ~(SZ_16M - 1);
958
cdd6928c
JH		 959 gpmc_cs_get_memconf(cs, &old_base, &size);
960 if (base == old_base)
961 return 0;
4cf27d2e 962
cdd6928c
JH		 963 ret = gpmc_cs_delete_mem(cs);
964 if (ret < 0)
965 return ret;
4cf27d2e 966
cdd6928c 967 ret = gpmc_cs_insert_mem(cs, base, size);
c71f8e9b
JH		 968 if (ret < 0)
969 return ret;
cdd6928c 970
4cf27d2e
RQ		 971 ret = gpmc_cs_set_memconf(cs, base, size);
972
973 return ret;
cdd6928c
JH		 974}
975
f37e4580
ID		 976int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
977{
9ed7a776
TL		 978 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
979 struct resource *res = &gpmc->mem;
f37e4580
ID		 980 int r = -1;
981
f34f3716
GP		 982 if (cs > gpmc_cs_num) {
983 pr_err("%s: requested chip-select is disabled\n", __func__);
f37e4580 984 return -ENODEV;
f34f3716 985 }
f37e4580
ID		 986 size = gpmc_mem_align(size);
987 if (size > (1 << GPMC_SECTION_SHIFT))
988 return -ENOMEM;
989
990 spin_lock(&gpmc_mem_lock);
991 if (gpmc_cs_reserved(cs)) {
992 r = -EBUSY;
993 goto out;
994 }
995 if (gpmc_cs_mem_enabled(cs))
996 r = adjust_resource(res, res->start & ~(size - 1), size);
997 if (r < 0)
998 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
999 size, NULL, NULL);
1000 if (r < 0)
1001 goto out;
1002
4cf27d2e
RQ		 1003 /* Disable CS while changing base address and size mask */
1004 gpmc_cs_disable_mem(cs);
1005
1006 r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
c71f8e9b
JH		 1007 if (r < 0) {
1008 release_resource(res);
1009 goto out;
1010 }
1011
4cf27d2e
RQ		 1012 /* Enable CS */
1013 gpmc_cs_enable_mem(cs);
f37e4580
ID		 1014 *base = res->start;
1015 gpmc_cs_set_reserved(cs, 1);
1016out:
1017 spin_unlock(&gpmc_mem_lock);
1018 return r;
1019}
fd1dc87d 1020EXPORT_SYMBOL(gpmc_cs_request);
f37e4580
ID		 1021
1022void gpmc_cs_free(int cs)
1023{
9ed7a776
TL		 1024 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1025 struct resource *res = &gpmc->mem;
efe80723 1026
f37e4580 1027 spin_lock(&gpmc_mem_lock);
f34f3716 1028 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
f37e4580
ID		 1029 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1030 BUG();
1031 spin_unlock(&gpmc_mem_lock);
1032 return;
1033 }
1034 gpmc_cs_disable_mem(cs);
efe80723
TL		 1035 if (res->flags)
1036 release_resource(res);
f37e4580
ID		 1037 gpmc_cs_set_reserved(cs, 0);
1038 spin_unlock(&gpmc_mem_lock);
1039}
fd1dc87d 1040EXPORT_SYMBOL(gpmc_cs_free);
f37e4580 1041
948d38e7 1042/**
3a544354 1043 * gpmc_configure - write request to configure gpmc
948d38e7
SG		 1044 * @cmd: command type
1045 * @wval: value to write
1046 * @return status of the operation
1047 */
3a544354 1048int gpmc_configure(int cmd, int wval)
948d38e7 1049{
3a544354 1050 u32 regval;
948d38e7
SG		 1051
1052 switch (cmd) {
948d38e7
SG		 1053 case GPMC_CONFIG_WP:
1054 regval = gpmc_read_reg(GPMC_CONFIG);
1055 if (wval)
1056 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1057 else
1058 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
1059 gpmc_write_reg(GPMC_CONFIG, regval);
1060 break;
1061
948d38e7 1062 default:
3a544354
JH		 1063 pr_err("%s: command not supported\n", __func__);
1064 return -EINVAL;
948d38e7
SG		 1065 }
1066
3a544354 1067 return 0;
948d38e7 1068}
3a544354 1069EXPORT_SYMBOL(gpmc_configure);
948d38e7 1070
a622c641
LM		 1071static bool gpmc_nand_writebuffer_empty(void)
1072{
1073 if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1074 return true;
1075
1076 return false;
1077}
1078
1079static struct gpmc_nand_ops nand_ops = {
1080 .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1081};
1082
1083/**
1084 * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
80c4f5a8 1085 * @reg: the GPMC NAND register map exclusive for NAND use.
a622c641
LM		 1086 * @cs: GPMC chip select number on which the NAND sits. The
1087 * register map returned will be specific to this chip select.
1088 *
1089 * Returns NULL on error e.g. invalid cs.
1090 */
1091struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
52bd138d 1092{
2fdf0c98
AM		 1093 int i;
1094
a622c641
LM		 1095 if (cs >= gpmc_cs_num)
1096 return NULL;
1097
52bd138d
AM		 1098 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1099 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1100 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1101 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1102 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1103 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1104 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1105 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1106 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1107 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1108 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1109 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1110 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1111 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
2fdf0c98
AM		 1112
1113 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1114 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1115 GPMC_BCH_SIZE * i;
1116 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1117 GPMC_BCH_SIZE * i;
1118 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1119 GPMC_BCH_SIZE * i;
1120 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1121 GPMC_BCH_SIZE * i;
27c9fd60 1122 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1123 i * GPMC_BCH_SIZE;
1124 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1125 i * GPMC_BCH_SIZE;
1126 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1127 i * GPMC_BCH_SIZE;
2fdf0c98 1128 }
f47fcad6
RQ		 1129
1130 return &nand_ops;
1131}
1132EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1133
a758f50f
LM		 1134static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
1135 struct gpmc_settings *s,
1136 int freq, int latency)
1137{
1138 struct gpmc_device_timings dev_t;
1139 const int t_cer = 15;
1140 const int t_avdp = 12;
1141 const int t_cez = 20; /* max of t_cez, t_oez */
1142 const int t_wpl = 40;
1143 const int t_wph = 30;
1144 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
1145
1146 switch (freq) {
1147 case 104:
1148 min_gpmc_clk_period = 9600; /* 104 MHz */
1149 t_ces = 3;
1150 t_avds = 4;
1151 t_avdh = 2;
1152 t_ach = 3;
1153 t_aavdh = 6;
1154 t_rdyo = 6;
1155 break;
1156 case 83:
1157 min_gpmc_clk_period = 12000; /* 83 MHz */
1158 t_ces = 5;
1159 t_avds = 4;
1160 t_avdh = 2;
1161 t_ach = 6;
1162 t_aavdh = 6;
1163 t_rdyo = 9;
1164 break;
1165 case 66:
1166 min_gpmc_clk_period = 15000; /* 66 MHz */
1167 t_ces = 6;
1168 t_avds = 5;
1169 t_avdh = 2;
1170 t_ach = 6;
1171 t_aavdh = 6;
1172 t_rdyo = 11;
1173 break;
1174 default:
1175 min_gpmc_clk_period = 18500; /* 54 MHz */
1176 t_ces = 7;
1177 t_avds = 7;
1178 t_avdh = 7;
1179 t_ach = 9;
1180 t_aavdh = 7;
1181 t_rdyo = 15;
1182 break;
1183 }
1184
1185 /* Set synchronous read timings */
1186 memset(&dev_t, 0, sizeof(dev_t));
1187
1188 if (!s->sync_write) {
1189 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
1190 dev_t.t_wpl = t_wpl * 1000;
1191 dev_t.t_wph = t_wph * 1000;
1192 dev_t.t_aavdh = t_aavdh * 1000;
1193 }
1194 dev_t.ce_xdelay = true;
1195 dev_t.avd_xdelay = true;
1196 dev_t.oe_xdelay = true;
1197 dev_t.we_xdelay = true;
1198 dev_t.clk = min_gpmc_clk_period;
1199 dev_t.t_bacc = dev_t.clk;
1200 dev_t.t_ces = t_ces * 1000;
1201 dev_t.t_avds = t_avds * 1000;
1202 dev_t.t_avdh = t_avdh * 1000;
1203 dev_t.t_ach = t_ach * 1000;
1204 dev_t.cyc_iaa = (latency + 1);
1205 dev_t.t_cez_r = t_cez * 1000;
1206 dev_t.t_cez_w = dev_t.t_cez_r;
1207 dev_t.cyc_aavdh_oe = 1;
1208 dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
1209
1210 gpmc_calc_timings(t, s, &dev_t);
1211}
1212
1213int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
1214 int latency,
1215 struct gpmc_onenand_info *info)
1216{
1217 int ret;
1218 struct gpmc_timings gpmc_t;
1219 struct gpmc_settings gpmc_s;
1220
1221 gpmc_read_settings_dt(dev->of_node, &gpmc_s);
1222
1223 info->sync_read = gpmc_s.sync_read;
1224 info->sync_write = gpmc_s.sync_write;
1225 info->burst_len = gpmc_s.burst_len;
1226
1227 if (!gpmc_s.sync_read && !gpmc_s.sync_write)
1228 return 0;
1229
1230 gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
1231
1232 ret = gpmc_cs_program_settings(cs, &gpmc_s);
1233 if (ret < 0)
1234 return ret;
1235
1236 return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1237}
1238EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
1239
1cd53458 1240int gpmc_get_client_irq(unsigned int irq_config)
6b6c32fc 1241{
384258f2
RQ		 1242 if (!gpmc_irq_domain) {
1243 pr_warn("%s called before GPMC IRQ domain available\n",
1244 __func__);
6b6c32fc 1245 return 0;
384258f2 1246 }
6b6c32fc 1247
b2bac25a
RQ		 1248 /* we restrict this to NAND IRQs only */
1249 if (irq_config >= GPMC_NR_NAND_IRQS)
384258f2 1250 return 0;
6b6c32fc 1251
384258f2 1252 return irq_create_mapping(gpmc_irq_domain, irq_config);
6b6c32fc
AM		 1253}
1254
384258f2 1255static int gpmc_irq_endis(unsigned long hwirq, bool endis)
6b6c32fc 1256{
6b6c32fc
AM		 1257 u32 regval;
1258
b2bac25a
RQ		 1259 /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
1260 if (hwirq >= GPMC_NR_NAND_IRQS)
1261 hwirq += 8 - GPMC_NR_NAND_IRQS;
1262
384258f2
RQ		 1263 regval = gpmc_read_reg(GPMC_IRQENABLE);
1264 if (endis)
1265 regval |= BIT(hwirq);
1266 else
1267 regval &= ~BIT(hwirq);
1268 gpmc_write_reg(GPMC_IRQENABLE, regval);
6b6c32fc
AM		 1269
1270 return 0;
1271}
1272
1273static void gpmc_irq_disable(struct irq_data *p)
1274{
384258f2 1275 gpmc_irq_endis(p->hwirq, false);
6b6c32fc
AM		 1276}
1277
1278static void gpmc_irq_enable(struct irq_data *p)
1279{
384258f2 1280 gpmc_irq_endis(p->hwirq, true);
6b6c32fc
AM		 1281}
1282
b2bac25a
RQ		 1283static void gpmc_irq_mask(struct irq_data *d)
1284{
1285 gpmc_irq_endis(d->hwirq, false);
1286}
1287
1288static void gpmc_irq_unmask(struct irq_data *d)
1289{
1290 gpmc_irq_endis(d->hwirq, true);
1291}
1292
1293static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
1294{
1295 u32 regval;
1296
1297 /* NAND IRQs polarity is not configurable */
1298 if (hwirq < GPMC_NR_NAND_IRQS)
1299 return;
1300
1301 /* WAITPIN starts at BIT 8 */
1302 hwirq += 8 - GPMC_NR_NAND_IRQS;
1303
1304 regval = gpmc_read_reg(GPMC_CONFIG);
1305 if (rising_edge)
1306 regval &= ~BIT(hwirq);
1307 else
1308 regval |= BIT(hwirq);
1309
1310 gpmc_write_reg(GPMC_CONFIG, regval);
1311}
1312
1313static void gpmc_irq_ack(struct irq_data *d)
1314{
1315 unsigned int hwirq = d->hwirq;
1316
1317 /* skip reserved bits */
1318 if (hwirq >= GPMC_NR_NAND_IRQS)
1319 hwirq += 8 - GPMC_NR_NAND_IRQS;
1320
1321 /* Setting bit to 1 clears (or Acks) the interrupt */
1322 gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
1323}
1324
1325static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
1326{
1327 /* can't set type for NAND IRQs */
1328 if (d->hwirq < GPMC_NR_NAND_IRQS)
1329 return -EINVAL;
1330
1331 /* We can support either rising or falling edge at a time */
1332 if (trigger == IRQ_TYPE_EDGE_FALLING)
1333 gpmc_irq_edge_config(d->hwirq, false);
1334 else if (trigger == IRQ_TYPE_EDGE_RISING)
1335 gpmc_irq_edge_config(d->hwirq, true);
1336 else
1337 return -EINVAL;
6b6c32fc 1338
b2bac25a
RQ		 1339 return 0;
1340}
6b6c32fc 1341
384258f2
RQ		 1342static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1343 irq_hw_number_t hw)
6b6c32fc 1344{
384258f2
RQ		 1345 struct gpmc_device *gpmc = d->host_data;
1346
1347 irq_set_chip_data(virq, gpmc);
b2bac25a
RQ		 1348 if (hw < GPMC_NR_NAND_IRQS) {
1349 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1350 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1351 handle_simple_irq);
1352 } else {
1353 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1354 handle_edge_irq);
1355 }
384258f2
RQ		 1356
1357 return 0;
1358}
1359
1360static const struct irq_domain_ops gpmc_irq_domain_ops = {
1361 .map = gpmc_irq_map,
1362 .xlate = irq_domain_xlate_twocell,
1363};
1364
1365static irqreturn_t gpmc_handle_irq(int irq, void *data)
1366{
1367 int hwirq, virq;
b2bac25a 1368 u32 regval, regvalx;
384258f2 1369 struct gpmc_device *gpmc = data;
6b6c32fc 1370
384258f2 1371 regval = gpmc_read_reg(GPMC_IRQSTATUS);
b2bac25a 1372 regvalx = regval;
6b6c32fc 1373
384258f2
RQ		 1374 if (!regval)
1375 return IRQ_NONE;
6b6c32fc 1376
b2bac25a
RQ		 1377 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
1378 /* skip reserved status bits */
1379 if (hwirq == GPMC_NR_NAND_IRQS)
1380 regvalx >>= 8 - GPMC_NR_NAND_IRQS;
1381
1382 if (regvalx & BIT(hwirq)) {
384258f2
RQ		 1383 virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1384 if (!virq) {
1385 dev_warn(gpmc->dev,
1386 "spurious irq detected hwirq %d, virq %d\n",
1387 hwirq, virq);
1388 }
1389
1390 generic_handle_irq(virq);
1391 }
6b6c32fc
AM		 1392 }
1393
384258f2
RQ		 1394 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1395
1396 return IRQ_HANDLED;
1397}
1398
1399static int gpmc_setup_irq(struct gpmc_device *gpmc)
1400{
1401 u32 regval;
1402 int rc;
1403
6b6c32fc
AM		 1404 /* Disable interrupts */
1405 gpmc_write_reg(GPMC_IRQENABLE, 0);
1406
1407 /* clear interrupts */
1408 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1409 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1410
384258f2 1411 gpmc->irq_chip.name = "gpmc";
384258f2
RQ		 1412 gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1413 gpmc->irq_chip.irq_disable = gpmc_irq_disable;
b2bac25a
RQ		 1414 gpmc->irq_chip.irq_ack = gpmc_irq_ack;
1415 gpmc->irq_chip.irq_mask = gpmc_irq_mask;
1416 gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
1417 gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
384258f2
RQ		 1418
1419 gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
b2bac25a 1420 gpmc->nirqs,
384258f2
RQ		 1421 &gpmc_irq_domain_ops,
1422 gpmc);
1423 if (!gpmc_irq_domain) {
1424 dev_err(gpmc->dev, "IRQ domain add failed\n");
1425 return -ENODEV;
1426 }
1427
1428 rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1429 if (rc) {
1430 dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1431 gpmc->irq, rc);
1432 irq_domain_remove(gpmc_irq_domain);
1433 gpmc_irq_domain = NULL;
1434 }
1435
1436 return rc;
6b6c32fc
AM		 1437}
1438
384258f2 1439static int gpmc_free_irq(struct gpmc_device *gpmc)
da496873 1440{
384258f2 1441 int hwirq;
da496873 1442
384258f2 1443 free_irq(gpmc->irq, gpmc);
da496873 1444
b2bac25a 1445 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
384258f2 1446 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
da496873 1447
384258f2
RQ		 1448 irq_domain_remove(gpmc_irq_domain);
1449 gpmc_irq_domain = NULL;
da496873
AM		 1450
1451 return 0;
1452}
1453
351a102d 1454static void gpmc_mem_exit(void)
da496873
AM		 1455{
1456 int cs;
1457
f34f3716 1458 for (cs = 0; cs < gpmc_cs_num; cs++) {
da496873
AM		 1459 if (!gpmc_cs_mem_enabled(cs))
1460 continue;
1461 gpmc_cs_delete_mem(cs);
1462 }
da496873
AM		 1463}
1464
84b00f0e 1465static void gpmc_mem_init(void)
f37e4580 1466{
84b00f0e 1467 int cs;
f37e4580 1468
bdd7e033 1469 gpmc_mem_root.start = GPMC_MEM_START;
f37e4580
ID		 1470 gpmc_mem_root.end = GPMC_MEM_END;
1471
1472 /* Reserve all regions that has been set up by bootloader */
f34f3716 1473 for (cs = 0; cs < gpmc_cs_num; cs++) {
f37e4580
ID		 1474 u32 base, size;
1475
1476 if (!gpmc_cs_mem_enabled(cs))
1477 continue;
1478 gpmc_cs_get_memconf(cs, &base, &size);
84b00f0e
JH		 1479 if (gpmc_cs_insert_mem(cs, base, size)) {
1480 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1481 __func__, cs, base, base + size);
1482 gpmc_cs_disable_mem(cs);
8119024e 1483 }
f37e4580 1484 }
4bbbc1ad
JY		 1485}
1486
246da26d
AM		 1487static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1488{
1489 u32 temp;
1490 int div;
1491
1492 div = gpmc_calc_divider(sync_clk);
1493 temp = gpmc_ps_to_ticks(time_ps);
1494 temp = (temp + div - 1) / div;
1495 return gpmc_ticks_to_ps(temp * div);
1496}
1497
1498/* XXX: can the cycles be avoided ? */
1499static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1500 struct gpmc_device_timings *dev_t,
1501 bool mux)
246da26d 1502{
246da26d
AM		 1503 u32 temp;
1504
1505 /* adv_rd_off */
1506 temp = dev_t->t_avdp_r;
1507 /* XXX: mux check required ? */
1508 if (mux) {
1509 /* XXX: t_avdp not to be required for sync, only added for tusb
1510 * this indirectly necessitates requirement of t_avdp_r and
1511 * t_avdp_w instead of having a single t_avdp
1512 */
1513 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1514 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1515 }
1516 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1517
1518 /* oe_on */
1519 temp = dev_t->t_oeasu; /* XXX: remove this ? */
1520 if (mux) {
1521 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1522 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1523 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1524 }
1525 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1526
1527 /* access */
1528 /* XXX: any scope for improvement ?, by combining oe_on
1529 * and clk_activation, need to check whether
1530 * access = clk_activation + round to sync clk ?
1531 */
1532 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1533 temp += gpmc_t->clk_activation;
1534 if (dev_t->cyc_oe)
1535 temp = max_t(u32, temp, gpmc_t->oe_on +
1536 gpmc_ticks_to_ps(dev_t->cyc_oe));
1537 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1538
1539 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1540 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1541
1542 /* rd_cycle */
1543 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1544 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1545 gpmc_t->access;
1546 /* XXX: barter t_ce_rdyz with t_cez_r ? */
1547 if (dev_t->t_ce_rdyz)
1548 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1549 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1550
1551 return 0;
1552}
1553
1554static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1555 struct gpmc_device_timings *dev_t,
1556 bool mux)
246da26d 1557{
246da26d
AM		 1558 u32 temp;
1559
1560 /* adv_wr_off */
1561 temp = dev_t->t_avdp_w;
1562 if (mux) {
1563 temp = max_t(u32, temp,
1564 gpmc_t->clk_activation + dev_t->t_avdh);
1565 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1566 }
1567 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1568
1569 /* wr_data_mux_bus */
1570 temp = max_t(u32, dev_t->t_weasu,
1571 gpmc_t->clk_activation + dev_t->t_rdyo);
1572 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1573 * and in that case remember to handle we_on properly
1574 */
1575 if (mux) {
1576 temp = max_t(u32, temp,
1577 gpmc_t->adv_wr_off + dev_t->t_aavdh);
1578 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1579 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1580 }
1581 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1582
1583 /* we_on */
1584 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1585 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1586 else
1587 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1588
1589 /* wr_access */
1590 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1591 gpmc_t->wr_access = gpmc_t->access;
1592
1593 /* we_off */
1594 temp = gpmc_t->we_on + dev_t->t_wpl;
1595 temp = max_t(u32, temp,
1596 gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1597 temp = max_t(u32, temp,
1598 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1599 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1600
1601 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1602 dev_t->t_wph);
1603
1604 /* wr_cycle */
1605 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1606 temp += gpmc_t->wr_access;
1607 /* XXX: barter t_ce_rdyz with t_cez_w ? */
1608 if (dev_t->t_ce_rdyz)
1609 temp = max_t(u32, temp,
1610 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1611 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1612
1613 return 0;
1614}
1615
1616static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1617 struct gpmc_device_timings *dev_t,
1618 bool mux)
246da26d 1619{
246da26d
AM		 1620 u32 temp;
1621
1622 /* adv_rd_off */
1623 temp = dev_t->t_avdp_r;
1624 if (mux)
1625 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1626 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1627
1628 /* oe_on */
1629 temp = dev_t->t_oeasu;
1630 if (mux)
cdd1aeae 1631 temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh);
246da26d
AM		 1632 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1633
1634 /* access */
1635 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
cdd1aeae
KK		 1636 gpmc_t->oe_on + dev_t->t_oe);
1637 temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce);
1638 temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa);
246da26d
AM		 1639 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1640
1641 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1642 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1643
1644 /* rd_cycle */
1645 temp = max_t(u32, dev_t->t_rd_cycle,
1646 gpmc_t->cs_rd_off + dev_t->t_cez_r);
1647 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1648 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1649
1650 return 0;
1651}
1652
1653static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1654 struct gpmc_device_timings *dev_t,
1655 bool mux)
246da26d 1656{
246da26d
AM		 1657 u32 temp;
1658
1659 /* adv_wr_off */
1660 temp = dev_t->t_avdp_w;
1661 if (mux)
1662 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1663 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1664
1665 /* wr_data_mux_bus */
1666 temp = dev_t->t_weasu;
1667 if (mux) {
1668 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1669 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1670 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1671 }
1672 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1673
1674 /* we_on */
1675 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1676 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1677 else
1678 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1679
1680 /* we_off */
1681 temp = gpmc_t->we_on + dev_t->t_wpl;
1682 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1683
1684 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1685 dev_t->t_wph);
1686
1687 /* wr_cycle */
1688 temp = max_t(u32, dev_t->t_wr_cycle,
1689 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1690 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1691
1692 return 0;
1693}
1694
1695static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1696 struct gpmc_device_timings *dev_t)
1697{
1698 u32 temp;
1699
1700 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1701 gpmc_get_fclk_period();
1702
1703 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1704 dev_t->t_bacc,
1705 gpmc_t->sync_clk);
1706
1707 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1708 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1709
1710 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1711 return 0;
1712
1713 if (dev_t->ce_xdelay)
1714 gpmc_t->bool_timings.cs_extra_delay = true;
1715 if (dev_t->avd_xdelay)
1716 gpmc_t->bool_timings.adv_extra_delay = true;
1717 if (dev_t->oe_xdelay)
1718 gpmc_t->bool_timings.oe_extra_delay = true;
1719 if (dev_t->we_xdelay)
1720 gpmc_t->bool_timings.we_extra_delay = true;
1721
1722 return 0;
1723}
1724
1725static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1726 struct gpmc_device_timings *dev_t,
1727 bool sync)
246da26d
AM		 1728{
1729 u32 temp;
1730
1731 /* cs_on */
1732 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1733
1734 /* adv_on */
1735 temp = dev_t->t_avdasu;
1736 if (dev_t->t_ce_avd)
1737 temp = max_t(u32, temp,
1738 gpmc_t->cs_on + dev_t->t_ce_avd);
1739 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1740
c3be5b45 1741 if (sync)
246da26d
AM		 1742 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1743
1744 return 0;
1745}
1746
1a1e7580
KK		 1747/*
1748 * TODO: remove this function once all peripherals are confirmed to
246da26d
AM		 1749 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1750 * has to be modified to handle timings in ps instead of ns
1a1e7580 1751 */
246da26d
AM		 1752static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1753{
1754 t->cs_on /= 1000;
1755 t->cs_rd_off /= 1000;
1756 t->cs_wr_off /= 1000;
1757 t->adv_on /= 1000;
1758 t->adv_rd_off /= 1000;
1759 t->adv_wr_off /= 1000;
1760 t->we_on /= 1000;
1761 t->we_off /= 1000;
1762 t->oe_on /= 1000;
1763 t->oe_off /= 1000;
1764 t->page_burst_access /= 1000;
1765 t->access /= 1000;
1766 t->rd_cycle /= 1000;
1767 t->wr_cycle /= 1000;
1768 t->bus_turnaround /= 1000;
1769 t->cycle2cycle_delay /= 1000;
1770 t->wait_monitoring /= 1000;
1771 t->clk_activation /= 1000;
1772 t->wr_access /= 1000;
1773 t->wr_data_mux_bus /= 1000;
1774}
1775
1776int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1777 struct gpmc_settings *gpmc_s,
1778 struct gpmc_device_timings *dev_t)
246da26d 1779{
c3be5b45
JH		 1780 bool mux = false, sync = false;
1781
1782 if (gpmc_s) {
1783 mux = gpmc_s->mux_add_data ? true : false;
1784 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1785 }
1786
246da26d
AM		 1787 memset(gpmc_t, 0, sizeof(*gpmc_t));
1788
c3be5b45 1789 gpmc_calc_common_timings(gpmc_t, dev_t, sync);
246da26d 1790
c3be5b45
JH		 1791 if (gpmc_s && gpmc_s->sync_read)
1792 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
246da26d 1793 else
c3be5b45 1794 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
246da26d 1795
c3be5b45
JH		 1796 if (gpmc_s && gpmc_s->sync_write)
1797 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
246da26d 1798 else
c3be5b45 1799 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
246da26d
AM		 1800
1801 /* TODO: remove, see function definition */
1802 gpmc_convert_ps_to_ns(gpmc_t);
1803
1804 return 0;
1805}
1806
aa8d4767
JH		 1807/**
1808 * gpmc_cs_program_settings - programs non-timing related settings
1809 * @cs: GPMC chip-select to program
1810 * @p: pointer to GPMC settings structure
1811 *
1812 * Programs non-timing related settings for a GPMC chip-select, such as
1813 * bus-width, burst configuration, etc. Function should be called once
1814 * for each chip-select that is being used and must be called before
1815 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1816 * register will be initialised to zero by this function. Returns 0 on
1817 * success and appropriate negative error code on failure.
1818 */
1819int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1820{
1821 u32 config1;
1822
1823 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1824 pr_err("%s: invalid width %d!", __func__, p->device_width);
1825 return -EINVAL;
1826 }
1827
1828 /* Address-data multiplexing not supported for NAND devices */
1829 if (p->device_nand && p->mux_add_data) {
1830 pr_err("%s: invalid configuration!\n", __func__);
1831 return -EINVAL;
1832 }
1833
1834 if ((p->mux_add_data > GPMC_MUX_AD) ||
1835 ((p->mux_add_data == GPMC_MUX_AAD) &&
1836 !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1837 pr_err("%s: invalid multiplex configuration!\n", __func__);
1838 return -EINVAL;
1839 }
1840
1841 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1842 if (p->burst_read || p->burst_write) {
1843 switch (p->burst_len) {
1844 case GPMC_BURST_4:
1845 case GPMC_BURST_8:
1846 case GPMC_BURST_16:
1847 break;
1848 default:
1849 pr_err("%s: invalid page/burst-length (%d)\n",
1850 __func__, p->burst_len);
1851 return -EINVAL;
1852 }
1853 }
1854
2b54057c 1855 if (p->wait_pin > gpmc_nr_waitpins) {
aa8d4767
JH		 1856 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1857 return -EINVAL;
1858 }
1859
1860 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1861
1862 if (p->sync_read)
1863 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1864 if (p->sync_write)
1865 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1866 if (p->wait_on_read)
1867 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1868 if (p->wait_on_write)
1869 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1870 if (p->wait_on_read || p->wait_on_write)
1871 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1872 if (p->device_nand)
1873 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1874 if (p->mux_add_data)
1875 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1876 if (p->burst_read)
1877 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1878 if (p->burst_write)
1879 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1880 if (p->burst_read || p->burst_write) {
1881 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1882 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1883 }
1884
1885 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1886
1887 return 0;
1888}
1889
bc6b1e7b 1890#ifdef CONFIG_OF
31957609 1891static const struct of_device_id gpmc_dt_ids[] = {
bc6b1e7b
DM		 1892 { .compatible = "ti,omap2420-gpmc" },
1893 { .compatible = "ti,omap2430-gpmc" },
1894 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1895 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1896 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
1897 { }
1898};
bc6b1e7b 1899
8c8a7771
JH		 1900/**
1901 * gpmc_read_settings_dt - read gpmc settings from device-tree
1902 * @np: pointer to device-tree node for a gpmc child device
1903 * @p: pointer to gpmc settings structure
1904 *
1905 * Reads the GPMC settings for a GPMC child device from device-tree and
1906 * stores them in the GPMC settings structure passed. The GPMC settings
1907 * structure is initialised to zero by this function and so any
1908 * previously stored settings will be cleared.
1909 */
1910void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1911{
1912 memset(p, 0, sizeof(struct gpmc_settings));
1913
1914 p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1915 p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
8c8a7771
JH		 1916 of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1917 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1918
1919 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1920 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1921 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1922 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1923 if (!p->burst_read && !p->burst_write)
1924 pr_warn("%s: page/burst-length set but not used!\n",
1925 __func__);
1926 }
1927
1928 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1929 p->wait_on_read = of_property_read_bool(np,
1930 "gpmc,wait-on-read");
1931 p->wait_on_write = of_property_read_bool(np,
1932 "gpmc,wait-on-write");
1933 if (!p->wait_on_read && !p->wait_on_write)
2b54057c
RQ		 1934 pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1935 __func__);
8c8a7771
JH		 1936 }
1937}
1938
bc6b1e7b
DM		 1939static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1940 struct gpmc_timings *gpmc_t)
1941{
d36b4cd4
JH		 1942 struct gpmc_bool_timings *p;
1943
1944 if (!np || !gpmc_t)
1945 return;
bc6b1e7b
DM		 1946
1947 memset(gpmc_t, 0, sizeof(*gpmc_t));
1948
1949 /* minimum clock period for syncronous mode */
d36b4cd4 1950 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
bc6b1e7b
DM		 1951
1952 /* chip select timtings */
d36b4cd4
JH		 1953 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1954 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1955 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
bc6b1e7b
DM		 1956
1957 /* ADV signal timings */
d36b4cd4
JH		 1958 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1959 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1960 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
2c92c04b
NA		 1961 of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
1962 &gpmc_t->adv_aad_mux_on);
1963 of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
1964 &gpmc_t->adv_aad_mux_rd_off);
1965 of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
1966 &gpmc_t->adv_aad_mux_wr_off);
bc6b1e7b
DM		 1967
1968 /* WE signal timings */
d36b4cd4
JH		 1969 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1970 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
bc6b1e7b
DM		 1971
1972 /* OE signal timings */
d36b4cd4
JH		 1973 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1974 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
2c92c04b
NA		 1975 of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
1976 &gpmc_t->oe_aad_mux_on);
1977 of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
1978 &gpmc_t->oe_aad_mux_off);
bc6b1e7b
DM		 1979
1980 /* access and cycle timings */
d36b4cd4
JH		 1981 of_property_read_u32(np, "gpmc,page-burst-access-ns",
1982 &gpmc_t->page_burst_access);
1983 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1984 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1985 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1986 of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1987 &gpmc_t->bus_turnaround);
1988 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1989 &gpmc_t->cycle2cycle_delay);
1990 of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1991 &gpmc_t->wait_monitoring);
1992 of_property_read_u32(np, "gpmc,clk-activation-ns",
1993 &gpmc_t->clk_activation);
1994
1995 /* only applicable to OMAP3+ */
1996 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1997 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1998 &gpmc_t->wr_data_mux_bus);
1999
2000 /* bool timing parameters */
2001 p = &gpmc_t->bool_timings;
2002
2003 p->cycle2cyclediffcsen =
2004 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
2005 p->cycle2cyclesamecsen =
2006 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
2007 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
2008 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
2009 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
2010 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
2011 p->time_para_granularity =
2012 of_property_read_bool(np, "gpmc,time-para-granularity");
bc6b1e7b
DM		 2013}
2014
cdd6928c 2015/**
3af91cf7 2016 * gpmc_probe_generic_child - configures the gpmc for a child device
cdd6928c 2017 * @pdev: pointer to gpmc platform device
3af91cf7 2018 * @child: pointer to device-tree node for child device
cdd6928c 2019 *
3af91cf7 2020 * Allocates and configures a GPMC chip-select for a child device.
cdd6928c
JH		 2021 * Returns 0 on success and appropriate negative error code on failure.
2022 */
3af91cf7 2023static int gpmc_probe_generic_child(struct platform_device *pdev,
cdd6928c
JH		 2024 struct device_node *child)
2025{
2026 struct gpmc_settings gpmc_s;
2027 struct gpmc_timings gpmc_t;
2028 struct resource res;
2029 unsigned long base;
9ed7a776 2030 const char *name;
cdd6928c 2031 int ret, cs;
e378d22b 2032 u32 val;
210325f0
RQ		 2033 struct gpio_desc *waitpin_desc = NULL;
2034 struct gpmc_device *gpmc = platform_get_drvdata(pdev);
cdd6928c
JH		 2035
2036 if (of_property_read_u32(child, "reg", &cs) < 0) {
db749d17
RH		 2037 dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
2038 child);
cdd6928c
JH		 2039 return -ENODEV;
2040 }
2041
2042 if (of_address_to_resource(child, 0, &res) < 0) {
db749d17
RH		 2043 dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
2044 child);
cdd6928c
JH		 2045 return -ENODEV;
2046 }
2047
9ed7a776
TL		 2048 /*
2049 * Check if we have multiple instances of the same device
2050 * on a single chip select. If so, use the already initialized
2051 * timings.
2052 */
2053 name = gpmc_cs_get_name(cs);
c2ade654 2054 if (name && of_node_name_eq(child, name))
d507178f 2055 goto no_timings;
9ed7a776 2056
cdd6928c
JH		 2057 ret = gpmc_cs_request(cs, resource_size(&res), &base);
2058 if (ret < 0) {
2059 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
2060 return ret;
2061 }
c2ade654 2062 gpmc_cs_set_name(cs, child->full_name);
cdd6928c 2063
35ac051e
TL		 2064 gpmc_read_settings_dt(child, &gpmc_s);
2065 gpmc_read_timings_dt(child, &gpmc_t);
cdd6928c 2066
fd4446f2
TL		 2067 /*
2068 * For some GPMC devices we still need to rely on the bootloader
35ac051e
TL		 2069 * timings because the devices can be connected via FPGA.
2070 * REVISIT: Add timing support from slls644g.pdf.
fd4446f2 2071 */
35ac051e
TL		 2072 if (!gpmc_t.cs_rd_off) {
2073 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2074 cs);
2075 gpmc_cs_show_timings(cs,
2076 "please add GPMC bootloader timings to .dts");
fd4446f2
TL		 2077 goto no_timings;
2078 }
2079
4cf27d2e
RQ		 2080 /* CS must be disabled while making changes to gpmc configuration */
2081 gpmc_cs_disable_mem(cs);
2082
cdd6928c
JH		 2083 /*
2084 * FIXME: gpmc_cs_request() will map the CS to an arbitary
2085 * location in the gpmc address space. When booting with
2086 * device-tree we want the NOR flash to be mapped to the
2087 * location specified in the device-tree blob. So remap the
2088 * CS to this location. Once DT migration is complete should
2089 * just make gpmc_cs_request() map a specific address.
2090 */
2091 ret = gpmc_cs_remap(cs, res.start);
2092 if (ret < 0) {
f70bf2a3
FE		 2093 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2094 cs, &res.start);
bdd7e033
RQ		 2095 if (res.start < GPMC_MEM_START) {
2096 dev_info(&pdev->dev,
2097 "GPMC CS %d start cannot be lesser than 0x%x\n",
2098 cs, GPMC_MEM_START);
2099 } else if (res.end > GPMC_MEM_END) {
2100 dev_info(&pdev->dev,
2101 "GPMC CS %d end cannot be greater than 0x%x\n",
2102 cs, GPMC_MEM_END);
2103 }
cdd6928c
JH		 2104 goto err;
2105 }
2106
c2ade654 2107 if (of_node_name_eq(child, "nand")) {
c9711ec5
RQ		 2108 /* Warn about older DT blobs with no compatible property */
2109 if (!of_property_read_bool(child, "compatible")) {
2110 dev_warn(&pdev->dev,
2111 "Incompatible NAND node: missing compatible");
2112 ret = -EINVAL;
2113 goto err;
2114 }
2115 }
2116
c2ade654 2117 if (of_node_name_eq(child, "onenand")) {
a758f50f
LM		 2118 /* Warn about older DT blobs with no compatible property */
2119 if (!of_property_read_bool(child, "compatible")) {
2120 dev_warn(&pdev->dev,
2121 "Incompatible OneNAND node: missing compatible");
2122 ret = -EINVAL;
2123 goto err;
2124 }
2125 }
2126
c9711ec5
RQ		 2127 if (of_device_is_compatible(child, "ti,omap2-nand")) {
2128 /* NAND specific setup */
f679888f
BB		 2129 val = 8;
2130 of_property_read_u32(child, "nand-bus-width", &val);
c9711ec5
RQ		 2131 switch (val) {
2132 case 8:
2133 gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2134 break;
2135 case 16:
2136 gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2137 break;
2138 default:
c86f9854
RH		 2139 dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n",
2140 child);
c9711ec5
RQ		 2141 ret = -EINVAL;
2142 goto err;
2143 }
2144
2145 /* disable write protect */
2146 gpmc_configure(GPMC_CONFIG_WP, 0);
2147 gpmc_s.device_nand = true;
2148 } else {
2149 ret = of_property_read_u32(child, "bank-width",
2150 &gpmc_s.device_width);
c18a7ac3
LM		 2151 if (ret < 0 && !gpmc_s.device_width) {
2152 dev_err(&pdev->dev,
2153 "%pOF has no 'gpmc,device-width' property\n",
db749d17 2154 child);
c9711ec5 2155 goto err;
c9eabf40 2156 }
c9711ec5 2157 }
cdd6928c 2158
210325f0
RQ		 2159 /* Reserve wait pin if it is required and valid */
2160 if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
2161 unsigned int wait_pin = gpmc_s.wait_pin;
2162
2163 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
21abf103 2164 wait_pin, "WAITPIN",
5923ea6c
LW		 2165 GPIO_ACTIVE_HIGH,
2166 GPIOD_IN);
210325f0
RQ		 2167 if (IS_ERR(waitpin_desc)) {
2168 dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
2169 ret = PTR_ERR(waitpin_desc);
2170 goto err;
2171 }
2172 }
2173
fd820a1e 2174 gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
210325f0 2175
cdd6928c
JH		 2176 ret = gpmc_cs_program_settings(cs, &gpmc_s);
2177 if (ret < 0)
210325f0 2178 goto err_cs;
cdd6928c 2179
2e676901 2180 ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
7604baf3 2181 if (ret) {
c86f9854
RH		 2182 dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n",
2183 child);
210325f0 2184 goto err_cs;
7604baf3 2185 }
cdd6928c 2186
e378d22b
RQ		 2187 /* Clear limited address i.e. enable A26-A11 */
2188 val = gpmc_read_reg(GPMC_CONFIG);
2189 val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2190 gpmc_write_reg(GPMC_CONFIG, val);
2191
4cf27d2e
RQ		 2192 /* Enable CS region */
2193 gpmc_cs_enable_mem(cs);
cdd6928c 2194
fd4446f2 2195no_timings:
b1dc1ca9
RA		 2196
2197 /* create platform device, NULL on error or when disabled */
2198 if (!of_platform_device_create(child, NULL, &pdev->dev))
2199 goto err_child_fail;
2200
2201 /* is child a common bus? */
2202 if (of_match_node(of_default_bus_match_table, child))
2203 /* create children and other common bus children */
9f2c519c 2204 if (of_platform_default_populate(child, NULL, &pdev->dev))
b1dc1ca9
RA		 2205 goto err_child_fail;
2206
2207 return 0;
2208
2209err_child_fail:
cdd6928c 2210
c86f9854 2211 dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child);
e8ffd6fd 2212 ret = -ENODEV;
cdd6928c 2213
210325f0 2214err_cs:
3f41a3c4 2215 gpiochip_free_own_desc(waitpin_desc);
cdd6928c
JH		 2216err:
2217 gpmc_cs_free(cs);
2218
2219 return ret;
2220}
2221
bc6b1e7b
DM		 2222static int gpmc_probe_dt(struct platform_device *pdev)
2223{
2224 int ret;
bc6b1e7b
DM		 2225 const struct of_device_id *of_id =
2226 of_match_device(gpmc_dt_ids, &pdev->dev);
2227
2228 if (!of_id)
2229 return 0;
2230
f34f3716
GP		 2231 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2232 &gpmc_cs_num);
2233 if (ret < 0) {
2234 pr_err("%s: number of chip-selects not defined\n", __func__);
2235 return ret;
2236 } else if (gpmc_cs_num < 1) {
2237 pr_err("%s: all chip-selects are disabled\n", __func__);
2238 return -EINVAL;
2239 } else if (gpmc_cs_num > GPMC_CS_NUM) {
2240 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2241 __func__, GPMC_CS_NUM);
2242 return -EINVAL;
2243 }
2244
9f833156
JH		 2245 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2246 &gpmc_nr_waitpins);
2247 if (ret < 0) {
2248 pr_err("%s: number of wait pins not found!\n", __func__);
2249 return ret;
2250 }
2251
d2d00862
RQ		 2252 return 0;
2253}
2254
23540d6e 2255static void gpmc_probe_dt_children(struct platform_device *pdev)
d2d00862
RQ		 2256{
2257 int ret;
2258 struct device_node *child;
2259
68e2eb53 2260 for_each_available_child_of_node(pdev->dev.of_node, child) {
a758f50f 2261 ret = gpmc_probe_generic_child(pdev, child);
23540d6e 2262 if (ret) {
c86f9854
RH		 2263 dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n",
2264 child, ret);
23540d6e 2265 }
5330dc16 2266 }
bc6b1e7b
DM		 2267}
2268#else
2269static int gpmc_probe_dt(struct platform_device *pdev)
2270{
2271 return 0;
2272}
d2d00862 2273
23540d6e 2274static void gpmc_probe_dt_children(struct platform_device *pdev)
d2d00862 2275{
d2d00862 2276}
32dd625a
RQ		 2277#endif /* CONFIG_OF */
2278
2279static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
2280{
2281 return 1; /* we're input only */
2282}
2283
2284static int gpmc_gpio_direction_input(struct gpio_chip *chip,
2285 unsigned int offset)
2286{
2287 return 0; /* we're input only */
2288}
2289
2290static int gpmc_gpio_direction_output(struct gpio_chip *chip,
2291 unsigned int offset, int value)
2292{
2293 return -EINVAL; /* we're input only */
2294}
2295
2296static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
2297 int value)
2298{
2299}
2300
2301static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
2302{
2303 u32 reg;
2304
2305 offset += 8;
2306
2307 reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
2308
2309 return !!reg;
2310}
2311
2312static int gpmc_gpio_init(struct gpmc_device *gpmc)
2313{
2314 int ret;
2315
2316 gpmc->gpio_chip.parent = gpmc->dev;
2317 gpmc->gpio_chip.owner = THIS_MODULE;
2318 gpmc->gpio_chip.label = DEVICE_NAME;
2319 gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
2320 gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
2321 gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
2322 gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
2323 gpmc->gpio_chip.set = gpmc_gpio_set;
2324 gpmc->gpio_chip.get = gpmc_gpio_get;
2325 gpmc->gpio_chip.base = -1;
2326
525fe43f 2327 ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
32dd625a
RQ		 2328 if (ret < 0) {
2329 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
2330 return ret;
2331 }
2332
2333 return 0;
2334}
2335
351a102d 2336static int gpmc_probe(struct platform_device *pdev)
4bbbc1ad 2337{
8119024e 2338 int rc;
6b6c32fc 2339 u32 l;
da496873 2340 struct resource *res;
384258f2
RQ		 2341 struct gpmc_device *gpmc;
2342
2343 gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2344 if (!gpmc)
2345 return -ENOMEM;
2346
2347 gpmc->dev = &pdev->dev;
2348 platform_set_drvdata(pdev, gpmc);
4bbbc1ad 2349
da496873
AM		 2350 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2351 if (res == NULL)
2352 return -ENOENT;
8d08436d 2353
da496873
AM		 2354 phys_base = res->start;
2355 mem_size = resource_size(res);
fd1dc87d 2356
5857bd98
TR		 2357 gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2358 if (IS_ERR(gpmc_base))
2359 return PTR_ERR(gpmc_base);
da496873
AM		 2360
2361 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
384258f2
RQ		 2362 if (!res) {
2363 dev_err(&pdev->dev, "Failed to get resource: irq\n");
2364 return -ENOENT;
2365 }
2366
2367 gpmc->irq = res->start;
da496873 2368
8bf9be56 2369 gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
da496873 2370 if (IS_ERR(gpmc_l3_clk)) {
8bf9be56 2371 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
da496873 2372 return PTR_ERR(gpmc_l3_clk);
fd1dc87d
PW		 2373 }
2374
8bf9be56
RQ		 2375 if (!clk_get_rate(gpmc_l3_clk)) {
2376 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2377 return -EINVAL;
2378 }
2379
d2d00862
RQ		 2380 if (pdev->dev.of_node) {
2381 rc = gpmc_probe_dt(pdev);
2382 if (rc)
2383 return rc;
2384 } else {
2385 gpmc_cs_num = GPMC_CS_NUM;
2386 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2387 }
2388
b3f5525c 2389 pm_runtime_enable(&pdev->dev);
2390 pm_runtime_get_sync(&pdev->dev);
1daa8c1d 2391
4bbbc1ad 2392 l = gpmc_read_reg(GPMC_REVISION);
aa8d4767
JH		 2393
2394 /*
2395 * FIXME: Once device-tree migration is complete the below flags
2396 * should be populated based upon the device-tree compatible
2397 * string. For now just use the IP revision. OMAP3+ devices have
2398 * the wr_access and wr_data_mux_bus register fields. OMAP4+
2399 * devices support the addr-addr-data multiplex protocol.
2400 *
2401 * GPMC IP revisions:
2402 * - OMAP24xx = 2.0
2403 * - OMAP3xxx = 5.0
2404 * - OMAP44xx/54xx/AM335x = 6.0
2405 */
da496873
AM		 2406 if (GPMC_REVISION_MAJOR(l) > 0x4)
2407 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
aa8d4767
JH		 2408 if (GPMC_REVISION_MAJOR(l) > 0x5)
2409 gpmc_capability |= GPMC_HAS_MUX_AAD;
384258f2 2410 dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
da496873
AM		 2411 GPMC_REVISION_MINOR(l));
2412
84b00f0e 2413 gpmc_mem_init();
d2d00862
RQ		 2414 rc = gpmc_gpio_init(gpmc);
2415 if (rc)
2416 goto gpio_init_failed;
db97eb7d 2417
b2bac25a 2418 gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
384258f2
RQ		 2419 rc = gpmc_setup_irq(gpmc);
2420 if (rc) {
2421 dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
525fe43f 2422 goto gpio_init_failed;
384258f2 2423 }
da496873 2424
23540d6e 2425 gpmc_probe_dt_children(pdev);
bc6b1e7b 2426
da496873 2427 return 0;
384258f2 2428
d2d00862
RQ		 2429gpio_init_failed:
2430 gpmc_mem_exit();
384258f2 2431 pm_runtime_put_sync(&pdev->dev);
d2d00862
RQ		 2432 pm_runtime_disable(&pdev->dev);
2433
384258f2 2434 return rc;
da496873
AM		 2435}
2436
351a102d 2437static int gpmc_remove(struct platform_device *pdev)
da496873 2438{
384258f2
RQ		 2439 struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2440
2441 gpmc_free_irq(gpmc);
da496873 2442 gpmc_mem_exit();
b3f5525c 2443 pm_runtime_put_sync(&pdev->dev);
2444 pm_runtime_disable(&pdev->dev);
384258f2 2445
da496873
AM		 2446 return 0;
2447}
2448
b536dd41 2449#ifdef CONFIG_PM_SLEEP
2450static int gpmc_suspend(struct device *dev)
2451{
2452 omap3_gpmc_save_context();
2453 pm_runtime_put_sync(dev);
2454 return 0;
2455}
2456
2457static int gpmc_resume(struct device *dev)
2458{
2459 pm_runtime_get_sync(dev);
2460 omap3_gpmc_restore_context();
2461 return 0;
2462}
2463#endif
2464
2465static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2466
da496873
AM		 2467static struct platform_driver gpmc_driver = {
2468 .probe = gpmc_probe,
351a102d 2469 .remove = gpmc_remove,
da496873
AM		 2470 .driver = {
2471 .name = DEVICE_NAME,
bc6b1e7b 2472 .of_match_table = of_match_ptr(gpmc_dt_ids),
b536dd41 2473 .pm = &gpmc_pm_ops,
da496873
AM		 2474 },
2475};
2476
2477static __init int gpmc_init(void)
2478{
2479 return platform_driver_register(&gpmc_driver);
2480}
a8612809 2481postcore_initcall(gpmc_init);
db97eb7d 2482
a2d3e7ba
RN		 2483static struct omap3_gpmc_regs gpmc_context;
2484
b2fa3b7c 2485void omap3_gpmc_save_context(void)
a2d3e7ba
RN		 2486{
2487 int i;
b2fa3b7c 2488
e984a179
TV		 2489 if (!gpmc_base)
2490 return;
2491
a2d3e7ba
RN		 2492 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2493 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2494 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2495 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2496 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2497 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2498 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
f34f3716 2499 for (i = 0; i < gpmc_cs_num; i++) {
a2d3e7ba
RN		 2500 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2501 if (gpmc_context.cs_context[i].is_valid) {
2502 gpmc_context.cs_context[i].config1 =
2503 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2504 gpmc_context.cs_context[i].config2 =
2505 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2506 gpmc_context.cs_context[i].config3 =
2507 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2508 gpmc_context.cs_context[i].config4 =
2509 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2510 gpmc_context.cs_context[i].config5 =
2511 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2512 gpmc_context.cs_context[i].config6 =
2513 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2514 gpmc_context.cs_context[i].config7 =
2515 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2516 }
2517 }
2518}
2519
b2fa3b7c 2520void omap3_gpmc_restore_context(void)
a2d3e7ba
RN		 2521{
2522 int i;
b2fa3b7c 2523
e984a179
TV		 2524 if (!gpmc_base)
2525 return;
2526
a2d3e7ba
RN		 2527 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2528 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2529 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2530 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2531 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2532 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2533 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
f34f3716 2534 for (i = 0; i < gpmc_cs_num; i++) {
a2d3e7ba
RN		 2535 if (gpmc_context.cs_context[i].is_valid) {
2536 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2537 gpmc_context.cs_context[i].config1);
2538 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2539 gpmc_context.cs_context[i].config2);
2540 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2541 gpmc_context.cs_context[i].config3);
2542 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2543 gpmc_context.cs_context[i].config4);
2544 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2545 gpmc_context.cs_context[i].config5);
2546 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2547 gpmc_context.cs_context[i].config6);
2548 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2549 gpmc_context.cs_context[i].config7);
2550 }
2551 }
2552}
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