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ARM OMAP2+ GPMC: always program GPMCFCLKDIVIDER
[mirror_ubuntu-artful-kernel.git] / drivers / memory / omap-gpmc.c
CommitLineData
4bbbc1ad
JY		 1/*
2 * GPMC support functions
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * Author: Juha Yrjola
7 *
44169075
SS		 8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 *
4bbbc1ad
JY		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
db97eb7d 15#include <linux/irq.h>
4bbbc1ad
JY		 16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/err.h>
19#include <linux/clk.h>
f37e4580
ID		 20#include <linux/ioport.h>
21#include <linux/spinlock.h>
fced80c7 22#include <linux/io.h>
fd1dc87d 23#include <linux/module.h>
db97eb7d 24#include <linux/interrupt.h>
da496873 25#include <linux/platform_device.h>
bc6b1e7b 26#include <linux/of.h>
cdd6928c 27#include <linux/of_address.h>
bc6b1e7b
DM		 28#include <linux/of_mtd.h>
29#include <linux/of_device.h>
b1dc1ca9 30#include <linux/of_platform.h>
e639cd5b 31#include <linux/omap-gpmc.h>
bc6b1e7b 32#include <linux/mtd/nand.h>
b3f5525c 33#include <linux/pm_runtime.h>
4bbbc1ad 34
bc3668ea 35#include <linux/platform_data/mtd-nand-omap2.h>
e639cd5b 36#include <linux/platform_data/mtd-onenand-omap2.h>
4bbbc1ad 37
7f245162 38#include <asm/mach-types.h>
72d0f1c3 39
4be48fd5
AM		 40#define DEVICE_NAME "omap-gpmc"
41
fd1dc87d 42/* GPMC register offsets */
4bbbc1ad
JY		 43#define GPMC_REVISION 0x00
44#define GPMC_SYSCONFIG 0x10
45#define GPMC_SYSSTATUS 0x14
46#define GPMC_IRQSTATUS 0x18
47#define GPMC_IRQENABLE 0x1c
48#define GPMC_TIMEOUT_CONTROL 0x40
49#define GPMC_ERR_ADDRESS 0x44
50#define GPMC_ERR_TYPE 0x48
51#define GPMC_CONFIG 0x50
52#define GPMC_STATUS 0x54
53#define GPMC_PREFETCH_CONFIG1 0x1e0
54#define GPMC_PREFETCH_CONFIG2 0x1e4
15e02a3b 55#define GPMC_PREFETCH_CONTROL 0x1ec
4bbbc1ad
JY		 56#define GPMC_PREFETCH_STATUS 0x1f0
57#define GPMC_ECC_CONFIG 0x1f4
58#define GPMC_ECC_CONTROL 0x1f8
59#define GPMC_ECC_SIZE_CONFIG 0x1fc
948d38e7 60#define GPMC_ECC1_RESULT 0x200
8d602cf5 61#define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
2fdf0c98
AM		 62#define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
63#define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
64#define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
27c9fd60 65#define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
66#define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
67#define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
4bbbc1ad 68
2c65e744
YY		 69/* GPMC ECC control settings */
70#define GPMC_ECC_CTRL_ECCCLEAR 0x100
71#define GPMC_ECC_CTRL_ECCDISABLE 0x000
72#define GPMC_ECC_CTRL_ECCREG1 0x001
73#define GPMC_ECC_CTRL_ECCREG2 0x002
74#define GPMC_ECC_CTRL_ECCREG3 0x003
75#define GPMC_ECC_CTRL_ECCREG4 0x004
76#define GPMC_ECC_CTRL_ECCREG5 0x005
77#define GPMC_ECC_CTRL_ECCREG6 0x006
78#define GPMC_ECC_CTRL_ECCREG7 0x007
79#define GPMC_ECC_CTRL_ECCREG8 0x008
80#define GPMC_ECC_CTRL_ECCREG9 0x009
81
e378d22b
RQ		 82#define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
83
559d94b0
AM		 84#define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
85#define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
86#define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
87#define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
88#define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
89#define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
90
948d38e7 91#define GPMC_CS0_OFFSET 0x60
4bbbc1ad 92#define GPMC_CS_SIZE 0x30
2fdf0c98 93#define GPMC_BCH_SIZE 0x10
4bbbc1ad 94
f37e4580 95#define GPMC_MEM_END 0x3FFFFFFF
f37e4580
ID		 96
97#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
98#define GPMC_SECTION_SHIFT 28 /* 128 MB */
99
59e9c5ae 100#define CS_NUM_SHIFT 24
101#define ENABLE_PREFETCH (0x1 << 7)
102#define DMA_MPU_MODE 2
103
da496873
AM		 104#define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
105#define GPMC_REVISION_MINOR(l) (l & 0xf)
106
107#define GPMC_HAS_WR_ACCESS 0x1
108#define GPMC_HAS_WR_DATA_MUX_BUS 0x2
aa8d4767 109#define GPMC_HAS_MUX_AAD 0x4
da496873 110
9f833156
JH		 111#define GPMC_NR_WAITPINS 4
112
e639cd5b
TL		 113#define GPMC_CS_CONFIG1 0x00
114#define GPMC_CS_CONFIG2 0x04
115#define GPMC_CS_CONFIG3 0x08
116#define GPMC_CS_CONFIG4 0x0c
117#define GPMC_CS_CONFIG5 0x10
118#define GPMC_CS_CONFIG6 0x14
119#define GPMC_CS_CONFIG7 0x18
120#define GPMC_CS_NAND_COMMAND 0x1c
121#define GPMC_CS_NAND_ADDRESS 0x20
122#define GPMC_CS_NAND_DATA 0x24
123
124/* Control Commands */
125#define GPMC_CONFIG_RDY_BSY 0x00000001
126#define GPMC_CONFIG_DEV_SIZE 0x00000002
127#define GPMC_CONFIG_DEV_TYPE 0x00000003
128#define GPMC_SET_IRQ_STATUS 0x00000004
129
130#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
131#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
132#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
133#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
134#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
135#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
136#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
137#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
138#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
139#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
140#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
141#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
142#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
143#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
144#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
145#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
146#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
147#define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
148#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
149#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
150#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
151#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
152#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
153#define GPMC_CONFIG7_CSVALID (1 << 6)
154
9c4f757e
SP		 155#define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
156#define GPMC_CONFIG7_CSVALID_MASK BIT(6)
157#define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
158#define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
159/* All CONFIG7 bits except reserved bits */
160#define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
161 GPMC_CONFIG7_CSVALID_MASK | \
162 GPMC_CONFIG7_MASKADDRESS_MASK)
163
e639cd5b
TL		 164#define GPMC_DEVICETYPE_NOR 0
165#define GPMC_DEVICETYPE_NAND 2
166#define GPMC_CONFIG_WRITEPROTECT 0x00000010
167#define WR_RD_PIN_MONITORING 0x00600000
168
169#define GPMC_ENABLE_IRQ 0x0000000d
170
171/* ECC commands */
172#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
173#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
174#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
175
6b6c32fc
AM		 176/* XXX: Only NAND irq has been considered,currently these are the only ones used
177 */
178#define GPMC_NR_IRQ 2
179
9ed7a776
TL		 180struct gpmc_cs_data {
181 const char *name;
182
183#define GPMC_CS_RESERVED (1 << 0)
184 u32 flags;
185
186 struct resource mem;
187};
188
6b6c32fc
AM		 189struct gpmc_client_irq {
190 unsigned irq;
191 u32 bitmask;
192};
193
a2d3e7ba
RN		 194/* Structure to save gpmc cs context */
195struct gpmc_cs_config {
196 u32 config1;
197 u32 config2;
198 u32 config3;
199 u32 config4;
200 u32 config5;
201 u32 config6;
202 u32 config7;
203 int is_valid;
204};
205
206/*
207 * Structure to save/restore gpmc context
208 * to support core off on OMAP3
209 */
210struct omap3_gpmc_regs {
211 u32 sysconfig;
212 u32 irqenable;
213 u32 timeout_ctrl;
214 u32 config;
215 u32 prefetch_config1;
216 u32 prefetch_config2;
217 u32 prefetch_control;
218 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
219};
220
6b6c32fc
AM		 221static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
222static struct irq_chip gpmc_irq_chip;
af072196 223static int gpmc_irq_start;
6b6c32fc 224
f37e4580 225static struct resource gpmc_mem_root;
9ed7a776 226static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
87b247c4 227static DEFINE_SPINLOCK(gpmc_mem_lock);
6797b4fe 228/* Define chip-selects as reserved by default until probe completes */
f34f3716 229static unsigned int gpmc_cs_num = GPMC_CS_NUM;
9f833156 230static unsigned int gpmc_nr_waitpins;
da496873
AM		 231static struct device *gpmc_dev;
232static int gpmc_irq;
233static resource_size_t phys_base, mem_size;
234static unsigned gpmc_capability;
fd1dc87d 235static void __iomem *gpmc_base;
4bbbc1ad 236
fd1dc87d 237static struct clk *gpmc_l3_clk;
4bbbc1ad 238
db97eb7d
SG		 239static irqreturn_t gpmc_handle_irq(int irq, void *dev);
240
4bbbc1ad
JY		 241static void gpmc_write_reg(int idx, u32 val)
242{
edfaf05c 243 writel_relaxed(val, gpmc_base + idx);
4bbbc1ad
JY		 244}
245
246static u32 gpmc_read_reg(int idx)
247{
edfaf05c 248 return readl_relaxed(gpmc_base + idx);
4bbbc1ad
JY		 249}
250
251void gpmc_cs_write_reg(int cs, int idx, u32 val)
252{
253 void __iomem *reg_addr;
254
948d38e7 255 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
edfaf05c 256 writel_relaxed(val, reg_addr);
4bbbc1ad
JY		 257}
258
3fc089e7 259static u32 gpmc_cs_read_reg(int cs, int idx)
4bbbc1ad 260{
fd1dc87d
PW		 261 void __iomem *reg_addr;
262
948d38e7 263 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
edfaf05c 264 return readl_relaxed(reg_addr);
4bbbc1ad
JY		 265}
266
fd1dc87d 267/* TODO: Add support for gpmc_fck to clock framework and use it */
3fc089e7 268static unsigned long gpmc_get_fclk_period(void)
4bbbc1ad 269{
fd1dc87d
PW		 270 unsigned long rate = clk_get_rate(gpmc_l3_clk);
271
fd1dc87d
PW		 272 rate /= 1000;
273 rate = 1000000000 / rate; /* In picoseconds */
274
275 return rate;
4bbbc1ad
JY		 276}
277
3fc089e7 278static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
4bbbc1ad
JY		 279{
280 unsigned long tick_ps;
281
282 /* Calculate in picosecs to yield more exact results */
283 tick_ps = gpmc_get_fclk_period();
284
285 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
286}
287
3fc089e7 288static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
a3551f5b
AH		 289{
290 unsigned long tick_ps;
291
292 /* Calculate in picosecs to yield more exact results */
293 tick_ps = gpmc_get_fclk_period();
294
295 return (time_ps + tick_ps - 1) / tick_ps;
296}
297
fd1dc87d
PW		 298unsigned int gpmc_ticks_to_ns(unsigned int ticks)
299{
300 return ticks * gpmc_get_fclk_period() / 1000;
301}
302
246da26d
AM		 303static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
304{
305 return ticks * gpmc_get_fclk_period();
306}
307
308static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
309{
310 unsigned long ticks = gpmc_ps_to_ticks(time_ps);
311
312 return ticks * gpmc_get_fclk_period();
313}
314
559d94b0
AM		 315static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
316{
317 u32 l;
318
319 l = gpmc_cs_read_reg(cs, reg);
320 if (value)
321 l |= mask;
322 else
323 l &= ~mask;
324 gpmc_cs_write_reg(cs, reg, l);
325}
326
327static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
328{
329 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
330 GPMC_CONFIG1_TIME_PARA_GRAN,
331 p->time_para_granularity);
332 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
333 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
334 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
335 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
336 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
337 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
338 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
339 GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
340 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
341 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
342 p->cycle2cyclesamecsen);
343 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
344 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
345 p->cycle2cyclediffcsen);
346}
347
4bbbc1ad 348#ifdef DEBUG
563dbb26
RA		 349/**
350 * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
351 * @cs: Chip Select Region
352 * @reg: GPMC_CS_CONFIGn register offset.
353 * @st_bit: Start Bit
354 * @end_bit: End Bit. Must be >= @st_bit.
355 * @name: DTS node name, w/o "gpmc,"
356 * @raw: Raw Format Option.
357 * raw format: gpmc,name = <value>
358 * tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
359 * Where x ns -- y ns result in the same tick value.
360 * @noval: Parameter values equal to 0 are not printed.
361 * @shift: Parameter value left shifts @shift, which is then printed instead of value.
362 * @return: Specified timing parameter (after optional @shift).
363 *
364 */
35ac051e
TL		 365static int get_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
366 bool raw, bool noval, int shift,
367 const char *name)
368{
369 u32 l;
563dbb26
RA		 370 int nr_bits;
371 int mask;
35ac051e
TL		 372
373 l = gpmc_cs_read_reg(cs, reg);
374 nr_bits = end_bit - st_bit + 1;
563dbb26
RA		 375 mask = (1 << nr_bits) - 1;
376 l = (l >> st_bit) & mask;
35ac051e
TL		 377 if (shift)
378 l = (shift << l);
379 if (noval && (l == 0))
380 return 0;
381 if (!raw) {
563dbb26
RA		 382 /* DTS tick format for timings in ns */
383 unsigned int time_ns;
384 unsigned int time_ns_min = 0;
35ac051e 385
563dbb26
RA		 386 if (l)
387 time_ns_min = gpmc_ticks_to_ns(l - 1) + 1;
35ac051e 388 time_ns = gpmc_ticks_to_ns(l);
563dbb26
RA		 389 pr_info("gpmc,%s = <%u> /* %u ns - %u ns; %i ticks */\n",
390 name, time_ns, time_ns_min, time_ns, l);
35ac051e 391 } else {
563dbb26 392 /* raw format */
35ac051e
TL		 393 pr_info("gpmc,%s = <%u>\n", name, l);
394 }
395
396 return l;
397}
398
399#define GPMC_PRINT_CONFIG(cs, config) \
400 pr_info("cs%i %s: 0x%08x\n", cs, #config, \
401 gpmc_cs_read_reg(cs, config))
402#define GPMC_GET_RAW(reg, st, end, field) \
403 get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 0, 0, field)
404#define GPMC_GET_RAW_BOOL(reg, st, end, field) \
405 get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, 0, field)
406#define GPMC_GET_RAW_SHIFT(reg, st, end, shift, field) \
407 get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, (shift), field)
408#define GPMC_GET_TICKS(reg, st, end, field) \
409 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, 0, 0, field)
410
411static void gpmc_show_regs(int cs, const char *desc)
412{
413 pr_info("gpmc cs%i %s:\n", cs, desc);
414 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
415 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
416 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
417 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
418 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
419 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
420}
421
422/*
423 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
424 * see commit c9fb809.
425 */
426static void gpmc_cs_show_timings(int cs, const char *desc)
427{
428 gpmc_show_regs(cs, desc);
429
430 pr_info("gpmc cs%i access configuration:\n", cs);
431 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
432 GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
433 GPMC_GET_RAW(GPMC_CS_CONFIG1, 12, 13, "device-width");
434 GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
435 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
436 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
437 GPMC_GET_RAW_SHIFT(GPMC_CS_CONFIG1, 23, 24, 4, "burst-length");
438 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
439 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
440 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
441 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
442 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
443
444 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay");
445
446 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay");
447
448 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
449 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay");
450
451 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen");
452 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen");
453
454 pr_info("gpmc cs%i timings configuration:\n", cs);
455 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns");
456 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns");
457 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
458
459 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns");
460 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns");
461 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
462
463 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns");
464 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns");
465 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
466 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
467
468 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns");
469 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns");
470 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
471
472 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
473
474 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
475 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
476
477 GPMC_GET_TICKS(GPMC_CS_CONFIG1, 18, 19, "wait-monitoring-ns");
478 GPMC_GET_TICKS(GPMC_CS_CONFIG1, 25, 26, "clk-activation-ns");
479
480 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
481 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
482}
4bbbc1ad 483#else
35ac051e
TL		 484static inline void gpmc_cs_show_timings(int cs, const char *desc)
485{
486}
4bbbc1ad 487#endif
35ac051e 488
4bbbc1ad 489static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
2aab6468 490 int time, const char *name)
4bbbc1ad
JY		 491{
492 u32 l;
493 int ticks, mask, nr_bits;
494
495 if (time == 0)
496 ticks = 0;
497 else
498 ticks = gpmc_ns_to_ticks(time);
499 nr_bits = end_bit - st_bit + 1;
80323742
RQ		 500 mask = (1 << nr_bits) - 1;
501
502 if (ticks > mask) {
503 pr_err("%s: GPMC error! CS%d: %s: %d ns, %d ticks > %d\n",
504 __func__, cs, name, time, ticks, mask);
505
4bbbc1ad 506 return -1;
1c22cc13 507 }
4bbbc1ad 508
4bbbc1ad
JY		 509 l = gpmc_cs_read_reg(cs, reg);
510#ifdef DEBUG
f585070b 511 pr_info(
2affc816 512 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
2aab6468 513 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
1c22cc13 514 (l >> st_bit) & mask, time);
4bbbc1ad
JY		 515#endif
516 l &= ~(mask << st_bit);
517 l |= ticks << st_bit;
518 gpmc_cs_write_reg(cs, reg, l);
519
520 return 0;
521}
522
4bbbc1ad
JY		 523#define GPMC_SET_ONE(reg, st, end, field) \
524 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
525 t->field, #field) < 0) \
526 return -1
4bbbc1ad 527
1b47ca1a 528int gpmc_calc_divider(unsigned int sync_clk)
4bbbc1ad
JY		 529{
530 int div;
531 u32 l;
532
a3551f5b 533 l = sync_clk + (gpmc_get_fclk_period() - 1);
4bbbc1ad
JY		 534 div = l / gpmc_get_fclk_period();
535 if (div > 4)
536 return -1;
1c22cc13 537 if (div <= 0)
4bbbc1ad
JY		 538 div = 1;
539
540 return div;
541}
542
543int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
544{
545 int div;
546 u32 l;
547
35ac051e 548 gpmc_cs_show_timings(cs, "before gpmc_cs_set_timings");
1b47ca1a 549 div = gpmc_calc_divider(t->sync_clk);
4bbbc1ad 550 if (div < 0)
a032d33b 551 return div;
4bbbc1ad
JY		 552
553 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
554 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
555 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
556
557 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
558 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
559 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
560
561 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
562 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
563 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
564 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
565
566 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
567 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
568 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
569
570 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
571
559d94b0
AM		 572 GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
573 GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
574
575 GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);
576 GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
577
da496873 578 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
cc26b3b0 579 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
da496873 580 if (gpmc_capability & GPMC_HAS_WR_ACCESS)
cc26b3b0 581 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
cc26b3b0 582
1c22cc13 583 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
4bbbc1ad 584#ifdef DEBUG
f585070b
RA		 585 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
586 cs, (div * gpmc_get_fclk_period()) / 1000, div);
4bbbc1ad 587#endif
f585070b
RA		 588 l &= ~0x03;
589 l |= (div - 1);
590 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
4bbbc1ad 591
559d94b0 592 gpmc_cs_bool_timings(cs, &t->bool_timings);
35ac051e 593 gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
559d94b0 594
4bbbc1ad
JY		 595 return 0;
596}
597
4cf27d2e 598static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
f37e4580
ID		 599{
600 u32 l;
601 u32 mask;
602
c71f8e9b
JH		 603 /*
604 * Ensure that base address is aligned on a
605 * boundary equal to or greater than size.
606 */
607 if (base & (size - 1))
608 return -EINVAL;
609
9c4f757e 610 base >>= GPMC_CHUNK_SHIFT;
f37e4580 611 mask = (1 << GPMC_SECTION_SHIFT) - size;
9c4f757e
SP		 612 mask >>= GPMC_CHUNK_SHIFT;
613 mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
614
f37e4580 615 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
9c4f757e
SP		 616 l &= ~GPMC_CONFIG7_MASK;
617 l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
618 l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
a2d3e7ba 619 l |= GPMC_CONFIG7_CSVALID;
f37e4580 620 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
c71f8e9b
JH		 621
622 return 0;
f37e4580
ID		 623}
624
4cf27d2e
RQ		 625static void gpmc_cs_enable_mem(int cs)
626{
627 u32 l;
628
629 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
630 l |= GPMC_CONFIG7_CSVALID;
631 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
632}
633
f37e4580
ID		 634static void gpmc_cs_disable_mem(int cs)
635{
636 u32 l;
637
638 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
a2d3e7ba 639 l &= ~GPMC_CONFIG7_CSVALID;
f37e4580
ID		 640 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
641}
642
643static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
644{
645 u32 l;
646 u32 mask;
647
648 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
649 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
650 mask = (l >> 8) & 0x0f;
651 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
652}
653
654static int gpmc_cs_mem_enabled(int cs)
655{
656 u32 l;
657
658 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
a2d3e7ba 659 return l & GPMC_CONFIG7_CSVALID;
f37e4580
ID		 660}
661
f5d8edaf 662static void gpmc_cs_set_reserved(int cs, int reserved)
4bbbc1ad 663{
9ed7a776
TL		 664 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
665
666 gpmc->flags |= GPMC_CS_RESERVED;
f37e4580
ID		 667}
668
ae9d908a 669static bool gpmc_cs_reserved(int cs)
f37e4580 670{
9ed7a776
TL		 671 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
672
673 return gpmc->flags & GPMC_CS_RESERVED;
674}
675
676static void gpmc_cs_set_name(int cs, const char *name)
677{
678 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
679
680 gpmc->name = name;
681}
682
2e25b0ec 683static const char *gpmc_cs_get_name(int cs)
9ed7a776
TL		 684{
685 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
686
687 return gpmc->name;
f37e4580
ID		 688}
689
690static unsigned long gpmc_mem_align(unsigned long size)
691{
692 int order;
693
694 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
695 order = GPMC_CHUNK_SHIFT - 1;
696 do {
697 size >>= 1;
698 order++;
699 } while (size);
700 size = 1 << order;
701 return size;
702}
703
704static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
705{
9ed7a776
TL		 706 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
707 struct resource *res = &gpmc->mem;
f37e4580
ID		 708 int r;
709
710 size = gpmc_mem_align(size);
711 spin_lock(&gpmc_mem_lock);
712 res->start = base;
713 res->end = base + size - 1;
714 r = request_resource(&gpmc_mem_root, res);
715 spin_unlock(&gpmc_mem_lock);
716
717 return r;
718}
719
da496873
AM		 720static int gpmc_cs_delete_mem(int cs)
721{
9ed7a776
TL		 722 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
723 struct resource *res = &gpmc->mem;
da496873
AM		 724 int r;
725
726 spin_lock(&gpmc_mem_lock);
efe80723 727 r = release_resource(res);
da496873
AM		 728 res->start = 0;
729 res->end = 0;
730 spin_unlock(&gpmc_mem_lock);
731
732 return r;
733}
734
cdd6928c
JH		 735/**
736 * gpmc_cs_remap - remaps a chip-select physical base address
737 * @cs: chip-select to remap
738 * @base: physical base address to re-map chip-select to
739 *
740 * Re-maps a chip-select to a new physical base address specified by
741 * "base". Returns 0 on success and appropriate negative error code
742 * on failure.
743 */
744static int gpmc_cs_remap(int cs, u32 base)
745{
746 int ret;
747 u32 old_base, size;
748
f34f3716
GP		 749 if (cs > gpmc_cs_num) {
750 pr_err("%s: requested chip-select is disabled\n", __func__);
cdd6928c 751 return -ENODEV;
f34f3716 752 }
fb677ef7
TL		 753
754 /*
755 * Make sure we ignore any device offsets from the GPMC partition
756 * allocated for the chip select and that the new base confirms
757 * to the GPMC 16MB minimum granularity.
758 */
759 base &= ~(SZ_16M - 1);
760
cdd6928c
JH		 761 gpmc_cs_get_memconf(cs, &old_base, &size);
762 if (base == old_base)
763 return 0;
4cf27d2e 764
cdd6928c
JH		 765 ret = gpmc_cs_delete_mem(cs);
766 if (ret < 0)
767 return ret;
4cf27d2e 768
cdd6928c 769 ret = gpmc_cs_insert_mem(cs, base, size);
c71f8e9b
JH		 770 if (ret < 0)
771 return ret;
cdd6928c 772
4cf27d2e
RQ		 773 ret = gpmc_cs_set_memconf(cs, base, size);
774
775 return ret;
cdd6928c
JH		 776}
777
f37e4580
ID		 778int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
779{
9ed7a776
TL		 780 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
781 struct resource *res = &gpmc->mem;
f37e4580
ID		 782 int r = -1;
783
f34f3716
GP		 784 if (cs > gpmc_cs_num) {
785 pr_err("%s: requested chip-select is disabled\n", __func__);
f37e4580 786 return -ENODEV;
f34f3716 787 }
f37e4580
ID		 788 size = gpmc_mem_align(size);
789 if (size > (1 << GPMC_SECTION_SHIFT))
790 return -ENOMEM;
791
792 spin_lock(&gpmc_mem_lock);
793 if (gpmc_cs_reserved(cs)) {
794 r = -EBUSY;
795 goto out;
796 }
797 if (gpmc_cs_mem_enabled(cs))
798 r = adjust_resource(res, res->start & ~(size - 1), size);
799 if (r < 0)
800 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
801 size, NULL, NULL);
802 if (r < 0)
803 goto out;
804
4cf27d2e
RQ		 805 /* Disable CS while changing base address and size mask */
806 gpmc_cs_disable_mem(cs);
807
808 r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
c71f8e9b
JH		 809 if (r < 0) {
810 release_resource(res);
811 goto out;
812 }
813
4cf27d2e
RQ		 814 /* Enable CS */
815 gpmc_cs_enable_mem(cs);
f37e4580
ID		 816 *base = res->start;
817 gpmc_cs_set_reserved(cs, 1);
818out:
819 spin_unlock(&gpmc_mem_lock);
820 return r;
821}
fd1dc87d 822EXPORT_SYMBOL(gpmc_cs_request);
f37e4580
ID		 823
824void gpmc_cs_free(int cs)
825{
9ed7a776
TL		 826 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
827 struct resource *res = &gpmc->mem;
efe80723 828
f37e4580 829 spin_lock(&gpmc_mem_lock);
f34f3716 830 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
f37e4580
ID		 831 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
832 BUG();
833 spin_unlock(&gpmc_mem_lock);
834 return;
835 }
836 gpmc_cs_disable_mem(cs);
efe80723
TL		 837 if (res->flags)
838 release_resource(res);
f37e4580
ID		 839 gpmc_cs_set_reserved(cs, 0);
840 spin_unlock(&gpmc_mem_lock);
841}
fd1dc87d 842EXPORT_SYMBOL(gpmc_cs_free);
f37e4580 843
948d38e7 844/**
3a544354 845 * gpmc_configure - write request to configure gpmc
948d38e7
SG		 846 * @cmd: command type
847 * @wval: value to write
848 * @return status of the operation
849 */
3a544354 850int gpmc_configure(int cmd, int wval)
948d38e7 851{
3a544354 852 u32 regval;
948d38e7
SG		 853
854 switch (cmd) {
db97eb7d
SG		 855 case GPMC_ENABLE_IRQ:
856 gpmc_write_reg(GPMC_IRQENABLE, wval);
857 break;
858
948d38e7
SG		 859 case GPMC_SET_IRQ_STATUS:
860 gpmc_write_reg(GPMC_IRQSTATUS, wval);
861 break;
862
863 case GPMC_CONFIG_WP:
864 regval = gpmc_read_reg(GPMC_CONFIG);
865 if (wval)
866 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
867 else
868 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
869 gpmc_write_reg(GPMC_CONFIG, regval);
870 break;
871
948d38e7 872 default:
3a544354
JH		 873 pr_err("%s: command not supported\n", __func__);
874 return -EINVAL;
948d38e7
SG		 875 }
876
3a544354 877 return 0;
948d38e7 878}
3a544354 879EXPORT_SYMBOL(gpmc_configure);
948d38e7 880
52bd138d
AM		 881void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
882{
2fdf0c98
AM		 883 int i;
884
52bd138d
AM		 885 reg->gpmc_status = gpmc_base + GPMC_STATUS;
886 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
887 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
888 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
889 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
890 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
891 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
892 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
893 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
894 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
895 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
896 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
897 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
898 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
899 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
2fdf0c98
AM		 900
901 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
902 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
903 GPMC_BCH_SIZE * i;
904 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
905 GPMC_BCH_SIZE * i;
906 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
907 GPMC_BCH_SIZE * i;
908 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
909 GPMC_BCH_SIZE * i;
27c9fd60 910 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
911 i * GPMC_BCH_SIZE;
912 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
913 i * GPMC_BCH_SIZE;
914 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
915 i * GPMC_BCH_SIZE;
2fdf0c98 916 }
52bd138d
AM		 917}
918
6b6c32fc
AM		 919int gpmc_get_client_irq(unsigned irq_config)
920{
921 int i;
922
923 if (hweight32(irq_config) > 1)
924 return 0;
925
926 for (i = 0; i < GPMC_NR_IRQ; i++)
927 if (gpmc_client_irq[i].bitmask & irq_config)
928 return gpmc_client_irq[i].irq;
929
930 return 0;
931}
932
933static int gpmc_irq_endis(unsigned irq, bool endis)
934{
935 int i;
936 u32 regval;
937
938 for (i = 0; i < GPMC_NR_IRQ; i++)
939 if (irq == gpmc_client_irq[i].irq) {
940 regval = gpmc_read_reg(GPMC_IRQENABLE);
941 if (endis)
942 regval |= gpmc_client_irq[i].bitmask;
943 else
944 regval &= ~gpmc_client_irq[i].bitmask;
945 gpmc_write_reg(GPMC_IRQENABLE, regval);
946 break;
947 }
948
949 return 0;
950}
951
952static void gpmc_irq_disable(struct irq_data *p)
953{
954 gpmc_irq_endis(p->irq, false);
955}
956
957static void gpmc_irq_enable(struct irq_data *p)
958{
959 gpmc_irq_endis(p->irq, true);
960}
961
962static void gpmc_irq_noop(struct irq_data *data) { }
963
964static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
965
da496873 966static int gpmc_setup_irq(void)
6b6c32fc
AM		 967{
968 int i;
969 u32 regval;
970
971 if (!gpmc_irq)
972 return -EINVAL;
973
974 gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
71856843 975 if (gpmc_irq_start < 0) {
6b6c32fc
AM		 976 pr_err("irq_alloc_descs failed\n");
977 return gpmc_irq_start;
978 }
979
980 gpmc_irq_chip.name = "gpmc";
981 gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
982 gpmc_irq_chip.irq_enable = gpmc_irq_enable;
983 gpmc_irq_chip.irq_disable = gpmc_irq_disable;
984 gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
985 gpmc_irq_chip.irq_ack = gpmc_irq_noop;
986 gpmc_irq_chip.irq_mask = gpmc_irq_noop;
987 gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
988
989 gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
990 gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
991
992 for (i = 0; i < GPMC_NR_IRQ; i++) {
993 gpmc_client_irq[i].irq = gpmc_irq_start + i;
994 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
995 &gpmc_irq_chip, handle_simple_irq);
996 set_irq_flags(gpmc_client_irq[i].irq,
997 IRQF_VALID | IRQF_NOAUTOEN);
998 }
999
1000 /* Disable interrupts */
1001 gpmc_write_reg(GPMC_IRQENABLE, 0);
1002
1003 /* clear interrupts */
1004 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1005 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1006
1007 return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
1008}
1009
351a102d 1010static int gpmc_free_irq(void)
da496873
AM		 1011{
1012 int i;
1013
1014 if (gpmc_irq)
1015 free_irq(gpmc_irq, NULL);
1016
1017 for (i = 0; i < GPMC_NR_IRQ; i++) {
1018 irq_set_handler(gpmc_client_irq[i].irq, NULL);
1019 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
1020 irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
1021 }
1022
1023 irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
1024
1025 return 0;
1026}
1027
351a102d 1028static void gpmc_mem_exit(void)
da496873
AM		 1029{
1030 int cs;
1031
f34f3716 1032 for (cs = 0; cs < gpmc_cs_num; cs++) {
da496873
AM		 1033 if (!gpmc_cs_mem_enabled(cs))
1034 continue;
1035 gpmc_cs_delete_mem(cs);
1036 }
1037
1038}
1039
84b00f0e 1040static void gpmc_mem_init(void)
f37e4580 1041{
84b00f0e 1042 int cs;
f37e4580 1043
bf234397
JH		 1044 /*
1045 * The first 1MB of GPMC address space is typically mapped to
1046 * the internal ROM. Never allocate the first page, to
1047 * facilitate bug detection; even if we didn't boot from ROM.
7f245162 1048 */
bf234397 1049 gpmc_mem_root.start = SZ_1M;
f37e4580
ID		 1050 gpmc_mem_root.end = GPMC_MEM_END;
1051
1052 /* Reserve all regions that has been set up by bootloader */
f34f3716 1053 for (cs = 0; cs < gpmc_cs_num; cs++) {
f37e4580
ID		 1054 u32 base, size;
1055
1056 if (!gpmc_cs_mem_enabled(cs))
1057 continue;
1058 gpmc_cs_get_memconf(cs, &base, &size);
84b00f0e
JH		 1059 if (gpmc_cs_insert_mem(cs, base, size)) {
1060 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1061 __func__, cs, base, base + size);
1062 gpmc_cs_disable_mem(cs);
8119024e 1063 }
f37e4580 1064 }
4bbbc1ad
JY		 1065}
1066
246da26d
AM		 1067static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1068{
1069 u32 temp;
1070 int div;
1071
1072 div = gpmc_calc_divider(sync_clk);
1073 temp = gpmc_ps_to_ticks(time_ps);
1074 temp = (temp + div - 1) / div;
1075 return gpmc_ticks_to_ps(temp * div);
1076}
1077
1078/* XXX: can the cycles be avoided ? */
1079static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1080 struct gpmc_device_timings *dev_t,
1081 bool mux)
246da26d 1082{
246da26d
AM		 1083 u32 temp;
1084
1085 /* adv_rd_off */
1086 temp = dev_t->t_avdp_r;
1087 /* XXX: mux check required ? */
1088 if (mux) {
1089 /* XXX: t_avdp not to be required for sync, only added for tusb
1090 * this indirectly necessitates requirement of t_avdp_r and
1091 * t_avdp_w instead of having a single t_avdp
1092 */
1093 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1094 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1095 }
1096 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1097
1098 /* oe_on */
1099 temp = dev_t->t_oeasu; /* XXX: remove this ? */
1100 if (mux) {
1101 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1102 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1103 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1104 }
1105 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1106
1107 /* access */
1108 /* XXX: any scope for improvement ?, by combining oe_on
1109 * and clk_activation, need to check whether
1110 * access = clk_activation + round to sync clk ?
1111 */
1112 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1113 temp += gpmc_t->clk_activation;
1114 if (dev_t->cyc_oe)
1115 temp = max_t(u32, temp, gpmc_t->oe_on +
1116 gpmc_ticks_to_ps(dev_t->cyc_oe));
1117 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1118
1119 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1120 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1121
1122 /* rd_cycle */
1123 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1124 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1125 gpmc_t->access;
1126 /* XXX: barter t_ce_rdyz with t_cez_r ? */
1127 if (dev_t->t_ce_rdyz)
1128 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1129 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1130
1131 return 0;
1132}
1133
1134static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1135 struct gpmc_device_timings *dev_t,
1136 bool mux)
246da26d 1137{
246da26d
AM		 1138 u32 temp;
1139
1140 /* adv_wr_off */
1141 temp = dev_t->t_avdp_w;
1142 if (mux) {
1143 temp = max_t(u32, temp,
1144 gpmc_t->clk_activation + dev_t->t_avdh);
1145 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1146 }
1147 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1148
1149 /* wr_data_mux_bus */
1150 temp = max_t(u32, dev_t->t_weasu,
1151 gpmc_t->clk_activation + dev_t->t_rdyo);
1152 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1153 * and in that case remember to handle we_on properly
1154 */
1155 if (mux) {
1156 temp = max_t(u32, temp,
1157 gpmc_t->adv_wr_off + dev_t->t_aavdh);
1158 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1159 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1160 }
1161 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1162
1163 /* we_on */
1164 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1165 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1166 else
1167 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1168
1169 /* wr_access */
1170 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1171 gpmc_t->wr_access = gpmc_t->access;
1172
1173 /* we_off */
1174 temp = gpmc_t->we_on + dev_t->t_wpl;
1175 temp = max_t(u32, temp,
1176 gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1177 temp = max_t(u32, temp,
1178 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1179 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1180
1181 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1182 dev_t->t_wph);
1183
1184 /* wr_cycle */
1185 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1186 temp += gpmc_t->wr_access;
1187 /* XXX: barter t_ce_rdyz with t_cez_w ? */
1188 if (dev_t->t_ce_rdyz)
1189 temp = max_t(u32, temp,
1190 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1191 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1192
1193 return 0;
1194}
1195
1196static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1197 struct gpmc_device_timings *dev_t,
1198 bool mux)
246da26d 1199{
246da26d
AM		 1200 u32 temp;
1201
1202 /* adv_rd_off */
1203 temp = dev_t->t_avdp_r;
1204 if (mux)
1205 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1206 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1207
1208 /* oe_on */
1209 temp = dev_t->t_oeasu;
1210 if (mux)
1211 temp = max_t(u32, temp,
1212 gpmc_t->adv_rd_off + dev_t->t_aavdh);
1213 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1214
1215 /* access */
1216 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1217 gpmc_t->oe_on + dev_t->t_oe);
1218 temp = max_t(u32, temp,
1219 gpmc_t->cs_on + dev_t->t_ce);
1220 temp = max_t(u32, temp,
1221 gpmc_t->adv_on + dev_t->t_aa);
1222 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1223
1224 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1225 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1226
1227 /* rd_cycle */
1228 temp = max_t(u32, dev_t->t_rd_cycle,
1229 gpmc_t->cs_rd_off + dev_t->t_cez_r);
1230 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1231 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1232
1233 return 0;
1234}
1235
1236static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1237 struct gpmc_device_timings *dev_t,
1238 bool mux)
246da26d 1239{
246da26d
AM		 1240 u32 temp;
1241
1242 /* adv_wr_off */
1243 temp = dev_t->t_avdp_w;
1244 if (mux)
1245 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1246 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1247
1248 /* wr_data_mux_bus */
1249 temp = dev_t->t_weasu;
1250 if (mux) {
1251 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1252 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1253 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1254 }
1255 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1256
1257 /* we_on */
1258 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1259 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1260 else
1261 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1262
1263 /* we_off */
1264 temp = gpmc_t->we_on + dev_t->t_wpl;
1265 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1266
1267 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1268 dev_t->t_wph);
1269
1270 /* wr_cycle */
1271 temp = max_t(u32, dev_t->t_wr_cycle,
1272 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1273 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1274
1275 return 0;
1276}
1277
1278static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1279 struct gpmc_device_timings *dev_t)
1280{
1281 u32 temp;
1282
1283 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1284 gpmc_get_fclk_period();
1285
1286 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1287 dev_t->t_bacc,
1288 gpmc_t->sync_clk);
1289
1290 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1291 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1292
1293 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1294 return 0;
1295
1296 if (dev_t->ce_xdelay)
1297 gpmc_t->bool_timings.cs_extra_delay = true;
1298 if (dev_t->avd_xdelay)
1299 gpmc_t->bool_timings.adv_extra_delay = true;
1300 if (dev_t->oe_xdelay)
1301 gpmc_t->bool_timings.oe_extra_delay = true;
1302 if (dev_t->we_xdelay)
1303 gpmc_t->bool_timings.we_extra_delay = true;
1304
1305 return 0;
1306}
1307
1308static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1309 struct gpmc_device_timings *dev_t,
1310 bool sync)
246da26d
AM		 1311{
1312 u32 temp;
1313
1314 /* cs_on */
1315 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1316
1317 /* adv_on */
1318 temp = dev_t->t_avdasu;
1319 if (dev_t->t_ce_avd)
1320 temp = max_t(u32, temp,
1321 gpmc_t->cs_on + dev_t->t_ce_avd);
1322 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1323
c3be5b45 1324 if (sync)
246da26d
AM		 1325 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1326
1327 return 0;
1328}
1329
1330/* TODO: remove this function once all peripherals are confirmed to
1331 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1332 * has to be modified to handle timings in ps instead of ns
1333*/
1334static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1335{
1336 t->cs_on /= 1000;
1337 t->cs_rd_off /= 1000;
1338 t->cs_wr_off /= 1000;
1339 t->adv_on /= 1000;
1340 t->adv_rd_off /= 1000;
1341 t->adv_wr_off /= 1000;
1342 t->we_on /= 1000;
1343 t->we_off /= 1000;
1344 t->oe_on /= 1000;
1345 t->oe_off /= 1000;
1346 t->page_burst_access /= 1000;
1347 t->access /= 1000;
1348 t->rd_cycle /= 1000;
1349 t->wr_cycle /= 1000;
1350 t->bus_turnaround /= 1000;
1351 t->cycle2cycle_delay /= 1000;
1352 t->wait_monitoring /= 1000;
1353 t->clk_activation /= 1000;
1354 t->wr_access /= 1000;
1355 t->wr_data_mux_bus /= 1000;
1356}
1357
1358int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1359 struct gpmc_settings *gpmc_s,
1360 struct gpmc_device_timings *dev_t)
246da26d 1361{
c3be5b45
JH		 1362 bool mux = false, sync = false;
1363
1364 if (gpmc_s) {
1365 mux = gpmc_s->mux_add_data ? true : false;
1366 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1367 }
1368
246da26d
AM		 1369 memset(gpmc_t, 0, sizeof(*gpmc_t));
1370
c3be5b45 1371 gpmc_calc_common_timings(gpmc_t, dev_t, sync);
246da26d 1372
c3be5b45
JH		 1373 if (gpmc_s && gpmc_s->sync_read)
1374 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
246da26d 1375 else
c3be5b45 1376 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
246da26d 1377
c3be5b45
JH		 1378 if (gpmc_s && gpmc_s->sync_write)
1379 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
246da26d 1380 else
c3be5b45 1381 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
246da26d
AM		 1382
1383 /* TODO: remove, see function definition */
1384 gpmc_convert_ps_to_ns(gpmc_t);
1385
1386 return 0;
1387}
1388
aa8d4767
JH		 1389/**
1390 * gpmc_cs_program_settings - programs non-timing related settings
1391 * @cs: GPMC chip-select to program
1392 * @p: pointer to GPMC settings structure
1393 *
1394 * Programs non-timing related settings for a GPMC chip-select, such as
1395 * bus-width, burst configuration, etc. Function should be called once
1396 * for each chip-select that is being used and must be called before
1397 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1398 * register will be initialised to zero by this function. Returns 0 on
1399 * success and appropriate negative error code on failure.
1400 */
1401int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1402{
1403 u32 config1;
1404
1405 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1406 pr_err("%s: invalid width %d!", __func__, p->device_width);
1407 return -EINVAL;
1408 }
1409
1410 /* Address-data multiplexing not supported for NAND devices */
1411 if (p->device_nand && p->mux_add_data) {
1412 pr_err("%s: invalid configuration!\n", __func__);
1413 return -EINVAL;
1414 }
1415
1416 if ((p->mux_add_data > GPMC_MUX_AD) ||
1417 ((p->mux_add_data == GPMC_MUX_AAD) &&
1418 !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1419 pr_err("%s: invalid multiplex configuration!\n", __func__);
1420 return -EINVAL;
1421 }
1422
1423 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1424 if (p->burst_read || p->burst_write) {
1425 switch (p->burst_len) {
1426 case GPMC_BURST_4:
1427 case GPMC_BURST_8:
1428 case GPMC_BURST_16:
1429 break;
1430 default:
1431 pr_err("%s: invalid page/burst-length (%d)\n",
1432 __func__, p->burst_len);
1433 return -EINVAL;
1434 }
1435 }
1436
2b54057c 1437 if (p->wait_pin > gpmc_nr_waitpins) {
aa8d4767
JH		 1438 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1439 return -EINVAL;
1440 }
1441
1442 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1443
1444 if (p->sync_read)
1445 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1446 if (p->sync_write)
1447 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1448 if (p->wait_on_read)
1449 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1450 if (p->wait_on_write)
1451 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1452 if (p->wait_on_read || p->wait_on_write)
1453 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1454 if (p->device_nand)
1455 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1456 if (p->mux_add_data)
1457 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1458 if (p->burst_read)
1459 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1460 if (p->burst_write)
1461 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1462 if (p->burst_read || p->burst_write) {
1463 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1464 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1465 }
1466
1467 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1468
1469 return 0;
1470}
1471
bc6b1e7b 1472#ifdef CONFIG_OF
31957609 1473static const struct of_device_id gpmc_dt_ids[] = {
bc6b1e7b
DM		 1474 { .compatible = "ti,omap2420-gpmc" },
1475 { .compatible = "ti,omap2430-gpmc" },
1476 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1477 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1478 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
1479 { }
1480};
1481MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1482
8c8a7771
JH		 1483/**
1484 * gpmc_read_settings_dt - read gpmc settings from device-tree
1485 * @np: pointer to device-tree node for a gpmc child device
1486 * @p: pointer to gpmc settings structure
1487 *
1488 * Reads the GPMC settings for a GPMC child device from device-tree and
1489 * stores them in the GPMC settings structure passed. The GPMC settings
1490 * structure is initialised to zero by this function and so any
1491 * previously stored settings will be cleared.
1492 */
1493void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1494{
1495 memset(p, 0, sizeof(struct gpmc_settings));
1496
1497 p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1498 p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
8c8a7771
JH		 1499 of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1500 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1501
1502 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1503 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1504 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1505 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1506 if (!p->burst_read && !p->burst_write)
1507 pr_warn("%s: page/burst-length set but not used!\n",
1508 __func__);
1509 }
1510
1511 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1512 p->wait_on_read = of_property_read_bool(np,
1513 "gpmc,wait-on-read");
1514 p->wait_on_write = of_property_read_bool(np,
1515 "gpmc,wait-on-write");
1516 if (!p->wait_on_read && !p->wait_on_write)
2b54057c
RQ		 1517 pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1518 __func__);
8c8a7771
JH		 1519 }
1520}
1521
bc6b1e7b
DM		 1522static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1523 struct gpmc_timings *gpmc_t)
1524{
d36b4cd4
JH		 1525 struct gpmc_bool_timings *p;
1526
1527 if (!np || !gpmc_t)
1528 return;
bc6b1e7b
DM		 1529
1530 memset(gpmc_t, 0, sizeof(*gpmc_t));
1531
1532 /* minimum clock period for syncronous mode */
d36b4cd4 1533 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
bc6b1e7b
DM		 1534
1535 /* chip select timtings */
d36b4cd4
JH		 1536 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1537 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1538 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
bc6b1e7b
DM		 1539
1540 /* ADV signal timings */
d36b4cd4
JH		 1541 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1542 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1543 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
bc6b1e7b
DM		 1544
1545 /* WE signal timings */
d36b4cd4
JH		 1546 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1547 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
bc6b1e7b
DM		 1548
1549 /* OE signal timings */
d36b4cd4
JH		 1550 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1551 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
bc6b1e7b
DM		 1552
1553 /* access and cycle timings */
d36b4cd4
JH		 1554 of_property_read_u32(np, "gpmc,page-burst-access-ns",
1555 &gpmc_t->page_burst_access);
1556 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1557 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1558 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1559 of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1560 &gpmc_t->bus_turnaround);
1561 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1562 &gpmc_t->cycle2cycle_delay);
1563 of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1564 &gpmc_t->wait_monitoring);
1565 of_property_read_u32(np, "gpmc,clk-activation-ns",
1566 &gpmc_t->clk_activation);
1567
1568 /* only applicable to OMAP3+ */
1569 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1570 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1571 &gpmc_t->wr_data_mux_bus);
1572
1573 /* bool timing parameters */
1574 p = &gpmc_t->bool_timings;
1575
1576 p->cycle2cyclediffcsen =
1577 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
1578 p->cycle2cyclesamecsen =
1579 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
1580 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
1581 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
1582 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
1583 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
1584 p->time_para_granularity =
1585 of_property_read_bool(np, "gpmc,time-para-granularity");
bc6b1e7b
DM		 1586}
1587
6b187b21 1588#if IS_ENABLED(CONFIG_MTD_NAND)
bc6b1e7b 1589
496c8a0b
MJ		 1590static const char * const nand_xfer_types[] = {
1591 [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
1592 [NAND_OMAP_POLLED] = "polled",
1593 [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma",
1594 [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq",
1595};
1596
bc6b1e7b
DM		 1597static int gpmc_probe_nand_child(struct platform_device *pdev,
1598 struct device_node *child)
1599{
1600 u32 val;
1601 const char *s;
1602 struct gpmc_timings gpmc_t;
1603 struct omap_nand_platform_data *gpmc_nand_data;
1604
1605 if (of_property_read_u32(child, "reg", &val) < 0) {
1606 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1607 child->full_name);
1608 return -ENODEV;
1609 }
1610
1611 gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
1612 GFP_KERNEL);
1613 if (!gpmc_nand_data)
1614 return -ENOMEM;
1615
1616 gpmc_nand_data->cs = val;
1617 gpmc_nand_data->of_node = child;
1618
ac65caf5
PG		 1619 /* Detect availability of ELM module */
1620 gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
1621 if (gpmc_nand_data->elm_of_node == NULL)
1622 gpmc_nand_data->elm_of_node =
1623 of_parse_phandle(child, "elm_id", 0);
ac65caf5
PG		 1624
1625 /* select ecc-scheme for NAND */
1626 if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
1627 pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
1628 return -ENODEV;
1629 }
a3e83f05
RQ		 1630
1631 if (!strcmp(s, "sw"))
1632 gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
1633 else if (!strcmp(s, "ham1") ||
1634 !strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
ac65caf5
PG		 1635 gpmc_nand_data->ecc_opt =
1636 OMAP_ECC_HAM1_CODE_HW;
1637 else if (!strcmp(s, "bch4"))
1638 if (gpmc_nand_data->elm_of_node)
1639 gpmc_nand_data->ecc_opt =
1640 OMAP_ECC_BCH4_CODE_HW;
1641 else
1642 gpmc_nand_data->ecc_opt =
1643 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
1644 else if (!strcmp(s, "bch8"))
1645 if (gpmc_nand_data->elm_of_node)
1646 gpmc_nand_data->ecc_opt =
1647 OMAP_ECC_BCH8_CODE_HW;
1648 else
1649 gpmc_nand_data->ecc_opt =
1650 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
27c9fd60 1651 else if (!strcmp(s, "bch16"))
1652 if (gpmc_nand_data->elm_of_node)
1653 gpmc_nand_data->ecc_opt =
1654 OMAP_ECC_BCH16_CODE_HW;
1655 else
1656 pr_err("%s: BCH16 requires ELM support\n", __func__);
ac65caf5
PG		 1657 else
1658 pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__);
bc6b1e7b 1659
ac65caf5 1660 /* select data transfer mode for NAND controller */
496c8a0b
MJ		 1661 if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
1662 for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++)
1663 if (!strcasecmp(s, nand_xfer_types[val])) {
1664 gpmc_nand_data->xfer_type = val;
1665 break;
1666 }
1667
fef775ca
EG		 1668 gpmc_nand_data->flash_bbt = of_get_nand_on_flash_bbt(child);
1669
bc6b1e7b
DM		 1670 val = of_get_nand_bus_width(child);
1671 if (val == 16)
1672 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
1673
1674 gpmc_read_timings_dt(child, &gpmc_t);
1675 gpmc_nand_init(gpmc_nand_data, &gpmc_t);
1676
1677 return 0;
1678}
1679#else
1680static int gpmc_probe_nand_child(struct platform_device *pdev,
1681 struct device_node *child)
1682{
1683 return 0;
1684}
1685#endif
1686
980386d2 1687#if IS_ENABLED(CONFIG_MTD_ONENAND)
75d3625e
EG		 1688static int gpmc_probe_onenand_child(struct platform_device *pdev,
1689 struct device_node *child)
1690{
1691 u32 val;
1692 struct omap_onenand_platform_data *gpmc_onenand_data;
1693
1694 if (of_property_read_u32(child, "reg", &val) < 0) {
1695 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1696 child->full_name);
1697 return -ENODEV;
1698 }
1699
1700 gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1701 GFP_KERNEL);
1702 if (!gpmc_onenand_data)
1703 return -ENOMEM;
1704
1705 gpmc_onenand_data->cs = val;
1706 gpmc_onenand_data->of_node = child;
1707 gpmc_onenand_data->dma_channel = -1;
1708
1709 if (!of_property_read_u32(child, "dma-channel", &val))
1710 gpmc_onenand_data->dma_channel = val;
1711
1712 gpmc_onenand_init(gpmc_onenand_data);
1713
1714 return 0;
1715}
1716#else
1717static int gpmc_probe_onenand_child(struct platform_device *pdev,
1718 struct device_node *child)
1719{
1720 return 0;
1721}
1722#endif
1723
cdd6928c 1724/**
3af91cf7 1725 * gpmc_probe_generic_child - configures the gpmc for a child device
cdd6928c 1726 * @pdev: pointer to gpmc platform device
3af91cf7 1727 * @child: pointer to device-tree node for child device
cdd6928c 1728 *
3af91cf7 1729 * Allocates and configures a GPMC chip-select for a child device.
cdd6928c
JH		 1730 * Returns 0 on success and appropriate negative error code on failure.
1731 */
3af91cf7 1732static int gpmc_probe_generic_child(struct platform_device *pdev,
cdd6928c
JH		 1733 struct device_node *child)
1734{
1735 struct gpmc_settings gpmc_s;
1736 struct gpmc_timings gpmc_t;
1737 struct resource res;
1738 unsigned long base;
9ed7a776 1739 const char *name;
cdd6928c 1740 int ret, cs;
e378d22b 1741 u32 val;
cdd6928c
JH		 1742
1743 if (of_property_read_u32(child, "reg", &cs) < 0) {
1744 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1745 child->full_name);
1746 return -ENODEV;
1747 }
1748
1749 if (of_address_to_resource(child, 0, &res) < 0) {
1750 dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1751 child->full_name);
1752 return -ENODEV;
1753 }
1754
9ed7a776
TL		 1755 /*
1756 * Check if we have multiple instances of the same device
1757 * on a single chip select. If so, use the already initialized
1758 * timings.
1759 */
1760 name = gpmc_cs_get_name(cs);
1761 if (name && child->name && of_node_cmp(child->name, name) == 0)
1762 goto no_timings;
1763
cdd6928c
JH		 1764 ret = gpmc_cs_request(cs, resource_size(&res), &base);
1765 if (ret < 0) {
1766 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
1767 return ret;
1768 }
9ed7a776 1769 gpmc_cs_set_name(cs, child->name);
cdd6928c 1770
35ac051e
TL		 1771 gpmc_read_settings_dt(child, &gpmc_s);
1772 gpmc_read_timings_dt(child, &gpmc_t);
cdd6928c 1773
fd4446f2
TL		 1774 /*
1775 * For some GPMC devices we still need to rely on the bootloader
35ac051e
TL		 1776 * timings because the devices can be connected via FPGA.
1777 * REVISIT: Add timing support from slls644g.pdf.
fd4446f2 1778 */
35ac051e
TL		 1779 if (!gpmc_t.cs_rd_off) {
1780 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
1781 cs);
1782 gpmc_cs_show_timings(cs,
1783 "please add GPMC bootloader timings to .dts");
fd4446f2
TL		 1784 goto no_timings;
1785 }
1786
4cf27d2e
RQ		 1787 /* CS must be disabled while making changes to gpmc configuration */
1788 gpmc_cs_disable_mem(cs);
1789
cdd6928c
JH		 1790 /*
1791 * FIXME: gpmc_cs_request() will map the CS to an arbitary
1792 * location in the gpmc address space. When booting with
1793 * device-tree we want the NOR flash to be mapped to the
1794 * location specified in the device-tree blob. So remap the
1795 * CS to this location. Once DT migration is complete should
1796 * just make gpmc_cs_request() map a specific address.
1797 */
1798 ret = gpmc_cs_remap(cs, res.start);
1799 if (ret < 0) {
f70bf2a3
FE		 1800 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
1801 cs, &res.start);
cdd6928c
JH		 1802 goto err;
1803 }
1804
cdd6928c
JH		 1805 ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
1806 if (ret < 0)
1807 goto err;
1808
1809 ret = gpmc_cs_program_settings(cs, &gpmc_s);
1810 if (ret < 0)
1811 goto err;
1812
7604baf3
RQ		 1813 ret = gpmc_cs_set_timings(cs, &gpmc_t);
1814 if (ret) {
1815 dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
1816 child->name);
1817 goto err;
1818 }
cdd6928c 1819
e378d22b
RQ		 1820 /* Clear limited address i.e. enable A26-A11 */
1821 val = gpmc_read_reg(GPMC_CONFIG);
1822 val &= ~GPMC_CONFIG_LIMITEDADDRESS;
1823 gpmc_write_reg(GPMC_CONFIG, val);
1824
4cf27d2e
RQ		 1825 /* Enable CS region */
1826 gpmc_cs_enable_mem(cs);
cdd6928c 1827
fd4446f2 1828no_timings:
b1dc1ca9
RA		 1829
1830 /* create platform device, NULL on error or when disabled */
1831 if (!of_platform_device_create(child, NULL, &pdev->dev))
1832 goto err_child_fail;
1833
1834 /* is child a common bus? */
1835 if (of_match_node(of_default_bus_match_table, child))
1836 /* create children and other common bus children */
1837 if (of_platform_populate(child, of_default_bus_match_table,
1838 NULL, &pdev->dev))
1839 goto err_child_fail;
1840
1841 return 0;
1842
1843err_child_fail:
cdd6928c
JH		 1844
1845 dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
e8ffd6fd 1846 ret = -ENODEV;
cdd6928c
JH		 1847
1848err:
1849 gpmc_cs_free(cs);
1850
1851 return ret;
1852}
1853
bc6b1e7b
DM		 1854static int gpmc_probe_dt(struct platform_device *pdev)
1855{
1856 int ret;
1857 struct device_node *child;
1858 const struct of_device_id *of_id =
1859 of_match_device(gpmc_dt_ids, &pdev->dev);
1860
1861 if (!of_id)
1862 return 0;
1863
f34f3716
GP		 1864 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
1865 &gpmc_cs_num);
1866 if (ret < 0) {
1867 pr_err("%s: number of chip-selects not defined\n", __func__);
1868 return ret;
1869 } else if (gpmc_cs_num < 1) {
1870 pr_err("%s: all chip-selects are disabled\n", __func__);
1871 return -EINVAL;
1872 } else if (gpmc_cs_num > GPMC_CS_NUM) {
1873 pr_err("%s: number of supported chip-selects cannot be > %d\n",
1874 __func__, GPMC_CS_NUM);
1875 return -EINVAL;
1876 }
1877
9f833156
JH		 1878 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
1879 &gpmc_nr_waitpins);
1880 if (ret < 0) {
1881 pr_err("%s: number of wait pins not found!\n", __func__);
1882 return ret;
1883 }
1884
68e2eb53 1885 for_each_available_child_of_node(pdev->dev.of_node, child) {
bc6b1e7b 1886
f2b09f67
JMC		 1887 if (!child->name)
1888 continue;
cdd6928c 1889
f2b09f67
JMC		 1890 if (of_node_cmp(child->name, "nand") == 0)
1891 ret = gpmc_probe_nand_child(pdev, child);
1892 else if (of_node_cmp(child->name, "onenand") == 0)
1893 ret = gpmc_probe_onenand_child(pdev, child);
1894 else if (of_node_cmp(child->name, "ethernet") == 0 ||
fd4446f2
TL		 1895 of_node_cmp(child->name, "nor") == 0 ||
1896 of_node_cmp(child->name, "uart") == 0)
f2b09f67 1897 ret = gpmc_probe_generic_child(pdev, child);
cdd6928c 1898
b327b362
JMC		 1899 if (WARN(ret < 0, "%s: probing gpmc child %s failed\n",
1900 __func__, child->full_name))
5330dc16 1901 of_node_put(child);
5330dc16
JMC		 1902 }
1903
bc6b1e7b
DM		 1904 return 0;
1905}
1906#else
1907static int gpmc_probe_dt(struct platform_device *pdev)
1908{
1909 return 0;
1910}
1911#endif
1912
351a102d 1913static int gpmc_probe(struct platform_device *pdev)
4bbbc1ad 1914{
8119024e 1915 int rc;
6b6c32fc 1916 u32 l;
da496873 1917 struct resource *res;
4bbbc1ad 1918
da496873
AM		 1919 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1920 if (res == NULL)
1921 return -ENOENT;
8d08436d 1922
da496873
AM		 1923 phys_base = res->start;
1924 mem_size = resource_size(res);
fd1dc87d 1925
5857bd98
TR		 1926 gpmc_base = devm_ioremap_resource(&pdev->dev, res);
1927 if (IS_ERR(gpmc_base))
1928 return PTR_ERR(gpmc_base);
da496873
AM		 1929
1930 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1931 if (res == NULL)
1932 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
1933 else
1934 gpmc_irq = res->start;
1935
8bf9be56 1936 gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
da496873 1937 if (IS_ERR(gpmc_l3_clk)) {
8bf9be56 1938 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
da496873
AM		 1939 gpmc_irq = 0;
1940 return PTR_ERR(gpmc_l3_clk);
fd1dc87d
PW		 1941 }
1942
8bf9be56
RQ		 1943 if (!clk_get_rate(gpmc_l3_clk)) {
1944 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
1945 return -EINVAL;
1946 }
1947
b3f5525c 1948 pm_runtime_enable(&pdev->dev);
1949 pm_runtime_get_sync(&pdev->dev);
1daa8c1d 1950
da496873
AM		 1951 gpmc_dev = &pdev->dev;
1952
4bbbc1ad 1953 l = gpmc_read_reg(GPMC_REVISION);
aa8d4767
JH		 1954
1955 /*
1956 * FIXME: Once device-tree migration is complete the below flags
1957 * should be populated based upon the device-tree compatible
1958 * string. For now just use the IP revision. OMAP3+ devices have
1959 * the wr_access and wr_data_mux_bus register fields. OMAP4+
1960 * devices support the addr-addr-data multiplex protocol.
1961 *
1962 * GPMC IP revisions:
1963 * - OMAP24xx = 2.0
1964 * - OMAP3xxx = 5.0
1965 * - OMAP44xx/54xx/AM335x = 6.0
1966 */
da496873
AM		 1967 if (GPMC_REVISION_MAJOR(l) > 0x4)
1968 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
aa8d4767
JH		 1969 if (GPMC_REVISION_MAJOR(l) > 0x5)
1970 gpmc_capability |= GPMC_HAS_MUX_AAD;
da496873
AM		 1971 dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
1972 GPMC_REVISION_MINOR(l));
1973
84b00f0e 1974 gpmc_mem_init();
db97eb7d 1975
71856843 1976 if (gpmc_setup_irq() < 0)
da496873
AM		 1977 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
1978
f34f3716
GP		 1979 if (!pdev->dev.of_node) {
1980 gpmc_cs_num = GPMC_CS_NUM;
9f833156 1981 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
f34f3716 1982 }
9f833156 1983
bc6b1e7b
DM		 1984 rc = gpmc_probe_dt(pdev);
1985 if (rc < 0) {
b3f5525c 1986 pm_runtime_put_sync(&pdev->dev);
bc6b1e7b
DM		 1987 dev_err(gpmc_dev, "failed to probe DT parameters\n");
1988 return rc;
1989 }
1990
da496873
AM		 1991 return 0;
1992}
1993
351a102d 1994static int gpmc_remove(struct platform_device *pdev)
da496873
AM		 1995{
1996 gpmc_free_irq();
1997 gpmc_mem_exit();
b3f5525c 1998 pm_runtime_put_sync(&pdev->dev);
1999 pm_runtime_disable(&pdev->dev);
da496873
AM		 2000 gpmc_dev = NULL;
2001 return 0;
2002}
2003
b536dd41 2004#ifdef CONFIG_PM_SLEEP
2005static int gpmc_suspend(struct device *dev)
2006{
2007 omap3_gpmc_save_context();
2008 pm_runtime_put_sync(dev);
2009 return 0;
2010}
2011
2012static int gpmc_resume(struct device *dev)
2013{
2014 pm_runtime_get_sync(dev);
2015 omap3_gpmc_restore_context();
2016 return 0;
2017}
2018#endif
2019
2020static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2021
da496873
AM		 2022static struct platform_driver gpmc_driver = {
2023 .probe = gpmc_probe,
351a102d 2024 .remove = gpmc_remove,
da496873
AM		 2025 .driver = {
2026 .name = DEVICE_NAME,
bc6b1e7b 2027 .of_match_table = of_match_ptr(gpmc_dt_ids),
b536dd41 2028 .pm = &gpmc_pm_ops,
da496873
AM		 2029 },
2030};
2031
2032static __init int gpmc_init(void)
2033{
2034 return platform_driver_register(&gpmc_driver);
2035}
2036
2037static __exit void gpmc_exit(void)
2038{
2039 platform_driver_unregister(&gpmc_driver);
2040
db97eb7d 2041}
da496873 2042
a8612809 2043postcore_initcall(gpmc_init);
da496873 2044module_exit(gpmc_exit);
db97eb7d
SG		 2045
2046static irqreturn_t gpmc_handle_irq(int irq, void *dev)
2047{
6b6c32fc
AM		 2048 int i;
2049 u32 regval;
2050
2051 regval = gpmc_read_reg(GPMC_IRQSTATUS);
2052
2053 if (!regval)
2054 return IRQ_NONE;
2055
2056 for (i = 0; i < GPMC_NR_IRQ; i++)
2057 if (regval & gpmc_client_irq[i].bitmask)
2058 generic_handle_irq(gpmc_client_irq[i].irq);
db97eb7d 2059
6b6c32fc 2060 gpmc_write_reg(GPMC_IRQSTATUS, regval);
db97eb7d
SG		 2061
2062 return IRQ_HANDLED;
4bbbc1ad 2063}
a2d3e7ba 2064
a2d3e7ba
RN		 2065static struct omap3_gpmc_regs gpmc_context;
2066
b2fa3b7c 2067void omap3_gpmc_save_context(void)
a2d3e7ba
RN		 2068{
2069 int i;
b2fa3b7c 2070
a2d3e7ba
RN		 2071 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2072 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2073 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2074 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2075 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2076 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2077 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
f34f3716 2078 for (i = 0; i < gpmc_cs_num; i++) {
a2d3e7ba
RN		 2079 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2080 if (gpmc_context.cs_context[i].is_valid) {
2081 gpmc_context.cs_context[i].config1 =
2082 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2083 gpmc_context.cs_context[i].config2 =
2084 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2085 gpmc_context.cs_context[i].config3 =
2086 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2087 gpmc_context.cs_context[i].config4 =
2088 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2089 gpmc_context.cs_context[i].config5 =
2090 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2091 gpmc_context.cs_context[i].config6 =
2092 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2093 gpmc_context.cs_context[i].config7 =
2094 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2095 }
2096 }
2097}
2098
b2fa3b7c 2099void omap3_gpmc_restore_context(void)
a2d3e7ba
RN		 2100{
2101 int i;
b2fa3b7c 2102
a2d3e7ba
RN		 2103 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2104 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2105 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2106 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2107 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2108 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2109 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
f34f3716 2110 for (i = 0; i < gpmc_cs_num; i++) {
a2d3e7ba
RN		 2111 if (gpmc_context.cs_context[i].is_valid) {
2112 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2113 gpmc_context.cs_context[i].config1);
2114 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2115 gpmc_context.cs_context[i].config2);
2116 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2117 gpmc_context.cs_context[i].config3);
2118 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2119 gpmc_context.cs_context[i].config4);
2120 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2121 gpmc_context.cs_context[i].config5);
2122 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2123 gpmc_context.cs_context[i].config6);
2124 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2125 gpmc_context.cs_context[i].config7);
2126 }
2127 }
2128}
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