[mirror_ubuntu-bionic-kernel.git] / drivers / memory / tegra / tegra114.c

/*
 * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/of.h>
#include <linux/mm.h>

#include <dt-bindings/memory/tegra114-mc.h>

#include "mc.h"

static const struct tegra_mc_client tegra114_mc_clients[] = {
	{
		.id = 0x00,
		.name = "ptcr",
		.swgroup = TEGRA_SWGROUP_PTC,
	}, {
		.id = 0x01,
		.name = "display0a",
		.swgroup = TEGRA_SWGROUP_DC,
		.smmu = {
			.reg = 0x228,
			.bit = 1,
		},
		.la = {
			.reg = 0x2e8,
			.shift = 0,
			.mask = 0xff,
			.def = 0x4e,
		},
	}, {
		.id = 0x02,
		.name = "display0ab",
		.swgroup = TEGRA_SWGROUP_DCB,
		.smmu = {
			.reg = 0x228,
			.bit = 2,
		},
		.la = {
			.reg = 0x2f4,
			.shift = 0,
			.mask = 0xff,
			.def = 0x4e,
		},
	}, {
		.id = 0x03,
		.name = "display0b",
		.swgroup = TEGRA_SWGROUP_DC,
		.smmu = {
			.reg = 0x228,
			.bit = 3,
		},
		.la = {
			.reg = 0x2e8,
			.shift = 16,
			.mask = 0xff,
			.def = 0x4e,
		},
	}, {
		.id = 0x04,
		.name = "display0bb",
		.swgroup = TEGRA_SWGROUP_DCB,
		.smmu = {
			.reg = 0x228,
			.bit = 4,
		},
		.la = {
			.reg = 0x2f4,
			.shift = 16,
			.mask = 0xff,
			.def = 0x4e,
		},
	}, {
		.id = 0x05,
		.name = "display0c",
		.swgroup = TEGRA_SWGROUP_DC,
		.smmu = {
			.reg = 0x228,
			.bit = 5,
		},
		.la = {
			.reg = 0x2ec,
			.shift = 0,
			.mask = 0xff,
			.def = 0x4e,
		},
	}, {
		.id = 0x06,
		.name = "display0cb",
		.swgroup = TEGRA_SWGROUP_DCB,
		.smmu = {
			.reg = 0x228,
			.bit = 6,
		},
		.la = {
			.reg = 0x2f8,
			.shift = 0,
			.mask = 0xff,
			.def = 0x4e,
		},
	}, {
		.id = 0x09,
		.name = "eppup",
		.swgroup = TEGRA_SWGROUP_EPP,
		.smmu = {
			.reg = 0x228,
			.bit = 9,
		},
		.la = {
			.reg = 0x300,
			.shift = 0,
			.mask = 0xff,
			.def = 0x33,
		},
	}, {
		.id = 0x0a,
		.name = "g2pr",
		.swgroup = TEGRA_SWGROUP_G2,
		.smmu = {
			.reg = 0x228,
			.bit = 10,
		},
		.la = {
			.reg = 0x308,
			.shift = 0,
			.mask = 0xff,
			.def = 0x09,
		},
	}, {
		.id = 0x0b,
		.name = "g2sr",
		.swgroup = TEGRA_SWGROUP_G2,
		.smmu = {
			.reg = 0x228,
			.bit = 11,
		},
		.la = {
			.reg = 0x308,
			.shift = 16,
			.mask = 0xff,
			.def = 0x09,
		},
	}, {
		.id = 0x0f,
		.name = "avpcarm7r",
		.swgroup = TEGRA_SWGROUP_AVPC,
		.smmu = {
			.reg = 0x228,
			.bit = 15,
		},
		.la = {
			.reg = 0x2e4,
			.shift = 0,
			.mask = 0xff,
			.def = 0x04,
		},
	}, {
		.id = 0x10,
		.name = "displayhc",
		.swgroup = TEGRA_SWGROUP_DC,
		.smmu = {
			.reg = 0x228,
			.bit = 16,
		},
		.la = {
			.reg = 0x2f0,
			.shift = 0,
			.mask = 0xff,
			.def = 0x68,
		},
	}, {
		.id = 0x11,
		.name = "displayhcb",
		.swgroup = TEGRA_SWGROUP_DCB,
		.smmu = {
			.reg = 0x228,
			.bit = 17,
		},
		.la = {
			.reg = 0x2fc,
			.shift = 0,
			.mask = 0xff,
			.def = 0x68,
		},
	}, {
		.id = 0x12,
		.name = "fdcdrd",
		.swgroup = TEGRA_SWGROUP_NV,
		.smmu = {
			.reg = 0x228,
			.bit = 18,
		},
		.la = {
			.reg = 0x334,
			.shift = 0,
			.mask = 0xff,
			.def = 0x0c,
		},
	}, {
		.id = 0x13,
		.name = "fdcdrd2",
		.swgroup = TEGRA_SWGROUP_NV,
		.smmu = {
			.reg = 0x228,
			.bit = 19,
		},
		.la = {
			.reg = 0x33c,
			.shift = 0,
			.mask = 0xff,
			.def = 0x0c,
		},
	}, {
		.id = 0x14,
		.name = "g2dr",
		.swgroup = TEGRA_SWGROUP_G2,
		.smmu = {
			.reg = 0x228,
			.bit = 20,
		},
		.la = {
			.reg = 0x30c,
			.shift = 0,
			.mask = 0xff,
			.def = 0x0a,
		},
	}, {
		.id = 0x15,
		.name = "hdar",
		.swgroup = TEGRA_SWGROUP_HDA,
		.smmu = {
			.reg = 0x228,
			.bit = 21,
		},
		.la = {
			.reg = 0x318,
			.shift = 0,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x16,
		.name = "host1xdmar",
		.swgroup = TEGRA_SWGROUP_HC,
		.smmu = {
			.reg = 0x228,
			.bit = 22,
		},
		.la = {
			.reg = 0x310,
			.shift = 0,
			.mask = 0xff,
			.def = 0x10,
		},
	}, {
		.id = 0x17,
		.name = "host1xr",
		.swgroup = TEGRA_SWGROUP_HC,
		.smmu = {
			.reg = 0x228,
			.bit = 23,
		},
		.la = {
			.reg = 0x310,
			.shift = 16,
			.mask = 0xff,
			.def = 0xa5,
		},
	}, {
		.id = 0x18,
		.name = "idxsrd",
		.swgroup = TEGRA_SWGROUP_NV,
		.smmu = {
			.reg = 0x228,
			.bit = 24,
		},
		.la = {
			.reg = 0x334,
			.shift = 16,
			.mask = 0xff,
			.def = 0x0b,
		},
	}, {
		.id = 0x1c,
		.name = "msencsrd",
		.swgroup = TEGRA_SWGROUP_MSENC,
		.smmu = {
			.reg = 0x228,
			.bit = 28,
		},
		.la = {
			.reg = 0x328,
			.shift = 0,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x1d,
		.name = "ppcsahbdmar",
		.swgroup = TEGRA_SWGROUP_PPCS,
		.smmu = {
			.reg = 0x228,
			.bit = 29,
		},
		.la = {
			.reg = 0x344,
			.shift = 0,
			.mask = 0xff,
			.def = 0x50,
		},
	}, {
		.id = 0x1e,
		.name = "ppcsahbslvr",
		.swgroup = TEGRA_SWGROUP_PPCS,
		.smmu = {
			.reg = 0x228,
			.bit = 30,
		},
		.la = {
			.reg = 0x344,
			.shift = 16,
			.mask = 0xff,
			.def = 0xe8,
		},
	}, {
		.id = 0x20,
		.name = "texl2srd",
		.swgroup = TEGRA_SWGROUP_NV,
		.smmu = {
			.reg = 0x22c,
			.bit = 0,
		},
		.la = {
			.reg = 0x338,
			.shift = 0,
			.mask = 0xff,
			.def = 0x0c,
		},
	}, {
		.id = 0x22,
		.name = "vdebsevr",
		.swgroup = TEGRA_SWGROUP_VDE,
		.smmu = {
			.reg = 0x22c,
			.bit = 2,
		},
		.la = {
			.reg = 0x354,
			.shift = 0,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x23,
		.name = "vdember",
		.swgroup = TEGRA_SWGROUP_VDE,
		.smmu = {
			.reg = 0x22c,
			.bit = 3,
		},
		.la = {
			.reg = 0x354,
			.shift = 16,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x24,
		.name = "vdemcer",
		.swgroup = TEGRA_SWGROUP_VDE,
		.smmu = {
			.reg = 0x22c,
			.bit = 4,
		},
		.la = {
			.reg = 0x358,
			.shift = 0,
			.mask = 0xff,
			.def = 0xb8,
		},
	}, {
		.id = 0x25,
		.name = "vdetper",
		.swgroup = TEGRA_SWGROUP_VDE,
		.smmu = {
			.reg = 0x22c,
			.bit = 5,
		},
		.la = {
			.reg = 0x358,
			.shift = 16,
			.mask = 0xff,
			.def = 0xee,
		},
	}, {
		.id = 0x26,
		.name = "mpcorelpr",
		.swgroup = TEGRA_SWGROUP_MPCORELP,
		.la = {
			.reg = 0x324,
			.shift = 0,
			.mask = 0xff,
			.def = 0x04,
		},
	}, {
		.id = 0x27,
		.name = "mpcorer",
		.swgroup = TEGRA_SWGROUP_MPCORE,
		.la = {
			.reg = 0x320,
			.shift = 0,
			.mask = 0xff,
			.def = 0x04,
		},
	}, {
		.id = 0x28,
		.name = "eppu",
		.swgroup = TEGRA_SWGROUP_EPP,
		.smmu = {
			.reg = 0x22c,
			.bit = 8,
		},
		.la = {
			.reg = 0x300,
			.shift = 16,
			.mask = 0xff,
			.def = 0x33,
		},
	}, {
		.id = 0x29,
		.name = "eppv",
		.swgroup = TEGRA_SWGROUP_EPP,
		.smmu = {
			.reg = 0x22c,
			.bit = 9,
		},
		.la = {
			.reg = 0x304,
			.shift = 0,
			.mask = 0xff,
			.def = 0x6c,
		},
	}, {
		.id = 0x2a,
		.name = "eppy",
		.swgroup = TEGRA_SWGROUP_EPP,
		.smmu = {
			.reg = 0x22c,
			.bit = 10,
		},
		.la = {
			.reg = 0x304,
			.shift = 16,
			.mask = 0xff,
			.def = 0x6c,
		},
	}, {
		.id = 0x2b,
		.name = "msencswr",
		.swgroup = TEGRA_SWGROUP_MSENC,
		.smmu = {
			.reg = 0x22c,
			.bit = 11,
		},
		.la = {
			.reg = 0x328,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x2c,
		.name = "viwsb",
		.swgroup = TEGRA_SWGROUP_VI,
		.smmu = {
			.reg = 0x22c,
			.bit = 12,
		},
		.la = {
			.reg = 0x364,
			.shift = 0,
			.mask = 0xff,
			.def = 0x47,
		},
	}, {
		.id = 0x2d,
		.name = "viwu",
		.swgroup = TEGRA_SWGROUP_VI,
		.smmu = {
			.reg = 0x22c,
			.bit = 13,
		},
		.la = {
			.reg = 0x368,
			.shift = 0,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x2e,
		.name = "viwv",
		.swgroup = TEGRA_SWGROUP_VI,
		.smmu = {
			.reg = 0x22c,
			.bit = 14,
		},
		.la = {
			.reg = 0x368,
			.shift = 16,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x2f,
		.name = "viwy",
		.swgroup = TEGRA_SWGROUP_VI,
		.smmu = {
			.reg = 0x22c,
			.bit = 15,
		},
		.la = {
			.reg = 0x36c,
			.shift = 0,
			.mask = 0xff,
			.def = 0x47,
		},
	}, {
		.id = 0x30,
		.name = "g2dw",
		.swgroup = TEGRA_SWGROUP_G2,
		.smmu = {
			.reg = 0x22c,
			.bit = 16,
		},
		.la = {
			.reg = 0x30c,
			.shift = 16,
			.mask = 0xff,
			.def = 0x9,
		},
	}, {
		.id = 0x32,
		.name = "avpcarm7w",
		.swgroup = TEGRA_SWGROUP_AVPC,
		.smmu = {
			.reg = 0x22c,
			.bit = 18,
		},
		.la = {
			.reg = 0x2e4,
			.shift = 16,
			.mask = 0xff,
			.def = 0x0e,
		},
	}, {
		.id = 0x33,
		.name = "fdcdwr",
		.swgroup = TEGRA_SWGROUP_NV,
		.smmu = {
			.reg = 0x22c,
			.bit = 19,
		},
		.la = {
			.reg = 0x338,
			.shift = 16,
			.mask = 0xff,
			.def = 0x10,
		},
	}, {
		.id = 0x34,
		.name = "fdcwr2",
		.swgroup = TEGRA_SWGROUP_NV,
		.smmu = {
			.reg = 0x22c,
			.bit = 20,
		},
		.la = {
			.reg = 0x340,
			.shift = 0,
			.mask = 0xff,
			.def = 0x10,
		},
	}, {
		.id = 0x35,
		.name = "hdaw",
		.swgroup = TEGRA_SWGROUP_HDA,
		.smmu = {
			.reg = 0x22c,
			.bit = 21,
		},
		.la = {
			.reg = 0x318,
			.shift = 16,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x36,
		.name = "host1xw",
		.swgroup = TEGRA_SWGROUP_HC,
		.smmu = {
			.reg = 0x22c,
			.bit = 22,
		},
		.la = {
			.reg = 0x314,
			.shift = 0,
			.mask = 0xff,
			.def = 0x25,
		},
	}, {
		.id = 0x37,
		.name = "ispw",
		.swgroup = TEGRA_SWGROUP_ISP,
		.smmu = {
			.reg = 0x22c,
			.bit = 23,
		},
		.la = {
			.reg = 0x31c,
			.shift = 0,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x38,
		.name = "mpcorelpw",
		.swgroup = TEGRA_SWGROUP_MPCORELP,
		.la = {
			.reg = 0x324,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x39,
		.name = "mpcorew",
		.swgroup = TEGRA_SWGROUP_MPCORE,
		.la = {
			.reg = 0x320,
			.shift = 16,
			.mask = 0xff,
			.def = 0x0e,
		},
	}, {
		.id = 0x3b,
		.name = "ppcsahbdmaw",
		.swgroup = TEGRA_SWGROUP_PPCS,
		.smmu = {
			.reg = 0x22c,
			.bit = 27,
		},
		.la = {
			.reg = 0x348,
			.shift = 0,
			.mask = 0xff,
			.def = 0xa5,
		},
	}, {
		.id = 0x3c,
		.name = "ppcsahbslvw",
		.swgroup = TEGRA_SWGROUP_PPCS,
		.smmu = {
			.reg = 0x22c,
			.bit = 28,
		},
		.la = {
			.reg = 0x348,
			.shift = 16,
			.mask = 0xff,
			.def = 0xe8,
		},
	}, {
		.id = 0x3e,
		.name = "vdebsevw",
		.swgroup = TEGRA_SWGROUP_VDE,
		.smmu = {
			.reg = 0x22c,
			.bit = 30,
		},
		.la = {
			.reg = 0x35c,
			.shift = 0,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x3f,
		.name = "vdedbgw",
		.swgroup = TEGRA_SWGROUP_VDE,
		.smmu = {
			.reg = 0x22c,
			.bit = 31,
		},
		.la = {
			.reg = 0x35c,
			.shift = 16,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x40,
		.name = "vdembew",
		.swgroup = TEGRA_SWGROUP_VDE,
		.smmu = {
			.reg = 0x230,
			.bit = 0,
		},
		.la = {
			.reg = 0x360,
			.shift = 0,
			.mask = 0xff,
			.def = 0x89,
		},
	}, {
		.id = 0x41,
		.name = "vdetpmw",
		.swgroup = TEGRA_SWGROUP_VDE,
		.smmu = {
			.reg = 0x230,
			.bit = 1,
		},
		.la = {
			.reg = 0x360,
			.shift = 16,
			.mask = 0xff,
			.def = 0x59,
		},
	}, {
		.id = 0x4a,
		.name = "xusb_hostr",
		.swgroup = TEGRA_SWGROUP_XUSB_HOST,
		.smmu = {
			.reg = 0x230,
			.bit = 10,
		},
		.la = {
			.reg = 0x37c,
			.shift = 0,
			.mask = 0xff,
			.def = 0xa5,
		},
	}, {
		.id = 0x4b,
		.name = "xusb_hostw",
		.swgroup = TEGRA_SWGROUP_XUSB_HOST,
		.smmu = {
			.reg = 0x230,
			.bit = 11,
		},
		.la = {
			.reg = 0x37c,
			.shift = 16,
			.mask = 0xff,
			.def = 0xa5,
		},
	}, {
		.id = 0x4c,
		.name = "xusb_devr",
		.swgroup = TEGRA_SWGROUP_XUSB_DEV,
		.smmu = {
			.reg = 0x230,
			.bit = 12,
		},
		.la = {
			.reg = 0x380,
			.shift = 0,
			.mask = 0xff,
			.def = 0xa5,
		},
	}, {
		.id = 0x4d,
		.name = "xusb_devw",
		.swgroup = TEGRA_SWGROUP_XUSB_DEV,
		.smmu = {
			.reg = 0x230,
			.bit = 13,
		},
		.la = {
			.reg = 0x380,
			.shift = 16,
			.mask = 0xff,
			.def = 0xa5,
		},
	}, {
		.id = 0x4e,
		.name = "fdcdwr3",
		.swgroup = TEGRA_SWGROUP_NV,
		.smmu = {
			.reg = 0x230,
			.bit = 14,
		},
		.la = {
			.reg = 0x388,
			.shift = 0,
			.mask = 0xff,
			.def = 0x10,
		},
	}, {
		.id = 0x4f,
		.name = "fdcdrd3",
		.swgroup = TEGRA_SWGROUP_NV,
		.smmu = {
			.reg = 0x230,
			.bit = 15,
		},
		.la = {
			.reg = 0x384,
			.shift = 0,
			.mask = 0xff,
			.def = 0x0c,
		},
	}, {
		.id = 0x50,
		.name = "fdcwr4",
		.swgroup = TEGRA_SWGROUP_NV,
		.smmu = {
			.reg = 0x230,
			.bit = 16,
		},
		.la = {
			.reg = 0x388,
			.shift = 16,
			.mask = 0xff,
			.def = 0x10,
		},
	}, {
		.id = 0x51,
		.name = "fdcrd4",
		.swgroup = TEGRA_SWGROUP_NV,
		.smmu = {
			.reg = 0x230,
			.bit = 17,
		},
		.la = {
			.reg = 0x384,
			.shift = 16,
			.mask = 0xff,
			.def = 0x0c,
		},
	}, {
		.id = 0x52,
		.name = "emucifr",
		.swgroup = TEGRA_SWGROUP_EMUCIF,
		.la = {
			.reg = 0x38c,
			.shift = 0,
			.mask = 0xff,
			.def = 0x04,
		},
	}, {
		.id = 0x53,
		.name = "emucifw",
		.swgroup = TEGRA_SWGROUP_EMUCIF,
		.la = {
			.reg = 0x38c,
			.shift = 16,
			.mask = 0xff,
			.def = 0x0e,
		},
	}, {
		.id = 0x54,
		.name = "tsecsrd",
		.swgroup = TEGRA_SWGROUP_TSEC,
		.smmu = {
			.reg = 0x230,
			.bit = 20,
		},
		.la = {
			.reg = 0x390,
			.shift = 0,
			.mask = 0xff,
			.def = 0x50,
		},
	}, {
		.id = 0x55,
		.name = "tsecswr",
		.swgroup = TEGRA_SWGROUP_TSEC,
		.smmu = {
			.reg = 0x230,
			.bit = 21,
		},
		.la = {
			.reg = 0x390,
			.shift = 16,
			.mask = 0xff,
			.def = 0x50,
		},
	},
};

static const struct tegra_smmu_swgroup tegra114_swgroups[] = {
	{ .name = "dc",        .swgroup = TEGRA_SWGROUP_DC,        .reg = 0x240 },
	{ .name = "dcb",       .swgroup = TEGRA_SWGROUP_DCB,       .reg = 0x244 },
	{ .name = "epp",       .swgroup = TEGRA_SWGROUP_EPP,       .reg = 0x248 },
	{ .name = "g2",        .swgroup = TEGRA_SWGROUP_G2,        .reg = 0x24c },
	{ .name = "avpc",      .swgroup = TEGRA_SWGROUP_AVPC,      .reg = 0x23c },
	{ .name = "nv",        .swgroup = TEGRA_SWGROUP_NV,        .reg = 0x268 },
	{ .name = "hda",       .swgroup = TEGRA_SWGROUP_HDA,       .reg = 0x254 },
	{ .name = "hc",        .swgroup = TEGRA_SWGROUP_HC,        .reg = 0x250 },
	{ .name = "msenc",     .swgroup = TEGRA_SWGROUP_MSENC,     .reg = 0x264 },
	{ .name = "ppcs",      .swgroup = TEGRA_SWGROUP_PPCS,      .reg = 0x270 },
	{ .name = "vde",       .swgroup = TEGRA_SWGROUP_VDE,       .reg = 0x27c },
	{ .name = "vi",        .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },
	{ .name = "isp",       .swgroup = TEGRA_SWGROUP_ISP,       .reg = 0x258 },
	{ .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
	{ .name = "xusb_dev",  .swgroup = TEGRA_SWGROUP_XUSB_DEV,  .reg = 0x28c },
	{ .name = "tsec",      .swgroup = TEGRA_SWGROUP_TSEC,      .reg = 0x294 },
};

static const struct tegra_smmu_soc tegra114_smmu_soc = {
	.clients = tegra114_mc_clients,
	.num_clients = ARRAY_SIZE(tegra114_mc_clients),
	.swgroups = tegra114_swgroups,
	.num_swgroups = ARRAY_SIZE(tegra114_swgroups),
	.supports_round_robin_arbitration = false,
	.supports_request_limit = false,
	.num_tlb_lines = 32,
	.num_asids = 4,
};

const struct tegra_mc_soc tegra114_mc_soc = {
	.clients = tegra114_mc_clients,
	.num_clients = ARRAY_SIZE(tegra114_mc_clients),
	.num_address_bits = 32,
	.atom_size = 32,
	.client_id_mask = 0x7f,
	.smmu = &tegra114_smmu_soc,
};
Commit	Line	Data
89184651 TR	1	/*
	2	* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	#include <linux/of.h>
	10	#include <linux/mm.h>
	11
89184651 TR	12	#include <dt-bindings/memory/tegra114-mc.h>
	13
	14	#include "mc.h"
	15
	16	static const struct tegra_mc_client tegra114_mc_clients[] = {
	17	{
	18	.id = 0x00,
	19	.name = "ptcr",
	20	.swgroup = TEGRA_SWGROUP_PTC,
	21	}, {
	22	.id = 0x01,
	23	.name = "display0a",
	24	.swgroup = TEGRA_SWGROUP_DC,
	25	.smmu = {
	26	.reg = 0x228,
	27	.bit = 1,
	28	},
	29	.la = {
	30	.reg = 0x2e8,
	31	.shift = 0,
	32	.mask = 0xff,
	33	.def = 0x4e,
	34	},
	35	}, {
	36	.id = 0x02,
	37	.name = "display0ab",
	38	.swgroup = TEGRA_SWGROUP_DCB,
	39	.smmu = {
	40	.reg = 0x228,
	41	.bit = 2,
	42	},
	43	.la = {
	44	.reg = 0x2f4,
	45	.shift = 0,
	46	.mask = 0xff,
	47	.def = 0x4e,
	48	},
	49	}, {
	50	.id = 0x03,
	51	.name = "display0b",
	52	.swgroup = TEGRA_SWGROUP_DC,
	53	.smmu = {
	54	.reg = 0x228,
	55	.bit = 3,
	56	},
	57	.la = {
	58	.reg = 0x2e8,
	59	.shift = 16,
	60	.mask = 0xff,
	61	.def = 0x4e,
	62	},
	63	}, {
	64	.id = 0x04,
	65	.name = "display0bb",
	66	.swgroup = TEGRA_SWGROUP_DCB,
	67	.smmu = {
	68	.reg = 0x228,
	69	.bit = 4,
	70	},
	71	.la = {
	72	.reg = 0x2f4,
	73	.shift = 16,
	74	.mask = 0xff,
	75	.def = 0x4e,
76	},
77	}, {
78	.id = 0x05,
79	.name = "display0c",
80	.swgroup = TEGRA_SWGROUP_DC,
81	.smmu = {
82	.reg = 0x228,
83	.bit = 5,
84	},
85	.la = {
86	.reg = 0x2ec,
87	.shift = 0,
88	.mask = 0xff,
89	.def = 0x4e,
90	},
91	}, {
92	.id = 0x06,
93	.name = "display0cb",
94	.swgroup = TEGRA_SWGROUP_DCB,
95	.smmu = {
96	.reg = 0x228,
97	.bit = 6,
98	},
99	.la = {
100	.reg = 0x2f8,
101	.shift = 0,
102	.mask = 0xff,
103	.def = 0x4e,
104	},
105	}, {
106	.id = 0x09,
107	.name = "eppup",
108	.swgroup = TEGRA_SWGROUP_EPP,
109	.smmu = {
110	.reg = 0x228,
111	.bit = 9,
112	},
113	.la = {
114	.reg = 0x300,
115	.shift = 0,
116	.mask = 0xff,
117	.def = 0x33,
118	},
119	}, {
120	.id = 0x0a,
121	.name = "g2pr",
122	.swgroup = TEGRA_SWGROUP_G2,
123	.smmu = {
124	.reg = 0x228,
125	.bit = 10,
126	},
127	.la = {
128	.reg = 0x308,
129	.shift = 0,
130	.mask = 0xff,
131	.def = 0x09,
132	},
133	}, {
134	.id = 0x0b,
135	.name = "g2sr",
136	.swgroup = TEGRA_SWGROUP_G2,
137	.smmu = {
138	.reg = 0x228,
139	.bit = 11,
140	},
141	.la = {
142	.reg = 0x308,
143	.shift = 16,
144	.mask = 0xff,
145	.def = 0x09,
146	},
147	}, {
148	.id = 0x0f,
149	.name = "avpcarm7r",
150	.swgroup = TEGRA_SWGROUP_AVPC,
151	.smmu = {
152	.reg = 0x228,
153	.bit = 15,
154	},
155	.la = {
156	.reg = 0x2e4,
157	.shift = 0,
158	.mask = 0xff,
159	.def = 0x04,
160	},
161	}, {
162	.id = 0x10,
163	.name = "displayhc",
164	.swgroup = TEGRA_SWGROUP_DC,
165	.smmu = {
166	.reg = 0x228,
167	.bit = 16,
168	},
169	.la = {
170	.reg = 0x2f0,
171	.shift = 0,
172	.mask = 0xff,
173	.def = 0x68,
174	},
175	}, {
176	.id = 0x11,
177	.name = "displayhcb",
178	.swgroup = TEGRA_SWGROUP_DCB,
179	.smmu = {
180	.reg = 0x228,
181	.bit = 17,
182	},
183	.la = {
184	.reg = 0x2fc,
185	.shift = 0,
186	.mask = 0xff,
187	.def = 0x68,
188	},
189	}, {
190	.id = 0x12,
191	.name = "fdcdrd",
192	.swgroup = TEGRA_SWGROUP_NV,
193	.smmu = {
194	.reg = 0x228,
195	.bit = 18,
196	},
197	.la = {
198	.reg = 0x334,
199	.shift = 0,
200	.mask = 0xff,
201	.def = 0x0c,
202	},
203	}, {
204	.id = 0x13,
205	.name = "fdcdrd2",
206	.swgroup = TEGRA_SWGROUP_NV,
207	.smmu = {
208	.reg = 0x228,
209	.bit = 19,
210	},
211	.la = {
212	.reg = 0x33c,
213	.shift = 0,
214	.mask = 0xff,
215	.def = 0x0c,
216	},
217	}, {
218	.id = 0x14,
219	.name = "g2dr",
220	.swgroup = TEGRA_SWGROUP_G2,
221	.smmu = {
222	.reg = 0x228,
223	.bit = 20,
224	},
225	.la = {
226	.reg = 0x30c,
227	.shift = 0,
228	.mask = 0xff,
229	.def = 0x0a,
230	},
231	}, {
232	.id = 0x15,
233	.name = "hdar",
234	.swgroup = TEGRA_SWGROUP_HDA,
235	.smmu = {
236	.reg = 0x228,
237	.bit = 21,
238	},
239	.la = {
240	.reg = 0x318,
241	.shift = 0,
242	.mask = 0xff,
243	.def = 0xff,
244	},
245	}, {
246	.id = 0x16,
247	.name = "host1xdmar",
248	.swgroup = TEGRA_SWGROUP_HC,
249	.smmu = {
250	.reg = 0x228,
251	.bit = 22,
252	},
253	.la = {
254	.reg = 0x310,
255	.shift = 0,
256	.mask = 0xff,
257	.def = 0x10,
258	},
259	}, {
260	.id = 0x17,
261	.name = "host1xr",
262	.swgroup = TEGRA_SWGROUP_HC,
263	.smmu = {
264	.reg = 0x228,
265	.bit = 23,
266	},
267	.la = {
268	.reg = 0x310,
269	.shift = 16,
270	.mask = 0xff,
271	.def = 0xa5,
272	},
273	}, {
274	.id = 0x18,
275	.name = "idxsrd",
276	.swgroup = TEGRA_SWGROUP_NV,
277	.smmu = {
278	.reg = 0x228,
279	.bit = 24,
280	},
281	.la = {
282	.reg = 0x334,
283	.shift = 16,
284	.mask = 0xff,
285	.def = 0x0b,
286	},
287	}, {
288	.id = 0x1c,
289	.name = "msencsrd",
290	.swgroup = TEGRA_SWGROUP_MSENC,
291	.smmu = {
292	.reg = 0x228,
293	.bit = 28,
294	},
295	.la = {
296	.reg = 0x328,
297	.shift = 0,
298	.mask = 0xff,
299	.def = 0x80,
300	},
301	}, {
302	.id = 0x1d,
303	.name = "ppcsahbdmar",
304	.swgroup = TEGRA_SWGROUP_PPCS,
305	.smmu = {
306	.reg = 0x228,
307	.bit = 29,
308	},
309	.la = {
310	.reg = 0x344,
311	.shift = 0,
312	.mask = 0xff,
313	.def = 0x50,
314	},
315	}, {
316	.id = 0x1e,
317	.name = "ppcsahbslvr",
318	.swgroup = TEGRA_SWGROUP_PPCS,
319	.smmu = {
320	.reg = 0x228,
321	.bit = 30,
322	},
323	.la = {
324	.reg = 0x344,
325	.shift = 16,
326	.mask = 0xff,
327	.def = 0xe8,
328	},
329	}, {
330	.id = 0x20,
331	.name = "texl2srd",
332	.swgroup = TEGRA_SWGROUP_NV,
333	.smmu = {
334	.reg = 0x22c,
335	.bit = 0,
336	},
337	.la = {
338	.reg = 0x338,
339	.shift = 0,
340	.mask = 0xff,
341	.def = 0x0c,
342	},
343	}, {
344	.id = 0x22,
345	.name = "vdebsevr",
346	.swgroup = TEGRA_SWGROUP_VDE,
347	.smmu = {
348	.reg = 0x22c,
349	.bit = 2,
350	},
351	.la = {
352	.reg = 0x354,
353	.shift = 0,
354	.mask = 0xff,
355	.def = 0xff,
356	},
357	}, {
358	.id = 0x23,
359	.name = "vdember",
360	.swgroup = TEGRA_SWGROUP_VDE,
361	.smmu = {
362	.reg = 0x22c,
363	.bit = 3,
364	},
365	.la = {
366	.reg = 0x354,
367	.shift = 16,
368	.mask = 0xff,
369	.def = 0xff,
370	},
371	}, {
372	.id = 0x24,
373	.name = "vdemcer",
374	.swgroup = TEGRA_SWGROUP_VDE,
375	.smmu = {
376	.reg = 0x22c,
377	.bit = 4,
378	},
379	.la = {
380	.reg = 0x358,
381	.shift = 0,
382	.mask = 0xff,
383	.def = 0xb8,
384	},
385	}, {
386	.id = 0x25,
387	.name = "vdetper",
388	.swgroup = TEGRA_SWGROUP_VDE,
389	.smmu = {
390	.reg = 0x22c,
391	.bit = 5,
392	},
393	.la = {
394	.reg = 0x358,
395	.shift = 16,
396	.mask = 0xff,
397	.def = 0xee,
398	},
399	}, {
400	.id = 0x26,
401	.name = "mpcorelpr",
402	.swgroup = TEGRA_SWGROUP_MPCORELP,
403	.la = {
404	.reg = 0x324,
405	.shift = 0,
406	.mask = 0xff,
407	.def = 0x04,
408	},
409	}, {
410	.id = 0x27,
411	.name = "mpcorer",
412	.swgroup = TEGRA_SWGROUP_MPCORE,
413	.la = {
414	.reg = 0x320,
415	.shift = 0,
416	.mask = 0xff,
417	.def = 0x04,
418	},
419	}, {
420	.id = 0x28,
421	.name = "eppu",
422	.swgroup = TEGRA_SWGROUP_EPP,
423	.smmu = {
424	.reg = 0x22c,
425	.bit = 8,
426	},
427	.la = {
428	.reg = 0x300,
429	.shift = 16,
430	.mask = 0xff,
431	.def = 0x33,
432	},
433	}, {
434	.id = 0x29,
435	.name = "eppv",
436	.swgroup = TEGRA_SWGROUP_EPP,
437	.smmu = {
438	.reg = 0x22c,
439	.bit = 9,
440	},
441	.la = {
442	.reg = 0x304,
443	.shift = 0,
444	.mask = 0xff,
445	.def = 0x6c,
446	},
447	}, {
448	.id = 0x2a,
449	.name = "eppy",
450	.swgroup = TEGRA_SWGROUP_EPP,
451	.smmu = {
452	.reg = 0x22c,
453	.bit = 10,
454	},
455	.la = {
456	.reg = 0x304,
457	.shift = 16,
458	.mask = 0xff,
459	.def = 0x6c,
460	},
461	}, {
462	.id = 0x2b,
463	.name = "msencswr",
464	.swgroup = TEGRA_SWGROUP_MSENC,
465	.smmu = {
466	.reg = 0x22c,
467	.bit = 11,
468	},
469	.la = {
470	.reg = 0x328,
471	.shift = 16,
472	.mask = 0xff,
473	.def = 0x80,
474	},
475	}, {
476	.id = 0x2c,
477	.name = "viwsb",
478	.swgroup = TEGRA_SWGROUP_VI,
479	.smmu = {
480	.reg = 0x22c,
481	.bit = 12,
482	},
483	.la = {
484	.reg = 0x364,
485	.shift = 0,
486	.mask = 0xff,
487	.def = 0x47,
488	},
489	}, {
490	.id = 0x2d,
491	.name = "viwu",
492	.swgroup = TEGRA_SWGROUP_VI,
493	.smmu = {
494	.reg = 0x22c,
495	.bit = 13,
496	},
497	.la = {
498	.reg = 0x368,
499	.shift = 0,
500	.mask = 0xff,
501	.def = 0xff,
502	},
503	}, {
504	.id = 0x2e,
505	.name = "viwv",
506	.swgroup = TEGRA_SWGROUP_VI,
507	.smmu = {
508	.reg = 0x22c,
509	.bit = 14,
510	},
511	.la = {
512	.reg = 0x368,
513	.shift = 16,
514	.mask = 0xff,
515	.def = 0xff,
516	},
517	}, {
518	.id = 0x2f,
519	.name = "viwy",
520	.swgroup = TEGRA_SWGROUP_VI,
521	.smmu = {
522	.reg = 0x22c,
523	.bit = 15,
524	},
525	.la = {
526	.reg = 0x36c,
527	.shift = 0,
528	.mask = 0xff,
529	.def = 0x47,
530	},
531	}, {
532	.id = 0x30,
533	.name = "g2dw",
534	.swgroup = TEGRA_SWGROUP_G2,
535	.smmu = {
536	.reg = 0x22c,
537	.bit = 16,
538	},
539	.la = {
540	.reg = 0x30c,
541	.shift = 16,
542	.mask = 0xff,
543	.def = 0x9,
544	},
545	}, {
546	.id = 0x32,
547	.name = "avpcarm7w",
548	.swgroup = TEGRA_SWGROUP_AVPC,
549	.smmu = {
550	.reg = 0x22c,
551	.bit = 18,
552	},
553	.la = {
554	.reg = 0x2e4,
555	.shift = 16,
556	.mask = 0xff,
557	.def = 0x0e,
558	},
559	}, {
560	.id = 0x33,
561	.name = "fdcdwr",
562	.swgroup = TEGRA_SWGROUP_NV,
563	.smmu = {
564	.reg = 0x22c,
565	.bit = 19,
566	},
567	.la = {
568	.reg = 0x338,
569	.shift = 16,
570	.mask = 0xff,
571	.def = 0x10,
572	},
573	}, {
574	.id = 0x34,
575	.name = "fdcwr2",
576	.swgroup = TEGRA_SWGROUP_NV,
577	.smmu = {
578	.reg = 0x22c,
579	.bit = 20,
580	},
581	.la = {
582	.reg = 0x340,
583	.shift = 0,
584	.mask = 0xff,
585	.def = 0x10,
586	},
587	}, {
588	.id = 0x35,
589	.name = "hdaw",
590	.swgroup = TEGRA_SWGROUP_HDA,
591	.smmu = {
592	.reg = 0x22c,
593	.bit = 21,
594	},
595	.la = {
596	.reg = 0x318,
597	.shift = 16,
598	.mask = 0xff,
599	.def = 0xff,
600	},
601	}, {
602	.id = 0x36,
603	.name = "host1xw",
604	.swgroup = TEGRA_SWGROUP_HC,
605	.smmu = {
606	.reg = 0x22c,
607	.bit = 22,
608	},
609	.la = {
610	.reg = 0x314,
611	.shift = 0,
612	.mask = 0xff,
613	.def = 0x25,
614	},
615	}, {
616	.id = 0x37,
617	.name = "ispw",
618	.swgroup = TEGRA_SWGROUP_ISP,
619	.smmu = {
620	.reg = 0x22c,
621	.bit = 23,
622	},
623	.la = {
624	.reg = 0x31c,
625	.shift = 0,
626	.mask = 0xff,
627	.def = 0xff,
628	},
629	}, {
630	.id = 0x38,
631	.name = "mpcorelpw",
632	.swgroup = TEGRA_SWGROUP_MPCORELP,
633	.la = {
634	.reg = 0x324,
635	.shift = 16,
636	.mask = 0xff,
637	.def = 0x80,
638	},
639	}, {
640	.id = 0x39,
641	.name = "mpcorew",
642	.swgroup = TEGRA_SWGROUP_MPCORE,
643	.la = {
644	.reg = 0x320,
645	.shift = 16,
646	.mask = 0xff,
647	.def = 0x0e,
648	},
649	}, {
650	.id = 0x3b,
651	.name = "ppcsahbdmaw",
652	.swgroup = TEGRA_SWGROUP_PPCS,
653	.smmu = {
654	.reg = 0x22c,
655	.bit = 27,
656	},
657	.la = {
658	.reg = 0x348,
659	.shift = 0,
660	.mask = 0xff,
661	.def = 0xa5,
662	},
663	}, {
664	.id = 0x3c,
665	.name = "ppcsahbslvw",
666	.swgroup = TEGRA_SWGROUP_PPCS,
667	.smmu = {
668	.reg = 0x22c,
669	.bit = 28,
670	},
671	.la = {
672	.reg = 0x348,
673	.shift = 16,
674	.mask = 0xff,
675	.def = 0xe8,
676	},
677	}, {
678	.id = 0x3e,
679	.name = "vdebsevw",
680	.swgroup = TEGRA_SWGROUP_VDE,
681	.smmu = {
682	.reg = 0x22c,
683	.bit = 30,
684	},
685	.la = {
686	.reg = 0x35c,
687	.shift = 0,
688	.mask = 0xff,
689	.def = 0xff,
690	},
691	}, {
692	.id = 0x3f,
693	.name = "vdedbgw",
694	.swgroup = TEGRA_SWGROUP_VDE,
695	.smmu = {
696	.reg = 0x22c,
697	.bit = 31,
698	},
699	.la = {
700	.reg = 0x35c,
701	.shift = 16,
702	.mask = 0xff,
703	.def = 0xff,
704	},
705	}, {
706	.id = 0x40,
707	.name = "vdembew",
708	.swgroup = TEGRA_SWGROUP_VDE,
709	.smmu = {
710	.reg = 0x230,
711	.bit = 0,
712	},
713	.la = {
714	.reg = 0x360,
715	.shift = 0,
716	.mask = 0xff,
717	.def = 0x89,
718	},
719	}, {
720	.id = 0x41,
721	.name = "vdetpmw",
722	.swgroup = TEGRA_SWGROUP_VDE,
723	.smmu = {
724	.reg = 0x230,
725	.bit = 1,
726	},
727	.la = {
728	.reg = 0x360,
729	.shift = 16,
730	.mask = 0xff,
731	.def = 0x59,
732	},
733	}, {
734	.id = 0x4a,
735	.name = "xusb_hostr",
736	.swgroup = TEGRA_SWGROUP_XUSB_HOST,
737	.smmu = {
738	.reg = 0x230,
739	.bit = 10,
740	},
741	.la = {
742	.reg = 0x37c,
743	.shift = 0,
744	.mask = 0xff,
745	.def = 0xa5,
746	},
747	}, {
748	.id = 0x4b,
749	.name = "xusb_hostw",
750	.swgroup = TEGRA_SWGROUP_XUSB_HOST,
751	.smmu = {
752	.reg = 0x230,
753	.bit = 11,
754	},
755	.la = {
756	.reg = 0x37c,
757	.shift = 16,
758	.mask = 0xff,
759	.def = 0xa5,
760	},
761	}, {
762	.id = 0x4c,
763	.name = "xusb_devr",
764	.swgroup = TEGRA_SWGROUP_XUSB_DEV,
765	.smmu = {
766	.reg = 0x230,
767	.bit = 12,
768	},
769	.la = {
770	.reg = 0x380,
771	.shift = 0,
772	.mask = 0xff,
773	.def = 0xa5,
774	},
775	}, {
776	.id = 0x4d,
777	.name = "xusb_devw",
778	.swgroup = TEGRA_SWGROUP_XUSB_DEV,
779	.smmu = {
780	.reg = 0x230,
781	.bit = 13,
782	},
783	.la = {
784	.reg = 0x380,
785	.shift = 16,
786	.mask = 0xff,
787	.def = 0xa5,
788	},
789	}, {
790	.id = 0x4e,
791	.name = "fdcdwr3",
792	.swgroup = TEGRA_SWGROUP_NV,
793	.smmu = {
794	.reg = 0x230,
795	.bit = 14,
796	},
797	.la = {
798	.reg = 0x388,
799	.shift = 0,
800	.mask = 0xff,
801	.def = 0x10,
802	},
803	}, {
804	.id = 0x4f,
805	.name = "fdcdrd3",
806	.swgroup = TEGRA_SWGROUP_NV,
807	.smmu = {
808	.reg = 0x230,
809	.bit = 15,
810	},
811	.la = {
812	.reg = 0x384,
813	.shift = 0,
814	.mask = 0xff,
815	.def = 0x0c,
816	},
817	}, {
818	.id = 0x50,
819	.name = "fdcwr4",
820	.swgroup = TEGRA_SWGROUP_NV,
821	.smmu = {
822	.reg = 0x230,
823	.bit = 16,
824	},
825	.la = {
826	.reg = 0x388,
827	.shift = 16,
828	.mask = 0xff,
829	.def = 0x10,
830	},
831	}, {
832	.id = 0x51,
833	.name = "fdcrd4",
834	.swgroup = TEGRA_SWGROUP_NV,
835	.smmu = {
836	.reg = 0x230,
837	.bit = 17,
838	},
839	.la = {
840	.reg = 0x384,
841	.shift = 16,
842	.mask = 0xff,
843	.def = 0x0c,
844	},
845	}, {
846	.id = 0x52,
847	.name = "emucifr",
848	.swgroup = TEGRA_SWGROUP_EMUCIF,
849	.la = {
850	.reg = 0x38c,
851	.shift = 0,
852	.mask = 0xff,
853	.def = 0x04,
854	},
855	}, {
856	.id = 0x53,
857	.name = "emucifw",
858	.swgroup = TEGRA_SWGROUP_EMUCIF,
859	.la = {
860	.reg = 0x38c,
861	.shift = 16,
862	.mask = 0xff,
863	.def = 0x0e,
864	},
865	}, {
866	.id = 0x54,
867	.name = "tsecsrd",
868	.swgroup = TEGRA_SWGROUP_TSEC,
869	.smmu = {
870	.reg = 0x230,
871	.bit = 20,
872	},
873	.la = {
874	.reg = 0x390,
875	.shift = 0,
876	.mask = 0xff,
877	.def = 0x50,
878	},
879	}, {
880	.id = 0x55,
881	.name = "tsecswr",
882	.swgroup = TEGRA_SWGROUP_TSEC,
883	.smmu = {
884	.reg = 0x230,
885	.bit = 21,
886	},
887	.la = {
888	.reg = 0x390,
889	.shift = 16,
890	.mask = 0xff,
891	.def = 0x50,
892	},
893	},
894	};
895
896	static const struct tegra_smmu_swgroup tegra114_swgroups[] = {
e660df07 TR	897	{ .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
	898	{ .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
	899	{ .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
	900	{ .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
	901	{ .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
	902	{ .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
	903	{ .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
	904	{ .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
	905	{ .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
	906	{ .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
	907	{ .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
	908	{ .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
	909	{ .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
	910	{ .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
	911	{ .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
	912	{ .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
89184651 TR	913	};
89184651 TR	914
89184651 TR	915	static const struct tegra_smmu_soc tegra114_smmu_soc = {
	916	.clients = tegra114_mc_clients,
	917	.num_clients = ARRAY_SIZE(tegra114_mc_clients),
	918	.swgroups = tegra114_swgroups,
	919	.num_swgroups = ARRAY_SIZE(tegra114_swgroups),
	920	.supports_round_robin_arbitration = false,
	921	.supports_request_limit = false,
11cec15b	922	.num_tlb_lines = 32,
89184651	923	.num_asids = 4,
89184651 TR	924	};
	925
	926	const struct tegra_mc_soc tegra114_mc_soc = {
	927	.clients = tegra114_mc_clients,
	928	.num_clients = ARRAY_SIZE(tegra114_mc_clients),
	929	.num_address_bits = 32,
	930	.atom_size = 32,
3c01cf3b	931	.client_id_mask = 0x7f,
89184651 TR	932	.smmu = &tegra114_smmu_soc,
89184651 TR	933	};