[mirror_ubuntu-bionic-kernel.git] / drivers / memory / tegra / tegra210.c

/*
 * Copyright (C) 2015 NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/of.h>
#include <linux/mm.h>

#include <asm/cacheflush.h>

#include <dt-bindings/memory/tegra210-mc.h>

#include "mc.h"

static const struct tegra_mc_client tegra210_mc_clients[] = {
	{
		.id = 0x00,
		.name = "ptcr",
		.swgroup = TEGRA_SWGROUP_PTC,
	}, {
		.id = 0x01,
		.name = "display0a",
		.swgroup = TEGRA_SWGROUP_DC,
		.smmu = {
			.reg = 0x228,
			.bit = 1,
		},
		.la = {
			.reg = 0x2e8,
			.shift = 0,
			.mask = 0xff,
			.def = 0xc2,
		},
	}, {
		.id = 0x02,
		.name = "display0ab",
		.swgroup = TEGRA_SWGROUP_DCB,
		.smmu = {
			.reg = 0x228,
			.bit = 2,
		},
		.la = {
			.reg = 0x2f4,
			.shift = 0,
			.mask = 0xff,
			.def = 0xc6,
		},
	}, {
		.id = 0x03,
		.name = "display0b",
		.swgroup = TEGRA_SWGROUP_DC,
		.smmu = {
			.reg = 0x228,
			.bit = 3,
		},
		.la = {
			.reg = 0x2e8,
			.shift = 16,
			.mask = 0xff,
			.def = 0x50,
		},
	}, {
		.id = 0x04,
		.name = "display0bb",
		.swgroup = TEGRA_SWGROUP_DCB,
		.smmu = {
			.reg = 0x228,
			.bit = 4,
		},
		.la = {
			.reg = 0x2f4,
			.shift = 16,
			.mask = 0xff,
			.def = 0x50,
		},
	}, {
		.id = 0x05,
		.name = "display0c",
		.swgroup = TEGRA_SWGROUP_DC,
		.smmu = {
			.reg = 0x228,
			.bit = 5,
		},
		.la = {
			.reg = 0x2ec,
			.shift = 0,
			.mask = 0xff,
			.def = 0x50,
		},
	}, {
		.id = 0x06,
		.name = "display0cb",
		.swgroup = TEGRA_SWGROUP_DCB,
		.smmu = {
			.reg = 0x228,
			.bit = 6,
		},
		.la = {
			.reg = 0x2f8,
			.shift = 0,
			.mask = 0xff,
			.def = 0x50,
		},
	}, {
		.id = 0x0e,
		.name = "afir",
		.swgroup = TEGRA_SWGROUP_AFI,
		.smmu = {
			.reg = 0x228,
			.bit = 14,
		},
		.la = {
			.reg = 0x2e0,
			.shift = 0,
			.mask = 0xff,
			.def = 0x13,
		},
	}, {
		.id = 0x0f,
		.name = "avpcarm7r",
		.swgroup = TEGRA_SWGROUP_AVPC,
		.smmu = {
			.reg = 0x228,
			.bit = 15,
		},
		.la = {
			.reg = 0x2e4,
			.shift = 0,
			.mask = 0xff,
			.def = 0x04,
		},
	}, {
		.id = 0x10,
		.name = "displayhc",
		.swgroup = TEGRA_SWGROUP_DC,
		.smmu = {
			.reg = 0x228,
			.bit = 16,
		},
		.la = {
			.reg = 0x2f0,
			.shift = 0,
			.mask = 0xff,
			.def = 0x50,
		},
	}, {
		.id = 0x11,
		.name = "displayhcb",
		.swgroup = TEGRA_SWGROUP_DCB,
		.smmu = {
			.reg = 0x228,
			.bit = 17,
		},
		.la = {
			.reg = 0x2fc,
			.shift = 0,
			.mask = 0xff,
			.def = 0x50,
		},
	}, {
		.id = 0x15,
		.name = "hdar",
		.swgroup = TEGRA_SWGROUP_HDA,
		.smmu = {
			.reg = 0x228,
			.bit = 21,
		},
		.la = {
			.reg = 0x318,
			.shift = 0,
			.mask = 0xff,
			.def = 0x24,
		},
	}, {
		.id = 0x16,
		.name = "host1xdmar",
		.swgroup = TEGRA_SWGROUP_HC,
		.smmu = {
			.reg = 0x228,
			.bit = 22,
		},
		.la = {
			.reg = 0x310,
			.shift = 0,
			.mask = 0xff,
			.def = 0x1e,
		},
	}, {
		.id = 0x17,
		.name = "host1xr",
		.swgroup = TEGRA_SWGROUP_HC,
		.smmu = {
			.reg = 0x228,
			.bit = 23,
		},
		.la = {
			.reg = 0x310,
			.shift = 16,
			.mask = 0xff,
			.def = 0x50,
		},
	}, {
		.id = 0x1c,
		.name = "nvencsrd",
		.swgroup = TEGRA_SWGROUP_NVENC,
		.smmu = {
			.reg = 0x228,
			.bit = 28,
		},
		.la = {
			.reg = 0x328,
			.shift = 0,
			.mask = 0xff,
			.def = 0x23,
		},
	}, {
		.id = 0x1d,
		.name = "ppcsahbdmar",
		.swgroup = TEGRA_SWGROUP_PPCS,
		.smmu = {
			.reg = 0x228,
			.bit = 29,
		},
		.la = {
			.reg = 0x344,
			.shift = 0,
			.mask = 0xff,
			.def = 0x49,
		},
	}, {
		.id = 0x1e,
		.name = "ppcsahbslvr",
		.swgroup = TEGRA_SWGROUP_PPCS,
		.smmu = {
			.reg = 0x228,
			.bit = 30,
		},
		.la = {
			.reg = 0x344,
			.shift = 16,
			.mask = 0xff,
			.def = 0x1a,
		},
	}, {
		.id = 0x1f,
		.name = "satar",
		.swgroup = TEGRA_SWGROUP_SATA,
		.smmu = {
			.reg = 0x228,
			.bit = 31,
		},
		.la = {
			.reg = 0x350,
			.shift = 0,
			.mask = 0xff,
			.def = 0x65,
		},
	}, {
		.id = 0x27,
		.name = "mpcorer",
		.swgroup = TEGRA_SWGROUP_MPCORE,
		.la = {
			.reg = 0x320,
			.shift = 0,
			.mask = 0xff,
			.def = 0x04,
		},
	}, {
		.id = 0x2b,
		.name = "nvencswr",
		.swgroup = TEGRA_SWGROUP_NVENC,
		.smmu = {
			.reg = 0x22c,
			.bit = 11,
		},
		.la = {
			.reg = 0x328,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x31,
		.name = "afiw",
		.swgroup = TEGRA_SWGROUP_AFI,
		.smmu = {
			.reg = 0x22c,
			.bit = 17,
		},
		.la = {
			.reg = 0x2e0,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x32,
		.name = "avpcarm7w",
		.swgroup = TEGRA_SWGROUP_AVPC,
		.smmu = {
			.reg = 0x22c,
			.bit = 18,
		},
		.la = {
			.reg = 0x2e4,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x35,
		.name = "hdaw",
		.swgroup = TEGRA_SWGROUP_HDA,
		.smmu = {
			.reg = 0x22c,
			.bit = 21,
		},
		.la = {
			.reg = 0x318,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x36,
		.name = "host1xw",
		.swgroup = TEGRA_SWGROUP_HC,
		.smmu = {
			.reg = 0x22c,
			.bit = 22,
		},
		.la = {
			.reg = 0x314,
			.shift = 0,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x39,
		.name = "mpcorew",
		.swgroup = TEGRA_SWGROUP_MPCORE,
		.la = {
			.reg = 0x320,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x3b,
		.name = "ppcsahbdmaw",
		.swgroup = TEGRA_SWGROUP_PPCS,
		.smmu = {
			.reg = 0x22c,
			.bit = 27,
		},
		.la = {
			.reg = 0x348,
			.shift = 0,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x3c,
		.name = "ppcsahbslvw",
		.swgroup = TEGRA_SWGROUP_PPCS,
		.smmu = {
			.reg = 0x22c,
			.bit = 28,
		},
		.la = {
			.reg = 0x348,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x3d,
		.name = "sataw",
		.swgroup = TEGRA_SWGROUP_SATA,
		.smmu = {
			.reg = 0x22c,
			.bit = 29,
		},
		.la = {
			.reg = 0x350,
			.shift = 16,
			.mask = 0xff,
			.def = 0x65,
		},
	}, {
		.id = 0x44,
		.name = "ispra",
		.swgroup = TEGRA_SWGROUP_ISP2,
		.smmu = {
			.reg = 0x230,
			.bit = 4,
		},
		.la = {
			.reg = 0x370,
			.shift = 0,
			.mask = 0xff,
			.def = 0x18,
		},
	}, {
		.id = 0x46,
		.name = "ispwa",
		.swgroup = TEGRA_SWGROUP_ISP2,
		.smmu = {
			.reg = 0x230,
			.bit = 6,
		},
		.la = {
			.reg = 0x374,
			.shift = 0,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x47,
		.name = "ispwb",
		.swgroup = TEGRA_SWGROUP_ISP2,
		.smmu = {
			.reg = 0x230,
			.bit = 7,
		},
		.la = {
			.reg = 0x374,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x4a,
		.name = "xusb_hostr",
		.swgroup = TEGRA_SWGROUP_XUSB_HOST,
		.smmu = {
			.reg = 0x230,
			.bit = 10,
		},
		.la = {
			.reg = 0x37c,
			.shift = 0,
			.mask = 0xff,
			.def = 0x39,
		},
	}, {
		.id = 0x4b,
		.name = "xusb_hostw",
		.swgroup = TEGRA_SWGROUP_XUSB_HOST,
		.smmu = {
			.reg = 0x230,
			.bit = 11,
		},
		.la = {
			.reg = 0x37c,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x4c,
		.name = "xusb_devr",
		.swgroup = TEGRA_SWGROUP_XUSB_DEV,
		.smmu = {
			.reg = 0x230,
			.bit = 12,
		},
		.la = {
			.reg = 0x380,
			.shift = 0,
			.mask = 0xff,
			.def = 0x39,
		},
	}, {
		.id = 0x4d,
		.name = "xusb_devw",
		.swgroup = TEGRA_SWGROUP_XUSB_DEV,
		.smmu = {
			.reg = 0x230,
			.bit = 13,
		},
		.la = {
			.reg = 0x380,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x4e,
		.name = "isprab",
		.swgroup = TEGRA_SWGROUP_ISP2B,
		.smmu = {
			.reg = 0x230,
			.bit = 14,
		},
		.la = {
			.reg = 0x384,
			.shift = 0,
			.mask = 0xff,
			.def = 0x18,
		},
	}, {
		.id = 0x50,
		.name = "ispwab",
		.swgroup = TEGRA_SWGROUP_ISP2B,
		.smmu = {
			.reg = 0x230,
			.bit = 16,
		},
		.la = {
			.reg = 0x388,
			.shift = 0,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x51,
		.name = "ispwbb",
		.swgroup = TEGRA_SWGROUP_ISP2B,
		.smmu = {
			.reg = 0x230,
			.bit = 17,
		},
		.la = {
			.reg = 0x388,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x54,
		.name = "tsecsrd",
		.swgroup = TEGRA_SWGROUP_TSEC,
		.smmu = {
			.reg = 0x230,
			.bit = 20,
		},
		.la = {
			.reg = 0x390,
			.shift = 0,
			.mask = 0xff,
			.def = 0x9b,
		},
	}, {
		.id = 0x55,
		.name = "tsecswr",
		.swgroup = TEGRA_SWGROUP_TSEC,
		.smmu = {
			.reg = 0x230,
			.bit = 21,
		},
		.la = {
			.reg = 0x390,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x56,
		.name = "a9avpscr",
		.swgroup = TEGRA_SWGROUP_A9AVP,
		.smmu = {
			.reg = 0x230,
			.bit = 22,
		},
		.la = {
			.reg = 0x3a4,
			.shift = 0,
			.mask = 0xff,
			.def = 0x04,
		},
	}, {
		.id = 0x57,
		.name = "a9avpscw",
		.swgroup = TEGRA_SWGROUP_A9AVP,
		.smmu = {
			.reg = 0x230,
			.bit = 23,
		},
		.la = {
			.reg = 0x3a4,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x58,
		.name = "gpusrd",
		.swgroup = TEGRA_SWGROUP_GPU,
		.smmu = {
			/* read-only */
			.reg = 0x230,
			.bit = 24,
		},
		.la = {
			.reg = 0x3c8,
			.shift = 0,
			.mask = 0xff,
			.def = 0x1a,
		},
	}, {
		.id = 0x59,
		.name = "gpuswr",
		.swgroup = TEGRA_SWGROUP_GPU,
		.smmu = {
			/* read-only */
			.reg = 0x230,
			.bit = 25,
		},
		.la = {
			.reg = 0x3c8,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x5a,
		.name = "displayt",
		.swgroup = TEGRA_SWGROUP_DC,
		.smmu = {
			.reg = 0x230,
			.bit = 26,
		},
		.la = {
			.reg = 0x2f0,
			.shift = 16,
			.mask = 0xff,
			.def = 0x50,
		},
	}, {
		.id = 0x60,
		.name = "sdmmcra",
		.swgroup = TEGRA_SWGROUP_SDMMC1A,
		.smmu = {
			.reg = 0x234,
			.bit = 0,
		},
		.la = {
			.reg = 0x3b8,
			.shift = 0,
			.mask = 0xff,
			.def = 0x49,
		},
	}, {
		.id = 0x61,
		.name = "sdmmcraa",
		.swgroup = TEGRA_SWGROUP_SDMMC2A,
		.smmu = {
			.reg = 0x234,
			.bit = 1,
		},
		.la = {
			.reg = 0x3bc,
			.shift = 0,
			.mask = 0xff,
			.def = 0x49,
		},
	}, {
		.id = 0x62,
		.name = "sdmmcr",
		.swgroup = TEGRA_SWGROUP_SDMMC3A,
		.smmu = {
			.reg = 0x234,
			.bit = 2,
		},
		.la = {
			.reg = 0x3c0,
			.shift = 0,
			.mask = 0xff,
			.def = 0x49,
		},
	}, {
		.id = 0x63,
		.swgroup = TEGRA_SWGROUP_SDMMC4A,
		.name = "sdmmcrab",
		.smmu = {
			.reg = 0x234,
			.bit = 3,
		},
		.la = {
			.reg = 0x3c4,
			.shift = 0,
			.mask = 0xff,
			.def = 0x49,
		},
	}, {
		.id = 0x64,
		.name = "sdmmcwa",
		.swgroup = TEGRA_SWGROUP_SDMMC1A,
		.smmu = {
			.reg = 0x234,
			.bit = 4,
		},
		.la = {
			.reg = 0x3b8,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x65,
		.name = "sdmmcwaa",
		.swgroup = TEGRA_SWGROUP_SDMMC2A,
		.smmu = {
			.reg = 0x234,
			.bit = 5,
		},
		.la = {
			.reg = 0x3bc,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x66,
		.name = "sdmmcw",
		.swgroup = TEGRA_SWGROUP_SDMMC3A,
		.smmu = {
			.reg = 0x234,
			.bit = 6,
		},
		.la = {
			.reg = 0x3c0,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x67,
		.name = "sdmmcwab",
		.swgroup = TEGRA_SWGROUP_SDMMC4A,
		.smmu = {
			.reg = 0x234,
			.bit = 7,
		},
		.la = {
			.reg = 0x3c4,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x6c,
		.name = "vicsrd",
		.swgroup = TEGRA_SWGROUP_VIC,
		.smmu = {
			.reg = 0x234,
			.bit = 12,
		},
		.la = {
			.reg = 0x394,
			.shift = 0,
			.mask = 0xff,
			.def = 0x1a,
		},
	}, {
		.id = 0x6d,
		.name = "vicswr",
		.swgroup = TEGRA_SWGROUP_VIC,
		.smmu = {
			.reg = 0x234,
			.bit = 13,
		},
		.la = {
			.reg = 0x394,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x72,
		.name = "viw",
		.swgroup = TEGRA_SWGROUP_VI,
		.smmu = {
			.reg = 0x234,
			.bit = 18,
		},
		.la = {
			.reg = 0x398,
			.shift = 0,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x73,
		.name = "displayd",
		.swgroup = TEGRA_SWGROUP_DC,
		.smmu = {
			.reg = 0x234,
			.bit = 19,
		},
		.la = {
			.reg = 0x3c8,
			.shift = 0,
			.mask = 0xff,
			.def = 0x50,
		},
	}, {
		.id = 0x78,
		.name = "nvdecsrd",
		.swgroup = TEGRA_SWGROUP_NVDEC,
		.smmu = {
			.reg = 0x234,
			.bit = 24,
		},
		.la = {
			.reg = 0x3d8,
			.shift = 0,
			.mask = 0xff,
			.def = 0x23,
		},
	}, {
		.id = 0x79,
		.name = "nvdecswr",
		.swgroup = TEGRA_SWGROUP_NVDEC,
		.smmu = {
			.reg = 0x234,
			.bit = 25,
		},
		.la = {
			.reg = 0x3d8,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x7a,
		.name = "aper",
		.swgroup = TEGRA_SWGROUP_APE,
		.smmu = {
			.reg = 0x234,
			.bit = 26,
		},
		.la = {
			.reg = 0x3dc,
			.shift = 0,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x7b,
		.name = "apew",
		.swgroup = TEGRA_SWGROUP_APE,
		.smmu = {
			.reg = 0x234,
			.bit = 27,
		},
		.la = {
			.reg = 0x3dc,
			.shift = 0,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x7e,
		.name = "nvjpgsrd",
		.swgroup = TEGRA_SWGROUP_NVJPG,
		.smmu = {
			.reg = 0x234,
			.bit = 30,
		},
		.la = {
			.reg = 0x3e4,
			.shift = 0,
			.mask = 0xff,
			.def = 0x23,
		},
	}, {
		.id = 0x7f,
		.name = "nvjpgswr",
		.swgroup = TEGRA_SWGROUP_NVJPG,
		.smmu = {
			.reg = 0x234,
			.bit = 31,
		},
		.la = {
			.reg = 0x3e4,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x80,
		.name = "sesrd",
		.swgroup = TEGRA_SWGROUP_SE,
		.smmu = {
			.reg = 0xb98,
			.bit = 0,
		},
		.la = {
			.reg = 0x3e0,
			.shift = 0,
			.mask = 0xff,
			.def = 0x2e,
		},
	}, {
		.id = 0x81,
		.name = "seswr",
		.swgroup = TEGRA_SWGROUP_SE,
		.smmu = {
			.reg = 0xb98,
			.bit = 1,
		},
		.la = {
			.reg = 0xb98,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x82,
		.name = "axiapr",
		.swgroup = TEGRA_SWGROUP_AXIAP,
		.smmu = {
			.reg = 0xb98,
			.bit = 2,
		},
		.la = {
			.reg = 0x3a0,
			.shift = 0,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x83,
		.name = "axiapw",
		.swgroup = TEGRA_SWGROUP_AXIAP,
		.smmu = {
			.reg = 0xb98,
			.bit = 3,
		},
		.la = {
			.reg = 0x3a0,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x84,
		.name = "etrr",
		.swgroup = TEGRA_SWGROUP_ETR,
		.smmu = {
			.reg = 0xb98,
			.bit = 4,
		},
		.la = {
			.reg = 0x3ec,
			.shift = 0,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x85,
		.name = "etrw",
		.swgroup = TEGRA_SWGROUP_ETR,
		.smmu = {
			.reg = 0xb98,
			.bit = 5,
		},
		.la = {
			.reg = 0x3ec,
			.shift = 16,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x86,
		.name = "tsecsrdb",
		.swgroup = TEGRA_SWGROUP_TSECB,
		.smmu = {
			.reg = 0xb98,
			.bit = 6,
		},
		.la = {
			.reg = 0x3f0,
			.shift = 0,
			.mask = 0xff,
			.def = 0x9b,
		},
	}, {
		.id = 0x87,
		.name = "tsecswrb",
		.swgroup = TEGRA_SWGROUP_TSECB,
		.smmu = {
			.reg = 0xb98,
			.bit = 7,
		},
		.la = {
			.reg = 0x3f0,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x88,
		.name = "gpusrd2",
		.swgroup = TEGRA_SWGROUP_GPU,
		.smmu = {
			/* read-only */
			.reg = 0xb98,
			.bit = 8,
		},
		.la = {
			.reg = 0x3e8,
			.shift = 0,
			.mask = 0xff,
			.def = 0x1a,
		},
	}, {
		.id = 0x89,
		.name = "gpuswr2",
		.swgroup = TEGRA_SWGROUP_GPU,
		.smmu = {
			/* read-only */
			.reg = 0xb98,
			.bit = 9,
		},
		.la = {
			.reg = 0x3e8,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	},
};

static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
	{ .name = "dc",        .swgroup = TEGRA_SWGROUP_DC,        .reg = 0x240 },
	{ .name = "dcb",       .swgroup = TEGRA_SWGROUP_DCB,       .reg = 0x244 },
	{ .name = "afi",       .swgroup = TEGRA_SWGROUP_AFI,       .reg = 0x238 },
	{ .name = "avpc",      .swgroup = TEGRA_SWGROUP_AVPC,      .reg = 0x23c },
	{ .name = "hda",       .swgroup = TEGRA_SWGROUP_HDA,       .reg = 0x254 },
	{ .name = "hc",        .swgroup = TEGRA_SWGROUP_HC,        .reg = 0x250 },
	{ .name = "nvenc",     .swgroup = TEGRA_SWGROUP_NVENC,     .reg = 0x264 },
	{ .name = "ppcs",      .swgroup = TEGRA_SWGROUP_PPCS,      .reg = 0x270 },
	{ .name = "sata",      .swgroup = TEGRA_SWGROUP_SATA,      .reg = 0x274 },
	{ .name = "isp2",      .swgroup = TEGRA_SWGROUP_ISP2,      .reg = 0x258 },
	{ .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
	{ .name = "xusb_dev",  .swgroup = TEGRA_SWGROUP_XUSB_DEV,  .reg = 0x28c },
	{ .name = "isp2b",     .swgroup = TEGRA_SWGROUP_ISP2B,     .reg = 0xaa4 },
	{ .name = "tsec",      .swgroup = TEGRA_SWGROUP_TSEC,      .reg = 0x294 },
	{ .name = "a9avp",     .swgroup = TEGRA_SWGROUP_A9AVP,     .reg = 0x290 },
	{ .name = "gpu",       .swgroup = TEGRA_SWGROUP_GPU,       .reg = 0xaac },
	{ .name = "sdmmc1a",   .swgroup = TEGRA_SWGROUP_SDMMC1A,   .reg = 0xa94 },
	{ .name = "sdmmc2a",   .swgroup = TEGRA_SWGROUP_SDMMC2A,   .reg = 0xa98 },
	{ .name = "sdmmc3a",   .swgroup = TEGRA_SWGROUP_SDMMC3A,   .reg = 0xa9c },
	{ .name = "sdmmc4a",   .swgroup = TEGRA_SWGROUP_SDMMC4A,   .reg = 0xaa0 },
	{ .name = "vic",       .swgroup = TEGRA_SWGROUP_VIC,       .reg = 0x284 },
	{ .name = "vi",        .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },
	{ .name = "nvdec",     .swgroup = TEGRA_SWGROUP_NVDEC,     .reg = 0xab4 },
	{ .name = "ape",       .swgroup = TEGRA_SWGROUP_APE,       .reg = 0xab8 },
	{ .name = "nvjpg",     .swgroup = TEGRA_SWGROUP_NVJPG,     .reg = 0xac0 },
	{ .name = "se",        .swgroup = TEGRA_SWGROUP_SE,        .reg = 0xabc },
	{ .name = "axiap",     .swgroup = TEGRA_SWGROUP_AXIAP,     .reg = 0xacc },
	{ .name = "etr",       .swgroup = TEGRA_SWGROUP_ETR,       .reg = 0xad0 },
	{ .name = "tsecb",     .swgroup = TEGRA_SWGROUP_TSECB,     .reg = 0xad4 },
};

static const struct tegra_smmu_soc tegra210_smmu_soc = {
	.clients = tegra210_mc_clients,
	.num_clients = ARRAY_SIZE(tegra210_mc_clients),
	.swgroups = tegra210_swgroups,
	.num_swgroups = ARRAY_SIZE(tegra210_swgroups),
	.supports_round_robin_arbitration = true,
	.supports_request_limit = true,
	.num_tlb_lines = 32,
	.num_asids = 128,
};

const struct tegra_mc_soc tegra210_mc_soc = {
	.clients = tegra210_mc_clients,
	.num_clients = ARRAY_SIZE(tegra210_mc_clients),
	.num_address_bits = 34,
	.atom_size = 64,
	.client_id_mask = 0xff,
	.smmu = &tegra210_smmu_soc,
	.intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
		   MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
		   MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
};
Commit	Line	Data
588c43a7 TR	1	/*
	2	* Copyright (C) 2015 NVIDIA CORPORATION. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	#include <linux/of.h>
	10	#include <linux/mm.h>
	11
	12	#include <asm/cacheflush.h>
	13
	14	#include <dt-bindings/memory/tegra210-mc.h>
	15
	16	#include "mc.h"
	17
	18	static const struct tegra_mc_client tegra210_mc_clients[] = {
	19	{
	20	.id = 0x00,
	21	.name = "ptcr",
	22	.swgroup = TEGRA_SWGROUP_PTC,
	23	}, {
	24	.id = 0x01,
	25	.name = "display0a",
	26	.swgroup = TEGRA_SWGROUP_DC,
	27	.smmu = {
	28	.reg = 0x228,
	29	.bit = 1,
	30	},
	31	.la = {
	32	.reg = 0x2e8,
	33	.shift = 0,
	34	.mask = 0xff,
	35	.def = 0xc2,
	36	},
	37	}, {
	38	.id = 0x02,
	39	.name = "display0ab",
	40	.swgroup = TEGRA_SWGROUP_DCB,
	41	.smmu = {
	42	.reg = 0x228,
	43	.bit = 2,
	44	},
	45	.la = {
	46	.reg = 0x2f4,
	47	.shift = 0,
	48	.mask = 0xff,
	49	.def = 0xc6,
	50	},
	51	}, {
	52	.id = 0x03,
	53	.name = "display0b",
	54	.swgroup = TEGRA_SWGROUP_DC,
	55	.smmu = {
	56	.reg = 0x228,
	57	.bit = 3,
	58	},
	59	.la = {
	60	.reg = 0x2e8,
	61	.shift = 16,
	62	.mask = 0xff,
	63	.def = 0x50,
	64	},
65	}, {
66	.id = 0x04,
67	.name = "display0bb",
68	.swgroup = TEGRA_SWGROUP_DCB,
69	.smmu = {
70	.reg = 0x228,
71	.bit = 4,
72	},
73	.la = {
74	.reg = 0x2f4,
75	.shift = 16,
76	.mask = 0xff,
77	.def = 0x50,
78	},
79	}, {
80	.id = 0x05,
81	.name = "display0c",
82	.swgroup = TEGRA_SWGROUP_DC,
83	.smmu = {
84	.reg = 0x228,
85	.bit = 5,
86	},
87	.la = {
88	.reg = 0x2ec,
89	.shift = 0,
90	.mask = 0xff,
91	.def = 0x50,
92	},
93	}, {
94	.id = 0x06,
95	.name = "display0cb",
96	.swgroup = TEGRA_SWGROUP_DCB,
97	.smmu = {
98	.reg = 0x228,
99	.bit = 6,
100	},
101	.la = {
102	.reg = 0x2f8,
103	.shift = 0,
104	.mask = 0xff,
105	.def = 0x50,
106	},
107	}, {
108	.id = 0x0e,
109	.name = "afir",
110	.swgroup = TEGRA_SWGROUP_AFI,
111	.smmu = {
112	.reg = 0x228,
113	.bit = 14,
114	},
115	.la = {
116	.reg = 0x2e0,
117	.shift = 0,
118	.mask = 0xff,
119	.def = 0x13,
120	},
121	}, {
122	.id = 0x0f,
123	.name = "avpcarm7r",
124	.swgroup = TEGRA_SWGROUP_AVPC,
125	.smmu = {
126	.reg = 0x228,
127	.bit = 15,
128	},
129	.la = {
130	.reg = 0x2e4,
131	.shift = 0,
132	.mask = 0xff,
133	.def = 0x04,
134	},
135	}, {
136	.id = 0x10,
137	.name = "displayhc",
138	.swgroup = TEGRA_SWGROUP_DC,
139	.smmu = {
140	.reg = 0x228,
141	.bit = 16,
142	},
143	.la = {
144	.reg = 0x2f0,
145	.shift = 0,
146	.mask = 0xff,
147	.def = 0x50,
148	},
149	}, {
150	.id = 0x11,
151	.name = "displayhcb",
152	.swgroup = TEGRA_SWGROUP_DCB,
153	.smmu = {
154	.reg = 0x228,
155	.bit = 17,
156	},
157	.la = {
158	.reg = 0x2fc,
159	.shift = 0,
160	.mask = 0xff,
161	.def = 0x50,
162	},
163	}, {
164	.id = 0x15,
165	.name = "hdar",
166	.swgroup = TEGRA_SWGROUP_HDA,
167	.smmu = {
168	.reg = 0x228,
169	.bit = 21,
170	},
171	.la = {
172	.reg = 0x318,
173	.shift = 0,
174	.mask = 0xff,
175	.def = 0x24,
176	},
177	}, {
178	.id = 0x16,
179	.name = "host1xdmar",
180	.swgroup = TEGRA_SWGROUP_HC,
181	.smmu = {
182	.reg = 0x228,
183	.bit = 22,
184	},
185	.la = {
186	.reg = 0x310,
187	.shift = 0,
188	.mask = 0xff,
189	.def = 0x1e,
190	},
191	}, {
192	.id = 0x17,
193	.name = "host1xr",
194	.swgroup = TEGRA_SWGROUP_HC,
195	.smmu = {
196	.reg = 0x228,
197	.bit = 23,
198	},
199	.la = {
200	.reg = 0x310,
201	.shift = 16,
202	.mask = 0xff,
203	.def = 0x50,
204	},
205	}, {
206	.id = 0x1c,
207	.name = "nvencsrd",
208	.swgroup = TEGRA_SWGROUP_NVENC,
209	.smmu = {
210	.reg = 0x228,
211	.bit = 28,
212	},
213	.la = {
214	.reg = 0x328,
215	.shift = 0,
216	.mask = 0xff,
217	.def = 0x23,
218	},
219	}, {
220	.id = 0x1d,
221	.name = "ppcsahbdmar",
222	.swgroup = TEGRA_SWGROUP_PPCS,
223	.smmu = {
224	.reg = 0x228,
225	.bit = 29,
226	},
227	.la = {
228	.reg = 0x344,
229	.shift = 0,
230	.mask = 0xff,
231	.def = 0x49,
232	},
233	}, {
234	.id = 0x1e,
235	.name = "ppcsahbslvr",
236	.swgroup = TEGRA_SWGROUP_PPCS,
237	.smmu = {
238	.reg = 0x228,
239	.bit = 30,
240	},
241	.la = {
242	.reg = 0x344,
243	.shift = 16,
244	.mask = 0xff,
245	.def = 0x1a,
246	},
247	}, {
248	.id = 0x1f,
249	.name = "satar",
250	.swgroup = TEGRA_SWGROUP_SATA,
251	.smmu = {
252	.reg = 0x228,
253	.bit = 31,
254	},
255	.la = {
256	.reg = 0x350,
257	.shift = 0,
258	.mask = 0xff,
259	.def = 0x65,
260	},
261	}, {
262	.id = 0x27,
263	.name = "mpcorer",
264	.swgroup = TEGRA_SWGROUP_MPCORE,
265	.la = {
266	.reg = 0x320,
267	.shift = 0,
268	.mask = 0xff,
269	.def = 0x04,
270	},
271	}, {
272	.id = 0x2b,
273	.name = "nvencswr",
274	.swgroup = TEGRA_SWGROUP_NVENC,
275	.smmu = {
276	.reg = 0x22c,
277	.bit = 11,
278	},
279	.la = {
280	.reg = 0x328,
281	.shift = 16,
282	.mask = 0xff,
283	.def = 0x80,
284	},
285	}, {
286	.id = 0x31,
287	.name = "afiw",
288	.swgroup = TEGRA_SWGROUP_AFI,
289	.smmu = {
290	.reg = 0x22c,
291	.bit = 17,
292	},
293	.la = {
294	.reg = 0x2e0,
295	.shift = 16,
296	.mask = 0xff,
297	.def = 0x80,
298	},
299	}, {
300	.id = 0x32,
301	.name = "avpcarm7w",
302	.swgroup = TEGRA_SWGROUP_AVPC,
303	.smmu = {
304	.reg = 0x22c,
305	.bit = 18,
306	},
307	.la = {
308	.reg = 0x2e4,
309	.shift = 16,
310	.mask = 0xff,
311	.def = 0x80,
312	},
313	}, {
314	.id = 0x35,
315	.name = "hdaw",
316	.swgroup = TEGRA_SWGROUP_HDA,
317	.smmu = {
318	.reg = 0x22c,
319	.bit = 21,
320	},
321	.la = {
322	.reg = 0x318,
323	.shift = 16,
324	.mask = 0xff,
325	.def = 0x80,
326	},
327	}, {
328	.id = 0x36,
329	.name = "host1xw",
330	.swgroup = TEGRA_SWGROUP_HC,
331	.smmu = {
332	.reg = 0x22c,
333	.bit = 22,
334	},
335	.la = {
336	.reg = 0x314,
337	.shift = 0,
338	.mask = 0xff,
339	.def = 0x80,
340	},
341	}, {
342	.id = 0x39,
343	.name = "mpcorew",
344	.swgroup = TEGRA_SWGROUP_MPCORE,
345	.la = {
346	.reg = 0x320,
347	.shift = 16,
348	.mask = 0xff,
349	.def = 0x80,
350	},
351	}, {
352	.id = 0x3b,
353	.name = "ppcsahbdmaw",
354	.swgroup = TEGRA_SWGROUP_PPCS,
355	.smmu = {
356	.reg = 0x22c,
357	.bit = 27,
358	},
359	.la = {
360	.reg = 0x348,
361	.shift = 0,
362	.mask = 0xff,
363	.def = 0x80,
364	},
365	}, {
366	.id = 0x3c,
367	.name = "ppcsahbslvw",
368	.swgroup = TEGRA_SWGROUP_PPCS,
369	.smmu = {
370	.reg = 0x22c,
371	.bit = 28,
372	},
373	.la = {
374	.reg = 0x348,
375	.shift = 16,
376	.mask = 0xff,
377	.def = 0x80,
378	},
379	}, {
380	.id = 0x3d,
381	.name = "sataw",
382	.swgroup = TEGRA_SWGROUP_SATA,
383	.smmu = {
384	.reg = 0x22c,
385	.bit = 29,
386	},
387	.la = {
388	.reg = 0x350,
389	.shift = 16,
390	.mask = 0xff,
391	.def = 0x65,
392	},
393	}, {
394	.id = 0x44,
395	.name = "ispra",
396	.swgroup = TEGRA_SWGROUP_ISP2,
397	.smmu = {
398	.reg = 0x230,
399	.bit = 4,
400	},
401	.la = {
402	.reg = 0x370,
403	.shift = 0,
404	.mask = 0xff,
405	.def = 0x18,
406	},
407	}, {
408	.id = 0x46,
409	.name = "ispwa",
410	.swgroup = TEGRA_SWGROUP_ISP2,
411	.smmu = {
412	.reg = 0x230,
413	.bit = 6,
414	},
415	.la = {
416	.reg = 0x374,
417	.shift = 0,
418	.mask = 0xff,
419	.def = 0x80,
420	},
421	}, {
422	.id = 0x47,
423	.name = "ispwb",
424	.swgroup = TEGRA_SWGROUP_ISP2,
425	.smmu = {
426	.reg = 0x230,
427	.bit = 7,
428	},
429	.la = {
430	.reg = 0x374,
431	.shift = 16,
432	.mask = 0xff,
433	.def = 0x80,
434	},
435	}, {
436	.id = 0x4a,
437	.name = "xusb_hostr",
438	.swgroup = TEGRA_SWGROUP_XUSB_HOST,
439	.smmu = {
440	.reg = 0x230,
441	.bit = 10,
442	},
443	.la = {
444	.reg = 0x37c,
445	.shift = 0,
446	.mask = 0xff,
447	.def = 0x39,
448	},
449	}, {
450	.id = 0x4b,
451	.name = "xusb_hostw",
452	.swgroup = TEGRA_SWGROUP_XUSB_HOST,
453	.smmu = {
454	.reg = 0x230,
455	.bit = 11,
456	},
457	.la = {
458	.reg = 0x37c,
459	.shift = 16,
460	.mask = 0xff,
461	.def = 0x80,
462	},
463	}, {
464	.id = 0x4c,
465	.name = "xusb_devr",
466	.swgroup = TEGRA_SWGROUP_XUSB_DEV,
467	.smmu = {
468	.reg = 0x230,
469	.bit = 12,
470	},
471	.la = {
472	.reg = 0x380,
473	.shift = 0,
474	.mask = 0xff,
475	.def = 0x39,
476	},
477	}, {
478	.id = 0x4d,
479	.name = "xusb_devw",
480	.swgroup = TEGRA_SWGROUP_XUSB_DEV,
481	.smmu = {
482	.reg = 0x230,
483	.bit = 13,
484	},
485	.la = {
486	.reg = 0x380,
487	.shift = 16,
488	.mask = 0xff,
489	.def = 0x80,
490	},
491	}, {
492	.id = 0x4e,
493	.name = "isprab",
494	.swgroup = TEGRA_SWGROUP_ISP2B,
495	.smmu = {
496	.reg = 0x230,
497	.bit = 14,
498	},
499	.la = {
500	.reg = 0x384,
501	.shift = 0,
502	.mask = 0xff,
503	.def = 0x18,
504	},
505	}, {
506	.id = 0x50,
507	.name = "ispwab",
508	.swgroup = TEGRA_SWGROUP_ISP2B,
509	.smmu = {
510	.reg = 0x230,
511	.bit = 16,
512	},
513	.la = {
514	.reg = 0x388,
515	.shift = 0,
516	.mask = 0xff,
517	.def = 0x80,
518	},
519	}, {
520	.id = 0x51,
521	.name = "ispwbb",
522	.swgroup = TEGRA_SWGROUP_ISP2B,
523	.smmu = {
524	.reg = 0x230,
525	.bit = 17,
526	},
527	.la = {
528	.reg = 0x388,
529	.shift = 16,
530	.mask = 0xff,
531	.def = 0x80,
532	},
533	}, {
534	.id = 0x54,
535	.name = "tsecsrd",
536	.swgroup = TEGRA_SWGROUP_TSEC,
537	.smmu = {
538	.reg = 0x230,
539	.bit = 20,
540	},
541	.la = {
542	.reg = 0x390,
543	.shift = 0,
544	.mask = 0xff,
545	.def = 0x9b,
546	},
547	}, {
548	.id = 0x55,
549	.name = "tsecswr",
550	.swgroup = TEGRA_SWGROUP_TSEC,
551	.smmu = {
552	.reg = 0x230,
553	.bit = 21,
554	},
555	.la = {
556	.reg = 0x390,
557	.shift = 16,
558	.mask = 0xff,
559	.def = 0x80,
560	},
561	}, {
562	.id = 0x56,
563	.name = "a9avpscr",
564	.swgroup = TEGRA_SWGROUP_A9AVP,
565	.smmu = {
566	.reg = 0x230,
567	.bit = 22,
568	},
569	.la = {
570	.reg = 0x3a4,
571	.shift = 0,
572	.mask = 0xff,
573	.def = 0x04,
574	},
575	}, {
576	.id = 0x57,
577	.name = "a9avpscw",
578	.swgroup = TEGRA_SWGROUP_A9AVP,
579	.smmu = {
580	.reg = 0x230,
581	.bit = 23,
582	},
583	.la = {
584	.reg = 0x3a4,
585	.shift = 16,
586	.mask = 0xff,
587	.def = 0x80,
588	},
589	}, {
590	.id = 0x58,
591	.name = "gpusrd",
592	.swgroup = TEGRA_SWGROUP_GPU,
593	.smmu = {
594	/* read-only */
595	.reg = 0x230,
596	.bit = 24,
597	},
598	.la = {
599	.reg = 0x3c8,
600	.shift = 0,
601	.mask = 0xff,
602	.def = 0x1a,
603	},
604	}, {
605	.id = 0x59,
606	.name = "gpuswr",
607	.swgroup = TEGRA_SWGROUP_GPU,
608	.smmu = {
609	/* read-only */
610	.reg = 0x230,
611	.bit = 25,
612	},
613	.la = {
614	.reg = 0x3c8,
615	.shift = 16,
616	.mask = 0xff,
617	.def = 0x80,
618	},
619	}, {
620	.id = 0x5a,
621	.name = "displayt",
622	.swgroup = TEGRA_SWGROUP_DC,
623	.smmu = {
624	.reg = 0x230,
625	.bit = 26,
626	},
627	.la = {
628	.reg = 0x2f0,
629	.shift = 16,
630	.mask = 0xff,
631	.def = 0x50,
632	},
633	}, {
634	.id = 0x60,
635	.name = "sdmmcra",
636	.swgroup = TEGRA_SWGROUP_SDMMC1A,
637	.smmu = {
638	.reg = 0x234,
639	.bit = 0,
640	},
641	.la = {
642	.reg = 0x3b8,
643	.shift = 0,
644	.mask = 0xff,
645	.def = 0x49,
646	},
647	}, {
648	.id = 0x61,
649	.name = "sdmmcraa",
650	.swgroup = TEGRA_SWGROUP_SDMMC2A,
651	.smmu = {
652	.reg = 0x234,
653	.bit = 1,
654	},
655	.la = {
656	.reg = 0x3bc,
657	.shift = 0,
658	.mask = 0xff,
659	.def = 0x49,
660	},
661	}, {
662	.id = 0x62,
663	.name = "sdmmcr",
664	.swgroup = TEGRA_SWGROUP_SDMMC3A,
665	.smmu = {
666	.reg = 0x234,
667	.bit = 2,
668	},
669	.la = {
670	.reg = 0x3c0,
671	.shift = 0,
672	.mask = 0xff,
673	.def = 0x49,
674	},
675	}, {
676	.id = 0x63,
677	.swgroup = TEGRA_SWGROUP_SDMMC4A,
678	.name = "sdmmcrab",
679	.smmu = {
680	.reg = 0x234,
681	.bit = 3,
682	},
683	.la = {
684	.reg = 0x3c4,
685	.shift = 0,
686	.mask = 0xff,
687	.def = 0x49,
688	},
689	}, {
690	.id = 0x64,
691	.name = "sdmmcwa",
692	.swgroup = TEGRA_SWGROUP_SDMMC1A,
693	.smmu = {
694	.reg = 0x234,
695	.bit = 4,
696	},
697	.la = {
698	.reg = 0x3b8,
699	.shift = 16,
700	.mask = 0xff,
701	.def = 0x80,
702	},
703	}, {
704	.id = 0x65,
705	.name = "sdmmcwaa",
706	.swgroup = TEGRA_SWGROUP_SDMMC2A,
707	.smmu = {
708	.reg = 0x234,
709	.bit = 5,
710	},
711	.la = {
712	.reg = 0x3bc,
713	.shift = 16,
714	.mask = 0xff,
715	.def = 0x80,
716	},
717	}, {
718	.id = 0x66,
719	.name = "sdmmcw",
720	.swgroup = TEGRA_SWGROUP_SDMMC3A,
721	.smmu = {
722	.reg = 0x234,
723	.bit = 6,
724	},
725	.la = {
726	.reg = 0x3c0,
727	.shift = 16,
728	.mask = 0xff,
729	.def = 0x80,
730	},
731	}, {
732	.id = 0x67,
733	.name = "sdmmcwab",
734	.swgroup = TEGRA_SWGROUP_SDMMC4A,
735	.smmu = {
736	.reg = 0x234,
737	.bit = 7,
738	},
739	.la = {
740	.reg = 0x3c4,
741	.shift = 16,
742	.mask = 0xff,
743	.def = 0x80,
744	},
745	}, {
746	.id = 0x6c,
747	.name = "vicsrd",
748	.swgroup = TEGRA_SWGROUP_VIC,
749	.smmu = {
750	.reg = 0x234,
751	.bit = 12,
752	},
753	.la = {
754	.reg = 0x394,
755	.shift = 0,
756	.mask = 0xff,
757	.def = 0x1a,
758	},
759	}, {
760	.id = 0x6d,
761	.name = "vicswr",
762	.swgroup = TEGRA_SWGROUP_VIC,
763	.smmu = {
764	.reg = 0x234,
765	.bit = 13,
766	},
767	.la = {
768	.reg = 0x394,
769	.shift = 16,
770	.mask = 0xff,
771	.def = 0x80,
772	},
773	}, {
774	.id = 0x72,
775	.name = "viw",
776	.swgroup = TEGRA_SWGROUP_VI,
777	.smmu = {
778	.reg = 0x234,
779	.bit = 18,
780	},
781	.la = {
782	.reg = 0x398,
783	.shift = 0,
784	.mask = 0xff,
785	.def = 0x80,
786	},
787	}, {
788	.id = 0x73,
789	.name = "displayd",
790	.swgroup = TEGRA_SWGROUP_DC,
791	.smmu = {
792	.reg = 0x234,
793	.bit = 19,
794	},
795	.la = {
796	.reg = 0x3c8,
797	.shift = 0,
798	.mask = 0xff,
799	.def = 0x50,
800	},
801	}, {
802	.id = 0x78,
803	.name = "nvdecsrd",
804	.swgroup = TEGRA_SWGROUP_NVDEC,
805	.smmu = {
806	.reg = 0x234,
807	.bit = 24,
808	},
809	.la = {
810	.reg = 0x3d8,
811	.shift = 0,
812	.mask = 0xff,
813	.def = 0x23,
814	},
815	}, {
816	.id = 0x79,
817	.name = "nvdecswr",
818	.swgroup = TEGRA_SWGROUP_NVDEC,
819	.smmu = {
820	.reg = 0x234,
821	.bit = 25,
822	},
823	.la = {
824	.reg = 0x3d8,
825	.shift = 16,
826	.mask = 0xff,
827	.def = 0x80,
828	},
829	}, {
830	.id = 0x7a,
831	.name = "aper",
832	.swgroup = TEGRA_SWGROUP_APE,
833	.smmu = {
834	.reg = 0x234,
835	.bit = 26,
836	},
837	.la = {
838	.reg = 0x3dc,
839	.shift = 0,
840	.mask = 0xff,
841	.def = 0xff,
842	},
843	}, {
844	.id = 0x7b,
845	.name = "apew",
846	.swgroup = TEGRA_SWGROUP_APE,
847	.smmu = {
848	.reg = 0x234,
849	.bit = 27,
850	},
851	.la = {
852	.reg = 0x3dc,
853	.shift = 0,
854	.mask = 0xff,
855	.def = 0x80,
856	},
857	}, {
858	.id = 0x7e,
859	.name = "nvjpgsrd",
860	.swgroup = TEGRA_SWGROUP_NVJPG,
861	.smmu = {
862	.reg = 0x234,
863	.bit = 30,
864	},
865	.la = {
866	.reg = 0x3e4,
867	.shift = 0,
868	.mask = 0xff,
869	.def = 0x23,
870	},
871	}, {
872	.id = 0x7f,
873	.name = "nvjpgswr",
874	.swgroup = TEGRA_SWGROUP_NVJPG,
875	.smmu = {
876	.reg = 0x234,
877	.bit = 31,
878	},
879	.la = {
880	.reg = 0x3e4,
881	.shift = 16,
882	.mask = 0xff,
883	.def = 0x80,
884	},
885	}, {
886	.id = 0x80,
887	.name = "sesrd",
888	.swgroup = TEGRA_SWGROUP_SE,
889	.smmu = {
890	.reg = 0xb98,
891	.bit = 0,
892	},
893	.la = {
894	.reg = 0x3e0,
895	.shift = 0,
896	.mask = 0xff,
897	.def = 0x2e,
898	},
899	}, {
900	.id = 0x81,
901	.name = "seswr",
902	.swgroup = TEGRA_SWGROUP_SE,
903	.smmu = {
904	.reg = 0xb98,
905	.bit = 1,
906	},
907	.la = {
908	.reg = 0xb98,
909	.shift = 16,
910	.mask = 0xff,
911	.def = 0x80,
912	},
913	}, {
914	.id = 0x82,
915	.name = "axiapr",
916	.swgroup = TEGRA_SWGROUP_AXIAP,
917	.smmu = {
918	.reg = 0xb98,
919	.bit = 2,
920	},
921	.la = {
922	.reg = 0x3a0,
923	.shift = 0,
924	.mask = 0xff,
925	.def = 0xff,
926	},
927	}, {
928	.id = 0x83,
929	.name = "axiapw",
930	.swgroup = TEGRA_SWGROUP_AXIAP,
931	.smmu = {
932	.reg = 0xb98,
933	.bit = 3,
934	},
935	.la = {
936	.reg = 0x3a0,
937	.shift = 16,
938	.mask = 0xff,
939	.def = 0x80,
940	},
941	}, {
942	.id = 0x84,
943	.name = "etrr",
944	.swgroup = TEGRA_SWGROUP_ETR,
945	.smmu = {
946	.reg = 0xb98,
947	.bit = 4,
948	},
949	.la = {
950	.reg = 0x3ec,
951	.shift = 0,
952	.mask = 0xff,
953	.def = 0xff,
954	},
955	}, {
956	.id = 0x85,
957	.name = "etrw",
958	.swgroup = TEGRA_SWGROUP_ETR,
959	.smmu = {
960	.reg = 0xb98,
961	.bit = 5,
962	},
963	.la = {
964	.reg = 0x3ec,
965	.shift = 16,
966	.mask = 0xff,
967	.def = 0xff,
968	},
969	}, {
970	.id = 0x86,
971	.name = "tsecsrdb",
972	.swgroup = TEGRA_SWGROUP_TSECB,
973	.smmu = {
974	.reg = 0xb98,
975	.bit = 6,
976	},
977	.la = {
978	.reg = 0x3f0,
979	.shift = 0,
980	.mask = 0xff,
981	.def = 0x9b,
982	},
983	}, {
984	.id = 0x87,
985	.name = "tsecswrb",
986	.swgroup = TEGRA_SWGROUP_TSECB,
987	.smmu = {
988	.reg = 0xb98,
989	.bit = 7,
990	},
991	.la = {
992	.reg = 0x3f0,
993	.shift = 16,
994	.mask = 0xff,
995	.def = 0x80,
996	},
997	}, {
998	.id = 0x88,
999	.name = "gpusrd2",
1000	.swgroup = TEGRA_SWGROUP_GPU,
1001	.smmu = {
1002	/* read-only */
1003	.reg = 0xb98,
1004	.bit = 8,
1005	},
1006	.la = {
1007	.reg = 0x3e8,
1008	.shift = 0,
1009	.mask = 0xff,
1010	.def = 0x1a,
1011	},
1012	}, {
1013	.id = 0x89,
1014	.name = "gpuswr2",
1015	.swgroup = TEGRA_SWGROUP_GPU,
1016	.smmu = {
1017	/* read-only */
1018	.reg = 0xb98,
1019	.bit = 9,
1020	},
1021	.la = {
1022	.reg = 0x3e8,
1023	.shift = 16,
1024	.mask = 0xff,
1025	.def = 0x80,
1026	},
1027	},
1028	};
1029
1030	static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
1031	{ .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1032	{ .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1033	{ .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
1034	{ .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1035	{ .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1036	{ .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1037	{ .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
1038	{ .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1039	{ .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
1040	{ .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
1041	{ .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1042	{ .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1043	{ .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
1044	{ .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
1045	{ .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
1046	{ .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
1047	{ .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
1048	{ .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
1049	{ .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
1050	{ .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
1051	{ .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
1052	{ .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1053	{ .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
1054	{ .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
1055	{ .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
1056	{ .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
1057	{ .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
1058	{ .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
1059	{ .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
1060	};
1061
1062	static const struct tegra_smmu_soc tegra210_smmu_soc = {
1063	.clients = tegra210_mc_clients,
1064	.num_clients = ARRAY_SIZE(tegra210_mc_clients),
1065	.swgroups = tegra210_swgroups,
1066	.num_swgroups = ARRAY_SIZE(tegra210_swgroups),
1067	.supports_round_robin_arbitration = true,
1068	.supports_request_limit = true,
1069	.num_tlb_lines = 32,
1070	.num_asids = 128,
1071	};
1072
1073	const struct tegra_mc_soc tegra210_mc_soc = {
1074	.clients = tegra210_mc_clients,
1075	.num_clients = ARRAY_SIZE(tegra210_mc_clients),
1076	.num_address_bits = 34,
1077	.atom_size = 64,
1078	.client_id_mask = 0xff,
1079	.smmu = &tegra210_smmu_soc,
1de828ce DO	1080	.intmask = MC_INT_DECERR_MTS \| MC_INT_SECERR_SEC \| MC_INT_DECERR_VPR \|
	1081	MC_INT_INVALID_APB_ASID_UPDATE \| MC_INT_INVALID_SMMU_PAGE \|
	1082	MC_INT_SECURITY_VIOLATION \| MC_INT_DECERR_EMEM,
588c43a7	1083	};