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CommitLineData
62579266
RV
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
6 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
adceed62 7 * Author: Mattias Wallin <mattias.wallin@stericsson.com>
62579266
RV
8 */
9
10#include <linux/kernel.h>
11#include <linux/slab.h>
12#include <linux/init.h>
13#include <linux/irq.h>
06e589ef 14#include <linux/irqdomain.h>
62579266
RV
15#include <linux/delay.h>
16#include <linux/interrupt.h>
31cbae22 17#include <linux/moduleparam.h>
62579266
RV
18#include <linux/platform_device.h>
19#include <linux/mfd/core.h>
47c16975 20#include <linux/mfd/abx500.h>
ee66e653 21#include <linux/mfd/abx500/ab8500.h>
00441b5e 22#include <linux/mfd/abx500/ab8500-bm.h>
d28f1db8 23#include <linux/mfd/dbx500-prcmu.h>
549931f9 24#include <linux/regulator/ab8500.h>
6bc4a568
LJ
25#include <linux/of.h>
26#include <linux/of_device.h>
62579266
RV
27
28/*
29 * Interrupt register offsets
30 * Bank : 0x0E
31 */
47c16975
MW
32#define AB8500_IT_SOURCE1_REG 0x00
33#define AB8500_IT_SOURCE2_REG 0x01
34#define AB8500_IT_SOURCE3_REG 0x02
35#define AB8500_IT_SOURCE4_REG 0x03
36#define AB8500_IT_SOURCE5_REG 0x04
37#define AB8500_IT_SOURCE6_REG 0x05
38#define AB8500_IT_SOURCE7_REG 0x06
39#define AB8500_IT_SOURCE8_REG 0x07
d6255529 40#define AB9540_IT_SOURCE13_REG 0x0C
47c16975
MW
41#define AB8500_IT_SOURCE19_REG 0x12
42#define AB8500_IT_SOURCE20_REG 0x13
43#define AB8500_IT_SOURCE21_REG 0x14
44#define AB8500_IT_SOURCE22_REG 0x15
45#define AB8500_IT_SOURCE23_REG 0x16
46#define AB8500_IT_SOURCE24_REG 0x17
62579266
RV
47
48/*
49 * latch registers
50 */
47c16975
MW
51#define AB8500_IT_LATCH1_REG 0x20
52#define AB8500_IT_LATCH2_REG 0x21
53#define AB8500_IT_LATCH3_REG 0x22
54#define AB8500_IT_LATCH4_REG 0x23
55#define AB8500_IT_LATCH5_REG 0x24
56#define AB8500_IT_LATCH6_REG 0x25
57#define AB8500_IT_LATCH7_REG 0x26
58#define AB8500_IT_LATCH8_REG 0x27
59#define AB8500_IT_LATCH9_REG 0x28
60#define AB8500_IT_LATCH10_REG 0x29
92d50a41 61#define AB8500_IT_LATCH12_REG 0x2B
d6255529 62#define AB9540_IT_LATCH13_REG 0x2C
47c16975
MW
63#define AB8500_IT_LATCH19_REG 0x32
64#define AB8500_IT_LATCH20_REG 0x33
65#define AB8500_IT_LATCH21_REG 0x34
66#define AB8500_IT_LATCH22_REG 0x35
67#define AB8500_IT_LATCH23_REG 0x36
68#define AB8500_IT_LATCH24_REG 0x37
62579266
RV
69
70/*
71 * mask registers
72 */
73
47c16975
MW
74#define AB8500_IT_MASK1_REG 0x40
75#define AB8500_IT_MASK2_REG 0x41
76#define AB8500_IT_MASK3_REG 0x42
77#define AB8500_IT_MASK4_REG 0x43
78#define AB8500_IT_MASK5_REG 0x44
79#define AB8500_IT_MASK6_REG 0x45
80#define AB8500_IT_MASK7_REG 0x46
81#define AB8500_IT_MASK8_REG 0x47
82#define AB8500_IT_MASK9_REG 0x48
83#define AB8500_IT_MASK10_REG 0x49
84#define AB8500_IT_MASK11_REG 0x4A
85#define AB8500_IT_MASK12_REG 0x4B
86#define AB8500_IT_MASK13_REG 0x4C
87#define AB8500_IT_MASK14_REG 0x4D
88#define AB8500_IT_MASK15_REG 0x4E
89#define AB8500_IT_MASK16_REG 0x4F
90#define AB8500_IT_MASK17_REG 0x50
91#define AB8500_IT_MASK18_REG 0x51
92#define AB8500_IT_MASK19_REG 0x52
93#define AB8500_IT_MASK20_REG 0x53
94#define AB8500_IT_MASK21_REG 0x54
95#define AB8500_IT_MASK22_REG 0x55
96#define AB8500_IT_MASK23_REG 0x56
97#define AB8500_IT_MASK24_REG 0x57
a29264b6 98#define AB8500_IT_MASK25_REG 0x58
47c16975 99
7ccfe9b1
MJ
100/*
101 * latch hierarchy registers
102 */
103#define AB8500_IT_LATCHHIER1_REG 0x60
104#define AB8500_IT_LATCHHIER2_REG 0x61
105#define AB8500_IT_LATCHHIER3_REG 0x62
3e1a498f 106#define AB8540_IT_LATCHHIER4_REG 0x63
7ccfe9b1
MJ
107
108#define AB8500_IT_LATCHHIER_NUM 3
3e1a498f 109#define AB8540_IT_LATCHHIER_NUM 4
7ccfe9b1 110
47c16975 111#define AB8500_REV_REG 0x80
0f620837 112#define AB8500_IC_NAME_REG 0x82
e5c238c3 113#define AB8500_SWITCH_OFF_STATUS 0x00
62579266 114
b4a31037 115#define AB8500_TURN_ON_STATUS 0x00
500e69a1 116#define AB8505_TURN_ON_STATUS_2 0x04
b4a31037 117
f04a9d8a
RK
118#define AB8500_CH_USBCH_STAT1_REG 0x02
119#define VBUS_DET_DBNC100 0x02
120#define VBUS_DET_DBNC1 0x01
121
122static DEFINE_SPINLOCK(on_stat_lock);
123static u8 turn_on_stat_mask = 0xFF;
124static u8 turn_on_stat_set;
6ef9418c 125static bool no_bm; /* No battery management */
31cbae22
PG
126/*
127 * not really modular, but the easiest way to keep compat with existing
128 * bootargs behaviour is to continue using module_param here.
129 */
6ef9418c
RA
130module_param(no_bm, bool, S_IRUGO);
131
d6255529
LW
132#define AB9540_MODEM_CTRL2_REG 0x23
133#define AB9540_MODEM_CTRL2_SWDBBRSTN_BIT BIT(2)
134
62579266
RV
135/*
136 * Map interrupt numbers to the LATCH and MASK register offsets, Interrupt
2ced445e
LW
137 * numbers are indexed into this array with (num / 8). The interupts are
138 * defined in linux/mfd/ab8500.h
62579266
RV
139 *
140 * This is one off from the register names, i.e. AB8500_IT_MASK1_REG is at
141 * offset 0.
142 */
2ced445e 143/* AB8500 support */
62579266 144static const int ab8500_irq_regoffset[AB8500_NUM_IRQ_REGS] = {
92d50a41 145 0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21,
62579266
RV
146};
147
a29264b6 148/* AB9540 / AB8505 support */
d6255529 149static const int ab9540_irq_regoffset[AB9540_NUM_IRQ_REGS] = {
a29264b6 150 0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21, 12, 13, 24, 5, 22, 23
d6255529
LW
151};
152
3e1a498f
LJ
153/* AB8540 support */
154static const int ab8540_irq_regoffset[AB8540_NUM_IRQ_REGS] = {
7ccf40b1
LJ
155 0, 1, 2, 3, 4, -1, -1, -1, -1, 11, 18, 19, 20, 21, 12, 13, 24, 5, 22,
156 23, 25, 26, 27, 28, 29, 30, 31,
3e1a498f
LJ
157};
158
0f620837
LW
159static const char ab8500_version_str[][7] = {
160 [AB8500_VERSION_AB8500] = "AB8500",
161 [AB8500_VERSION_AB8505] = "AB8505",
162 [AB8500_VERSION_AB9540] = "AB9540",
163 [AB8500_VERSION_AB8540] = "AB8540",
164};
165
822672a7 166static int ab8500_prcmu_write(struct ab8500 *ab8500, u16 addr, u8 data)
d28f1db8
LJ
167{
168 int ret;
169
170 ret = prcmu_abb_write((u8)(addr >> 8), (u8)(addr & 0xFF), &data, 1);
171 if (ret < 0)
172 dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
173 return ret;
174}
175
822672a7 176static int ab8500_prcmu_write_masked(struct ab8500 *ab8500, u16 addr, u8 mask,
d28f1db8
LJ
177 u8 data)
178{
179 int ret;
180
181 ret = prcmu_abb_write_masked((u8)(addr >> 8), (u8)(addr & 0xFF), &data,
182 &mask, 1);
183 if (ret < 0)
184 dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
185 return ret;
186}
187
822672a7 188static int ab8500_prcmu_read(struct ab8500 *ab8500, u16 addr)
d28f1db8
LJ
189{
190 int ret;
191 u8 data;
192
193 ret = prcmu_abb_read((u8)(addr >> 8), (u8)(addr & 0xFF), &data, 1);
194 if (ret < 0) {
195 dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
196 return ret;
197 }
198 return (int)data;
199}
200
47c16975
MW
201static int ab8500_get_chip_id(struct device *dev)
202{
6bce7bf1
MW
203 struct ab8500 *ab8500;
204
205 if (!dev)
206 return -EINVAL;
207 ab8500 = dev_get_drvdata(dev->parent);
208 return ab8500 ? (int)ab8500->chip_id : -EINVAL;
47c16975
MW
209}
210
211static int set_register_interruptible(struct ab8500 *ab8500, u8 bank,
212 u8 reg, u8 data)
62579266
RV
213{
214 int ret;
47c16975
MW
215 /*
216 * Put the u8 bank and u8 register together into a an u16.
217 * The bank on higher 8 bits and register in lower 8 bits.
500e69a1 218 */
47c16975 219 u16 addr = ((u16)bank) << 8 | reg;
62579266
RV
220
221 dev_vdbg(ab8500->dev, "wr: addr %#x <= %#x\n", addr, data);
222
392cbd1e 223 mutex_lock(&ab8500->lock);
47c16975 224
62579266
RV
225 ret = ab8500->write(ab8500, addr, data);
226 if (ret < 0)
227 dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
228 addr, ret);
47c16975 229 mutex_unlock(&ab8500->lock);
62579266
RV
230
231 return ret;
232}
233
47c16975
MW
234static int ab8500_set_register(struct device *dev, u8 bank,
235 u8 reg, u8 value)
62579266 236{
112a80d2 237 int ret;
47c16975 238 struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
62579266 239
112a80d2
JA
240 atomic_inc(&ab8500->transfer_ongoing);
241 ret = set_register_interruptible(ab8500, bank, reg, value);
242 atomic_dec(&ab8500->transfer_ongoing);
243 return ret;
62579266 244}
62579266 245
47c16975
MW
246static int get_register_interruptible(struct ab8500 *ab8500, u8 bank,
247 u8 reg, u8 *value)
62579266
RV
248{
249 int ret;
47c16975
MW
250 u16 addr = ((u16)bank) << 8 | reg;
251
392cbd1e 252 mutex_lock(&ab8500->lock);
62579266
RV
253
254 ret = ab8500->read(ab8500, addr);
255 if (ret < 0)
256 dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
257 addr, ret);
47c16975
MW
258 else
259 *value = ret;
62579266 260
47c16975 261 mutex_unlock(&ab8500->lock);
62579266
RV
262 dev_vdbg(ab8500->dev, "rd: addr %#x => data %#x\n", addr, ret);
263
264 return ret;
265}
266
47c16975
MW
267static int ab8500_get_register(struct device *dev, u8 bank,
268 u8 reg, u8 *value)
62579266 269{
112a80d2 270 int ret;
47c16975 271 struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
62579266 272
112a80d2
JA
273 atomic_inc(&ab8500->transfer_ongoing);
274 ret = get_register_interruptible(ab8500, bank, reg, value);
275 atomic_dec(&ab8500->transfer_ongoing);
276 return ret;
62579266 277}
47c16975
MW
278
279static int mask_and_set_register_interruptible(struct ab8500 *ab8500, u8 bank,
280 u8 reg, u8 bitmask, u8 bitvalues)
62579266
RV
281{
282 int ret;
47c16975 283 u16 addr = ((u16)bank) << 8 | reg;
62579266 284
392cbd1e 285 mutex_lock(&ab8500->lock);
62579266 286
bc628fd1
MN
287 if (ab8500->write_masked == NULL) {
288 u8 data;
62579266 289
bc628fd1
MN
290 ret = ab8500->read(ab8500, addr);
291 if (ret < 0) {
292 dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
293 addr, ret);
294 goto out;
295 }
62579266 296
bc628fd1
MN
297 data = (u8)ret;
298 data = (~bitmask & data) | (bitmask & bitvalues);
299
300 ret = ab8500->write(ab8500, addr, data);
301 if (ret < 0)
302 dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
303 addr, ret);
62579266 304
bc628fd1
MN
305 dev_vdbg(ab8500->dev, "mask: addr %#x => data %#x\n", addr,
306 data);
307 goto out;
308 }
309 ret = ab8500->write_masked(ab8500, addr, bitmask, bitvalues);
310 if (ret < 0)
311 dev_err(ab8500->dev, "failed to modify reg %#x: %d\n", addr,
312 ret);
62579266
RV
313out:
314 mutex_unlock(&ab8500->lock);
315 return ret;
316}
47c16975
MW
317
318static int ab8500_mask_and_set_register(struct device *dev,
319 u8 bank, u8 reg, u8 bitmask, u8 bitvalues)
320{
112a80d2 321 int ret;
47c16975
MW
322 struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
323
112a80d2 324 atomic_inc(&ab8500->transfer_ongoing);
7ccf40b1 325 ret = mask_and_set_register_interruptible(ab8500, bank, reg,
112a80d2
JA
326 bitmask, bitvalues);
327 atomic_dec(&ab8500->transfer_ongoing);
328 return ret;
47c16975
MW
329}
330
331static struct abx500_ops ab8500_ops = {
332 .get_chip_id = ab8500_get_chip_id,
333 .get_register = ab8500_get_register,
334 .set_register = ab8500_set_register,
335 .get_register_page = NULL,
336 .set_register_page = NULL,
337 .mask_and_set_register = ab8500_mask_and_set_register,
338 .event_registers_startup_state_get = NULL,
339 .startup_irq_enabled = NULL,
1d843a6c 340 .dump_all_banks = ab8500_dump_all_banks,
47c16975 341};
62579266 342
9505a0a0 343static void ab8500_irq_lock(struct irq_data *data)
62579266 344{
9505a0a0 345 struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
62579266
RV
346
347 mutex_lock(&ab8500->irq_lock);
112a80d2 348 atomic_inc(&ab8500->transfer_ongoing);
62579266
RV
349}
350
9505a0a0 351static void ab8500_irq_sync_unlock(struct irq_data *data)
62579266 352{
9505a0a0 353 struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
62579266
RV
354 int i;
355
2ced445e 356 for (i = 0; i < ab8500->mask_size; i++) {
62579266
RV
357 u8 old = ab8500->oldmask[i];
358 u8 new = ab8500->mask[i];
359 int reg;
360
361 if (new == old)
362 continue;
363
0f620837
LW
364 /*
365 * Interrupt register 12 doesn't exist prior to AB8500 version
366 * 2.0
367 */
368 if (ab8500->irq_reg_offset[i] == 11 &&
369 is_ab8500_1p1_or_earlier(ab8500))
92d50a41
MW
370 continue;
371
3e1a498f
LJ
372 if (ab8500->irq_reg_offset[i] < 0)
373 continue;
374
62579266
RV
375 ab8500->oldmask[i] = new;
376
2ced445e 377 reg = AB8500_IT_MASK1_REG + ab8500->irq_reg_offset[i];
47c16975 378 set_register_interruptible(ab8500, AB8500_INTERRUPT, reg, new);
62579266 379 }
112a80d2 380 atomic_dec(&ab8500->transfer_ongoing);
62579266
RV
381 mutex_unlock(&ab8500->irq_lock);
382}
383
9505a0a0 384static void ab8500_irq_mask(struct irq_data *data)
62579266 385{
9505a0a0 386 struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
06e589ef 387 int offset = data->hwirq;
62579266
RV
388 int index = offset / 8;
389 int mask = 1 << (offset % 8);
390
391 ab8500->mask[index] |= mask;
9c677b9b
LJ
392
393 /* The AB8500 GPIOs have two interrupts each (rising & falling). */
394 if (offset >= AB8500_INT_GPIO6R && offset <= AB8500_INT_GPIO41R)
395 ab8500->mask[index + 2] |= mask;
396 if (offset >= AB9540_INT_GPIO50R && offset <= AB9540_INT_GPIO54R)
397 ab8500->mask[index + 1] |= mask;
398 if (offset == AB8540_INT_GPIO43R || offset == AB8540_INT_GPIO44R)
e2ddf46a
LW
399 /* Here the falling IRQ is one bit lower */
400 ab8500->mask[index] |= (mask << 1);
62579266
RV
401}
402
9505a0a0 403static void ab8500_irq_unmask(struct irq_data *data)
62579266 404{
9505a0a0 405 struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
9c677b9b 406 unsigned int type = irqd_get_trigger_type(data);
06e589ef 407 int offset = data->hwirq;
62579266
RV
408 int index = offset / 8;
409 int mask = 1 << (offset % 8);
410
9c677b9b
LJ
411 if (type & IRQ_TYPE_EDGE_RISING)
412 ab8500->mask[index] &= ~mask;
413
414 /* The AB8500 GPIOs have two interrupts each (rising & falling). */
415 if (type & IRQ_TYPE_EDGE_FALLING) {
416 if (offset >= AB8500_INT_GPIO6R && offset <= AB8500_INT_GPIO41R)
417 ab8500->mask[index + 2] &= ~mask;
7ccf40b1
LJ
418 else if (offset >= AB9540_INT_GPIO50R &&
419 offset <= AB9540_INT_GPIO54R)
9c677b9b 420 ab8500->mask[index + 1] &= ~mask;
7ccf40b1
LJ
421 else if (offset == AB8540_INT_GPIO43R ||
422 offset == AB8540_INT_GPIO44R)
e2ddf46a
LW
423 /* Here the falling IRQ is one bit lower */
424 ab8500->mask[index] &= ~(mask << 1);
9c677b9b
LJ
425 else
426 ab8500->mask[index] &= ~mask;
e2ddf46a 427 } else {
9c677b9b
LJ
428 /* Satisfies the case where type is not set. */
429 ab8500->mask[index] &= ~mask;
e2ddf46a 430 }
62579266
RV
431}
432
40f6e5a2
LJ
433static int ab8500_irq_set_type(struct irq_data *data, unsigned int type)
434{
435 return 0;
62579266
RV
436}
437
438static struct irq_chip ab8500_irq_chip = {
439 .name = "ab8500",
9505a0a0
MB
440 .irq_bus_lock = ab8500_irq_lock,
441 .irq_bus_sync_unlock = ab8500_irq_sync_unlock,
442 .irq_mask = ab8500_irq_mask,
e6f9306e 443 .irq_disable = ab8500_irq_mask,
9505a0a0 444 .irq_unmask = ab8500_irq_unmask,
40f6e5a2 445 .irq_set_type = ab8500_irq_set_type,
62579266
RV
446};
447
3e1a498f
LJ
448static void update_latch_offset(u8 *offset, int i)
449{
450 /* Fix inconsistent ITFromLatch25 bit mapping... */
451 if (unlikely(*offset == 17))
500e69a1 452 *offset = 24;
3e1a498f
LJ
453 /* Fix inconsistent ab8540 bit mapping... */
454 if (unlikely(*offset == 16))
500e69a1 455 *offset = 25;
7ccf40b1 456 if ((i == 3) && (*offset >= 24))
500e69a1 457 *offset += 2;
3e1a498f
LJ
458}
459
7ccfe9b1
MJ
460static int ab8500_handle_hierarchical_line(struct ab8500 *ab8500,
461 int latch_offset, u8 latch_val)
462{
7a93fb37 463 int int_bit, line, i;
7ccfe9b1 464
7a93fb37
FB
465 for (i = 0; i < ab8500->mask_size; i++)
466 if (ab8500->irq_reg_offset[i] == latch_offset)
467 break;
7ccfe9b1 468
7a93fb37
FB
469 if (i >= ab8500->mask_size) {
470 dev_err(ab8500->dev, "Register offset 0x%2x not declared\n",
471 latch_offset);
472 return -ENXIO;
473 }
7ccfe9b1 474
7a93fb37
FB
475 /* ignore masked out interrupts */
476 latch_val &= ~ab8500->mask[i];
7ccfe9b1 477
7a93fb37
FB
478 while (latch_val) {
479 int_bit = __ffs(latch_val);
7ccfe9b1
MJ
480 line = (i << 3) + int_bit;
481 latch_val &= ~(1 << int_bit);
482
e2ddf46a
LW
483 /*
484 * This handles the falling edge hwirqs from the GPIO
485 * lines. Route them back to the line registered for the
486 * rising IRQ, as this is merely a flag for the same IRQ
487 * in linux terms.
488 */
489 if (line >= AB8500_INT_GPIO6F && line <= AB8500_INT_GPIO41F)
490 line -= 16;
491 if (line >= AB9540_INT_GPIO50F && line <= AB9540_INT_GPIO54F)
492 line -= 8;
493 if (line == AB8540_INT_GPIO43F || line == AB8540_INT_GPIO44F)
494 line += 1;
495
ed83d301 496 handle_nested_irq(irq_create_mapping(ab8500->domain, line));
7a93fb37 497 }
7ccfe9b1
MJ
498
499 return 0;
500}
501
502static int ab8500_handle_hierarchical_latch(struct ab8500 *ab8500,
503 int hier_offset, u8 hier_val)
504{
505 int latch_bit, status;
506 u8 latch_offset, latch_val;
507
508 do {
509 latch_bit = __ffs(hier_val);
510 latch_offset = (hier_offset << 3) + latch_bit;
511
3e1a498f 512 update_latch_offset(&latch_offset, hier_offset);
7ccfe9b1
MJ
513
514 status = get_register_interruptible(ab8500,
515 AB8500_INTERRUPT,
516 AB8500_IT_LATCH1_REG + latch_offset,
517 &latch_val);
518 if (status < 0 || latch_val == 0)
519 goto discard;
520
521 status = ab8500_handle_hierarchical_line(ab8500,
522 latch_offset, latch_val);
523 if (status < 0)
524 return status;
525discard:
526 hier_val &= ~(1 << latch_bit);
527 } while (hier_val);
528
529 return 0;
530}
531
532static irqreturn_t ab8500_hierarchical_irq(int irq, void *dev)
533{
534 struct ab8500 *ab8500 = dev;
535 u8 i;
536
537 dev_vdbg(ab8500->dev, "interrupt\n");
538
539 /* Hierarchical interrupt version */
3e1a498f 540 for (i = 0; i < (ab8500->it_latchhier_num); i++) {
7ccfe9b1
MJ
541 int status;
542 u8 hier_val;
543
544 status = get_register_interruptible(ab8500, AB8500_INTERRUPT,
545 AB8500_IT_LATCHHIER1_REG + i, &hier_val);
546 if (status < 0 || hier_val == 0)
547 continue;
548
549 status = ab8500_handle_hierarchical_latch(ab8500, i, hier_val);
550 if (status < 0)
551 break;
552 }
553 return IRQ_HANDLED;
554}
555
06e589ef
LJ
556static int ab8500_irq_map(struct irq_domain *d, unsigned int virq,
557 irq_hw_number_t hwirq)
558{
559 struct ab8500 *ab8500 = d->host_data;
560
561 if (!ab8500)
562 return -EINVAL;
563
564 irq_set_chip_data(virq, ab8500);
565 irq_set_chip_and_handler(virq, &ab8500_irq_chip,
566 handle_simple_irq);
567 irq_set_nested_thread(virq, 1);
06e589ef 568 irq_set_noprobe(virq);
62579266
RV
569
570 return 0;
571}
572
7ce7b26f 573static const struct irq_domain_ops ab8500_irq_ops = {
7ccf40b1
LJ
574 .map = ab8500_irq_map,
575 .xlate = irq_domain_xlate_twocell,
06e589ef
LJ
576};
577
578static int ab8500_irq_init(struct ab8500 *ab8500, struct device_node *np)
62579266 579{
2ced445e
LW
580 int num_irqs;
581
3e1a498f
LJ
582 if (is_ab8540(ab8500))
583 num_irqs = AB8540_NR_IRQS;
584 else if (is_ab9540(ab8500))
d6255529 585 num_irqs = AB9540_NR_IRQS;
a982362c
BJ
586 else if (is_ab8505(ab8500))
587 num_irqs = AB8505_NR_IRQS;
d6255529
LW
588 else
589 num_irqs = AB8500_NR_IRQS;
62579266 590
f1d11f39 591 /* If ->irq_base is zero this will give a linear mapping */
7602e05d 592 ab8500->domain = irq_domain_add_simple(ab8500->dev->of_node,
500e69a1
LJ
593 num_irqs, 0,
594 &ab8500_irq_ops, ab8500);
06e589ef
LJ
595
596 if (!ab8500->domain) {
597 dev_err(ab8500->dev, "Failed to create irqdomain\n");
500e69a1 598 return -ENODEV;
06e589ef
LJ
599 }
600
601 return 0;
62579266
RV
602}
603
112a80d2
JA
604int ab8500_suspend(struct ab8500 *ab8500)
605{
606 if (atomic_read(&ab8500->transfer_ongoing))
607 return -EINVAL;
f3556302
LJ
608
609 return 0;
112a80d2
JA
610}
611
5ac98553 612static const struct mfd_cell ab8500_bm_devs[] = {
4b106fb9
LJ
613 {
614 .name = "ab8500-charger",
615 .of_compatible = "stericsson,ab8500-charger",
4b106fb9
LJ
616 .platform_data = &ab8500_bm_data,
617 .pdata_size = sizeof(ab8500_bm_data),
618 },
619 {
620 .name = "ab8500-btemp",
621 .of_compatible = "stericsson,ab8500-btemp",
4b106fb9
LJ
622 .platform_data = &ab8500_bm_data,
623 .pdata_size = sizeof(ab8500_bm_data),
624 },
625 {
626 .name = "ab8500-fg",
627 .of_compatible = "stericsson,ab8500-fg",
4b106fb9
LJ
628 .platform_data = &ab8500_bm_data,
629 .pdata_size = sizeof(ab8500_bm_data),
630 },
631 {
632 .name = "ab8500-chargalg",
633 .of_compatible = "stericsson,ab8500-chargalg",
4b106fb9
LJ
634 .platform_data = &ab8500_bm_data,
635 .pdata_size = sizeof(ab8500_bm_data),
636 },
637};
638
5ac98553 639static const struct mfd_cell ab8500_devs[] = {
5814fc35
MW
640#ifdef CONFIG_DEBUG_FS
641 {
642 .name = "ab8500-debug",
bad76991 643 .of_compatible = "stericsson,ab8500-debug",
5814fc35
MW
644 },
645#endif
e098aded
MW
646 {
647 .name = "ab8500-sysctrl",
bad76991 648 .of_compatible = "stericsson,ab8500-sysctrl",
e098aded 649 },
53f325be
LJ
650 {
651 .name = "ab8500-ext-regulator",
652 .of_compatible = "stericsson,ab8500-ext-regulator",
653 },
e098aded
MW
654 {
655 .name = "ab8500-regulator",
bad76991 656 .of_compatible = "stericsson,ab8500-regulator",
e098aded 657 },
916a871c
UH
658 {
659 .name = "abx500-clk",
660 .of_compatible = "stericsson,abx500-clk",
661 },
4b106fb9
LJ
662 {
663 .name = "ab8500-gpadc",
955de2ea 664 .of_compatible = "stericsson,ab8500-gpadc",
4b106fb9 665 },
62579266
RV
666 {
667 .name = "ab8500-rtc",
bad76991 668 .of_compatible = "stericsson,ab8500-rtc",
62579266 669 },
6af75ecd
LW
670 {
671 .name = "ab8500-acc-det",
bad76991 672 .of_compatible = "stericsson,ab8500-acc-det",
6af75ecd 673 },
e098aded 674 {
4b106fb9 675
e098aded 676 .name = "ab8500-poweron-key",
bad76991 677 .of_compatible = "stericsson,ab8500-poweron-key",
e098aded 678 },
f0f05b1c
AM
679 {
680 .name = "ab8500-pwm",
bad76991 681 .of_compatible = "stericsson,ab8500-pwm",
f0f05b1c
AM
682 .id = 1,
683 },
684 {
685 .name = "ab8500-pwm",
bad76991 686 .of_compatible = "stericsson,ab8500-pwm",
f0f05b1c
AM
687 .id = 2,
688 },
689 {
690 .name = "ab8500-pwm",
bad76991 691 .of_compatible = "stericsson,ab8500-pwm",
f0f05b1c
AM
692 .id = 3,
693 },
77686517 694 {
e098aded 695 .name = "ab8500-denc",
bad76991 696 .of_compatible = "stericsson,ab8500-denc",
e098aded 697 },
4b106fb9 698 {
eb696c31 699 .name = "pinctrl-ab8500",
4b106fb9
LJ
700 .of_compatible = "stericsson,ab8500-gpio",
701 },
e098aded 702 {
151621a7
HZ
703 .name = "abx500-temp",
704 .of_compatible = "stericsson,abx500-temp",
77686517 705 },
6ef9418c 706 {
4b106fb9 707 .name = "ab8500-usb",
f201f730 708 .of_compatible = "stericsson,ab8500-usb",
6ef9418c
RA
709 },
710 {
4b106fb9 711 .name = "ab8500-codec",
fccf14ad 712 .of_compatible = "stericsson,ab8500-codec",
6ef9418c
RA
713 },
714};
715
5ac98553 716static const struct mfd_cell ab9540_devs[] = {
4b106fb9 717#ifdef CONFIG_DEBUG_FS
d6255529 718 {
4b106fb9 719 .name = "ab8500-debug",
d6255529 720 },
4b106fb9 721#endif
d6255529 722 {
4b106fb9 723 .name = "ab8500-sysctrl",
d6255529 724 },
53f325be
LJ
725 {
726 .name = "ab8500-ext-regulator",
727 },
44f72e53 728 {
4b106fb9 729 .name = "ab8500-regulator",
44f72e53 730 },
9ee17676
UH
731 {
732 .name = "abx500-clk",
733 .of_compatible = "stericsson,abx500-clk",
734 },
c0eda9ae
LJ
735 {
736 .name = "ab8500-gpadc",
737 .of_compatible = "stericsson,ab8500-gpadc",
c0eda9ae 738 },
4b106fb9
LJ
739 {
740 .name = "ab8500-rtc",
4b106fb9
LJ
741 },
742 {
743 .name = "ab8500-acc-det",
4b106fb9
LJ
744 },
745 {
746 .name = "ab8500-poweron-key",
4b106fb9
LJ
747 },
748 {
749 .name = "ab8500-pwm",
750 .id = 1,
751 },
4b106fb9
LJ
752 {
753 .name = "abx500-temp",
4b106fb9 754 },
d6255529 755 {
e64d905e
LJ
756 .name = "pinctrl-ab9540",
757 .of_compatible = "stericsson,ab9540-gpio",
d6255529
LW
758 },
759 {
760 .name = "ab9540-usb",
d6255529 761 },
44f72e53
VS
762 {
763 .name = "ab9540-codec",
764 },
c0eda9ae
LJ
765 {
766 .name = "ab-iddet",
c0eda9ae 767 },
44f72e53
VS
768};
769
c0eda9ae 770/* Device list for ab8505 */
5ac98553 771static const struct mfd_cell ab8505_devs[] = {
4b106fb9
LJ
772#ifdef CONFIG_DEBUG_FS
773 {
774 .name = "ab8500-debug",
4b106fb9
LJ
775 },
776#endif
777 {
778 .name = "ab8500-sysctrl",
779 },
780 {
781 .name = "ab8500-regulator",
782 },
9ee17676
UH
783 {
784 .name = "abx500-clk",
785 .of_compatible = "stericsson,abx500-clk",
786 },
4b106fb9
LJ
787 {
788 .name = "ab8500-gpadc",
955de2ea 789 .of_compatible = "stericsson,ab8500-gpadc",
4b106fb9
LJ
790 },
791 {
792 .name = "ab8500-rtc",
4b106fb9
LJ
793 },
794 {
795 .name = "ab8500-acc-det",
4b106fb9
LJ
796 },
797 {
798 .name = "ab8500-poweron-key",
4b106fb9
LJ
799 },
800 {
801 .name = "ab8500-pwm",
802 .id = 1,
803 },
4b106fb9 804 {
eb696c31 805 .name = "pinctrl-ab8505",
4b106fb9
LJ
806 },
807 {
808 .name = "ab8500-usb",
4b106fb9
LJ
809 },
810 {
811 .name = "ab8500-codec",
812 },
c0eda9ae
LJ
813 {
814 .name = "ab-iddet",
c0eda9ae
LJ
815 },
816};
817
5ac98553 818static const struct mfd_cell ab8540_devs[] = {
4b106fb9
LJ
819#ifdef CONFIG_DEBUG_FS
820 {
821 .name = "ab8500-debug",
4b106fb9
LJ
822 },
823#endif
824 {
825 .name = "ab8500-sysctrl",
826 },
53f325be
LJ
827 {
828 .name = "ab8500-ext-regulator",
829 },
4b106fb9
LJ
830 {
831 .name = "ab8500-regulator",
832 },
9ee17676
UH
833 {
834 .name = "abx500-clk",
835 .of_compatible = "stericsson,abx500-clk",
836 },
4b106fb9
LJ
837 {
838 .name = "ab8500-gpadc",
955de2ea 839 .of_compatible = "stericsson,ab8500-gpadc",
4b106fb9 840 },
4b106fb9
LJ
841 {
842 .name = "ab8500-acc-det",
4b106fb9
LJ
843 },
844 {
845 .name = "ab8500-poweron-key",
4b106fb9
LJ
846 },
847 {
848 .name = "ab8500-pwm",
849 .id = 1,
850 },
4b106fb9
LJ
851 {
852 .name = "abx500-temp",
4b106fb9 853 },
c0eda9ae 854 {
eb696c31 855 .name = "pinctrl-ab8540",
c0eda9ae
LJ
856 },
857 {
858 .name = "ab8540-usb",
c0eda9ae
LJ
859 },
860 {
861 .name = "ab8540-codec",
862 },
44f72e53
VS
863 {
864 .name = "ab-iddet",
44f72e53 865 },
d6255529
LW
866};
867
5ac98553 868static const struct mfd_cell ab8540_cut1_devs[] = {
9c717cf3
AT
869 {
870 .name = "ab8500-rtc",
871 .of_compatible = "stericsson,ab8500-rtc",
9c717cf3
AT
872 },
873};
874
5ac98553 875static const struct mfd_cell ab8540_cut2_devs[] = {
9c717cf3
AT
876 {
877 .name = "ab8540-rtc",
878 .of_compatible = "stericsson,ab8540-rtc",
9c717cf3
AT
879 },
880};
881
cca69b67
MW
882static ssize_t show_chip_id(struct device *dev,
883 struct device_attribute *attr, char *buf)
884{
885 struct ab8500 *ab8500;
886
887 ab8500 = dev_get_drvdata(dev);
e436ddff 888
cca69b67
MW
889 return sprintf(buf, "%#x\n", ab8500 ? ab8500->chip_id : -EINVAL);
890}
891
e5c238c3
MW
892/*
893 * ab8500 has switched off due to (SWITCH_OFF_STATUS):
894 * 0x01 Swoff bit programming
895 * 0x02 Thermal protection activation
896 * 0x04 Vbat lower then BattOk falling threshold
897 * 0x08 Watchdog expired
898 * 0x10 Non presence of 32kHz clock
899 * 0x20 Battery level lower than power on reset threshold
900 * 0x40 Power on key 1 pressed longer than 10 seconds
901 * 0x80 DB8500 thermal shutdown
902 */
903static ssize_t show_switch_off_status(struct device *dev,
904 struct device_attribute *attr, char *buf)
905{
906 int ret;
907 u8 value;
908 struct ab8500 *ab8500;
909
910 ab8500 = dev_get_drvdata(dev);
911 ret = get_register_interruptible(ab8500, AB8500_RTC,
912 AB8500_SWITCH_OFF_STATUS, &value);
913 if (ret < 0)
914 return ret;
915 return sprintf(buf, "%#x\n", value);
916}
917
f04a9d8a
RK
918/* use mask and set to override the register turn_on_stat value */
919void ab8500_override_turn_on_stat(u8 mask, u8 set)
920{
921 spin_lock(&on_stat_lock);
922 turn_on_stat_mask = mask;
923 turn_on_stat_set = set;
924 spin_unlock(&on_stat_lock);
925}
926
b4a31037
AL
927/*
928 * ab8500 has turned on due to (TURN_ON_STATUS):
929 * 0x01 PORnVbat
930 * 0x02 PonKey1dbF
931 * 0x04 PonKey2dbF
932 * 0x08 RTCAlarm
933 * 0x10 MainChDet
934 * 0x20 VbusDet
935 * 0x40 UsbIDDetect
936 * 0x80 Reserved
937 */
938static ssize_t show_turn_on_status(struct device *dev,
939 struct device_attribute *attr, char *buf)
940{
941 int ret;
942 u8 value;
943 struct ab8500 *ab8500;
944
945 ab8500 = dev_get_drvdata(dev);
946 ret = get_register_interruptible(ab8500, AB8500_SYS_CTRL1_BLOCK,
947 AB8500_TURN_ON_STATUS, &value);
948 if (ret < 0)
949 return ret;
f04a9d8a
RK
950
951 /*
952 * In L9540, turn_on_status register is not updated correctly if
953 * the device is rebooted with AC/USB charger connected. Due to
954 * this, the device boots android instead of entering into charge
955 * only mode. Read the AC/USB status register to detect the charger
956 * presence and update the turn on status manually.
957 */
958 if (is_ab9540(ab8500)) {
959 spin_lock(&on_stat_lock);
960 value = (value & turn_on_stat_mask) | turn_on_stat_set;
961 spin_unlock(&on_stat_lock);
962 }
963
b4a31037
AL
964 return sprintf(buf, "%#x\n", value);
965}
966
93ff722e
LJ
967static ssize_t show_turn_on_status_2(struct device *dev,
968 struct device_attribute *attr, char *buf)
969{
970 int ret;
971 u8 value;
972 struct ab8500 *ab8500;
973
974 ab8500 = dev_get_drvdata(dev);
975 ret = get_register_interruptible(ab8500, AB8500_SYS_CTRL1_BLOCK,
976 AB8505_TURN_ON_STATUS_2, &value);
977 if (ret < 0)
978 return ret;
979 return sprintf(buf, "%#x\n", (value & 0x1));
980}
981
d6255529
LW
982static ssize_t show_ab9540_dbbrstn(struct device *dev,
983 struct device_attribute *attr, char *buf)
984{
985 struct ab8500 *ab8500;
986 int ret;
987 u8 value;
988
989 ab8500 = dev_get_drvdata(dev);
990
991 ret = get_register_interruptible(ab8500, AB8500_REGU_CTRL2,
992 AB9540_MODEM_CTRL2_REG, &value);
993 if (ret < 0)
994 return ret;
995
996 return sprintf(buf, "%d\n",
997 (value & AB9540_MODEM_CTRL2_SWDBBRSTN_BIT) ? 1 : 0);
998}
999
1000static ssize_t store_ab9540_dbbrstn(struct device *dev,
1001 struct device_attribute *attr, const char *buf, size_t count)
1002{
1003 struct ab8500 *ab8500;
1004 int ret = count;
1005 int err;
1006 u8 bitvalues;
1007
1008 ab8500 = dev_get_drvdata(dev);
1009
1010 if (count > 0) {
1011 switch (buf[0]) {
1012 case '0':
1013 bitvalues = 0;
1014 break;
1015 case '1':
1016 bitvalues = AB9540_MODEM_CTRL2_SWDBBRSTN_BIT;
1017 break;
1018 default:
1019 goto exit;
1020 }
1021
1022 err = mask_and_set_register_interruptible(ab8500,
1023 AB8500_REGU_CTRL2, AB9540_MODEM_CTRL2_REG,
1024 AB9540_MODEM_CTRL2_SWDBBRSTN_BIT, bitvalues);
1025 if (err)
1026 dev_info(ab8500->dev,
1027 "Failed to set DBBRSTN %c, err %#x\n",
1028 buf[0], err);
1029 }
1030
1031exit:
1032 return ret;
1033}
1034
cca69b67 1035static DEVICE_ATTR(chip_id, S_IRUGO, show_chip_id, NULL);
e5c238c3 1036static DEVICE_ATTR(switch_off_status, S_IRUGO, show_switch_off_status, NULL);
b4a31037 1037static DEVICE_ATTR(turn_on_status, S_IRUGO, show_turn_on_status, NULL);
93ff722e 1038static DEVICE_ATTR(turn_on_status_2, S_IRUGO, show_turn_on_status_2, NULL);
d6255529
LW
1039static DEVICE_ATTR(dbbrstn, S_IRUGO | S_IWUSR,
1040 show_ab9540_dbbrstn, store_ab9540_dbbrstn);
cca69b67
MW
1041
1042static struct attribute *ab8500_sysfs_entries[] = {
1043 &dev_attr_chip_id.attr,
e5c238c3 1044 &dev_attr_switch_off_status.attr,
b4a31037 1045 &dev_attr_turn_on_status.attr,
cca69b67
MW
1046 NULL,
1047};
1048
93ff722e
LJ
1049static struct attribute *ab8505_sysfs_entries[] = {
1050 &dev_attr_turn_on_status_2.attr,
1051 NULL,
1052};
1053
d6255529
LW
1054static struct attribute *ab9540_sysfs_entries[] = {
1055 &dev_attr_chip_id.attr,
1056 &dev_attr_switch_off_status.attr,
1057 &dev_attr_turn_on_status.attr,
1058 &dev_attr_dbbrstn.attr,
1059 NULL,
1060};
1061
cca69b67
MW
1062static struct attribute_group ab8500_attr_group = {
1063 .attrs = ab8500_sysfs_entries,
1064};
1065
93ff722e
LJ
1066static struct attribute_group ab8505_attr_group = {
1067 .attrs = ab8505_sysfs_entries,
1068};
1069
d6255529
LW
1070static struct attribute_group ab9540_attr_group = {
1071 .attrs = ab9540_sysfs_entries,
1072};
1073
f791be49 1074static int ab8500_probe(struct platform_device *pdev)
62579266 1075{
500e69a1 1076 static const char * const switch_off_status[] = {
b04c530c
JA
1077 "Swoff bit programming",
1078 "Thermal protection activation",
1079 "Vbat lower then BattOk falling threshold",
1080 "Watchdog expired",
1081 "Non presence of 32kHz clock",
1082 "Battery level lower than power on reset threshold",
1083 "Power on key 1 pressed longer than 10 seconds",
1084 "DB8500 thermal shutdown"};
500e69a1 1085 static const char * const turn_on_status[] = {
abee26cd
MW
1086 "Battery rising (Vbat)",
1087 "Power On Key 1 dbF",
1088 "Power On Key 2 dbF",
1089 "RTC Alarm",
1090 "Main Charger Detect",
1091 "Vbus Detect (USB)",
1092 "USB ID Detect",
1093 "UART Factory Mode Detect"};
d28f1db8 1094 const struct platform_device_id *platid = platform_get_device_id(pdev);
6bc4a568
LJ
1095 enum ab8500_version version = AB8500_VERSION_UNDEFINED;
1096 struct device_node *np = pdev->dev.of_node;
d28f1db8
LJ
1097 struct ab8500 *ab8500;
1098 struct resource *resource;
62579266
RV
1099 int ret;
1100 int i;
47c16975 1101 u8 value;
62579266 1102
7ccf40b1 1103 ab8500 = devm_kzalloc(&pdev->dev, sizeof(*ab8500), GFP_KERNEL);
d28f1db8
LJ
1104 if (!ab8500)
1105 return -ENOMEM;
1106
d28f1db8
LJ
1107 ab8500->dev = &pdev->dev;
1108
1109 resource = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
f864c46a
LW
1110 if (!resource) {
1111 dev_err(&pdev->dev, "no IRQ resource\n");
8c4203cb 1112 return -ENODEV;
f864c46a 1113 }
d28f1db8
LJ
1114
1115 ab8500->irq = resource->start;
1116
822672a7
LJ
1117 ab8500->read = ab8500_prcmu_read;
1118 ab8500->write = ab8500_prcmu_write;
1119 ab8500->write_masked = ab8500_prcmu_write_masked;
d28f1db8 1120
62579266
RV
1121 mutex_init(&ab8500->lock);
1122 mutex_init(&ab8500->irq_lock);
112a80d2 1123 atomic_set(&ab8500->transfer_ongoing, 0);
62579266 1124
d28f1db8
LJ
1125 platform_set_drvdata(pdev, ab8500);
1126
6bc4a568
LJ
1127 if (platid)
1128 version = platid->driver_data;
6bc4a568 1129
0f620837
LW
1130 if (version != AB8500_VERSION_UNDEFINED)
1131 ab8500->version = version;
1132 else {
1133 ret = get_register_interruptible(ab8500, AB8500_MISC,
1134 AB8500_IC_NAME_REG, &value);
f864c46a
LW
1135 if (ret < 0) {
1136 dev_err(&pdev->dev, "could not probe HW\n");
8c4203cb 1137 return ret;
f864c46a 1138 }
0f620837
LW
1139
1140 ab8500->version = value;
1141 }
1142
47c16975
MW
1143 ret = get_register_interruptible(ab8500, AB8500_MISC,
1144 AB8500_REV_REG, &value);
62579266 1145 if (ret < 0)
8c4203cb 1146 return ret;
62579266 1147
47c16975 1148 ab8500->chip_id = value;
62579266 1149
0f620837
LW
1150 dev_info(ab8500->dev, "detected chip, %s rev. %1x.%1x\n",
1151 ab8500_version_str[ab8500->version],
1152 ab8500->chip_id >> 4,
1153 ab8500->chip_id & 0x0F);
1154
3e1a498f
LJ
1155 /* Configure AB8540 */
1156 if (is_ab8540(ab8500)) {
1157 ab8500->mask_size = AB8540_NUM_IRQ_REGS;
1158 ab8500->irq_reg_offset = ab8540_irq_regoffset;
1159 ab8500->it_latchhier_num = AB8540_IT_LATCHHIER_NUM;
7ccf40b1 1160 } /* Configure AB8500 or AB9540 IRQ */
3e1a498f 1161 else if (is_ab9540(ab8500) || is_ab8505(ab8500)) {
d6255529
LW
1162 ab8500->mask_size = AB9540_NUM_IRQ_REGS;
1163 ab8500->irq_reg_offset = ab9540_irq_regoffset;
3e1a498f 1164 ab8500->it_latchhier_num = AB8500_IT_LATCHHIER_NUM;
d6255529
LW
1165 } else {
1166 ab8500->mask_size = AB8500_NUM_IRQ_REGS;
1167 ab8500->irq_reg_offset = ab8500_irq_regoffset;
3e1a498f 1168 ab8500->it_latchhier_num = AB8500_IT_LATCHHIER_NUM;
d6255529 1169 }
7ccf40b1
LJ
1170 ab8500->mask = devm_kzalloc(&pdev->dev, ab8500->mask_size,
1171 GFP_KERNEL);
2ced445e
LW
1172 if (!ab8500->mask)
1173 return -ENOMEM;
7ccf40b1
LJ
1174 ab8500->oldmask = devm_kzalloc(&pdev->dev, ab8500->mask_size,
1175 GFP_KERNEL);
8c4203cb
LJ
1176 if (!ab8500->oldmask)
1177 return -ENOMEM;
1178
e5c238c3
MW
1179 /*
1180 * ab8500 has switched off due to (SWITCH_OFF_STATUS):
1181 * 0x01 Swoff bit programming
1182 * 0x02 Thermal protection activation
1183 * 0x04 Vbat lower then BattOk falling threshold
1184 * 0x08 Watchdog expired
1185 * 0x10 Non presence of 32kHz clock
1186 * 0x20 Battery level lower than power on reset threshold
1187 * 0x40 Power on key 1 pressed longer than 10 seconds
1188 * 0x80 DB8500 thermal shutdown
1189 */
1190
1191 ret = get_register_interruptible(ab8500, AB8500_RTC,
1192 AB8500_SWITCH_OFF_STATUS, &value);
1193 if (ret < 0)
1194 return ret;
b04c530c
JA
1195 dev_info(ab8500->dev, "switch off cause(s) (%#x): ", value);
1196
1197 if (value) {
1198 for (i = 0; i < ARRAY_SIZE(switch_off_status); i++) {
1199 if (value & 1)
7ccf40b1 1200 pr_cont(" \"%s\"", switch_off_status[i]);
b04c530c
JA
1201 value = value >> 1;
1202
1203 }
7ccf40b1 1204 pr_cont("\n");
b04c530c 1205 } else {
7ccf40b1 1206 pr_cont(" None\n");
b04c530c 1207 }
abee26cd
MW
1208 ret = get_register_interruptible(ab8500, AB8500_SYS_CTRL1_BLOCK,
1209 AB8500_TURN_ON_STATUS, &value);
1210 if (ret < 0)
1211 return ret;
1212 dev_info(ab8500->dev, "turn on reason(s) (%#x): ", value);
1213
1214 if (value) {
1215 for (i = 0; i < ARRAY_SIZE(turn_on_status); i++) {
1216 if (value & 1)
7ccf40b1 1217 pr_cont("\"%s\" ", turn_on_status[i]);
abee26cd
MW
1218 value = value >> 1;
1219 }
7ccf40b1 1220 pr_cont("\n");
abee26cd 1221 } else {
7ccf40b1 1222 pr_cont("None\n");
abee26cd 1223 }
e5c238c3 1224
f04a9d8a
RK
1225 if (is_ab9540(ab8500)) {
1226 ret = get_register_interruptible(ab8500, AB8500_CHARGER,
1227 AB8500_CH_USBCH_STAT1_REG, &value);
1228 if (ret < 0)
1229 return ret;
1230 if ((value & VBUS_DET_DBNC1) && (value & VBUS_DET_DBNC100))
1231 ab8500_override_turn_on_stat(~AB8500_POW_KEY_1_ON,
1232 AB8500_VBUS_DET);
1233 }
62579266
RV
1234
1235 /* Clear and mask all interrupts */
2ced445e 1236 for (i = 0; i < ab8500->mask_size; i++) {
0f620837
LW
1237 /*
1238 * Interrupt register 12 doesn't exist prior to AB8500 version
1239 * 2.0
1240 */
1241 if (ab8500->irq_reg_offset[i] == 11 &&
1242 is_ab8500_1p1_or_earlier(ab8500))
92d50a41 1243 continue;
62579266 1244
3e1a498f
LJ
1245 if (ab8500->irq_reg_offset[i] < 0)
1246 continue;
1247
47c16975 1248 get_register_interruptible(ab8500, AB8500_INTERRUPT,
2ced445e 1249 AB8500_IT_LATCH1_REG + ab8500->irq_reg_offset[i],
92d50a41 1250 &value);
47c16975 1251 set_register_interruptible(ab8500, AB8500_INTERRUPT,
2ced445e 1252 AB8500_IT_MASK1_REG + ab8500->irq_reg_offset[i], 0xff);
62579266
RV
1253 }
1254
47c16975
MW
1255 ret = abx500_register_ops(ab8500->dev, &ab8500_ops);
1256 if (ret)
8c4203cb 1257 return ret;
47c16975 1258
2ced445e 1259 for (i = 0; i < ab8500->mask_size; i++)
62579266
RV
1260 ab8500->mask[i] = ab8500->oldmask[i] = 0xff;
1261
06e589ef
LJ
1262 ret = ab8500_irq_init(ab8500, np);
1263 if (ret)
8c4203cb 1264 return ret;
62579266 1265
f348fefd
DS
1266 ret = devm_request_threaded_irq(&pdev->dev, ab8500->irq, NULL,
1267 ab8500_hierarchical_irq,
1268 IRQF_ONESHOT | IRQF_NO_SUSPEND,
1269 "ab8500", ab8500);
1270 if (ret)
1271 return ret;
62579266 1272
bad76991
LJ
1273 if (is_ab9540(ab8500))
1274 ret = mfd_add_devices(ab8500->dev, 0, ab9540_devs,
1275 ARRAY_SIZE(ab9540_devs), NULL,
f864c46a 1276 0, ab8500->domain);
9c717cf3 1277 else if (is_ab8540(ab8500)) {
c0eda9ae
LJ
1278 ret = mfd_add_devices(ab8500->dev, 0, ab8540_devs,
1279 ARRAY_SIZE(ab8540_devs), NULL,
f864c46a 1280 0, ab8500->domain);
9c717cf3
AT
1281 if (ret)
1282 return ret;
1283
1284 if (is_ab8540_1p2_or_earlier(ab8500))
1285 ret = mfd_add_devices(ab8500->dev, 0, ab8540_cut1_devs,
1286 ARRAY_SIZE(ab8540_cut1_devs), NULL,
f864c46a 1287 0, ab8500->domain);
9c717cf3
AT
1288 else /* ab8540 >= cut2 */
1289 ret = mfd_add_devices(ab8500->dev, 0, ab8540_cut2_devs,
1290 ARRAY_SIZE(ab8540_cut2_devs), NULL,
f864c46a 1291 0, ab8500->domain);
9c717cf3 1292 } else if (is_ab8505(ab8500))
c0eda9ae
LJ
1293 ret = mfd_add_devices(ab8500->dev, 0, ab8505_devs,
1294 ARRAY_SIZE(ab8505_devs), NULL,
f864c46a 1295 0, ab8500->domain);
bad76991
LJ
1296 else
1297 ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs,
1298 ARRAY_SIZE(ab8500_devs), NULL,
f864c46a 1299 0, ab8500->domain);
bad76991 1300 if (ret)
8c4203cb 1301 return ret;
44f72e53 1302
6ef9418c
RA
1303 if (!no_bm) {
1304 /* Add battery management devices */
1305 ret = mfd_add_devices(ab8500->dev, 0, ab8500_bm_devs,
1306 ARRAY_SIZE(ab8500_bm_devs), NULL,
f864c46a 1307 0, ab8500->domain);
6ef9418c
RA
1308 if (ret)
1309 dev_err(ab8500->dev, "error adding bm devices\n");
1310 }
1311
e436ddff
LJ
1312 if (((is_ab8505(ab8500) || is_ab9540(ab8500)) &&
1313 ab8500->chip_id >= AB8500_CUT2P0) || is_ab8540(ab8500))
d6255529
LW
1314 ret = sysfs_create_group(&ab8500->dev->kobj,
1315 &ab9540_attr_group);
1316 else
1317 ret = sysfs_create_group(&ab8500->dev->kobj,
1318 &ab8500_attr_group);
93ff722e
LJ
1319
1320 if ((is_ab8505(ab8500) || is_ab9540(ab8500)) &&
1321 ab8500->chip_id >= AB8500_CUT2P0)
1322 ret = sysfs_create_group(&ab8500->dev->kobj,
1323 &ab8505_attr_group);
1324
cca69b67
MW
1325 if (ret)
1326 dev_err(ab8500->dev, "error creating sysfs entries\n");
06e589ef
LJ
1327
1328 return ret;
62579266
RV
1329}
1330
d28f1db8
LJ
1331static const struct platform_device_id ab8500_id[] = {
1332 { "ab8500-core", AB8500_VERSION_AB8500 },
1333 { "ab8505-i2c", AB8500_VERSION_AB8505 },
1334 { "ab9540-i2c", AB8500_VERSION_AB9540 },
1335 { "ab8540-i2c", AB8500_VERSION_AB8540 },
1336 { }
1337};
1338
1339static struct platform_driver ab8500_core_driver = {
1340 .driver = {
1341 .name = "ab8500-core",
31cbae22 1342 .suppress_bind_attrs = true,
d28f1db8
LJ
1343 },
1344 .probe = ab8500_probe,
d28f1db8
LJ
1345 .id_table = ab8500_id,
1346};
1347
1348static int __init ab8500_core_init(void)
1349{
1350 return platform_driver_register(&ab8500_core_driver);
1351}
ba7cbc3e 1352core_initcall(ab8500_core_init);