[mirror_ubuntu-bionic-kernel.git] / drivers / mfd / ab8500-core.c

/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * License Terms: GNU General Public License v2
 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
 */

#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/ab8500.h>

/*
 * Interrupt register offsets
 * Bank : 0x0E
 */
#define AB8500_IT_SOURCE1_REG		0x0E00
#define AB8500_IT_SOURCE2_REG		0x0E01
#define AB8500_IT_SOURCE3_REG		0x0E02
#define AB8500_IT_SOURCE4_REG		0x0E03
#define AB8500_IT_SOURCE5_REG		0x0E04
#define AB8500_IT_SOURCE6_REG		0x0E05
#define AB8500_IT_SOURCE7_REG		0x0E06
#define AB8500_IT_SOURCE8_REG		0x0E07
#define AB8500_IT_SOURCE19_REG		0x0E12
#define AB8500_IT_SOURCE20_REG		0x0E13
#define AB8500_IT_SOURCE21_REG		0x0E14
#define AB8500_IT_SOURCE22_REG		0x0E15
#define AB8500_IT_SOURCE23_REG		0x0E16
#define AB8500_IT_SOURCE24_REG		0x0E17

/*
 * latch registers
 */
#define AB8500_IT_LATCH1_REG		0x0E20
#define AB8500_IT_LATCH2_REG		0x0E21
#define AB8500_IT_LATCH3_REG		0x0E22
#define AB8500_IT_LATCH4_REG		0x0E23
#define AB8500_IT_LATCH5_REG		0x0E24
#define AB8500_IT_LATCH6_REG		0x0E25
#define AB8500_IT_LATCH7_REG		0x0E26
#define AB8500_IT_LATCH8_REG		0x0E27
#define AB8500_IT_LATCH9_REG		0x0E28
#define AB8500_IT_LATCH10_REG		0x0E29
#define AB8500_IT_LATCH19_REG		0x0E32
#define AB8500_IT_LATCH20_REG		0x0E33
#define AB8500_IT_LATCH21_REG		0x0E34
#define AB8500_IT_LATCH22_REG		0x0E35
#define AB8500_IT_LATCH23_REG		0x0E36
#define AB8500_IT_LATCH24_REG		0x0E37

/*
 * mask registers
 */

#define AB8500_IT_MASK1_REG		0x0E40
#define AB8500_IT_MASK2_REG		0x0E41
#define AB8500_IT_MASK3_REG		0x0E42
#define AB8500_IT_MASK4_REG		0x0E43
#define AB8500_IT_MASK5_REG		0x0E44
#define AB8500_IT_MASK6_REG		0x0E45
#define AB8500_IT_MASK7_REG		0x0E46
#define AB8500_IT_MASK8_REG		0x0E47
#define AB8500_IT_MASK9_REG		0x0E48
#define AB8500_IT_MASK10_REG		0x0E49
#define AB8500_IT_MASK11_REG		0x0E4A
#define AB8500_IT_MASK12_REG		0x0E4B
#define AB8500_IT_MASK13_REG		0x0E4C
#define AB8500_IT_MASK14_REG		0x0E4D
#define AB8500_IT_MASK15_REG		0x0E4E
#define AB8500_IT_MASK16_REG		0x0E4F
#define AB8500_IT_MASK17_REG		0x0E50
#define AB8500_IT_MASK18_REG		0x0E51
#define AB8500_IT_MASK19_REG		0x0E52
#define AB8500_IT_MASK20_REG		0x0E53
#define AB8500_IT_MASK21_REG		0x0E54
#define AB8500_IT_MASK22_REG		0x0E55
#define AB8500_IT_MASK23_REG		0x0E56
#define AB8500_IT_MASK24_REG		0x0E57

#define AB8500_REV_REG			0x1080

/*
 * Map interrupt numbers to the LATCH and MASK register offsets, Interrupt
 * numbers are indexed into this array with (num / 8).
 *
 * This is one off from the register names, i.e. AB8500_IT_MASK1_REG is at
 * offset 0.
 */
static const int ab8500_irq_regoffset[AB8500_NUM_IRQ_REGS] = {
	0, 1, 2, 3, 4, 6, 7, 8, 9, 18, 19, 20, 21,
};

static int __ab8500_write(struct ab8500 *ab8500, u16 addr, u8 data)
{
	int ret;

	dev_vdbg(ab8500->dev, "wr: addr %#x <= %#x\n", addr, data);

	ret = ab8500->write(ab8500, addr, data);
	if (ret < 0)
		dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
			addr, ret);

	return ret;
}

/**
 * ab8500_write() - write an AB8500 register
 * @ab8500: device to write to
 * @addr: address of the register
 * @data: value to write
 */
int ab8500_write(struct ab8500 *ab8500, u16 addr, u8 data)
{
	int ret;

	mutex_lock(&ab8500->lock);
	ret = __ab8500_write(ab8500, addr, data);
	mutex_unlock(&ab8500->lock);

	return ret;
}
EXPORT_SYMBOL_GPL(ab8500_write);

static int __ab8500_read(struct ab8500 *ab8500, u16 addr)
{
	int ret;

	ret = ab8500->read(ab8500, addr);
	if (ret < 0)
		dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
			addr, ret);

	dev_vdbg(ab8500->dev, "rd: addr %#x => data %#x\n", addr, ret);

	return ret;
}

/**
 * ab8500_read() - read an AB8500 register
 * @ab8500: device to read from
 * @addr: address of the register
 */
int ab8500_read(struct ab8500 *ab8500, u16 addr)
{
	int ret;

	mutex_lock(&ab8500->lock);
	ret = __ab8500_read(ab8500, addr);
	mutex_unlock(&ab8500->lock);

	return ret;
}
EXPORT_SYMBOL_GPL(ab8500_read);

/**
 * ab8500_set_bits() - set a bitfield in an AB8500 register
 * @ab8500: device to read from
 * @addr: address of the register
 * @mask: mask of the bitfield to modify
 * @data: value to set to the bitfield
 */
int ab8500_set_bits(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data)
{
	int ret;

	mutex_lock(&ab8500->lock);

	ret = __ab8500_read(ab8500, addr);
	if (ret < 0)
		goto out;

	ret &= ~mask;
	ret |= data;

	ret = __ab8500_write(ab8500, addr, ret);

out:
	mutex_unlock(&ab8500->lock);
	return ret;
}
EXPORT_SYMBOL_GPL(ab8500_set_bits);

static void ab8500_irq_lock(unsigned int irq)
{
	struct ab8500 *ab8500 = get_irq_chip_data(irq);

	mutex_lock(&ab8500->irq_lock);
}

static void ab8500_irq_sync_unlock(unsigned int irq)
{
	struct ab8500 *ab8500 = get_irq_chip_data(irq);
	int i;

	for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) {
		u8 old = ab8500->oldmask[i];
		u8 new = ab8500->mask[i];
		int reg;

		if (new == old)
			continue;

		ab8500->oldmask[i] = new;

		reg = AB8500_IT_MASK1_REG + ab8500_irq_regoffset[i];
		ab8500_write(ab8500, reg, new);
	}

	mutex_unlock(&ab8500->irq_lock);
}

static void ab8500_irq_mask(unsigned int irq)
{
	struct ab8500 *ab8500 = get_irq_chip_data(irq);
	int offset = irq - ab8500->irq_base;
	int index = offset / 8;
	int mask = 1 << (offset % 8);

	ab8500->mask[index] |= mask;
}

static void ab8500_irq_unmask(unsigned int irq)
{
	struct ab8500 *ab8500 = get_irq_chip_data(irq);
	int offset = irq - ab8500->irq_base;
	int index = offset / 8;
	int mask = 1 << (offset % 8);

	ab8500->mask[index] &= ~mask;
}

static struct irq_chip ab8500_irq_chip = {
	.name			= "ab8500",
	.bus_lock		= ab8500_irq_lock,
	.bus_sync_unlock	= ab8500_irq_sync_unlock,
	.mask			= ab8500_irq_mask,
	.unmask			= ab8500_irq_unmask,
};

static irqreturn_t ab8500_irq(int irq, void *dev)
{
	struct ab8500 *ab8500 = dev;
	int i;

	dev_vdbg(ab8500->dev, "interrupt\n");

	for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) {
		int regoffset = ab8500_irq_regoffset[i];
		int status;

		status = ab8500_read(ab8500, AB8500_IT_LATCH1_REG + regoffset);
		if (status <= 0)
			continue;

		do {
			int bit = __ffs(status);
			int line = i * 8 + bit;

			handle_nested_irq(ab8500->irq_base + line);
			status &= ~(1 << bit);
		} while (status);
	}

	return IRQ_HANDLED;
}

static int ab8500_irq_init(struct ab8500 *ab8500)
{
	int base = ab8500->irq_base;
	int irq;

	for (irq = base; irq < base + AB8500_NR_IRQS; irq++) {
		set_irq_chip_data(irq, ab8500);
		set_irq_chip_and_handler(irq, &ab8500_irq_chip,
					 handle_simple_irq);
		set_irq_nested_thread(irq, 1);
#ifdef CONFIG_ARM
		set_irq_flags(irq, IRQF_VALID);
#else
		set_irq_noprobe(irq);
#endif
	}

	return 0;
}

static void ab8500_irq_remove(struct ab8500 *ab8500)
{
	int base = ab8500->irq_base;
	int irq;

	for (irq = base; irq < base + AB8500_NR_IRQS; irq++) {
#ifdef CONFIG_ARM
		set_irq_flags(irq, 0);
#endif
		set_irq_chip_and_handler(irq, NULL, NULL);
		set_irq_chip_data(irq, NULL);
	}
}

static struct resource ab8500_gpadc_resources[] = {
	{
		.name	= "HW_CONV_END",
		.start	= AB8500_INT_GP_HW_ADC_CONV_END,
		.end	= AB8500_INT_GP_HW_ADC_CONV_END,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.name	= "SW_CONV_END",
		.start	= AB8500_INT_GP_SW_ADC_CONV_END,
		.end	= AB8500_INT_GP_SW_ADC_CONV_END,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct resource ab8500_rtc_resources[] = {
	{
		.name	= "60S",
		.start	= AB8500_INT_RTC_60S,
		.end	= AB8500_INT_RTC_60S,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.name	= "ALARM",
		.start	= AB8500_INT_RTC_ALARM,
		.end	= AB8500_INT_RTC_ALARM,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mfd_cell ab8500_devs[] = {
	{
		.name = "ab8500-gpadc",
		.num_resources = ARRAY_SIZE(ab8500_gpadc_resources),
		.resources = ab8500_gpadc_resources,
	},
	{
		.name = "ab8500-rtc",
		.num_resources = ARRAY_SIZE(ab8500_rtc_resources),
		.resources = ab8500_rtc_resources,
	},
	{ .name = "ab8500-charger", },
	{ .name = "ab8500-audio", },
	{ .name = "ab8500-usb", },
	{ .name = "ab8500-pwm", },
};

int __devinit ab8500_init(struct ab8500 *ab8500)
{
	struct ab8500_platform_data *plat = dev_get_platdata(ab8500->dev);
	int ret;
	int i;

	if (plat)
		ab8500->irq_base = plat->irq_base;

	mutex_init(&ab8500->lock);
	mutex_init(&ab8500->irq_lock);

	ret = ab8500_read(ab8500, AB8500_REV_REG);
	if (ret < 0)
		return ret;

	/*
	 * 0x0 - Early Drop
	 * 0x10 - Cut 1.0
	 * 0x11 - Cut 1.1
	 */
	if (ret == 0x0 || ret == 0x10 || ret == 0x11) {
		ab8500->revision = ret;
		dev_info(ab8500->dev, "detected chip, revision: %#x\n", ret);
	} else {
		dev_err(ab8500->dev, "unknown chip, revision: %#x\n", ret);
		return -EINVAL;
	}

	if (plat && plat->init)
		plat->init(ab8500);

	/* Clear and mask all interrupts */
	for (i = 0; i < 10; i++) {
		ab8500_read(ab8500, AB8500_IT_LATCH1_REG + i);
		ab8500_write(ab8500, AB8500_IT_MASK1_REG + i, 0xff);
	}

	for (i = 18; i < 24; i++) {
		ab8500_read(ab8500, AB8500_IT_LATCH1_REG + i);
		ab8500_write(ab8500, AB8500_IT_MASK1_REG + i, 0xff);
	}

	for (i = 0; i < AB8500_NUM_IRQ_REGS; i++)
		ab8500->mask[i] = ab8500->oldmask[i] = 0xff;

	if (ab8500->irq_base) {
		ret = ab8500_irq_init(ab8500);
		if (ret)
			return ret;

		ret = request_threaded_irq(ab8500->irq, NULL, ab8500_irq,
					   IRQF_ONESHOT, "ab8500", ab8500);
		if (ret)
			goto out_removeirq;
	}

	ret = mfd_add_devices(ab8500->dev, -1, ab8500_devs,
			      ARRAY_SIZE(ab8500_devs), NULL,
			      ab8500->irq_base);
	if (ret)
		goto out_freeirq;

	return ret;

out_freeirq:
	if (ab8500->irq_base) {
		free_irq(ab8500->irq, ab8500);
out_removeirq:
		ab8500_irq_remove(ab8500);
	}
	return ret;
}

int __devexit ab8500_exit(struct ab8500 *ab8500)
{
	mfd_remove_devices(ab8500->dev);
	if (ab8500->irq_base) {
		free_irq(ab8500->irq, ab8500);
		ab8500_irq_remove(ab8500);
	}

	return 0;
}

MODULE_AUTHOR("Srinidhi Kasagar, Rabin Vincent");
MODULE_DESCRIPTION("AB8500 MFD core");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
62579266 RV	1	/*
	2	* Copyright (C) ST-Ericsson SA 2010
	3	*
	4	* License Terms: GNU General Public License v2
	5	* Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
	6	* Author: Rabin Vincent <rabin.vincent@stericsson.com>
	7	*/
	8
	9	#include <linux/kernel.h>
	10	#include <linux/slab.h>
	11	#include <linux/init.h>
	12	#include <linux/irq.h>
	13	#include <linux/delay.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/module.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/mfd/core.h>
	18	#include <linux/mfd/ab8500.h>
	19
	20	/*
	21	* Interrupt register offsets
	22	* Bank : 0x0E
	23	*/
	24	#define AB8500_IT_SOURCE1_REG 0x0E00
	25	#define AB8500_IT_SOURCE2_REG 0x0E01
	26	#define AB8500_IT_SOURCE3_REG 0x0E02
	27	#define AB8500_IT_SOURCE4_REG 0x0E03
	28	#define AB8500_IT_SOURCE5_REG 0x0E04
	29	#define AB8500_IT_SOURCE6_REG 0x0E05
	30	#define AB8500_IT_SOURCE7_REG 0x0E06
	31	#define AB8500_IT_SOURCE8_REG 0x0E07
	32	#define AB8500_IT_SOURCE19_REG 0x0E12
	33	#define AB8500_IT_SOURCE20_REG 0x0E13
	34	#define AB8500_IT_SOURCE21_REG 0x0E14
	35	#define AB8500_IT_SOURCE22_REG 0x0E15
	36	#define AB8500_IT_SOURCE23_REG 0x0E16
	37	#define AB8500_IT_SOURCE24_REG 0x0E17
	38
	39	/*
	40	* latch registers
	41	*/
	42	#define AB8500_IT_LATCH1_REG 0x0E20
	43	#define AB8500_IT_LATCH2_REG 0x0E21
	44	#define AB8500_IT_LATCH3_REG 0x0E22
	45	#define AB8500_IT_LATCH4_REG 0x0E23
	46	#define AB8500_IT_LATCH5_REG 0x0E24
	47	#define AB8500_IT_LATCH6_REG 0x0E25
	48	#define AB8500_IT_LATCH7_REG 0x0E26
	49	#define AB8500_IT_LATCH8_REG 0x0E27
	50	#define AB8500_IT_LATCH9_REG 0x0E28
	51	#define AB8500_IT_LATCH10_REG 0x0E29
	52	#define AB8500_IT_LATCH19_REG 0x0E32
	53	#define AB8500_IT_LATCH20_REG 0x0E33
	54	#define AB8500_IT_LATCH21_REG 0x0E34
	55	#define AB8500_IT_LATCH22_REG 0x0E35
	56	#define AB8500_IT_LATCH23_REG 0x0E36
	57	#define AB8500_IT_LATCH24_REG 0x0E37
	58
	59	/*
	60	* mask registers
	61	*/
	62
	63	#define AB8500_IT_MASK1_REG 0x0E40
	64	#define AB8500_IT_MASK2_REG 0x0E41
65	#define AB8500_IT_MASK3_REG 0x0E42
66	#define AB8500_IT_MASK4_REG 0x0E43
67	#define AB8500_IT_MASK5_REG 0x0E44
68	#define AB8500_IT_MASK6_REG 0x0E45
69	#define AB8500_IT_MASK7_REG 0x0E46
70	#define AB8500_IT_MASK8_REG 0x0E47
71	#define AB8500_IT_MASK9_REG 0x0E48
72	#define AB8500_IT_MASK10_REG 0x0E49
73	#define AB8500_IT_MASK11_REG 0x0E4A
74	#define AB8500_IT_MASK12_REG 0x0E4B
75	#define AB8500_IT_MASK13_REG 0x0E4C
76	#define AB8500_IT_MASK14_REG 0x0E4D
77	#define AB8500_IT_MASK15_REG 0x0E4E
78	#define AB8500_IT_MASK16_REG 0x0E4F
79	#define AB8500_IT_MASK17_REG 0x0E50
80	#define AB8500_IT_MASK18_REG 0x0E51
81	#define AB8500_IT_MASK19_REG 0x0E52
82	#define AB8500_IT_MASK20_REG 0x0E53
83	#define AB8500_IT_MASK21_REG 0x0E54
84	#define AB8500_IT_MASK22_REG 0x0E55
85	#define AB8500_IT_MASK23_REG 0x0E56
86	#define AB8500_IT_MASK24_REG 0x0E57
87
88	#define AB8500_REV_REG 0x1080
89
90	/*
91	* Map interrupt numbers to the LATCH and MASK register offsets, Interrupt
92	* numbers are indexed into this array with (num / 8).
93	*
94	* This is one off from the register names, i.e. AB8500_IT_MASK1_REG is at
95	* offset 0.
96	*/
97	static const int ab8500_irq_regoffset[AB8500_NUM_IRQ_REGS] = {
98	0, 1, 2, 3, 4, 6, 7, 8, 9, 18, 19, 20, 21,
99	};
100
101	static int __ab8500_write(struct ab8500 *ab8500, u16 addr, u8 data)
102	{
103	int ret;
104
105	dev_vdbg(ab8500->dev, "wr: addr %#x <= %#x\n", addr, data);
106
107	ret = ab8500->write(ab8500, addr, data);
108	if (ret < 0)
109	dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
110	addr, ret);
111
112	return ret;
113	}
114
115	/**
116	* ab8500_write() - write an AB8500 register
117	* @ab8500: device to write to
118	* @addr: address of the register
119	* @data: value to write
120	*/
121	int ab8500_write(struct ab8500 *ab8500, u16 addr, u8 data)
122	{
123	int ret;
124
125	mutex_lock(&ab8500->lock);
126	ret = __ab8500_write(ab8500, addr, data);
127	mutex_unlock(&ab8500->lock);
128
129	return ret;
130	}
131	EXPORT_SYMBOL_GPL(ab8500_write);
132
133	static int __ab8500_read(struct ab8500 *ab8500, u16 addr)
134	{
135	int ret;
136
137	ret = ab8500->read(ab8500, addr);
138	if (ret < 0)
139	dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
140	addr, ret);
141
142	dev_vdbg(ab8500->dev, "rd: addr %#x => data %#x\n", addr, ret);
143
144	return ret;
145	}
146
147	/**
148	* ab8500_read() - read an AB8500 register
149	* @ab8500: device to read from
150	* @addr: address of the register
151	*/
152	int ab8500_read(struct ab8500 *ab8500, u16 addr)
153	{
154	int ret;
155
156	mutex_lock(&ab8500->lock);
157	ret = __ab8500_read(ab8500, addr);
158	mutex_unlock(&ab8500->lock);
159
160	return ret;
161	}
162	EXPORT_SYMBOL_GPL(ab8500_read);
163
164	/**
165	* ab8500_set_bits() - set a bitfield in an AB8500 register
166	* @ab8500: device to read from
167	* @addr: address of the register
168	* @mask: mask of the bitfield to modify
169	* @data: value to set to the bitfield
170	*/
171	int ab8500_set_bits(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data)
172	{
173	int ret;
174
175	mutex_lock(&ab8500->lock);
176
177	ret = __ab8500_read(ab8500, addr);
178	if (ret < 0)
179	goto out;
180
181	ret &= ~mask;
182	ret \|= data;
183
184	ret = __ab8500_write(ab8500, addr, ret);
185
186	out:
187	mutex_unlock(&ab8500->lock);
188	return ret;
189	}
190	EXPORT_SYMBOL_GPL(ab8500_set_bits);
191
192	static void ab8500_irq_lock(unsigned int irq)
193	{
194	struct ab8500 *ab8500 = get_irq_chip_data(irq);
195
196	mutex_lock(&ab8500->irq_lock);
197	}
198
199	static void ab8500_irq_sync_unlock(unsigned int irq)
200	{
201	struct ab8500 *ab8500 = get_irq_chip_data(irq);
202	int i;
203
204	for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) {
205	u8 old = ab8500->oldmask[i];
206	u8 new = ab8500->mask[i];
207	int reg;
208
209	if (new == old)
210	continue;
211
212	ab8500->oldmask[i] = new;
213
214	reg = AB8500_IT_MASK1_REG + ab8500_irq_regoffset[i];
215	ab8500_write(ab8500, reg, new);
216	}
217
218	mutex_unlock(&ab8500->irq_lock);
219	}
220
221	static void ab8500_irq_mask(unsigned int irq)
222	{
223	struct ab8500 *ab8500 = get_irq_chip_data(irq);
224	int offset = irq - ab8500->irq_base;
225	int index = offset / 8;
226	int mask = 1 << (offset % 8);
227
228	ab8500->mask[index] \|= mask;
229	}
230
231	static void ab8500_irq_unmask(unsigned int irq)
232	{
233	struct ab8500 *ab8500 = get_irq_chip_data(irq);
234	int offset = irq - ab8500->irq_base;
235	int index = offset / 8;
236	int mask = 1 << (offset % 8);
237
238	ab8500->mask[index] &= ~mask;
239	}
240
241	static struct irq_chip ab8500_irq_chip = {
242	.name = "ab8500",
243	.bus_lock = ab8500_irq_lock,
244	.bus_sync_unlock = ab8500_irq_sync_unlock,
245	.mask = ab8500_irq_mask,
246	.unmask = ab8500_irq_unmask,
247	};
248
249	static irqreturn_t ab8500_irq(int irq, void *dev)
250	{
251	struct ab8500 *ab8500 = dev;
252	int i;
253
254	dev_vdbg(ab8500->dev, "interrupt\n");
255
256	for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) {
257	int regoffset = ab8500_irq_regoffset[i];
258	int status;
259
260	status = ab8500_read(ab8500, AB8500_IT_LATCH1_REG + regoffset);
261	if (status <= 0)
262	continue;
263
264	do {
265	int bit = __ffs(status);
266	int line = i * 8 + bit;
267
268	handle_nested_irq(ab8500->irq_base + line);
269	status &= ~(1 << bit);
270	} while (status);
271	}
272
273	return IRQ_HANDLED;
274	}
275
276	static int ab8500_irq_init(struct ab8500 *ab8500)
277	{
278	int base = ab8500->irq_base;
279	int irq;
280
281	for (irq = base; irq < base + AB8500_NR_IRQS; irq++) {
282	set_irq_chip_data(irq, ab8500);
283	set_irq_chip_and_handler(irq, &ab8500_irq_chip,
284	handle_simple_irq);
285	set_irq_nested_thread(irq, 1);
286	#ifdef CONFIG_ARM
287	set_irq_flags(irq, IRQF_VALID);
288	#else
289	set_irq_noprobe(irq);
290	#endif
291	}
292
293	return 0;
294	}
295
296	static void ab8500_irq_remove(struct ab8500 *ab8500)
297	{
298	int base = ab8500->irq_base;
299	int irq;
300
301	for (irq = base; irq < base + AB8500_NR_IRQS; irq++) {
302	#ifdef CONFIG_ARM
303	set_irq_flags(irq, 0);
304	#endif
305	set_irq_chip_and_handler(irq, NULL, NULL);
306	set_irq_chip_data(irq, NULL);
307	}
308	}
309
310	static struct resource ab8500_gpadc_resources[] = {
311	{
312	.name = "HW_CONV_END",
313	.start = AB8500_INT_GP_HW_ADC_CONV_END,
314	.end = AB8500_INT_GP_HW_ADC_CONV_END,
315	.flags = IORESOURCE_IRQ,
316	},
317	{
318	.name = "SW_CONV_END",
319	.start = AB8500_INT_GP_SW_ADC_CONV_END,
320	.end = AB8500_INT_GP_SW_ADC_CONV_END,
321	.flags = IORESOURCE_IRQ,
322	},
323	};
324
325	static struct resource ab8500_rtc_resources[] = {
326	{
327	.name = "60S",
328	.start = AB8500_INT_RTC_60S,
329	.end = AB8500_INT_RTC_60S,
330	.flags = IORESOURCE_IRQ,
331	},
332	{
333	.name = "ALARM",
334	.start = AB8500_INT_RTC_ALARM,
335	.end = AB8500_INT_RTC_ALARM,
336	.flags = IORESOURCE_IRQ,
337	},
338	};
339
340	static struct mfd_cell ab8500_devs[] = {
341	{
342	.name = "ab8500-gpadc",
343	.num_resources = ARRAY_SIZE(ab8500_gpadc_resources),
344	.resources = ab8500_gpadc_resources,
345	},
346	{
347	.name = "ab8500-rtc",
348	.num_resources = ARRAY_SIZE(ab8500_rtc_resources),
349	.resources = ab8500_rtc_resources,
350	},
351	{ .name = "ab8500-charger", },
352	{ .name = "ab8500-audio", },
353	{ .name = "ab8500-usb", },
354	{ .name = "ab8500-pwm", },
355	};
356
357	int __devinit ab8500_init(struct ab8500 *ab8500)
358	{
359	struct ab8500_platform_data *plat = dev_get_platdata(ab8500->dev);
360	int ret;
361	int i;
362
363	if (plat)
364	ab8500->irq_base = plat->irq_base;
365
366	mutex_init(&ab8500->lock);
367	mutex_init(&ab8500->irq_lock);
368
369	ret = ab8500_read(ab8500, AB8500_REV_REG);
370	if (ret < 0)
371	return ret;
372
373	/*
374	* 0x0 - Early Drop
375	* 0x10 - Cut 1.0
376	* 0x11 - Cut 1.1
377	*/
378	if (ret == 0x0 \|\| ret == 0x10 \|\| ret == 0x11) {
379	ab8500->revision = ret;
380	dev_info(ab8500->dev, "detected chip, revision: %#x\n", ret);
381	} else {
382	dev_err(ab8500->dev, "unknown chip, revision: %#x\n", ret);
383	return -EINVAL;
384	}
385
386	if (plat && plat->init)
387	plat->init(ab8500);
388
389	/* Clear and mask all interrupts */
390	for (i = 0; i < 10; i++) {
391	ab8500_read(ab8500, AB8500_IT_LATCH1_REG + i);
392	ab8500_write(ab8500, AB8500_IT_MASK1_REG + i, 0xff);
393	}
394
395	for (i = 18; i < 24; i++) {
396	ab8500_read(ab8500, AB8500_IT_LATCH1_REG + i);
397	ab8500_write(ab8500, AB8500_IT_MASK1_REG + i, 0xff);
398	}
399
400	for (i = 0; i < AB8500_NUM_IRQ_REGS; i++)
401	ab8500->mask[i] = ab8500->oldmask[i] = 0xff;
402
403	if (ab8500->irq_base) {
404	ret = ab8500_irq_init(ab8500);
405	if (ret)
406	return ret;
407
408	ret = request_threaded_irq(ab8500->irq, NULL, ab8500_irq,
409	IRQF_ONESHOT, "ab8500", ab8500);
410	if (ret)
411	goto out_removeirq;
412	}
413
414	ret = mfd_add_devices(ab8500->dev, -1, ab8500_devs,
415	ARRAY_SIZE(ab8500_devs), NULL,
416	ab8500->irq_base);
417	if (ret)
418	goto out_freeirq;
419
420	return ret;
421
422	out_freeirq:
423	if (ab8500->irq_base) {
424	free_irq(ab8500->irq, ab8500);
425	out_removeirq:
426	ab8500_irq_remove(ab8500);
427	}
428	return ret;
429	}
430
431	int __devexit ab8500_exit(struct ab8500 *ab8500)
432	{
433	mfd_remove_devices(ab8500->dev);
434	if (ab8500->irq_base) {
435	free_irq(ab8500->irq, ab8500);
436	ab8500_irq_remove(ab8500);
437	}
438
439	return 0;
440	}
441
442	MODULE_AUTHOR("Srinidhi Kasagar, Rabin Vincent");
443	MODULE_DESCRIPTION("AB8500 MFD core");
444	MODULE_LICENSE("GPL v2");