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Commit | Line | Data |
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fa9ff4b1 SO |
1 | /* |
2 | * driver/mfd/asic3.c | |
3 | * | |
4 | * Compaq ASIC3 support. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Copyright 2001 Compaq Computer Corporation. | |
11 | * Copyright 2004-2005 Phil Blundell | |
6f2384c4 | 12 | * Copyright 2007-2008 OpenedHand Ltd. |
fa9ff4b1 SO |
13 | * |
14 | * Authors: Phil Blundell <pb@handhelds.org>, | |
15 | * Samuel Ortiz <sameo@openedhand.com> | |
16 | * | |
17 | */ | |
18 | ||
fa9ff4b1 | 19 | #include <linux/kernel.h> |
9461f65a | 20 | #include <linux/delay.h> |
fa9ff4b1 | 21 | #include <linux/irq.h> |
6f2384c4 | 22 | #include <linux/gpio.h> |
5d4a357d | 23 | #include <linux/export.h> |
fa9ff4b1 | 24 | #include <linux/io.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
fa9ff4b1 SO |
26 | #include <linux/spinlock.h> |
27 | #include <linux/platform_device.h> | |
28 | ||
29 | #include <linux/mfd/asic3.h> | |
9461f65a PZ |
30 | #include <linux/mfd/core.h> |
31 | #include <linux/mfd/ds1wm.h> | |
09f05ce8 | 32 | #include <linux/mfd/tmio.h> |
fa9ff4b1 | 33 | |
e956a2a8 PZ |
34 | enum { |
35 | ASIC3_CLOCK_SPI, | |
36 | ASIC3_CLOCK_OWM, | |
37 | ASIC3_CLOCK_PWM0, | |
38 | ASIC3_CLOCK_PWM1, | |
39 | ASIC3_CLOCK_LED0, | |
40 | ASIC3_CLOCK_LED1, | |
41 | ASIC3_CLOCK_LED2, | |
42 | ASIC3_CLOCK_SD_HOST, | |
43 | ASIC3_CLOCK_SD_BUS, | |
44 | ASIC3_CLOCK_SMBUS, | |
45 | ASIC3_CLOCK_EX0, | |
46 | ASIC3_CLOCK_EX1, | |
47 | }; | |
48 | ||
49 | struct asic3_clk { | |
50 | int enabled; | |
51 | unsigned int cdex; | |
52 | unsigned long rate; | |
53 | }; | |
54 | ||
55 | #define INIT_CDEX(_name, _rate) \ | |
56 | [ASIC3_CLOCK_##_name] = { \ | |
57 | .cdex = CLOCK_CDEX_##_name, \ | |
58 | .rate = _rate, \ | |
59 | } | |
60 | ||
59f2ad2e | 61 | static struct asic3_clk asic3_clk_init[] __initdata = { |
e956a2a8 PZ |
62 | INIT_CDEX(SPI, 0), |
63 | INIT_CDEX(OWM, 5000000), | |
64 | INIT_CDEX(PWM0, 0), | |
65 | INIT_CDEX(PWM1, 0), | |
66 | INIT_CDEX(LED0, 0), | |
67 | INIT_CDEX(LED1, 0), | |
68 | INIT_CDEX(LED2, 0), | |
69 | INIT_CDEX(SD_HOST, 24576000), | |
70 | INIT_CDEX(SD_BUS, 12288000), | |
71 | INIT_CDEX(SMBUS, 0), | |
72 | INIT_CDEX(EX0, 32768), | |
73 | INIT_CDEX(EX1, 24576000), | |
74 | }; | |
75 | ||
6f2384c4 SO |
76 | struct asic3 { |
77 | void __iomem *mapping; | |
78 | unsigned int bus_shift; | |
79 | unsigned int irq_nr; | |
80 | unsigned int irq_base; | |
81 | spinlock_t lock; | |
82 | u16 irq_bothedge[4]; | |
83 | struct gpio_chip gpio; | |
84 | struct device *dev; | |
64e8867b | 85 | void __iomem *tmio_cnf; |
e956a2a8 PZ |
86 | |
87 | struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)]; | |
6f2384c4 SO |
88 | }; |
89 | ||
90 | static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset); | |
91 | ||
13ca4f66 | 92 | void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 value) |
fa9ff4b1 | 93 | { |
b32661e0 | 94 | iowrite16(value, asic->mapping + |
fa9ff4b1 SO |
95 | (reg >> asic->bus_shift)); |
96 | } | |
13ca4f66 | 97 | EXPORT_SYMBOL_GPL(asic3_write_register); |
fa9ff4b1 | 98 | |
13ca4f66 | 99 | u32 asic3_read_register(struct asic3 *asic, unsigned int reg) |
fa9ff4b1 | 100 | { |
b32661e0 | 101 | return ioread16(asic->mapping + |
fa9ff4b1 SO |
102 | (reg >> asic->bus_shift)); |
103 | } | |
13ca4f66 | 104 | EXPORT_SYMBOL_GPL(asic3_read_register); |
fa9ff4b1 | 105 | |
59f2ad2e | 106 | static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set) |
6483c1b5 PZ |
107 | { |
108 | unsigned long flags; | |
109 | u32 val; | |
110 | ||
111 | spin_lock_irqsave(&asic->lock, flags); | |
112 | val = asic3_read_register(asic, reg); | |
113 | if (set) | |
114 | val |= bits; | |
115 | else | |
116 | val &= ~bits; | |
117 | asic3_write_register(asic, reg, val); | |
118 | spin_unlock_irqrestore(&asic->lock, flags); | |
119 | } | |
120 | ||
fa9ff4b1 SO |
121 | /* IRQs */ |
122 | #define MAX_ASIC_ISR_LOOPS 20 | |
3b8139f8 SO |
123 | #define ASIC3_GPIO_BASE_INCR \ |
124 | (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE) | |
fa9ff4b1 SO |
125 | |
126 | static void asic3_irq_flip_edge(struct asic3 *asic, | |
127 | u32 base, int bit) | |
128 | { | |
129 | u16 edge; | |
130 | unsigned long flags; | |
131 | ||
132 | spin_lock_irqsave(&asic->lock, flags); | |
133 | edge = asic3_read_register(asic, | |
3b8139f8 | 134 | base + ASIC3_GPIO_EDGE_TRIGGER); |
fa9ff4b1 SO |
135 | edge ^= bit; |
136 | asic3_write_register(asic, | |
3b8139f8 | 137 | base + ASIC3_GPIO_EDGE_TRIGGER, edge); |
fa9ff4b1 SO |
138 | spin_unlock_irqrestore(&asic->lock, flags); |
139 | } | |
140 | ||
141 | static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc) | |
142 | { | |
52a7d607 TG |
143 | struct asic3 *asic = irq_desc_get_handler_data(desc); |
144 | struct irq_data *data = irq_desc_get_irq_data(desc); | |
fa9ff4b1 SO |
145 | int iter, i; |
146 | unsigned long flags; | |
fa9ff4b1 | 147 | |
a09aee8b | 148 | data->chip->irq_ack(data); |
fa9ff4b1 SO |
149 | |
150 | for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) { | |
151 | u32 status; | |
152 | int bank; | |
153 | ||
154 | spin_lock_irqsave(&asic->lock, flags); | |
155 | status = asic3_read_register(asic, | |
3b8139f8 | 156 | ASIC3_OFFSET(INTR, P_INT_STAT)); |
fa9ff4b1 SO |
157 | spin_unlock_irqrestore(&asic->lock, flags); |
158 | ||
159 | /* Check all ten register bits */ | |
160 | if ((status & 0x3ff) == 0) | |
161 | break; | |
162 | ||
163 | /* Handle GPIO IRQs */ | |
164 | for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) { | |
165 | if (status & (1 << bank)) { | |
166 | unsigned long base, istat; | |
167 | ||
3b8139f8 SO |
168 | base = ASIC3_GPIO_A_BASE |
169 | + bank * ASIC3_GPIO_BASE_INCR; | |
fa9ff4b1 SO |
170 | |
171 | spin_lock_irqsave(&asic->lock, flags); | |
172 | istat = asic3_read_register(asic, | |
173 | base + | |
3b8139f8 | 174 | ASIC3_GPIO_INT_STATUS); |
fa9ff4b1 SO |
175 | /* Clearing IntStatus */ |
176 | asic3_write_register(asic, | |
177 | base + | |
3b8139f8 | 178 | ASIC3_GPIO_INT_STATUS, 0); |
fa9ff4b1 SO |
179 | spin_unlock_irqrestore(&asic->lock, flags); |
180 | ||
181 | for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) { | |
182 | int bit = (1 << i); | |
183 | unsigned int irqnr; | |
184 | ||
185 | if (!(istat & bit)) | |
186 | continue; | |
187 | ||
188 | irqnr = asic->irq_base + | |
189 | (ASIC3_GPIOS_PER_BANK * bank) | |
190 | + i; | |
52a7d607 | 191 | generic_handle_irq(irqnr); |
fa9ff4b1 SO |
192 | if (asic->irq_bothedge[bank] & bit) |
193 | asic3_irq_flip_edge(asic, base, | |
194 | bit); | |
195 | } | |
196 | } | |
197 | } | |
198 | ||
199 | /* Handle remaining IRQs in the status register */ | |
200 | for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) { | |
201 | /* They start at bit 4 and go up */ | |
52a7d607 TG |
202 | if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) |
203 | generic_handle_irq(asic->irq_base + i); | |
fa9ff4b1 SO |
204 | } |
205 | } | |
206 | ||
207 | if (iter >= MAX_ASIC_ISR_LOOPS) | |
24f4f2ee | 208 | dev_err(asic->dev, "interrupt processing overrun\n"); |
fa9ff4b1 SO |
209 | } |
210 | ||
211 | static inline int asic3_irq_to_bank(struct asic3 *asic, int irq) | |
212 | { | |
213 | int n; | |
214 | ||
215 | n = (irq - asic->irq_base) >> 4; | |
216 | ||
3b8139f8 | 217 | return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)); |
fa9ff4b1 SO |
218 | } |
219 | ||
220 | static inline int asic3_irq_to_index(struct asic3 *asic, int irq) | |
221 | { | |
222 | return (irq - asic->irq_base) & 0xf; | |
223 | } | |
224 | ||
0f76aaeb | 225 | static void asic3_mask_gpio_irq(struct irq_data *data) |
fa9ff4b1 | 226 | { |
0f76aaeb | 227 | struct asic3 *asic = irq_data_get_irq_chip_data(data); |
fa9ff4b1 SO |
228 | u32 val, bank, index; |
229 | unsigned long flags; | |
230 | ||
0f76aaeb MB |
231 | bank = asic3_irq_to_bank(asic, data->irq); |
232 | index = asic3_irq_to_index(asic, data->irq); | |
fa9ff4b1 SO |
233 | |
234 | spin_lock_irqsave(&asic->lock, flags); | |
3b8139f8 | 235 | val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); |
fa9ff4b1 | 236 | val |= 1 << index; |
3b8139f8 | 237 | asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val); |
fa9ff4b1 SO |
238 | spin_unlock_irqrestore(&asic->lock, flags); |
239 | } | |
240 | ||
0f76aaeb | 241 | static void asic3_mask_irq(struct irq_data *data) |
fa9ff4b1 | 242 | { |
0f76aaeb | 243 | struct asic3 *asic = irq_data_get_irq_chip_data(data); |
fa9ff4b1 SO |
244 | int regval; |
245 | unsigned long flags; | |
246 | ||
247 | spin_lock_irqsave(&asic->lock, flags); | |
248 | regval = asic3_read_register(asic, | |
3b8139f8 SO |
249 | ASIC3_INTR_BASE + |
250 | ASIC3_INTR_INT_MASK); | |
fa9ff4b1 SO |
251 | |
252 | regval &= ~(ASIC3_INTMASK_MASK0 << | |
0f76aaeb | 253 | (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS))); |
fa9ff4b1 SO |
254 | |
255 | asic3_write_register(asic, | |
3b8139f8 SO |
256 | ASIC3_INTR_BASE + |
257 | ASIC3_INTR_INT_MASK, | |
fa9ff4b1 SO |
258 | regval); |
259 | spin_unlock_irqrestore(&asic->lock, flags); | |
260 | } | |
261 | ||
0f76aaeb | 262 | static void asic3_unmask_gpio_irq(struct irq_data *data) |
fa9ff4b1 | 263 | { |
0f76aaeb | 264 | struct asic3 *asic = irq_data_get_irq_chip_data(data); |
fa9ff4b1 SO |
265 | u32 val, bank, index; |
266 | unsigned long flags; | |
267 | ||
0f76aaeb MB |
268 | bank = asic3_irq_to_bank(asic, data->irq); |
269 | index = asic3_irq_to_index(asic, data->irq); | |
fa9ff4b1 SO |
270 | |
271 | spin_lock_irqsave(&asic->lock, flags); | |
3b8139f8 | 272 | val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); |
fa9ff4b1 | 273 | val &= ~(1 << index); |
3b8139f8 | 274 | asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val); |
fa9ff4b1 SO |
275 | spin_unlock_irqrestore(&asic->lock, flags); |
276 | } | |
277 | ||
0f76aaeb | 278 | static void asic3_unmask_irq(struct irq_data *data) |
fa9ff4b1 | 279 | { |
0f76aaeb | 280 | struct asic3 *asic = irq_data_get_irq_chip_data(data); |
fa9ff4b1 SO |
281 | int regval; |
282 | unsigned long flags; | |
283 | ||
284 | spin_lock_irqsave(&asic->lock, flags); | |
285 | regval = asic3_read_register(asic, | |
3b8139f8 SO |
286 | ASIC3_INTR_BASE + |
287 | ASIC3_INTR_INT_MASK); | |
fa9ff4b1 SO |
288 | |
289 | regval |= (ASIC3_INTMASK_MASK0 << | |
0f76aaeb | 290 | (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS))); |
fa9ff4b1 SO |
291 | |
292 | asic3_write_register(asic, | |
3b8139f8 SO |
293 | ASIC3_INTR_BASE + |
294 | ASIC3_INTR_INT_MASK, | |
fa9ff4b1 SO |
295 | regval); |
296 | spin_unlock_irqrestore(&asic->lock, flags); | |
297 | } | |
298 | ||
0f76aaeb | 299 | static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type) |
fa9ff4b1 | 300 | { |
0f76aaeb | 301 | struct asic3 *asic = irq_data_get_irq_chip_data(data); |
fa9ff4b1 SO |
302 | u32 bank, index; |
303 | u16 trigger, level, edge, bit; | |
304 | unsigned long flags; | |
305 | ||
0f76aaeb MB |
306 | bank = asic3_irq_to_bank(asic, data->irq); |
307 | index = asic3_irq_to_index(asic, data->irq); | |
fa9ff4b1 SO |
308 | bit = 1<<index; |
309 | ||
310 | spin_lock_irqsave(&asic->lock, flags); | |
311 | level = asic3_read_register(asic, | |
3b8139f8 | 312 | bank + ASIC3_GPIO_LEVEL_TRIGGER); |
fa9ff4b1 | 313 | edge = asic3_read_register(asic, |
3b8139f8 | 314 | bank + ASIC3_GPIO_EDGE_TRIGGER); |
fa9ff4b1 | 315 | trigger = asic3_read_register(asic, |
3b8139f8 | 316 | bank + ASIC3_GPIO_TRIGGER_TYPE); |
0f76aaeb | 317 | asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit; |
fa9ff4b1 | 318 | |
6cab4860 | 319 | if (type == IRQ_TYPE_EDGE_RISING) { |
fa9ff4b1 SO |
320 | trigger |= bit; |
321 | edge |= bit; | |
6cab4860 | 322 | } else if (type == IRQ_TYPE_EDGE_FALLING) { |
fa9ff4b1 SO |
323 | trigger |= bit; |
324 | edge &= ~bit; | |
6cab4860 | 325 | } else if (type == IRQ_TYPE_EDGE_BOTH) { |
fa9ff4b1 | 326 | trigger |= bit; |
0f76aaeb | 327 | if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base)) |
fa9ff4b1 SO |
328 | edge &= ~bit; |
329 | else | |
330 | edge |= bit; | |
0f76aaeb | 331 | asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit; |
6cab4860 | 332 | } else if (type == IRQ_TYPE_LEVEL_LOW) { |
fa9ff4b1 SO |
333 | trigger &= ~bit; |
334 | level &= ~bit; | |
6cab4860 | 335 | } else if (type == IRQ_TYPE_LEVEL_HIGH) { |
fa9ff4b1 SO |
336 | trigger &= ~bit; |
337 | level |= bit; | |
338 | } else { | |
339 | /* | |
6cab4860 | 340 | * if type == IRQ_TYPE_NONE, we should mask interrupts, but |
fa9ff4b1 SO |
341 | * be careful to not unmask them if mask was also called. |
342 | * Probably need internal state for mask. | |
343 | */ | |
24f4f2ee | 344 | dev_notice(asic->dev, "irq type not changed\n"); |
fa9ff4b1 | 345 | } |
3b8139f8 | 346 | asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER, |
fa9ff4b1 | 347 | level); |
3b8139f8 | 348 | asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER, |
fa9ff4b1 | 349 | edge); |
3b8139f8 | 350 | asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE, |
fa9ff4b1 SO |
351 | trigger); |
352 | spin_unlock_irqrestore(&asic->lock, flags); | |
353 | return 0; | |
354 | } | |
355 | ||
356 | static struct irq_chip asic3_gpio_irq_chip = { | |
357 | .name = "ASIC3-GPIO", | |
0f76aaeb MB |
358 | .irq_ack = asic3_mask_gpio_irq, |
359 | .irq_mask = asic3_mask_gpio_irq, | |
360 | .irq_unmask = asic3_unmask_gpio_irq, | |
361 | .irq_set_type = asic3_gpio_irq_type, | |
fa9ff4b1 SO |
362 | }; |
363 | ||
364 | static struct irq_chip asic3_irq_chip = { | |
365 | .name = "ASIC3", | |
0f76aaeb MB |
366 | .irq_ack = asic3_mask_irq, |
367 | .irq_mask = asic3_mask_irq, | |
368 | .irq_unmask = asic3_unmask_irq, | |
fa9ff4b1 SO |
369 | }; |
370 | ||
065032f6 | 371 | static int __init asic3_irq_probe(struct platform_device *pdev) |
fa9ff4b1 SO |
372 | { |
373 | struct asic3 *asic = platform_get_drvdata(pdev); | |
374 | unsigned long clksel = 0; | |
375 | unsigned int irq, irq_base; | |
c491b2ff | 376 | int ret; |
fa9ff4b1 | 377 | |
c491b2ff RK |
378 | ret = platform_get_irq(pdev, 0); |
379 | if (ret < 0) | |
380 | return ret; | |
381 | asic->irq_nr = ret; | |
fa9ff4b1 SO |
382 | |
383 | /* turn on clock to IRQ controller */ | |
384 | clksel |= CLOCK_SEL_CX; | |
385 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), | |
386 | clksel); | |
387 | ||
388 | irq_base = asic->irq_base; | |
389 | ||
390 | for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) { | |
391 | if (irq < asic->irq_base + ASIC3_NUM_GPIOS) | |
d5bb1221 | 392 | irq_set_chip(irq, &asic3_gpio_irq_chip); |
fa9ff4b1 | 393 | else |
d5bb1221 | 394 | irq_set_chip(irq, &asic3_irq_chip); |
fa9ff4b1 | 395 | |
d5bb1221 TG |
396 | irq_set_chip_data(irq, asic); |
397 | irq_set_handler(irq, handle_level_irq); | |
fa9ff4b1 SO |
398 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
399 | } | |
400 | ||
3b8139f8 | 401 | asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK), |
fa9ff4b1 SO |
402 | ASIC3_INTMASK_GINTMASK); |
403 | ||
d5bb1221 TG |
404 | irq_set_chained_handler(asic->irq_nr, asic3_irq_demux); |
405 | irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING); | |
406 | irq_set_handler_data(asic->irq_nr, asic); | |
fa9ff4b1 SO |
407 | |
408 | return 0; | |
409 | } | |
410 | ||
411 | static void asic3_irq_remove(struct platform_device *pdev) | |
412 | { | |
413 | struct asic3 *asic = platform_get_drvdata(pdev); | |
414 | unsigned int irq, irq_base; | |
415 | ||
416 | irq_base = asic->irq_base; | |
417 | ||
418 | for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) { | |
419 | set_irq_flags(irq, 0); | |
d6f7ce9f | 420 | irq_set_chip_and_handler(irq, NULL, NULL); |
d5bb1221 | 421 | irq_set_chip_data(irq, NULL); |
fa9ff4b1 | 422 | } |
d5bb1221 | 423 | irq_set_chained_handler(asic->irq_nr, NULL); |
fa9ff4b1 SO |
424 | } |
425 | ||
426 | /* GPIOs */ | |
6f2384c4 SO |
427 | static int asic3_gpio_direction(struct gpio_chip *chip, |
428 | unsigned offset, int out) | |
429 | { | |
430 | u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg; | |
431 | unsigned int gpio_base; | |
432 | unsigned long flags; | |
433 | struct asic3 *asic; | |
434 | ||
435 | asic = container_of(chip, struct asic3, gpio); | |
436 | gpio_base = ASIC3_GPIO_TO_BASE(offset); | |
437 | ||
3b8139f8 | 438 | if (gpio_base > ASIC3_GPIO_D_BASE) { |
24f4f2ee SO |
439 | dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", |
440 | gpio_base, offset); | |
6f2384c4 SO |
441 | return -EINVAL; |
442 | } | |
443 | ||
444 | spin_lock_irqsave(&asic->lock, flags); | |
445 | ||
3b8139f8 | 446 | out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION); |
6f2384c4 SO |
447 | |
448 | /* Input is 0, Output is 1 */ | |
449 | if (out) | |
450 | out_reg |= mask; | |
451 | else | |
452 | out_reg &= ~mask; | |
453 | ||
3b8139f8 | 454 | asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg); |
6f2384c4 SO |
455 | |
456 | spin_unlock_irqrestore(&asic->lock, flags); | |
457 | ||
458 | return 0; | |
459 | ||
460 | } | |
461 | ||
462 | static int asic3_gpio_direction_input(struct gpio_chip *chip, | |
463 | unsigned offset) | |
464 | { | |
465 | return asic3_gpio_direction(chip, offset, 0); | |
466 | } | |
467 | ||
468 | static int asic3_gpio_direction_output(struct gpio_chip *chip, | |
469 | unsigned offset, int value) | |
470 | { | |
471 | return asic3_gpio_direction(chip, offset, 1); | |
472 | } | |
473 | ||
474 | static int asic3_gpio_get(struct gpio_chip *chip, | |
475 | unsigned offset) | |
476 | { | |
477 | unsigned int gpio_base; | |
478 | u32 mask = ASIC3_GPIO_TO_MASK(offset); | |
479 | struct asic3 *asic; | |
480 | ||
481 | asic = container_of(chip, struct asic3, gpio); | |
482 | gpio_base = ASIC3_GPIO_TO_BASE(offset); | |
483 | ||
3b8139f8 | 484 | if (gpio_base > ASIC3_GPIO_D_BASE) { |
24f4f2ee SO |
485 | dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", |
486 | gpio_base, offset); | |
6f2384c4 SO |
487 | return -EINVAL; |
488 | } | |
489 | ||
3b8139f8 | 490 | return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask; |
6f2384c4 SO |
491 | } |
492 | ||
493 | static void asic3_gpio_set(struct gpio_chip *chip, | |
494 | unsigned offset, int value) | |
495 | { | |
496 | u32 mask, out_reg; | |
497 | unsigned int gpio_base; | |
498 | unsigned long flags; | |
499 | struct asic3 *asic; | |
500 | ||
501 | asic = container_of(chip, struct asic3, gpio); | |
502 | gpio_base = ASIC3_GPIO_TO_BASE(offset); | |
503 | ||
3b8139f8 | 504 | if (gpio_base > ASIC3_GPIO_D_BASE) { |
24f4f2ee SO |
505 | dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", |
506 | gpio_base, offset); | |
6f2384c4 SO |
507 | return; |
508 | } | |
509 | ||
510 | mask = ASIC3_GPIO_TO_MASK(offset); | |
511 | ||
512 | spin_lock_irqsave(&asic->lock, flags); | |
513 | ||
3b8139f8 | 514 | out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT); |
6f2384c4 SO |
515 | |
516 | if (value) | |
517 | out_reg |= mask; | |
518 | else | |
519 | out_reg &= ~mask; | |
520 | ||
3b8139f8 | 521 | asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg); |
6f2384c4 SO |
522 | |
523 | spin_unlock_irqrestore(&asic->lock, flags); | |
524 | ||
525 | return; | |
526 | } | |
527 | ||
065032f6 PZ |
528 | static __init int asic3_gpio_probe(struct platform_device *pdev, |
529 | u16 *gpio_config, int num) | |
fa9ff4b1 | 530 | { |
fa9ff4b1 | 531 | struct asic3 *asic = platform_get_drvdata(pdev); |
3b26bf17 SO |
532 | u16 alt_reg[ASIC3_NUM_GPIO_BANKS]; |
533 | u16 out_reg[ASIC3_NUM_GPIO_BANKS]; | |
534 | u16 dir_reg[ASIC3_NUM_GPIO_BANKS]; | |
535 | int i; | |
fa9ff4b1 | 536 | |
59f0cb0f RK |
537 | memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); |
538 | memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); | |
539 | memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); | |
3b26bf17 SO |
540 | |
541 | /* Enable all GPIOs */ | |
3b8139f8 SO |
542 | asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff); |
543 | asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff); | |
544 | asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff); | |
545 | asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff); | |
fa9ff4b1 | 546 | |
3b26bf17 SO |
547 | for (i = 0; i < num; i++) { |
548 | u8 alt, pin, dir, init, bank_num, bit_num; | |
549 | u16 config = gpio_config[i]; | |
550 | ||
551 | pin = ASIC3_CONFIG_GPIO_PIN(config); | |
552 | alt = ASIC3_CONFIG_GPIO_ALT(config); | |
553 | dir = ASIC3_CONFIG_GPIO_DIR(config); | |
554 | init = ASIC3_CONFIG_GPIO_INIT(config); | |
555 | ||
556 | bank_num = ASIC3_GPIO_TO_BANK(pin); | |
557 | bit_num = ASIC3_GPIO_TO_BIT(pin); | |
558 | ||
559 | alt_reg[bank_num] |= (alt << bit_num); | |
560 | out_reg[bank_num] |= (init << bit_num); | |
561 | dir_reg[bank_num] |= (dir << bit_num); | |
562 | } | |
563 | ||
564 | for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) { | |
565 | asic3_write_register(asic, | |
566 | ASIC3_BANK_TO_BASE(i) + | |
3b8139f8 | 567 | ASIC3_GPIO_DIRECTION, |
3b26bf17 SO |
568 | dir_reg[i]); |
569 | asic3_write_register(asic, | |
3b8139f8 | 570 | ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT, |
3b26bf17 SO |
571 | out_reg[i]); |
572 | asic3_write_register(asic, | |
573 | ASIC3_BANK_TO_BASE(i) + | |
3b8139f8 | 574 | ASIC3_GPIO_ALT_FUNCTION, |
3b26bf17 | 575 | alt_reg[i]); |
fa9ff4b1 SO |
576 | } |
577 | ||
6f2384c4 | 578 | return gpiochip_add(&asic->gpio); |
fa9ff4b1 SO |
579 | } |
580 | ||
6f2384c4 | 581 | static int asic3_gpio_remove(struct platform_device *pdev) |
fa9ff4b1 | 582 | { |
6f2384c4 SO |
583 | struct asic3 *asic = platform_get_drvdata(pdev); |
584 | ||
585 | return gpiochip_remove(&asic->gpio); | |
fa9ff4b1 SO |
586 | } |
587 | ||
c29a8127 | 588 | static void asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk) |
e956a2a8 PZ |
589 | { |
590 | unsigned long flags; | |
591 | u32 cdex; | |
592 | ||
593 | spin_lock_irqsave(&asic->lock, flags); | |
594 | if (clk->enabled++ == 0) { | |
595 | cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX)); | |
596 | cdex |= clk->cdex; | |
597 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex); | |
598 | } | |
599 | spin_unlock_irqrestore(&asic->lock, flags); | |
e956a2a8 PZ |
600 | } |
601 | ||
602 | static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk) | |
603 | { | |
604 | unsigned long flags; | |
605 | u32 cdex; | |
606 | ||
607 | WARN_ON(clk->enabled == 0); | |
608 | ||
609 | spin_lock_irqsave(&asic->lock, flags); | |
610 | if (--clk->enabled == 0) { | |
611 | cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX)); | |
612 | cdex &= ~clk->cdex; | |
613 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex); | |
614 | } | |
615 | spin_unlock_irqrestore(&asic->lock, flags); | |
616 | } | |
fa9ff4b1 | 617 | |
9461f65a PZ |
618 | /* MFD cells (SPI, PWM, LED, DS1WM, MMC) */ |
619 | static struct ds1wm_driver_data ds1wm_pdata = { | |
620 | .active_high = 1, | |
f607e7fc | 621 | .reset_recover_delay = 1, |
9461f65a PZ |
622 | }; |
623 | ||
624 | static struct resource ds1wm_resources[] = { | |
625 | { | |
626 | .start = ASIC3_OWM_BASE, | |
627 | .end = ASIC3_OWM_BASE + 0x13, | |
628 | .flags = IORESOURCE_MEM, | |
629 | }, | |
630 | { | |
631 | .start = ASIC3_IRQ_OWM, | |
fe421425 | 632 | .end = ASIC3_IRQ_OWM, |
9461f65a PZ |
633 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, |
634 | }, | |
635 | }; | |
636 | ||
637 | static int ds1wm_enable(struct platform_device *pdev) | |
638 | { | |
639 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
640 | ||
641 | /* Turn on external clocks and the OWM clock */ | |
642 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); | |
643 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); | |
644 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); | |
645 | msleep(1); | |
646 | ||
647 | /* Reset and enable DS1WM */ | |
648 | asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET), | |
649 | ASIC3_EXTCF_OWM_RESET, 1); | |
650 | msleep(1); | |
651 | asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET), | |
652 | ASIC3_EXTCF_OWM_RESET, 0); | |
653 | msleep(1); | |
654 | asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), | |
655 | ASIC3_EXTCF_OWM_EN, 1); | |
656 | msleep(1); | |
657 | ||
658 | return 0; | |
659 | } | |
660 | ||
661 | static int ds1wm_disable(struct platform_device *pdev) | |
662 | { | |
663 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
664 | ||
665 | asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), | |
666 | ASIC3_EXTCF_OWM_EN, 0); | |
667 | ||
668 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); | |
669 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); | |
670 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); | |
671 | ||
672 | return 0; | |
673 | } | |
674 | ||
675 | static struct mfd_cell asic3_cell_ds1wm = { | |
676 | .name = "ds1wm", | |
677 | .enable = ds1wm_enable, | |
678 | .disable = ds1wm_disable, | |
121ea573 SO |
679 | .platform_data = &ds1wm_pdata, |
680 | .pdata_size = sizeof(ds1wm_pdata), | |
9461f65a PZ |
681 | .num_resources = ARRAY_SIZE(ds1wm_resources), |
682 | .resources = ds1wm_resources, | |
683 | }; | |
684 | ||
64e8867b IM |
685 | static void asic3_mmc_pwr(struct platform_device *pdev, int state) |
686 | { | |
687 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
688 | ||
689 | tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state); | |
690 | } | |
691 | ||
692 | static void asic3_mmc_clk_div(struct platform_device *pdev, int state) | |
693 | { | |
694 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
695 | ||
696 | tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state); | |
697 | } | |
698 | ||
09f05ce8 | 699 | static struct tmio_mmc_data asic3_mmc_data = { |
64e8867b IM |
700 | .hclk = 24576000, |
701 | .set_pwr = asic3_mmc_pwr, | |
702 | .set_clk_div = asic3_mmc_clk_div, | |
09f05ce8 PZ |
703 | }; |
704 | ||
705 | static struct resource asic3_mmc_resources[] = { | |
706 | { | |
707 | .start = ASIC3_SD_CTRL_BASE, | |
708 | .end = ASIC3_SD_CTRL_BASE + 0x3ff, | |
709 | .flags = IORESOURCE_MEM, | |
710 | }, | |
09f05ce8 PZ |
711 | { |
712 | .start = 0, | |
713 | .end = 0, | |
714 | .flags = IORESOURCE_IRQ, | |
715 | }, | |
716 | }; | |
717 | ||
718 | static int asic3_mmc_enable(struct platform_device *pdev) | |
719 | { | |
720 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
721 | ||
722 | /* Not sure if it must be done bit by bit, but leaving as-is */ | |
723 | asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), | |
724 | ASIC3_SDHWCTRL_LEVCD, 1); | |
725 | asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), | |
726 | ASIC3_SDHWCTRL_LEVWP, 1); | |
727 | asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), | |
728 | ASIC3_SDHWCTRL_SUSPEND, 0); | |
729 | asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), | |
730 | ASIC3_SDHWCTRL_PCLR, 0); | |
731 | ||
732 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); | |
733 | /* CLK32 used for card detection and for interruption detection | |
734 | * when HCLK is stopped. | |
735 | */ | |
736 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); | |
737 | msleep(1); | |
738 | ||
739 | /* HCLK 24.576 MHz, BCLK 12.288 MHz: */ | |
740 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), | |
741 | CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL); | |
742 | ||
743 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]); | |
744 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]); | |
745 | msleep(1); | |
746 | ||
747 | asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), | |
748 | ASIC3_EXTCF_SD_MEM_ENABLE, 1); | |
749 | ||
750 | /* Enable SD card slot 3.3V power supply */ | |
751 | asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), | |
752 | ASIC3_SDHWCTRL_SDPWR, 1); | |
753 | ||
64e8867b IM |
754 | /* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */ |
755 | tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift, | |
756 | ASIC3_SD_CTRL_BASE >> 1); | |
757 | ||
09f05ce8 PZ |
758 | return 0; |
759 | } | |
760 | ||
761 | static int asic3_mmc_disable(struct platform_device *pdev) | |
762 | { | |
763 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
764 | ||
765 | /* Put in suspend mode */ | |
766 | asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), | |
767 | ASIC3_SDHWCTRL_SUSPEND, 1); | |
768 | ||
769 | /* Disable clocks */ | |
770 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]); | |
771 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]); | |
772 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); | |
773 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); | |
774 | return 0; | |
775 | } | |
776 | ||
777 | static struct mfd_cell asic3_cell_mmc = { | |
778 | .name = "tmio-mmc", | |
779 | .enable = asic3_mmc_enable, | |
780 | .disable = asic3_mmc_disable, | |
3c6e3653 PP |
781 | .suspend = asic3_mmc_disable, |
782 | .resume = asic3_mmc_enable, | |
ec71974f SO |
783 | .platform_data = &asic3_mmc_data, |
784 | .pdata_size = sizeof(asic3_mmc_data), | |
09f05ce8 PZ |
785 | .num_resources = ARRAY_SIZE(asic3_mmc_resources), |
786 | .resources = asic3_mmc_resources, | |
787 | }; | |
788 | ||
13ca4f66 PP |
789 | static const int clock_ledn[ASIC3_NUM_LEDS] = { |
790 | [0] = ASIC3_CLOCK_LED0, | |
791 | [1] = ASIC3_CLOCK_LED1, | |
792 | [2] = ASIC3_CLOCK_LED2, | |
793 | }; | |
794 | ||
795 | static int asic3_leds_enable(struct platform_device *pdev) | |
796 | { | |
797 | const struct mfd_cell *cell = mfd_get_cell(pdev); | |
798 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
799 | ||
800 | asic3_clk_enable(asic, &asic->clocks[clock_ledn[cell->id]]); | |
801 | ||
802 | return 0; | |
803 | } | |
804 | ||
805 | static int asic3_leds_disable(struct platform_device *pdev) | |
806 | { | |
807 | const struct mfd_cell *cell = mfd_get_cell(pdev); | |
808 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
809 | ||
810 | asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]); | |
811 | ||
812 | return 0; | |
813 | } | |
814 | ||
e0b13b5b PP |
815 | static int asic3_leds_suspend(struct platform_device *pdev) |
816 | { | |
817 | const struct mfd_cell *cell = mfd_get_cell(pdev); | |
818 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
819 | ||
820 | while (asic3_gpio_get(&asic->gpio, ASIC3_GPIO(C, cell->id)) != 0) | |
821 | msleep(1); | |
822 | ||
823 | asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]); | |
824 | ||
825 | return 0; | |
826 | } | |
827 | ||
13ca4f66 PP |
828 | static struct mfd_cell asic3_cell_leds[ASIC3_NUM_LEDS] = { |
829 | [0] = { | |
830 | .name = "leds-asic3", | |
831 | .id = 0, | |
832 | .enable = asic3_leds_enable, | |
833 | .disable = asic3_leds_disable, | |
e0b13b5b PP |
834 | .suspend = asic3_leds_suspend, |
835 | .resume = asic3_leds_enable, | |
13ca4f66 PP |
836 | }, |
837 | [1] = { | |
838 | .name = "leds-asic3", | |
839 | .id = 1, | |
840 | .enable = asic3_leds_enable, | |
841 | .disable = asic3_leds_disable, | |
e0b13b5b PP |
842 | .suspend = asic3_leds_suspend, |
843 | .resume = asic3_leds_enable, | |
13ca4f66 PP |
844 | }, |
845 | [2] = { | |
846 | .name = "leds-asic3", | |
847 | .id = 2, | |
848 | .enable = asic3_leds_enable, | |
849 | .disable = asic3_leds_disable, | |
e0b13b5b PP |
850 | .suspend = asic3_leds_suspend, |
851 | .resume = asic3_leds_enable, | |
13ca4f66 PP |
852 | }, |
853 | }; | |
854 | ||
9461f65a | 855 | static int __init asic3_mfd_probe(struct platform_device *pdev, |
13ca4f66 | 856 | struct asic3_platform_data *pdata, |
9461f65a PZ |
857 | struct resource *mem) |
858 | { | |
859 | struct asic3 *asic = platform_get_drvdata(pdev); | |
09f05ce8 PZ |
860 | struct resource *mem_sdio; |
861 | int irq, ret; | |
862 | ||
863 | mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
864 | if (!mem_sdio) | |
865 | dev_dbg(asic->dev, "no SDIO MEM resource\n"); | |
866 | ||
867 | irq = platform_get_irq(pdev, 1); | |
868 | if (irq < 0) | |
869 | dev_dbg(asic->dev, "no SDIO IRQ resource\n"); | |
9461f65a PZ |
870 | |
871 | /* DS1WM */ | |
872 | asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), | |
873 | ASIC3_EXTCF_OWM_SMB, 0); | |
874 | ||
875 | ds1wm_resources[0].start >>= asic->bus_shift; | |
876 | ds1wm_resources[0].end >>= asic->bus_shift; | |
877 | ||
09f05ce8 | 878 | /* MMC */ |
64e8867b | 879 | asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >> asic->bus_shift) + |
74e32d1b PP |
880 | mem_sdio->start, |
881 | ASIC3_SD_CONFIG_SIZE >> asic->bus_shift); | |
64e8867b IM |
882 | if (!asic->tmio_cnf) { |
883 | ret = -ENOMEM; | |
884 | dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n"); | |
885 | goto out; | |
886 | } | |
09f05ce8 PZ |
887 | asic3_mmc_resources[0].start >>= asic->bus_shift; |
888 | asic3_mmc_resources[0].end >>= asic->bus_shift; | |
09f05ce8 | 889 | |
9461f65a PZ |
890 | ret = mfd_add_devices(&pdev->dev, pdev->id, |
891 | &asic3_cell_ds1wm, 1, mem, asic->irq_base); | |
09f05ce8 PZ |
892 | if (ret < 0) |
893 | goto out; | |
894 | ||
13ca4f66 | 895 | if (mem_sdio && (irq >= 0)) { |
09f05ce8 PZ |
896 | ret = mfd_add_devices(&pdev->dev, pdev->id, |
897 | &asic3_cell_mmc, 1, mem_sdio, irq); | |
13ca4f66 PP |
898 | if (ret < 0) |
899 | goto out; | |
900 | } | |
901 | ||
902 | if (pdata->leds) { | |
903 | int i; | |
904 | ||
905 | for (i = 0; i < ASIC3_NUM_LEDS; ++i) { | |
906 | asic3_cell_leds[i].platform_data = &pdata->leds[i]; | |
907 | asic3_cell_leds[i].pdata_size = sizeof(pdata->leds[i]); | |
908 | } | |
909 | ret = mfd_add_devices(&pdev->dev, 0, | |
910 | asic3_cell_leds, ASIC3_NUM_LEDS, NULL, 0); | |
911 | } | |
9461f65a | 912 | |
09f05ce8 | 913 | out: |
9461f65a PZ |
914 | return ret; |
915 | } | |
916 | ||
917 | static void asic3_mfd_remove(struct platform_device *pdev) | |
918 | { | |
64e8867b IM |
919 | struct asic3 *asic = platform_get_drvdata(pdev); |
920 | ||
9461f65a | 921 | mfd_remove_devices(&pdev->dev); |
64e8867b | 922 | iounmap(asic->tmio_cnf); |
9461f65a PZ |
923 | } |
924 | ||
fa9ff4b1 | 925 | /* Core */ |
065032f6 | 926 | static int __init asic3_probe(struct platform_device *pdev) |
fa9ff4b1 SO |
927 | { |
928 | struct asic3_platform_data *pdata = pdev->dev.platform_data; | |
929 | struct asic3 *asic; | |
930 | struct resource *mem; | |
931 | unsigned long clksel; | |
6f2384c4 | 932 | int ret = 0; |
fa9ff4b1 SO |
933 | |
934 | asic = kzalloc(sizeof(struct asic3), GFP_KERNEL); | |
6f2384c4 SO |
935 | if (asic == NULL) { |
936 | printk(KERN_ERR "kzalloc failed\n"); | |
fa9ff4b1 | 937 | return -ENOMEM; |
6f2384c4 | 938 | } |
fa9ff4b1 SO |
939 | |
940 | spin_lock_init(&asic->lock); | |
941 | platform_set_drvdata(pdev, asic); | |
942 | asic->dev = &pdev->dev; | |
943 | ||
944 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
945 | if (!mem) { | |
946 | ret = -ENOMEM; | |
24f4f2ee | 947 | dev_err(asic->dev, "no MEM resource\n"); |
6f2384c4 | 948 | goto out_free; |
fa9ff4b1 SO |
949 | } |
950 | ||
be584bd5 | 951 | asic->mapping = ioremap(mem->start, resource_size(mem)); |
fa9ff4b1 SO |
952 | if (!asic->mapping) { |
953 | ret = -ENOMEM; | |
24f4f2ee | 954 | dev_err(asic->dev, "Couldn't ioremap\n"); |
6f2384c4 | 955 | goto out_free; |
fa9ff4b1 SO |
956 | } |
957 | ||
958 | asic->irq_base = pdata->irq_base; | |
959 | ||
99cdb0c8 | 960 | /* calculate bus shift from mem resource */ |
be584bd5 | 961 | asic->bus_shift = 2 - (resource_size(mem) >> 12); |
fa9ff4b1 SO |
962 | |
963 | clksel = 0; | |
964 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel); | |
965 | ||
966 | ret = asic3_irq_probe(pdev); | |
967 | if (ret < 0) { | |
24f4f2ee | 968 | dev_err(asic->dev, "Couldn't probe IRQs\n"); |
6f2384c4 SO |
969 | goto out_unmap; |
970 | } | |
971 | ||
d8e4a88b | 972 | asic->gpio.label = "asic3"; |
6f2384c4 SO |
973 | asic->gpio.base = pdata->gpio_base; |
974 | asic->gpio.ngpio = ASIC3_NUM_GPIOS; | |
975 | asic->gpio.get = asic3_gpio_get; | |
976 | asic->gpio.set = asic3_gpio_set; | |
977 | asic->gpio.direction_input = asic3_gpio_direction_input; | |
978 | asic->gpio.direction_output = asic3_gpio_direction_output; | |
979 | ||
3b26bf17 SO |
980 | ret = asic3_gpio_probe(pdev, |
981 | pdata->gpio_config, | |
982 | pdata->gpio_config_num); | |
6f2384c4 | 983 | if (ret < 0) { |
24f4f2ee | 984 | dev_err(asic->dev, "GPIO probe failed\n"); |
6f2384c4 | 985 | goto out_irq; |
fa9ff4b1 | 986 | } |
fa9ff4b1 | 987 | |
e956a2a8 PZ |
988 | /* Making a per-device copy is only needed for the |
989 | * theoretical case of multiple ASIC3s on one board: | |
990 | */ | |
991 | memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init)); | |
992 | ||
13ca4f66 | 993 | asic3_mfd_probe(pdev, pdata, mem); |
9461f65a | 994 | |
24f4f2ee | 995 | dev_info(asic->dev, "ASIC3 Core driver\n"); |
fa9ff4b1 SO |
996 | |
997 | return 0; | |
998 | ||
6f2384c4 SO |
999 | out_irq: |
1000 | asic3_irq_remove(pdev); | |
1001 | ||
1002 | out_unmap: | |
fa9ff4b1 | 1003 | iounmap(asic->mapping); |
6f2384c4 SO |
1004 | |
1005 | out_free: | |
fa9ff4b1 SO |
1006 | kfree(asic); |
1007 | ||
1008 | return ret; | |
1009 | } | |
1010 | ||
1e3edaf6 | 1011 | static int __devexit asic3_remove(struct platform_device *pdev) |
fa9ff4b1 | 1012 | { |
6f2384c4 | 1013 | int ret; |
fa9ff4b1 SO |
1014 | struct asic3 *asic = platform_get_drvdata(pdev); |
1015 | ||
9461f65a PZ |
1016 | asic3_mfd_remove(pdev); |
1017 | ||
6f2384c4 SO |
1018 | ret = asic3_gpio_remove(pdev); |
1019 | if (ret < 0) | |
1020 | return ret; | |
fa9ff4b1 SO |
1021 | asic3_irq_remove(pdev); |
1022 | ||
1023 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0); | |
1024 | ||
1025 | iounmap(asic->mapping); | |
1026 | ||
1027 | kfree(asic); | |
1028 | ||
1029 | return 0; | |
1030 | } | |
1031 | ||
1032 | static void asic3_shutdown(struct platform_device *pdev) | |
1033 | { | |
1034 | } | |
1035 | ||
1036 | static struct platform_driver asic3_device_driver = { | |
1037 | .driver = { | |
1038 | .name = "asic3", | |
1039 | }, | |
fa9ff4b1 SO |
1040 | .remove = __devexit_p(asic3_remove), |
1041 | .shutdown = asic3_shutdown, | |
1042 | }; | |
1043 | ||
1044 | static int __init asic3_init(void) | |
1045 | { | |
1046 | int retval = 0; | |
065032f6 | 1047 | retval = platform_driver_probe(&asic3_device_driver, asic3_probe); |
fa9ff4b1 SO |
1048 | return retval; |
1049 | } | |
1050 | ||
1051 | subsys_initcall(asic3_init); |