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Commit | Line | Data |
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fa9ff4b1 SO |
1 | /* |
2 | * driver/mfd/asic3.c | |
3 | * | |
4 | * Compaq ASIC3 support. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Copyright 2001 Compaq Computer Corporation. | |
11 | * Copyright 2004-2005 Phil Blundell | |
6f2384c4 | 12 | * Copyright 2007-2008 OpenedHand Ltd. |
fa9ff4b1 SO |
13 | * |
14 | * Authors: Phil Blundell <pb@handhelds.org>, | |
15 | * Samuel Ortiz <sameo@openedhand.com> | |
16 | * | |
17 | */ | |
18 | ||
fa9ff4b1 | 19 | #include <linux/kernel.h> |
9461f65a | 20 | #include <linux/delay.h> |
fa9ff4b1 | 21 | #include <linux/irq.h> |
6f2384c4 | 22 | #include <linux/gpio.h> |
fa9ff4b1 | 23 | #include <linux/io.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
fa9ff4b1 SO |
25 | #include <linux/spinlock.h> |
26 | #include <linux/platform_device.h> | |
27 | ||
28 | #include <linux/mfd/asic3.h> | |
9461f65a PZ |
29 | #include <linux/mfd/core.h> |
30 | #include <linux/mfd/ds1wm.h> | |
09f05ce8 | 31 | #include <linux/mfd/tmio.h> |
fa9ff4b1 | 32 | |
e956a2a8 PZ |
33 | enum { |
34 | ASIC3_CLOCK_SPI, | |
35 | ASIC3_CLOCK_OWM, | |
36 | ASIC3_CLOCK_PWM0, | |
37 | ASIC3_CLOCK_PWM1, | |
38 | ASIC3_CLOCK_LED0, | |
39 | ASIC3_CLOCK_LED1, | |
40 | ASIC3_CLOCK_LED2, | |
41 | ASIC3_CLOCK_SD_HOST, | |
42 | ASIC3_CLOCK_SD_BUS, | |
43 | ASIC3_CLOCK_SMBUS, | |
44 | ASIC3_CLOCK_EX0, | |
45 | ASIC3_CLOCK_EX1, | |
46 | }; | |
47 | ||
48 | struct asic3_clk { | |
49 | int enabled; | |
50 | unsigned int cdex; | |
51 | unsigned long rate; | |
52 | }; | |
53 | ||
54 | #define INIT_CDEX(_name, _rate) \ | |
55 | [ASIC3_CLOCK_##_name] = { \ | |
56 | .cdex = CLOCK_CDEX_##_name, \ | |
57 | .rate = _rate, \ | |
58 | } | |
59 | ||
59f2ad2e | 60 | static struct asic3_clk asic3_clk_init[] __initdata = { |
e956a2a8 PZ |
61 | INIT_CDEX(SPI, 0), |
62 | INIT_CDEX(OWM, 5000000), | |
63 | INIT_CDEX(PWM0, 0), | |
64 | INIT_CDEX(PWM1, 0), | |
65 | INIT_CDEX(LED0, 0), | |
66 | INIT_CDEX(LED1, 0), | |
67 | INIT_CDEX(LED2, 0), | |
68 | INIT_CDEX(SD_HOST, 24576000), | |
69 | INIT_CDEX(SD_BUS, 12288000), | |
70 | INIT_CDEX(SMBUS, 0), | |
71 | INIT_CDEX(EX0, 32768), | |
72 | INIT_CDEX(EX1, 24576000), | |
73 | }; | |
74 | ||
6f2384c4 SO |
75 | struct asic3 { |
76 | void __iomem *mapping; | |
77 | unsigned int bus_shift; | |
78 | unsigned int irq_nr; | |
79 | unsigned int irq_base; | |
80 | spinlock_t lock; | |
81 | u16 irq_bothedge[4]; | |
82 | struct gpio_chip gpio; | |
83 | struct device *dev; | |
64e8867b | 84 | void __iomem *tmio_cnf; |
e956a2a8 PZ |
85 | |
86 | struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)]; | |
6f2384c4 SO |
87 | }; |
88 | ||
89 | static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset); | |
90 | ||
fa9ff4b1 SO |
91 | static inline void asic3_write_register(struct asic3 *asic, |
92 | unsigned int reg, u32 value) | |
93 | { | |
b32661e0 | 94 | iowrite16(value, asic->mapping + |
fa9ff4b1 SO |
95 | (reg >> asic->bus_shift)); |
96 | } | |
97 | ||
98 | static inline u32 asic3_read_register(struct asic3 *asic, | |
99 | unsigned int reg) | |
100 | { | |
b32661e0 | 101 | return ioread16(asic->mapping + |
fa9ff4b1 SO |
102 | (reg >> asic->bus_shift)); |
103 | } | |
104 | ||
59f2ad2e | 105 | static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set) |
6483c1b5 PZ |
106 | { |
107 | unsigned long flags; | |
108 | u32 val; | |
109 | ||
110 | spin_lock_irqsave(&asic->lock, flags); | |
111 | val = asic3_read_register(asic, reg); | |
112 | if (set) | |
113 | val |= bits; | |
114 | else | |
115 | val &= ~bits; | |
116 | asic3_write_register(asic, reg, val); | |
117 | spin_unlock_irqrestore(&asic->lock, flags); | |
118 | } | |
119 | ||
fa9ff4b1 SO |
120 | /* IRQs */ |
121 | #define MAX_ASIC_ISR_LOOPS 20 | |
3b8139f8 SO |
122 | #define ASIC3_GPIO_BASE_INCR \ |
123 | (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE) | |
fa9ff4b1 SO |
124 | |
125 | static void asic3_irq_flip_edge(struct asic3 *asic, | |
126 | u32 base, int bit) | |
127 | { | |
128 | u16 edge; | |
129 | unsigned long flags; | |
130 | ||
131 | spin_lock_irqsave(&asic->lock, flags); | |
132 | edge = asic3_read_register(asic, | |
3b8139f8 | 133 | base + ASIC3_GPIO_EDGE_TRIGGER); |
fa9ff4b1 SO |
134 | edge ^= bit; |
135 | asic3_write_register(asic, | |
3b8139f8 | 136 | base + ASIC3_GPIO_EDGE_TRIGGER, edge); |
fa9ff4b1 SO |
137 | spin_unlock_irqrestore(&asic->lock, flags); |
138 | } | |
139 | ||
140 | static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc) | |
141 | { | |
52a7d607 TG |
142 | struct asic3 *asic = irq_desc_get_handler_data(desc); |
143 | struct irq_data *data = irq_desc_get_irq_data(desc); | |
fa9ff4b1 SO |
144 | int iter, i; |
145 | unsigned long flags; | |
fa9ff4b1 | 146 | |
52a7d607 | 147 | data->chip->irq_ack(irq_data); |
fa9ff4b1 SO |
148 | |
149 | for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) { | |
150 | u32 status; | |
151 | int bank; | |
152 | ||
153 | spin_lock_irqsave(&asic->lock, flags); | |
154 | status = asic3_read_register(asic, | |
3b8139f8 | 155 | ASIC3_OFFSET(INTR, P_INT_STAT)); |
fa9ff4b1 SO |
156 | spin_unlock_irqrestore(&asic->lock, flags); |
157 | ||
158 | /* Check all ten register bits */ | |
159 | if ((status & 0x3ff) == 0) | |
160 | break; | |
161 | ||
162 | /* Handle GPIO IRQs */ | |
163 | for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) { | |
164 | if (status & (1 << bank)) { | |
165 | unsigned long base, istat; | |
166 | ||
3b8139f8 SO |
167 | base = ASIC3_GPIO_A_BASE |
168 | + bank * ASIC3_GPIO_BASE_INCR; | |
fa9ff4b1 SO |
169 | |
170 | spin_lock_irqsave(&asic->lock, flags); | |
171 | istat = asic3_read_register(asic, | |
172 | base + | |
3b8139f8 | 173 | ASIC3_GPIO_INT_STATUS); |
fa9ff4b1 SO |
174 | /* Clearing IntStatus */ |
175 | asic3_write_register(asic, | |
176 | base + | |
3b8139f8 | 177 | ASIC3_GPIO_INT_STATUS, 0); |
fa9ff4b1 SO |
178 | spin_unlock_irqrestore(&asic->lock, flags); |
179 | ||
180 | for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) { | |
181 | int bit = (1 << i); | |
182 | unsigned int irqnr; | |
183 | ||
184 | if (!(istat & bit)) | |
185 | continue; | |
186 | ||
187 | irqnr = asic->irq_base + | |
188 | (ASIC3_GPIOS_PER_BANK * bank) | |
189 | + i; | |
52a7d607 | 190 | generic_handle_irq(irqnr); |
fa9ff4b1 SO |
191 | if (asic->irq_bothedge[bank] & bit) |
192 | asic3_irq_flip_edge(asic, base, | |
193 | bit); | |
194 | } | |
195 | } | |
196 | } | |
197 | ||
198 | /* Handle remaining IRQs in the status register */ | |
199 | for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) { | |
200 | /* They start at bit 4 and go up */ | |
52a7d607 TG |
201 | if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) |
202 | generic_handle_irq(asic->irq_base + i); | |
fa9ff4b1 SO |
203 | } |
204 | } | |
205 | ||
206 | if (iter >= MAX_ASIC_ISR_LOOPS) | |
24f4f2ee | 207 | dev_err(asic->dev, "interrupt processing overrun\n"); |
fa9ff4b1 SO |
208 | } |
209 | ||
210 | static inline int asic3_irq_to_bank(struct asic3 *asic, int irq) | |
211 | { | |
212 | int n; | |
213 | ||
214 | n = (irq - asic->irq_base) >> 4; | |
215 | ||
3b8139f8 | 216 | return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)); |
fa9ff4b1 SO |
217 | } |
218 | ||
219 | static inline int asic3_irq_to_index(struct asic3 *asic, int irq) | |
220 | { | |
221 | return (irq - asic->irq_base) & 0xf; | |
222 | } | |
223 | ||
0f76aaeb | 224 | static void asic3_mask_gpio_irq(struct irq_data *data) |
fa9ff4b1 | 225 | { |
0f76aaeb | 226 | struct asic3 *asic = irq_data_get_irq_chip_data(data); |
fa9ff4b1 SO |
227 | u32 val, bank, index; |
228 | unsigned long flags; | |
229 | ||
0f76aaeb MB |
230 | bank = asic3_irq_to_bank(asic, data->irq); |
231 | index = asic3_irq_to_index(asic, data->irq); | |
fa9ff4b1 SO |
232 | |
233 | spin_lock_irqsave(&asic->lock, flags); | |
3b8139f8 | 234 | val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); |
fa9ff4b1 | 235 | val |= 1 << index; |
3b8139f8 | 236 | asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val); |
fa9ff4b1 SO |
237 | spin_unlock_irqrestore(&asic->lock, flags); |
238 | } | |
239 | ||
0f76aaeb | 240 | static void asic3_mask_irq(struct irq_data *data) |
fa9ff4b1 | 241 | { |
0f76aaeb | 242 | struct asic3 *asic = irq_data_get_irq_chip_data(data); |
fa9ff4b1 SO |
243 | int regval; |
244 | unsigned long flags; | |
245 | ||
246 | spin_lock_irqsave(&asic->lock, flags); | |
247 | regval = asic3_read_register(asic, | |
3b8139f8 SO |
248 | ASIC3_INTR_BASE + |
249 | ASIC3_INTR_INT_MASK); | |
fa9ff4b1 SO |
250 | |
251 | regval &= ~(ASIC3_INTMASK_MASK0 << | |
0f76aaeb | 252 | (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS))); |
fa9ff4b1 SO |
253 | |
254 | asic3_write_register(asic, | |
3b8139f8 SO |
255 | ASIC3_INTR_BASE + |
256 | ASIC3_INTR_INT_MASK, | |
fa9ff4b1 SO |
257 | regval); |
258 | spin_unlock_irqrestore(&asic->lock, flags); | |
259 | } | |
260 | ||
0f76aaeb | 261 | static void asic3_unmask_gpio_irq(struct irq_data *data) |
fa9ff4b1 | 262 | { |
0f76aaeb | 263 | struct asic3 *asic = irq_data_get_irq_chip_data(data); |
fa9ff4b1 SO |
264 | u32 val, bank, index; |
265 | unsigned long flags; | |
266 | ||
0f76aaeb MB |
267 | bank = asic3_irq_to_bank(asic, data->irq); |
268 | index = asic3_irq_to_index(asic, data->irq); | |
fa9ff4b1 SO |
269 | |
270 | spin_lock_irqsave(&asic->lock, flags); | |
3b8139f8 | 271 | val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); |
fa9ff4b1 | 272 | val &= ~(1 << index); |
3b8139f8 | 273 | asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val); |
fa9ff4b1 SO |
274 | spin_unlock_irqrestore(&asic->lock, flags); |
275 | } | |
276 | ||
0f76aaeb | 277 | static void asic3_unmask_irq(struct irq_data *data) |
fa9ff4b1 | 278 | { |
0f76aaeb | 279 | struct asic3 *asic = irq_data_get_irq_chip_data(data); |
fa9ff4b1 SO |
280 | int regval; |
281 | unsigned long flags; | |
282 | ||
283 | spin_lock_irqsave(&asic->lock, flags); | |
284 | regval = asic3_read_register(asic, | |
3b8139f8 SO |
285 | ASIC3_INTR_BASE + |
286 | ASIC3_INTR_INT_MASK); | |
fa9ff4b1 SO |
287 | |
288 | regval |= (ASIC3_INTMASK_MASK0 << | |
0f76aaeb | 289 | (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS))); |
fa9ff4b1 SO |
290 | |
291 | asic3_write_register(asic, | |
3b8139f8 SO |
292 | ASIC3_INTR_BASE + |
293 | ASIC3_INTR_INT_MASK, | |
fa9ff4b1 SO |
294 | regval); |
295 | spin_unlock_irqrestore(&asic->lock, flags); | |
296 | } | |
297 | ||
0f76aaeb | 298 | static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type) |
fa9ff4b1 | 299 | { |
0f76aaeb | 300 | struct asic3 *asic = irq_data_get_irq_chip_data(data); |
fa9ff4b1 SO |
301 | u32 bank, index; |
302 | u16 trigger, level, edge, bit; | |
303 | unsigned long flags; | |
304 | ||
0f76aaeb MB |
305 | bank = asic3_irq_to_bank(asic, data->irq); |
306 | index = asic3_irq_to_index(asic, data->irq); | |
fa9ff4b1 SO |
307 | bit = 1<<index; |
308 | ||
309 | spin_lock_irqsave(&asic->lock, flags); | |
310 | level = asic3_read_register(asic, | |
3b8139f8 | 311 | bank + ASIC3_GPIO_LEVEL_TRIGGER); |
fa9ff4b1 | 312 | edge = asic3_read_register(asic, |
3b8139f8 | 313 | bank + ASIC3_GPIO_EDGE_TRIGGER); |
fa9ff4b1 | 314 | trigger = asic3_read_register(asic, |
3b8139f8 | 315 | bank + ASIC3_GPIO_TRIGGER_TYPE); |
0f76aaeb | 316 | asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit; |
fa9ff4b1 | 317 | |
6cab4860 | 318 | if (type == IRQ_TYPE_EDGE_RISING) { |
fa9ff4b1 SO |
319 | trigger |= bit; |
320 | edge |= bit; | |
6cab4860 | 321 | } else if (type == IRQ_TYPE_EDGE_FALLING) { |
fa9ff4b1 SO |
322 | trigger |= bit; |
323 | edge &= ~bit; | |
6cab4860 | 324 | } else if (type == IRQ_TYPE_EDGE_BOTH) { |
fa9ff4b1 | 325 | trigger |= bit; |
0f76aaeb | 326 | if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base)) |
fa9ff4b1 SO |
327 | edge &= ~bit; |
328 | else | |
329 | edge |= bit; | |
0f76aaeb | 330 | asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit; |
6cab4860 | 331 | } else if (type == IRQ_TYPE_LEVEL_LOW) { |
fa9ff4b1 SO |
332 | trigger &= ~bit; |
333 | level &= ~bit; | |
6cab4860 | 334 | } else if (type == IRQ_TYPE_LEVEL_HIGH) { |
fa9ff4b1 SO |
335 | trigger &= ~bit; |
336 | level |= bit; | |
337 | } else { | |
338 | /* | |
6cab4860 | 339 | * if type == IRQ_TYPE_NONE, we should mask interrupts, but |
fa9ff4b1 SO |
340 | * be careful to not unmask them if mask was also called. |
341 | * Probably need internal state for mask. | |
342 | */ | |
24f4f2ee | 343 | dev_notice(asic->dev, "irq type not changed\n"); |
fa9ff4b1 | 344 | } |
3b8139f8 | 345 | asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER, |
fa9ff4b1 | 346 | level); |
3b8139f8 | 347 | asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER, |
fa9ff4b1 | 348 | edge); |
3b8139f8 | 349 | asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE, |
fa9ff4b1 SO |
350 | trigger); |
351 | spin_unlock_irqrestore(&asic->lock, flags); | |
352 | return 0; | |
353 | } | |
354 | ||
355 | static struct irq_chip asic3_gpio_irq_chip = { | |
356 | .name = "ASIC3-GPIO", | |
0f76aaeb MB |
357 | .irq_ack = asic3_mask_gpio_irq, |
358 | .irq_mask = asic3_mask_gpio_irq, | |
359 | .irq_unmask = asic3_unmask_gpio_irq, | |
360 | .irq_set_type = asic3_gpio_irq_type, | |
fa9ff4b1 SO |
361 | }; |
362 | ||
363 | static struct irq_chip asic3_irq_chip = { | |
364 | .name = "ASIC3", | |
0f76aaeb MB |
365 | .irq_ack = asic3_mask_irq, |
366 | .irq_mask = asic3_mask_irq, | |
367 | .irq_unmask = asic3_unmask_irq, | |
fa9ff4b1 SO |
368 | }; |
369 | ||
065032f6 | 370 | static int __init asic3_irq_probe(struct platform_device *pdev) |
fa9ff4b1 SO |
371 | { |
372 | struct asic3 *asic = platform_get_drvdata(pdev); | |
373 | unsigned long clksel = 0; | |
374 | unsigned int irq, irq_base; | |
c491b2ff | 375 | int ret; |
fa9ff4b1 | 376 | |
c491b2ff RK |
377 | ret = platform_get_irq(pdev, 0); |
378 | if (ret < 0) | |
379 | return ret; | |
380 | asic->irq_nr = ret; | |
fa9ff4b1 SO |
381 | |
382 | /* turn on clock to IRQ controller */ | |
383 | clksel |= CLOCK_SEL_CX; | |
384 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), | |
385 | clksel); | |
386 | ||
387 | irq_base = asic->irq_base; | |
388 | ||
389 | for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) { | |
390 | if (irq < asic->irq_base + ASIC3_NUM_GPIOS) | |
d5bb1221 | 391 | irq_set_chip(irq, &asic3_gpio_irq_chip); |
fa9ff4b1 | 392 | else |
d5bb1221 | 393 | irq_set_chip(irq, &asic3_irq_chip); |
fa9ff4b1 | 394 | |
d5bb1221 TG |
395 | irq_set_chip_data(irq, asic); |
396 | irq_set_handler(irq, handle_level_irq); | |
fa9ff4b1 SO |
397 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
398 | } | |
399 | ||
3b8139f8 | 400 | asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK), |
fa9ff4b1 SO |
401 | ASIC3_INTMASK_GINTMASK); |
402 | ||
d5bb1221 TG |
403 | irq_set_chained_handler(asic->irq_nr, asic3_irq_demux); |
404 | irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING); | |
405 | irq_set_handler_data(asic->irq_nr, asic); | |
fa9ff4b1 SO |
406 | |
407 | return 0; | |
408 | } | |
409 | ||
410 | static void asic3_irq_remove(struct platform_device *pdev) | |
411 | { | |
412 | struct asic3 *asic = platform_get_drvdata(pdev); | |
413 | unsigned int irq, irq_base; | |
414 | ||
415 | irq_base = asic->irq_base; | |
416 | ||
417 | for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) { | |
418 | set_irq_flags(irq, 0); | |
d5bb1221 TG |
419 | irq_set_handler(irq, NULL); |
420 | irq_set_chip(irq, NULL); | |
421 | irq_set_chip_data(irq, NULL); | |
fa9ff4b1 | 422 | } |
d5bb1221 | 423 | irq_set_chained_handler(asic->irq_nr, NULL); |
fa9ff4b1 SO |
424 | } |
425 | ||
426 | /* GPIOs */ | |
6f2384c4 SO |
427 | static int asic3_gpio_direction(struct gpio_chip *chip, |
428 | unsigned offset, int out) | |
429 | { | |
430 | u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg; | |
431 | unsigned int gpio_base; | |
432 | unsigned long flags; | |
433 | struct asic3 *asic; | |
434 | ||
435 | asic = container_of(chip, struct asic3, gpio); | |
436 | gpio_base = ASIC3_GPIO_TO_BASE(offset); | |
437 | ||
3b8139f8 | 438 | if (gpio_base > ASIC3_GPIO_D_BASE) { |
24f4f2ee SO |
439 | dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", |
440 | gpio_base, offset); | |
6f2384c4 SO |
441 | return -EINVAL; |
442 | } | |
443 | ||
444 | spin_lock_irqsave(&asic->lock, flags); | |
445 | ||
3b8139f8 | 446 | out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION); |
6f2384c4 SO |
447 | |
448 | /* Input is 0, Output is 1 */ | |
449 | if (out) | |
450 | out_reg |= mask; | |
451 | else | |
452 | out_reg &= ~mask; | |
453 | ||
3b8139f8 | 454 | asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg); |
6f2384c4 SO |
455 | |
456 | spin_unlock_irqrestore(&asic->lock, flags); | |
457 | ||
458 | return 0; | |
459 | ||
460 | } | |
461 | ||
462 | static int asic3_gpio_direction_input(struct gpio_chip *chip, | |
463 | unsigned offset) | |
464 | { | |
465 | return asic3_gpio_direction(chip, offset, 0); | |
466 | } | |
467 | ||
468 | static int asic3_gpio_direction_output(struct gpio_chip *chip, | |
469 | unsigned offset, int value) | |
470 | { | |
471 | return asic3_gpio_direction(chip, offset, 1); | |
472 | } | |
473 | ||
474 | static int asic3_gpio_get(struct gpio_chip *chip, | |
475 | unsigned offset) | |
476 | { | |
477 | unsigned int gpio_base; | |
478 | u32 mask = ASIC3_GPIO_TO_MASK(offset); | |
479 | struct asic3 *asic; | |
480 | ||
481 | asic = container_of(chip, struct asic3, gpio); | |
482 | gpio_base = ASIC3_GPIO_TO_BASE(offset); | |
483 | ||
3b8139f8 | 484 | if (gpio_base > ASIC3_GPIO_D_BASE) { |
24f4f2ee SO |
485 | dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", |
486 | gpio_base, offset); | |
6f2384c4 SO |
487 | return -EINVAL; |
488 | } | |
489 | ||
3b8139f8 | 490 | return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask; |
6f2384c4 SO |
491 | } |
492 | ||
493 | static void asic3_gpio_set(struct gpio_chip *chip, | |
494 | unsigned offset, int value) | |
495 | { | |
496 | u32 mask, out_reg; | |
497 | unsigned int gpio_base; | |
498 | unsigned long flags; | |
499 | struct asic3 *asic; | |
500 | ||
501 | asic = container_of(chip, struct asic3, gpio); | |
502 | gpio_base = ASIC3_GPIO_TO_BASE(offset); | |
503 | ||
3b8139f8 | 504 | if (gpio_base > ASIC3_GPIO_D_BASE) { |
24f4f2ee SO |
505 | dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", |
506 | gpio_base, offset); | |
6f2384c4 SO |
507 | return; |
508 | } | |
509 | ||
510 | mask = ASIC3_GPIO_TO_MASK(offset); | |
511 | ||
512 | spin_lock_irqsave(&asic->lock, flags); | |
513 | ||
3b8139f8 | 514 | out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT); |
6f2384c4 SO |
515 | |
516 | if (value) | |
517 | out_reg |= mask; | |
518 | else | |
519 | out_reg &= ~mask; | |
520 | ||
3b8139f8 | 521 | asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg); |
6f2384c4 SO |
522 | |
523 | spin_unlock_irqrestore(&asic->lock, flags); | |
524 | ||
525 | return; | |
526 | } | |
527 | ||
065032f6 PZ |
528 | static __init int asic3_gpio_probe(struct platform_device *pdev, |
529 | u16 *gpio_config, int num) | |
fa9ff4b1 | 530 | { |
fa9ff4b1 | 531 | struct asic3 *asic = platform_get_drvdata(pdev); |
3b26bf17 SO |
532 | u16 alt_reg[ASIC3_NUM_GPIO_BANKS]; |
533 | u16 out_reg[ASIC3_NUM_GPIO_BANKS]; | |
534 | u16 dir_reg[ASIC3_NUM_GPIO_BANKS]; | |
535 | int i; | |
fa9ff4b1 | 536 | |
59f0cb0f RK |
537 | memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); |
538 | memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); | |
539 | memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); | |
3b26bf17 SO |
540 | |
541 | /* Enable all GPIOs */ | |
3b8139f8 SO |
542 | asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff); |
543 | asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff); | |
544 | asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff); | |
545 | asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff); | |
fa9ff4b1 | 546 | |
3b26bf17 SO |
547 | for (i = 0; i < num; i++) { |
548 | u8 alt, pin, dir, init, bank_num, bit_num; | |
549 | u16 config = gpio_config[i]; | |
550 | ||
551 | pin = ASIC3_CONFIG_GPIO_PIN(config); | |
552 | alt = ASIC3_CONFIG_GPIO_ALT(config); | |
553 | dir = ASIC3_CONFIG_GPIO_DIR(config); | |
554 | init = ASIC3_CONFIG_GPIO_INIT(config); | |
555 | ||
556 | bank_num = ASIC3_GPIO_TO_BANK(pin); | |
557 | bit_num = ASIC3_GPIO_TO_BIT(pin); | |
558 | ||
559 | alt_reg[bank_num] |= (alt << bit_num); | |
560 | out_reg[bank_num] |= (init << bit_num); | |
561 | dir_reg[bank_num] |= (dir << bit_num); | |
562 | } | |
563 | ||
564 | for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) { | |
565 | asic3_write_register(asic, | |
566 | ASIC3_BANK_TO_BASE(i) + | |
3b8139f8 | 567 | ASIC3_GPIO_DIRECTION, |
3b26bf17 SO |
568 | dir_reg[i]); |
569 | asic3_write_register(asic, | |
3b8139f8 | 570 | ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT, |
3b26bf17 SO |
571 | out_reg[i]); |
572 | asic3_write_register(asic, | |
573 | ASIC3_BANK_TO_BASE(i) + | |
3b8139f8 | 574 | ASIC3_GPIO_ALT_FUNCTION, |
3b26bf17 | 575 | alt_reg[i]); |
fa9ff4b1 SO |
576 | } |
577 | ||
6f2384c4 | 578 | return gpiochip_add(&asic->gpio); |
fa9ff4b1 SO |
579 | } |
580 | ||
6f2384c4 | 581 | static int asic3_gpio_remove(struct platform_device *pdev) |
fa9ff4b1 | 582 | { |
6f2384c4 SO |
583 | struct asic3 *asic = platform_get_drvdata(pdev); |
584 | ||
585 | return gpiochip_remove(&asic->gpio); | |
fa9ff4b1 SO |
586 | } |
587 | ||
e956a2a8 PZ |
588 | static int asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk) |
589 | { | |
590 | unsigned long flags; | |
591 | u32 cdex; | |
592 | ||
593 | spin_lock_irqsave(&asic->lock, flags); | |
594 | if (clk->enabled++ == 0) { | |
595 | cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX)); | |
596 | cdex |= clk->cdex; | |
597 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex); | |
598 | } | |
599 | spin_unlock_irqrestore(&asic->lock, flags); | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
604 | static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk) | |
605 | { | |
606 | unsigned long flags; | |
607 | u32 cdex; | |
608 | ||
609 | WARN_ON(clk->enabled == 0); | |
610 | ||
611 | spin_lock_irqsave(&asic->lock, flags); | |
612 | if (--clk->enabled == 0) { | |
613 | cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX)); | |
614 | cdex &= ~clk->cdex; | |
615 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex); | |
616 | } | |
617 | spin_unlock_irqrestore(&asic->lock, flags); | |
618 | } | |
fa9ff4b1 | 619 | |
9461f65a PZ |
620 | /* MFD cells (SPI, PWM, LED, DS1WM, MMC) */ |
621 | static struct ds1wm_driver_data ds1wm_pdata = { | |
622 | .active_high = 1, | |
623 | }; | |
624 | ||
625 | static struct resource ds1wm_resources[] = { | |
626 | { | |
627 | .start = ASIC3_OWM_BASE, | |
628 | .end = ASIC3_OWM_BASE + 0x13, | |
629 | .flags = IORESOURCE_MEM, | |
630 | }, | |
631 | { | |
632 | .start = ASIC3_IRQ_OWM, | |
fe421425 | 633 | .end = ASIC3_IRQ_OWM, |
9461f65a PZ |
634 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, |
635 | }, | |
636 | }; | |
637 | ||
638 | static int ds1wm_enable(struct platform_device *pdev) | |
639 | { | |
640 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
641 | ||
642 | /* Turn on external clocks and the OWM clock */ | |
643 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); | |
644 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); | |
645 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); | |
646 | msleep(1); | |
647 | ||
648 | /* Reset and enable DS1WM */ | |
649 | asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET), | |
650 | ASIC3_EXTCF_OWM_RESET, 1); | |
651 | msleep(1); | |
652 | asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET), | |
653 | ASIC3_EXTCF_OWM_RESET, 0); | |
654 | msleep(1); | |
655 | asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), | |
656 | ASIC3_EXTCF_OWM_EN, 1); | |
657 | msleep(1); | |
658 | ||
659 | return 0; | |
660 | } | |
661 | ||
662 | static int ds1wm_disable(struct platform_device *pdev) | |
663 | { | |
664 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
665 | ||
666 | asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), | |
667 | ASIC3_EXTCF_OWM_EN, 0); | |
668 | ||
669 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); | |
670 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); | |
671 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); | |
672 | ||
673 | return 0; | |
674 | } | |
675 | ||
676 | static struct mfd_cell asic3_cell_ds1wm = { | |
677 | .name = "ds1wm", | |
678 | .enable = ds1wm_enable, | |
679 | .disable = ds1wm_disable, | |
fcd67979 | 680 | .mfd_data = &ds1wm_pdata, |
9461f65a PZ |
681 | .num_resources = ARRAY_SIZE(ds1wm_resources), |
682 | .resources = ds1wm_resources, | |
683 | }; | |
684 | ||
64e8867b IM |
685 | static void asic3_mmc_pwr(struct platform_device *pdev, int state) |
686 | { | |
687 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
688 | ||
689 | tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state); | |
690 | } | |
691 | ||
692 | static void asic3_mmc_clk_div(struct platform_device *pdev, int state) | |
693 | { | |
694 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
695 | ||
696 | tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state); | |
697 | } | |
698 | ||
09f05ce8 | 699 | static struct tmio_mmc_data asic3_mmc_data = { |
64e8867b IM |
700 | .hclk = 24576000, |
701 | .set_pwr = asic3_mmc_pwr, | |
702 | .set_clk_div = asic3_mmc_clk_div, | |
09f05ce8 PZ |
703 | }; |
704 | ||
705 | static struct resource asic3_mmc_resources[] = { | |
706 | { | |
707 | .start = ASIC3_SD_CTRL_BASE, | |
708 | .end = ASIC3_SD_CTRL_BASE + 0x3ff, | |
709 | .flags = IORESOURCE_MEM, | |
710 | }, | |
09f05ce8 PZ |
711 | { |
712 | .start = 0, | |
713 | .end = 0, | |
714 | .flags = IORESOURCE_IRQ, | |
715 | }, | |
716 | }; | |
717 | ||
718 | static int asic3_mmc_enable(struct platform_device *pdev) | |
719 | { | |
720 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
721 | ||
722 | /* Not sure if it must be done bit by bit, but leaving as-is */ | |
723 | asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), | |
724 | ASIC3_SDHWCTRL_LEVCD, 1); | |
725 | asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), | |
726 | ASIC3_SDHWCTRL_LEVWP, 1); | |
727 | asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), | |
728 | ASIC3_SDHWCTRL_SUSPEND, 0); | |
729 | asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), | |
730 | ASIC3_SDHWCTRL_PCLR, 0); | |
731 | ||
732 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); | |
733 | /* CLK32 used for card detection and for interruption detection | |
734 | * when HCLK is stopped. | |
735 | */ | |
736 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); | |
737 | msleep(1); | |
738 | ||
739 | /* HCLK 24.576 MHz, BCLK 12.288 MHz: */ | |
740 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), | |
741 | CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL); | |
742 | ||
743 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]); | |
744 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]); | |
745 | msleep(1); | |
746 | ||
747 | asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), | |
748 | ASIC3_EXTCF_SD_MEM_ENABLE, 1); | |
749 | ||
750 | /* Enable SD card slot 3.3V power supply */ | |
751 | asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), | |
752 | ASIC3_SDHWCTRL_SDPWR, 1); | |
753 | ||
64e8867b IM |
754 | /* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */ |
755 | tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift, | |
756 | ASIC3_SD_CTRL_BASE >> 1); | |
757 | ||
09f05ce8 PZ |
758 | return 0; |
759 | } | |
760 | ||
761 | static int asic3_mmc_disable(struct platform_device *pdev) | |
762 | { | |
763 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
764 | ||
765 | /* Put in suspend mode */ | |
766 | asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), | |
767 | ASIC3_SDHWCTRL_SUSPEND, 1); | |
768 | ||
769 | /* Disable clocks */ | |
770 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]); | |
771 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]); | |
772 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); | |
773 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); | |
774 | return 0; | |
775 | } | |
776 | ||
777 | static struct mfd_cell asic3_cell_mmc = { | |
778 | .name = "tmio-mmc", | |
779 | .enable = asic3_mmc_enable, | |
780 | .disable = asic3_mmc_disable, | |
4f95bf40 | 781 | .mfd_data = &asic3_mmc_data, |
09f05ce8 PZ |
782 | .num_resources = ARRAY_SIZE(asic3_mmc_resources), |
783 | .resources = asic3_mmc_resources, | |
784 | }; | |
785 | ||
9461f65a PZ |
786 | static int __init asic3_mfd_probe(struct platform_device *pdev, |
787 | struct resource *mem) | |
788 | { | |
789 | struct asic3 *asic = platform_get_drvdata(pdev); | |
09f05ce8 PZ |
790 | struct resource *mem_sdio; |
791 | int irq, ret; | |
792 | ||
793 | mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
794 | if (!mem_sdio) | |
795 | dev_dbg(asic->dev, "no SDIO MEM resource\n"); | |
796 | ||
797 | irq = platform_get_irq(pdev, 1); | |
798 | if (irq < 0) | |
799 | dev_dbg(asic->dev, "no SDIO IRQ resource\n"); | |
9461f65a PZ |
800 | |
801 | /* DS1WM */ | |
802 | asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), | |
803 | ASIC3_EXTCF_OWM_SMB, 0); | |
804 | ||
805 | ds1wm_resources[0].start >>= asic->bus_shift; | |
806 | ds1wm_resources[0].end >>= asic->bus_shift; | |
807 | ||
09f05ce8 | 808 | /* MMC */ |
64e8867b IM |
809 | asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >> asic->bus_shift) + |
810 | mem_sdio->start, 0x400 >> asic->bus_shift); | |
811 | if (!asic->tmio_cnf) { | |
812 | ret = -ENOMEM; | |
813 | dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n"); | |
814 | goto out; | |
815 | } | |
09f05ce8 PZ |
816 | asic3_mmc_resources[0].start >>= asic->bus_shift; |
817 | asic3_mmc_resources[0].end >>= asic->bus_shift; | |
09f05ce8 | 818 | |
9461f65a PZ |
819 | ret = mfd_add_devices(&pdev->dev, pdev->id, |
820 | &asic3_cell_ds1wm, 1, mem, asic->irq_base); | |
09f05ce8 PZ |
821 | if (ret < 0) |
822 | goto out; | |
823 | ||
824 | if (mem_sdio && (irq >= 0)) | |
825 | ret = mfd_add_devices(&pdev->dev, pdev->id, | |
826 | &asic3_cell_mmc, 1, mem_sdio, irq); | |
9461f65a | 827 | |
09f05ce8 | 828 | out: |
9461f65a PZ |
829 | return ret; |
830 | } | |
831 | ||
832 | static void asic3_mfd_remove(struct platform_device *pdev) | |
833 | { | |
64e8867b IM |
834 | struct asic3 *asic = platform_get_drvdata(pdev); |
835 | ||
9461f65a | 836 | mfd_remove_devices(&pdev->dev); |
64e8867b | 837 | iounmap(asic->tmio_cnf); |
9461f65a PZ |
838 | } |
839 | ||
fa9ff4b1 | 840 | /* Core */ |
065032f6 | 841 | static int __init asic3_probe(struct platform_device *pdev) |
fa9ff4b1 SO |
842 | { |
843 | struct asic3_platform_data *pdata = pdev->dev.platform_data; | |
844 | struct asic3 *asic; | |
845 | struct resource *mem; | |
846 | unsigned long clksel; | |
6f2384c4 | 847 | int ret = 0; |
fa9ff4b1 SO |
848 | |
849 | asic = kzalloc(sizeof(struct asic3), GFP_KERNEL); | |
6f2384c4 SO |
850 | if (asic == NULL) { |
851 | printk(KERN_ERR "kzalloc failed\n"); | |
fa9ff4b1 | 852 | return -ENOMEM; |
6f2384c4 | 853 | } |
fa9ff4b1 SO |
854 | |
855 | spin_lock_init(&asic->lock); | |
856 | platform_set_drvdata(pdev, asic); | |
857 | asic->dev = &pdev->dev; | |
858 | ||
859 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
860 | if (!mem) { | |
861 | ret = -ENOMEM; | |
24f4f2ee | 862 | dev_err(asic->dev, "no MEM resource\n"); |
6f2384c4 | 863 | goto out_free; |
fa9ff4b1 SO |
864 | } |
865 | ||
be584bd5 | 866 | asic->mapping = ioremap(mem->start, resource_size(mem)); |
fa9ff4b1 SO |
867 | if (!asic->mapping) { |
868 | ret = -ENOMEM; | |
24f4f2ee | 869 | dev_err(asic->dev, "Couldn't ioremap\n"); |
6f2384c4 | 870 | goto out_free; |
fa9ff4b1 SO |
871 | } |
872 | ||
873 | asic->irq_base = pdata->irq_base; | |
874 | ||
99cdb0c8 | 875 | /* calculate bus shift from mem resource */ |
be584bd5 | 876 | asic->bus_shift = 2 - (resource_size(mem) >> 12); |
fa9ff4b1 SO |
877 | |
878 | clksel = 0; | |
879 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel); | |
880 | ||
881 | ret = asic3_irq_probe(pdev); | |
882 | if (ret < 0) { | |
24f4f2ee | 883 | dev_err(asic->dev, "Couldn't probe IRQs\n"); |
6f2384c4 SO |
884 | goto out_unmap; |
885 | } | |
886 | ||
887 | asic->gpio.base = pdata->gpio_base; | |
888 | asic->gpio.ngpio = ASIC3_NUM_GPIOS; | |
889 | asic->gpio.get = asic3_gpio_get; | |
890 | asic->gpio.set = asic3_gpio_set; | |
891 | asic->gpio.direction_input = asic3_gpio_direction_input; | |
892 | asic->gpio.direction_output = asic3_gpio_direction_output; | |
893 | ||
3b26bf17 SO |
894 | ret = asic3_gpio_probe(pdev, |
895 | pdata->gpio_config, | |
896 | pdata->gpio_config_num); | |
6f2384c4 | 897 | if (ret < 0) { |
24f4f2ee | 898 | dev_err(asic->dev, "GPIO probe failed\n"); |
6f2384c4 | 899 | goto out_irq; |
fa9ff4b1 | 900 | } |
fa9ff4b1 | 901 | |
e956a2a8 PZ |
902 | /* Making a per-device copy is only needed for the |
903 | * theoretical case of multiple ASIC3s on one board: | |
904 | */ | |
905 | memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init)); | |
906 | ||
9461f65a PZ |
907 | asic3_mfd_probe(pdev, mem); |
908 | ||
24f4f2ee | 909 | dev_info(asic->dev, "ASIC3 Core driver\n"); |
fa9ff4b1 SO |
910 | |
911 | return 0; | |
912 | ||
6f2384c4 SO |
913 | out_irq: |
914 | asic3_irq_remove(pdev); | |
915 | ||
916 | out_unmap: | |
fa9ff4b1 | 917 | iounmap(asic->mapping); |
6f2384c4 SO |
918 | |
919 | out_free: | |
fa9ff4b1 SO |
920 | kfree(asic); |
921 | ||
922 | return ret; | |
923 | } | |
924 | ||
1e3edaf6 | 925 | static int __devexit asic3_remove(struct platform_device *pdev) |
fa9ff4b1 | 926 | { |
6f2384c4 | 927 | int ret; |
fa9ff4b1 SO |
928 | struct asic3 *asic = platform_get_drvdata(pdev); |
929 | ||
9461f65a PZ |
930 | asic3_mfd_remove(pdev); |
931 | ||
6f2384c4 SO |
932 | ret = asic3_gpio_remove(pdev); |
933 | if (ret < 0) | |
934 | return ret; | |
fa9ff4b1 SO |
935 | asic3_irq_remove(pdev); |
936 | ||
937 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0); | |
938 | ||
939 | iounmap(asic->mapping); | |
940 | ||
941 | kfree(asic); | |
942 | ||
943 | return 0; | |
944 | } | |
945 | ||
946 | static void asic3_shutdown(struct platform_device *pdev) | |
947 | { | |
948 | } | |
949 | ||
950 | static struct platform_driver asic3_device_driver = { | |
951 | .driver = { | |
952 | .name = "asic3", | |
953 | }, | |
fa9ff4b1 SO |
954 | .remove = __devexit_p(asic3_remove), |
955 | .shutdown = asic3_shutdown, | |
956 | }; | |
957 | ||
958 | static int __init asic3_init(void) | |
959 | { | |
960 | int retval = 0; | |
065032f6 | 961 | retval = platform_driver_probe(&asic3_device_driver, asic3_probe); |
fa9ff4b1 SO |
962 | return retval; |
963 | } | |
964 | ||
965 | subsys_initcall(asic3_init); |