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[mirror_ubuntu-bionic-kernel.git] / drivers / mfd / axp20x.c
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cfb61a41 1/*
4fd41151 2 * MFD core driver for the X-Powers' Power Management ICs
cfb61a41 3 *
af7e9069
JP		 4 * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK DC-DC
5 * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
6 * as well as configurable GPIOs.
cfb61a41 7 *
4fd41151
CYT		 8 * This file contains the interface independent core functions.
9 *
e740235d
CYT		 10 * Copyright (C) 2014 Carlo Caione
11 *
cfb61a41
CC		 12 * Author: Carlo Caione <carlo@caione.org>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/err.h>
cfb61a41
CC		 20#include <linux/interrupt.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pm_runtime.h>
24#include <linux/regmap.h>
cfb61a41
CC		 25#include <linux/regulator/consumer.h>
26#include <linux/mfd/axp20x.h>
27#include <linux/mfd/core.h>
28#include <linux/of_device.h>
af7e9069 29#include <linux/acpi.h>
cfb61a41
CC		 30
31#define AXP20X_OFF 0x80
32
c31e858b 33static const char * const axp20x_model_names[] = {
d8d79f8f 34 "AXP152",
af7e9069
JP		 35 "AXP202",
36 "AXP209",
f05be589 37 "AXP221",
02071f0f 38 "AXP223",
af7e9069 39 "AXP288",
20147f0d 40 "AXP809",
af7e9069
JP		 41};
42
d8d79f8f
MS		 43static const struct regmap_range axp152_writeable_ranges[] = {
44 regmap_reg_range(AXP152_LDO3456_DC1234_CTRL, AXP152_IRQ3_STATE),
45 regmap_reg_range(AXP152_DCDC_MODE, AXP152_PWM1_DUTY_CYCLE),
46};
47
48static const struct regmap_range axp152_volatile_ranges[] = {
49 regmap_reg_range(AXP152_PWR_OP_MODE, AXP152_PWR_OP_MODE),
50 regmap_reg_range(AXP152_IRQ1_EN, AXP152_IRQ3_STATE),
51 regmap_reg_range(AXP152_GPIO_INPUT, AXP152_GPIO_INPUT),
52};
53
54static const struct regmap_access_table axp152_writeable_table = {
55 .yes_ranges = axp152_writeable_ranges,
56 .n_yes_ranges = ARRAY_SIZE(axp152_writeable_ranges),
57};
58
59static const struct regmap_access_table axp152_volatile_table = {
60 .yes_ranges = axp152_volatile_ranges,
61 .n_yes_ranges = ARRAY_SIZE(axp152_volatile_ranges),
62};
63
cfb61a41
CC		 64static const struct regmap_range axp20x_writeable_ranges[] = {
65 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
66 regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES),
553ed4b5 67 regmap_reg_range(AXP20X_RDC_H, AXP20X_OCV(AXP20X_OCV_MAX)),
cfb61a41
CC		 68};
69
70static const struct regmap_range axp20x_volatile_ranges[] = {
553ed4b5
BP		 71 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_USB_OTG_STATUS),
72 regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
cfb61a41 73 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
553ed4b5
BP		 74 regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
75 regmap_reg_range(AXP20X_GPIO20_SS, AXP20X_GPIO3_CTRL),
76 regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L),
cfb61a41
CC		 77};
78
79static const struct regmap_access_table axp20x_writeable_table = {
80 .yes_ranges = axp20x_writeable_ranges,
81 .n_yes_ranges = ARRAY_SIZE(axp20x_writeable_ranges),
82};
83
84static const struct regmap_access_table axp20x_volatile_table = {
85 .yes_ranges = axp20x_volatile_ranges,
86 .n_yes_ranges = ARRAY_SIZE(axp20x_volatile_ranges),
87};
88
20147f0d 89/* AXP22x ranges are shared with the AXP809, as they cover the same range */
f05be589
BB		 90static const struct regmap_range axp22x_writeable_ranges[] = {
91 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
92 regmap_reg_range(AXP20X_DCDC_MODE, AXP22X_BATLOW_THRES1),
93};
94
95static const struct regmap_range axp22x_volatile_ranges[] = {
96 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
97};
98
99static const struct regmap_access_table axp22x_writeable_table = {
100 .yes_ranges = axp22x_writeable_ranges,
101 .n_yes_ranges = ARRAY_SIZE(axp22x_writeable_ranges),
102};
103
104static const struct regmap_access_table axp22x_volatile_table = {
105 .yes_ranges = axp22x_volatile_ranges,
106 .n_yes_ranges = ARRAY_SIZE(axp22x_volatile_ranges),
107};
108
af7e9069
JP		 109static const struct regmap_range axp288_writeable_ranges[] = {
110 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE),
111 regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5),
112};
113
114static const struct regmap_range axp288_volatile_ranges[] = {
115 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
116};
117
118static const struct regmap_access_table axp288_writeable_table = {
119 .yes_ranges = axp288_writeable_ranges,
120 .n_yes_ranges = ARRAY_SIZE(axp288_writeable_ranges),
121};
122
123static const struct regmap_access_table axp288_volatile_table = {
124 .yes_ranges = axp288_volatile_ranges,
125 .n_yes_ranges = ARRAY_SIZE(axp288_volatile_ranges),
126};
127
d8d79f8f
MS		 128static struct resource axp152_pek_resources[] = {
129 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
130 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
131};
132
cd7cf27b
MH		 133static struct resource axp20x_ac_power_supply_resources[] = {
134 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"),
135 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"),
136 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_OVER_V, "ACIN_OVER_V"),
137};
138
cfb61a41
CC		 139static struct resource axp20x_pek_resources[] = {
140 {
141 .name = "PEK_DBR",
142 .start = AXP20X_IRQ_PEK_RIS_EDGE,
143 .end = AXP20X_IRQ_PEK_RIS_EDGE,
144 .flags = IORESOURCE_IRQ,
145 }, {
146 .name = "PEK_DBF",
147 .start = AXP20X_IRQ_PEK_FAL_EDGE,
148 .end = AXP20X_IRQ_PEK_FAL_EDGE,
149 .flags = IORESOURCE_IRQ,
150 },
151};
152
8de4efda
HG		 153static struct resource axp20x_usb_power_supply_resources[] = {
154 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
155 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
156 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_VALID, "VBUS_VALID"),
157 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"),
158};
159
f05be589
BB		 160static struct resource axp22x_pek_resources[] = {
161 {
162 .name = "PEK_DBR",
163 .start = AXP22X_IRQ_PEK_RIS_EDGE,
164 .end = AXP22X_IRQ_PEK_RIS_EDGE,
165 .flags = IORESOURCE_IRQ,
166 }, {
167 .name = "PEK_DBF",
168 .start = AXP22X_IRQ_PEK_FAL_EDGE,
169 .end = AXP22X_IRQ_PEK_FAL_EDGE,
170 .flags = IORESOURCE_IRQ,
171 },
172};
173
e56e5ad6
BF		 174static struct resource axp288_power_button_resources[] = {
175 {
176 .name = "PEK_DBR",
177 .start = AXP288_IRQ_POKN,
178 .end = AXP288_IRQ_POKN,
179 .flags = IORESOURCE_IRQ,
180 },
181 {
182 .name = "PEK_DBF",
183 .start = AXP288_IRQ_POKP,
184 .end = AXP288_IRQ_POKP,
185 .flags = IORESOURCE_IRQ,
186 },
187};
188
d6387874 189static struct resource axp288_fuel_gauge_resources[] = {
af7e9069
JP		 190 {
191 .start = AXP288_IRQ_QWBTU,
192 .end = AXP288_IRQ_QWBTU,
193 .flags = IORESOURCE_IRQ,
194 },
195 {
196 .start = AXP288_IRQ_WBTU,
197 .end = AXP288_IRQ_WBTU,
198 .flags = IORESOURCE_IRQ,
199 },
200 {
201 .start = AXP288_IRQ_QWBTO,
202 .end = AXP288_IRQ_QWBTO,
203 .flags = IORESOURCE_IRQ,
204 },
205 {
206 .start = AXP288_IRQ_WBTO,
207 .end = AXP288_IRQ_WBTO,
208 .flags = IORESOURCE_IRQ,
209 },
210 {
211 .start = AXP288_IRQ_WL2,
212 .end = AXP288_IRQ_WL2,
213 .flags = IORESOURCE_IRQ,
214 },
215 {
216 .start = AXP288_IRQ_WL1,
217 .end = AXP288_IRQ_WL1,
218 .flags = IORESOURCE_IRQ,
219 },
220};
221
20147f0d
CYT		 222static struct resource axp809_pek_resources[] = {
223 {
224 .name = "PEK_DBR",
225 .start = AXP809_IRQ_PEK_RIS_EDGE,
226 .end = AXP809_IRQ_PEK_RIS_EDGE,
227 .flags = IORESOURCE_IRQ,
228 }, {
229 .name = "PEK_DBF",
230 .start = AXP809_IRQ_PEK_FAL_EDGE,
231 .end = AXP809_IRQ_PEK_FAL_EDGE,
232 .flags = IORESOURCE_IRQ,
233 },
234};
235
d8d79f8f
MS		 236static const struct regmap_config axp152_regmap_config = {
237 .reg_bits = 8,
238 .val_bits = 8,
239 .wr_table = &axp152_writeable_table,
240 .volatile_table = &axp152_volatile_table,
241 .max_register = AXP152_PWM1_DUTY_CYCLE,
242 .cache_type = REGCACHE_RBTREE,
243};
244
cfb61a41
CC		 245static const struct regmap_config axp20x_regmap_config = {
246 .reg_bits = 8,
247 .val_bits = 8,
248 .wr_table = &axp20x_writeable_table,
249 .volatile_table = &axp20x_volatile_table,
553ed4b5 250 .max_register = AXP20X_OCV(AXP20X_OCV_MAX),
cfb61a41
CC		 251 .cache_type = REGCACHE_RBTREE,
252};
253
f05be589
BB		 254static const struct regmap_config axp22x_regmap_config = {
255 .reg_bits = 8,
256 .val_bits = 8,
257 .wr_table = &axp22x_writeable_table,
258 .volatile_table = &axp22x_volatile_table,
259 .max_register = AXP22X_BATLOW_THRES1,
260 .cache_type = REGCACHE_RBTREE,
261};
262
af7e9069
JP		 263static const struct regmap_config axp288_regmap_config = {
264 .reg_bits = 8,
265 .val_bits = 8,
266 .wr_table = &axp288_writeable_table,
267 .volatile_table = &axp288_volatile_table,
268 .max_register = AXP288_FG_TUNE5,
269 .cache_type = REGCACHE_RBTREE,
270};
271
272#define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask) \
273 [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) }
cfb61a41 274
d8d79f8f
MS		 275static const struct regmap_irq axp152_regmap_irqs[] = {
276 INIT_REGMAP_IRQ(AXP152, LDO0IN_CONNECT, 0, 6),
277 INIT_REGMAP_IRQ(AXP152, LDO0IN_REMOVAL, 0, 5),
278 INIT_REGMAP_IRQ(AXP152, ALDO0IN_CONNECT, 0, 3),
279 INIT_REGMAP_IRQ(AXP152, ALDO0IN_REMOVAL, 0, 2),
280 INIT_REGMAP_IRQ(AXP152, DCDC1_V_LOW, 1, 5),
281 INIT_REGMAP_IRQ(AXP152, DCDC2_V_LOW, 1, 4),
282 INIT_REGMAP_IRQ(AXP152, DCDC3_V_LOW, 1, 3),
283 INIT_REGMAP_IRQ(AXP152, DCDC4_V_LOW, 1, 2),
284 INIT_REGMAP_IRQ(AXP152, PEK_SHORT, 1, 1),
285 INIT_REGMAP_IRQ(AXP152, PEK_LONG, 1, 0),
286 INIT_REGMAP_IRQ(AXP152, TIMER, 2, 7),
287 INIT_REGMAP_IRQ(AXP152, PEK_RIS_EDGE, 2, 6),
288 INIT_REGMAP_IRQ(AXP152, PEK_FAL_EDGE, 2, 5),
289 INIT_REGMAP_IRQ(AXP152, GPIO3_INPUT, 2, 3),
290 INIT_REGMAP_IRQ(AXP152, GPIO2_INPUT, 2, 2),
291 INIT_REGMAP_IRQ(AXP152, GPIO1_INPUT, 2, 1),
292 INIT_REGMAP_IRQ(AXP152, GPIO0_INPUT, 2, 0),
293};
294
cfb61a41 295static const struct regmap_irq axp20x_regmap_irqs[] = {
af7e9069
JP		 296 INIT_REGMAP_IRQ(AXP20X, ACIN_OVER_V, 0, 7),
297 INIT_REGMAP_IRQ(AXP20X, ACIN_PLUGIN, 0, 6),
298 INIT_REGMAP_IRQ(AXP20X, ACIN_REMOVAL, 0, 5),
299 INIT_REGMAP_IRQ(AXP20X, VBUS_OVER_V, 0, 4),
300 INIT_REGMAP_IRQ(AXP20X, VBUS_PLUGIN, 0, 3),
301 INIT_REGMAP_IRQ(AXP20X, VBUS_REMOVAL, 0, 2),
302 INIT_REGMAP_IRQ(AXP20X, VBUS_V_LOW, 0, 1),
303 INIT_REGMAP_IRQ(AXP20X, BATT_PLUGIN, 1, 7),
304 INIT_REGMAP_IRQ(AXP20X, BATT_REMOVAL, 1, 6),
305 INIT_REGMAP_IRQ(AXP20X, BATT_ENT_ACT_MODE, 1, 5),
306 INIT_REGMAP_IRQ(AXP20X, BATT_EXIT_ACT_MODE, 1, 4),
307 INIT_REGMAP_IRQ(AXP20X, CHARG, 1, 3),
308 INIT_REGMAP_IRQ(AXP20X, CHARG_DONE, 1, 2),
309 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_HIGH, 1, 1),
310 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_LOW, 1, 0),
311 INIT_REGMAP_IRQ(AXP20X, DIE_TEMP_HIGH, 2, 7),
312 INIT_REGMAP_IRQ(AXP20X, CHARG_I_LOW, 2, 6),
313 INIT_REGMAP_IRQ(AXP20X, DCDC1_V_LONG, 2, 5),
314 INIT_REGMAP_IRQ(AXP20X, DCDC2_V_LONG, 2, 4),
315 INIT_REGMAP_IRQ(AXP20X, DCDC3_V_LONG, 2, 3),
316 INIT_REGMAP_IRQ(AXP20X, PEK_SHORT, 2, 1),
317 INIT_REGMAP_IRQ(AXP20X, PEK_LONG, 2, 0),
318 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_ON, 3, 7),
319 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_OFF, 3, 6),
320 INIT_REGMAP_IRQ(AXP20X, VBUS_VALID, 3, 5),
321 INIT_REGMAP_IRQ(AXP20X, VBUS_NOT_VALID, 3, 4),
322 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_VALID, 3, 3),
323 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_END, 3, 2),
324 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL1, 3, 1),
325 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL2, 3, 0),
326 INIT_REGMAP_IRQ(AXP20X, TIMER, 4, 7),
327 INIT_REGMAP_IRQ(AXP20X, PEK_RIS_EDGE, 4, 6),
328 INIT_REGMAP_IRQ(AXP20X, PEK_FAL_EDGE, 4, 5),
329 INIT_REGMAP_IRQ(AXP20X, GPIO3_INPUT, 4, 3),
330 INIT_REGMAP_IRQ(AXP20X, GPIO2_INPUT, 4, 2),
331 INIT_REGMAP_IRQ(AXP20X, GPIO1_INPUT, 4, 1),
332 INIT_REGMAP_IRQ(AXP20X, GPIO0_INPUT, 4, 0),
333};
334
f05be589
BB		 335static const struct regmap_irq axp22x_regmap_irqs[] = {
336 INIT_REGMAP_IRQ(AXP22X, ACIN_OVER_V, 0, 7),
337 INIT_REGMAP_IRQ(AXP22X, ACIN_PLUGIN, 0, 6),
338 INIT_REGMAP_IRQ(AXP22X, ACIN_REMOVAL, 0, 5),
339 INIT_REGMAP_IRQ(AXP22X, VBUS_OVER_V, 0, 4),
340 INIT_REGMAP_IRQ(AXP22X, VBUS_PLUGIN, 0, 3),
341 INIT_REGMAP_IRQ(AXP22X, VBUS_REMOVAL, 0, 2),
342 INIT_REGMAP_IRQ(AXP22X, VBUS_V_LOW, 0, 1),
343 INIT_REGMAP_IRQ(AXP22X, BATT_PLUGIN, 1, 7),
344 INIT_REGMAP_IRQ(AXP22X, BATT_REMOVAL, 1, 6),
345 INIT_REGMAP_IRQ(AXP22X, BATT_ENT_ACT_MODE, 1, 5),
346 INIT_REGMAP_IRQ(AXP22X, BATT_EXIT_ACT_MODE, 1, 4),
347 INIT_REGMAP_IRQ(AXP22X, CHARG, 1, 3),
348 INIT_REGMAP_IRQ(AXP22X, CHARG_DONE, 1, 2),
349 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_HIGH, 1, 1),
350 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_LOW, 1, 0),
351 INIT_REGMAP_IRQ(AXP22X, DIE_TEMP_HIGH, 2, 7),
352 INIT_REGMAP_IRQ(AXP22X, PEK_SHORT, 2, 1),
353 INIT_REGMAP_IRQ(AXP22X, PEK_LONG, 2, 0),
354 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL1, 3, 1),
355 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL2, 3, 0),
356 INIT_REGMAP_IRQ(AXP22X, TIMER, 4, 7),
357 INIT_REGMAP_IRQ(AXP22X, PEK_RIS_EDGE, 4, 6),
358 INIT_REGMAP_IRQ(AXP22X, PEK_FAL_EDGE, 4, 5),
359 INIT_REGMAP_IRQ(AXP22X, GPIO1_INPUT, 4, 1),
360 INIT_REGMAP_IRQ(AXP22X, GPIO0_INPUT, 4, 0),
361};
362
af7e9069
JP		 363/* some IRQs are compatible with axp20x models */
364static const struct regmap_irq axp288_regmap_irqs[] = {
ff3bbc5c
JP		 365 INIT_REGMAP_IRQ(AXP288, VBUS_FALL, 0, 2),
366 INIT_REGMAP_IRQ(AXP288, VBUS_RISE, 0, 3),
367 INIT_REGMAP_IRQ(AXP288, OV, 0, 4),
af7e9069 368
ff3bbc5c
JP		 369 INIT_REGMAP_IRQ(AXP288, DONE, 1, 2),
370 INIT_REGMAP_IRQ(AXP288, CHARGING, 1, 3),
af7e9069
JP		 371 INIT_REGMAP_IRQ(AXP288, SAFE_QUIT, 1, 4),
372 INIT_REGMAP_IRQ(AXP288, SAFE_ENTER, 1, 5),
ff3bbc5c
JP		 373 INIT_REGMAP_IRQ(AXP288, ABSENT, 1, 6),
374 INIT_REGMAP_IRQ(AXP288, APPEND, 1, 7),
af7e9069
JP		 375
376 INIT_REGMAP_IRQ(AXP288, QWBTU, 2, 0),
377 INIT_REGMAP_IRQ(AXP288, WBTU, 2, 1),
378 INIT_REGMAP_IRQ(AXP288, QWBTO, 2, 2),
ff3bbc5c 379 INIT_REGMAP_IRQ(AXP288, WBTO, 2, 3),
af7e9069
JP		 380 INIT_REGMAP_IRQ(AXP288, QCBTU, 2, 4),
381 INIT_REGMAP_IRQ(AXP288, CBTU, 2, 5),
382 INIT_REGMAP_IRQ(AXP288, QCBTO, 2, 6),
383 INIT_REGMAP_IRQ(AXP288, CBTO, 2, 7),
384
385 INIT_REGMAP_IRQ(AXP288, WL2, 3, 0),
386 INIT_REGMAP_IRQ(AXP288, WL1, 3, 1),
387 INIT_REGMAP_IRQ(AXP288, GPADC, 3, 2),
388 INIT_REGMAP_IRQ(AXP288, OT, 3, 7),
389
390 INIT_REGMAP_IRQ(AXP288, GPIO0, 4, 0),
391 INIT_REGMAP_IRQ(AXP288, GPIO1, 4, 1),
392 INIT_REGMAP_IRQ(AXP288, POKO, 4, 2),
393 INIT_REGMAP_IRQ(AXP288, POKL, 4, 3),
394 INIT_REGMAP_IRQ(AXP288, POKS, 4, 4),
395 INIT_REGMAP_IRQ(AXP288, POKN, 4, 5),
396 INIT_REGMAP_IRQ(AXP288, POKP, 4, 6),
ff3bbc5c 397 INIT_REGMAP_IRQ(AXP288, TIMER, 4, 7),
af7e9069
JP		 398
399 INIT_REGMAP_IRQ(AXP288, MV_CHNG, 5, 0),
400 INIT_REGMAP_IRQ(AXP288, BC_USB_CHNG, 5, 1),
cfb61a41
CC		 401};
402
20147f0d
CYT		 403static const struct regmap_irq axp809_regmap_irqs[] = {
404 INIT_REGMAP_IRQ(AXP809, ACIN_OVER_V, 0, 7),
405 INIT_REGMAP_IRQ(AXP809, ACIN_PLUGIN, 0, 6),
406 INIT_REGMAP_IRQ(AXP809, ACIN_REMOVAL, 0, 5),
407 INIT_REGMAP_IRQ(AXP809, VBUS_OVER_V, 0, 4),
408 INIT_REGMAP_IRQ(AXP809, VBUS_PLUGIN, 0, 3),
409 INIT_REGMAP_IRQ(AXP809, VBUS_REMOVAL, 0, 2),
410 INIT_REGMAP_IRQ(AXP809, VBUS_V_LOW, 0, 1),
411 INIT_REGMAP_IRQ(AXP809, BATT_PLUGIN, 1, 7),
412 INIT_REGMAP_IRQ(AXP809, BATT_REMOVAL, 1, 6),
413 INIT_REGMAP_IRQ(AXP809, BATT_ENT_ACT_MODE, 1, 5),
414 INIT_REGMAP_IRQ(AXP809, BATT_EXIT_ACT_MODE, 1, 4),
415 INIT_REGMAP_IRQ(AXP809, CHARG, 1, 3),
416 INIT_REGMAP_IRQ(AXP809, CHARG_DONE, 1, 2),
417 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH, 2, 7),
418 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH_END, 2, 6),
419 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW, 2, 5),
420 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW_END, 2, 4),
421 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH, 2, 3),
422 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH_END, 2, 2),
423 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW, 2, 1),
424 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW_END, 2, 0),
425 INIT_REGMAP_IRQ(AXP809, DIE_TEMP_HIGH, 3, 7),
426 INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL1, 3, 1),
427 INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL2, 3, 0),
428 INIT_REGMAP_IRQ(AXP809, TIMER, 4, 7),
429 INIT_REGMAP_IRQ(AXP809, PEK_RIS_EDGE, 4, 6),
430 INIT_REGMAP_IRQ(AXP809, PEK_FAL_EDGE, 4, 5),
431 INIT_REGMAP_IRQ(AXP809, PEK_SHORT, 4, 4),
432 INIT_REGMAP_IRQ(AXP809, PEK_LONG, 4, 3),
433 INIT_REGMAP_IRQ(AXP809, PEK_OVER_OFF, 4, 2),
434 INIT_REGMAP_IRQ(AXP809, GPIO1_INPUT, 4, 1),
435 INIT_REGMAP_IRQ(AXP809, GPIO0_INPUT, 4, 0),
436};
437
d8d79f8f
MS		 438static const struct regmap_irq_chip axp152_regmap_irq_chip = {
439 .name = "axp152_irq_chip",
440 .status_base = AXP152_IRQ1_STATE,
441 .ack_base = AXP152_IRQ1_STATE,
442 .mask_base = AXP152_IRQ1_EN,
443 .mask_invert = true,
444 .init_ack_masked = true,
445 .irqs = axp152_regmap_irqs,
446 .num_irqs = ARRAY_SIZE(axp152_regmap_irqs),
447 .num_regs = 3,
448};
449
cfb61a41
CC		 450static const struct regmap_irq_chip axp20x_regmap_irq_chip = {
451 .name = "axp20x_irq_chip",
452 .status_base = AXP20X_IRQ1_STATE,
453 .ack_base = AXP20X_IRQ1_STATE,
454 .mask_base = AXP20X_IRQ1_EN,
af7e9069
JP		 455 .mask_invert = true,
456 .init_ack_masked = true,
cfb61a41
CC		 457 .irqs = axp20x_regmap_irqs,
458 .num_irqs = ARRAY_SIZE(axp20x_regmap_irqs),
af7e9069
JP		 459 .num_regs = 5,
460
461};
462
f05be589
BB		 463static const struct regmap_irq_chip axp22x_regmap_irq_chip = {
464 .name = "axp22x_irq_chip",
465 .status_base = AXP20X_IRQ1_STATE,
466 .ack_base = AXP20X_IRQ1_STATE,
467 .mask_base = AXP20X_IRQ1_EN,
468 .mask_invert = true,
469 .init_ack_masked = true,
470 .irqs = axp22x_regmap_irqs,
471 .num_irqs = ARRAY_SIZE(axp22x_regmap_irqs),
472 .num_regs = 5,
473};
474
af7e9069
JP		 475static const struct regmap_irq_chip axp288_regmap_irq_chip = {
476 .name = "axp288_irq_chip",
477 .status_base = AXP20X_IRQ1_STATE,
478 .ack_base = AXP20X_IRQ1_STATE,
479 .mask_base = AXP20X_IRQ1_EN,
cfb61a41
CC		 480 .mask_invert = true,
481 .init_ack_masked = true,
af7e9069
JP		 482 .irqs = axp288_regmap_irqs,
483 .num_irqs = ARRAY_SIZE(axp288_regmap_irqs),
484 .num_regs = 6,
485
cfb61a41
CC		 486};
487
20147f0d
CYT		 488static const struct regmap_irq_chip axp809_regmap_irq_chip = {
489 .name = "axp809",
490 .status_base = AXP20X_IRQ1_STATE,
491 .ack_base = AXP20X_IRQ1_STATE,
492 .mask_base = AXP20X_IRQ1_EN,
493 .mask_invert = true,
494 .init_ack_masked = true,
495 .irqs = axp809_regmap_irqs,
496 .num_irqs = ARRAY_SIZE(axp809_regmap_irqs),
497 .num_regs = 5,
498};
499
cfb61a41
CC		 500static struct mfd_cell axp20x_cells[] = {
501 {
8de4efda
HG		 502 .name = "axp20x-pek",
503 .num_resources = ARRAY_SIZE(axp20x_pek_resources),
504 .resources = axp20x_pek_resources,
cfb61a41 505 }, {
8de4efda 506 .name = "axp20x-regulator",
cd7cf27b
MH		 507 }, {
508 .name = "axp20x-ac-power-supply",
509 .of_compatible = "x-powers,axp202-ac-power-supply",
510 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
511 .resources = axp20x_ac_power_supply_resources,
8de4efda
HG		 512 }, {
513 .name = "axp20x-usb-power-supply",
514 .of_compatible = "x-powers,axp202-usb-power-supply",
515 .num_resources = ARRAY_SIZE(axp20x_usb_power_supply_resources),
516 .resources = axp20x_usb_power_supply_resources,
cfb61a41
CC		 517 },
518};
519
f05be589
BB		 520static struct mfd_cell axp22x_cells[] = {
521 {
522 .name = "axp20x-pek",
523 .num_resources = ARRAY_SIZE(axp22x_pek_resources),
524 .resources = axp22x_pek_resources,
6d4fa89d
CYT		 525 }, {
526 .name = "axp20x-regulator",
f05be589
BB		 527 },
528};
529
d8d79f8f
MS		 530static struct mfd_cell axp152_cells[] = {
531 {
532 .name = "axp20x-pek",
533 .num_resources = ARRAY_SIZE(axp152_pek_resources),
534 .resources = axp152_pek_resources,
535 },
536};
537
af7e9069
JP		 538static struct resource axp288_adc_resources[] = {
539 {
540 .name = "GPADC",
541 .start = AXP288_IRQ_GPADC,
542 .end = AXP288_IRQ_GPADC,
543 .flags = IORESOURCE_IRQ,
544 },
545};
546
bdb01f78
RP		 547static struct resource axp288_extcon_resources[] = {
548 {
549 .start = AXP288_IRQ_VBUS_FALL,
550 .end = AXP288_IRQ_VBUS_FALL,
551 .flags = IORESOURCE_IRQ,
552 },
553 {
554 .start = AXP288_IRQ_VBUS_RISE,
555 .end = AXP288_IRQ_VBUS_RISE,
556 .flags = IORESOURCE_IRQ,
557 },
558 {
559 .start = AXP288_IRQ_MV_CHNG,
560 .end = AXP288_IRQ_MV_CHNG,
561 .flags = IORESOURCE_IRQ,
562 },
563 {
564 .start = AXP288_IRQ_BC_USB_CHNG,
565 .end = AXP288_IRQ_BC_USB_CHNG,
566 .flags = IORESOURCE_IRQ,
567 },
568};
569
af7e9069
JP		 570static struct resource axp288_charger_resources[] = {
571 {
572 .start = AXP288_IRQ_OV,
573 .end = AXP288_IRQ_OV,
574 .flags = IORESOURCE_IRQ,
575 },
576 {
577 .start = AXP288_IRQ_DONE,
578 .end = AXP288_IRQ_DONE,
579 .flags = IORESOURCE_IRQ,
580 },
581 {
582 .start = AXP288_IRQ_CHARGING,
583 .end = AXP288_IRQ_CHARGING,
584 .flags = IORESOURCE_IRQ,
585 },
586 {
587 .start = AXP288_IRQ_SAFE_QUIT,
588 .end = AXP288_IRQ_SAFE_QUIT,
589 .flags = IORESOURCE_IRQ,
590 },
591 {
592 .start = AXP288_IRQ_SAFE_ENTER,
593 .end = AXP288_IRQ_SAFE_ENTER,
594 .flags = IORESOURCE_IRQ,
595 },
596 {
597 .start = AXP288_IRQ_QCBTU,
598 .end = AXP288_IRQ_QCBTU,
599 .flags = IORESOURCE_IRQ,
600 },
601 {
602 .start = AXP288_IRQ_CBTU,
603 .end = AXP288_IRQ_CBTU,
604 .flags = IORESOURCE_IRQ,
605 },
606 {
607 .start = AXP288_IRQ_QCBTO,
608 .end = AXP288_IRQ_QCBTO,
609 .flags = IORESOURCE_IRQ,
610 },
611 {
612 .start = AXP288_IRQ_CBTO,
613 .end = AXP288_IRQ_CBTO,
614 .flags = IORESOURCE_IRQ,
615 },
616};
617
618static struct mfd_cell axp288_cells[] = {
619 {
620 .name = "axp288_adc",
621 .num_resources = ARRAY_SIZE(axp288_adc_resources),
622 .resources = axp288_adc_resources,
623 },
bdb01f78
RP		 624 {
625 .name = "axp288_extcon",
626 .num_resources = ARRAY_SIZE(axp288_extcon_resources),
627 .resources = axp288_extcon_resources,
628 },
af7e9069
JP		 629 {
630 .name = "axp288_charger",
631 .num_resources = ARRAY_SIZE(axp288_charger_resources),
632 .resources = axp288_charger_resources,
633 },
634 {
d6387874
TB		 635 .name = "axp288_fuel_gauge",
636 .num_resources = ARRAY_SIZE(axp288_fuel_gauge_resources),
637 .resources = axp288_fuel_gauge_resources,
af7e9069 638 },
e56e5ad6
BF		 639 {
640 .name = "axp20x-pek",
641 .num_resources = ARRAY_SIZE(axp288_power_button_resources),
642 .resources = axp288_power_button_resources,
643 },
d8139f63
AL		 644 {
645 .name = "axp288_pmic_acpi",
646 },
af7e9069
JP		 647};
648
20147f0d
CYT		 649static struct mfd_cell axp809_cells[] = {
650 {
651 .name = "axp20x-pek",
652 .num_resources = ARRAY_SIZE(axp809_pek_resources),
653 .resources = axp809_pek_resources,
654 }, {
655 .name = "axp20x-regulator",
656 },
657};
658
cfb61a41
CC		 659static struct axp20x_dev *axp20x_pm_power_off;
660static void axp20x_power_off(void)
661{
af7e9069
JP		 662 if (axp20x_pm_power_off->variant == AXP288_ID)
663 return;
664
cfb61a41
CC		 665 regmap_write(axp20x_pm_power_off->regmap, AXP20X_OFF_CTRL,
666 AXP20X_OFF);
667}
668
4fd41151 669int axp20x_match_device(struct axp20x_dev *axp20x)
af7e9069 670{
e47a3cf7 671 struct device *dev = axp20x->dev;
af7e9069
JP		 672 const struct acpi_device_id *acpi_id;
673 const struct of_device_id *of_id;
674
675 if (dev->of_node) {
af7acc3d 676 of_id = of_match_device(dev->driver->of_match_table, dev);
af7e9069
JP		 677 if (!of_id) {
678 dev_err(dev, "Unable to match OF ID\n");
679 return -ENODEV;
680 }
2260a453 681 axp20x->variant = (long)of_id->data;
af7e9069
JP		 682 } else {
683 acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev);
684 if (!acpi_id || !acpi_id->driver_data) {
685 dev_err(dev, "Unable to match ACPI ID and data\n");
686 return -ENODEV;
687 }
2260a453 688 axp20x->variant = (long)acpi_id->driver_data;
af7e9069
JP		 689 }
690
691 switch (axp20x->variant) {
d8d79f8f
MS		 692 case AXP152_ID:
693 axp20x->nr_cells = ARRAY_SIZE(axp152_cells);
694 axp20x->cells = axp152_cells;
695 axp20x->regmap_cfg = &axp152_regmap_config;
696 axp20x->regmap_irq_chip = &axp152_regmap_irq_chip;
697 break;
af7e9069
JP		 698 case AXP202_ID:
699 case AXP209_ID:
700 axp20x->nr_cells = ARRAY_SIZE(axp20x_cells);
701 axp20x->cells = axp20x_cells;
702 axp20x->regmap_cfg = &axp20x_regmap_config;
703 axp20x->regmap_irq_chip = &axp20x_regmap_irq_chip;
704 break;
f05be589 705 case AXP221_ID:
02071f0f 706 case AXP223_ID:
f05be589
BB		 707 axp20x->nr_cells = ARRAY_SIZE(axp22x_cells);
708 axp20x->cells = axp22x_cells;
709 axp20x->regmap_cfg = &axp22x_regmap_config;
710 axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
711 break;
af7e9069
JP		 712 case AXP288_ID:
713 axp20x->cells = axp288_cells;
714 axp20x->nr_cells = ARRAY_SIZE(axp288_cells);
715 axp20x->regmap_cfg = &axp288_regmap_config;
716 axp20x->regmap_irq_chip = &axp288_regmap_irq_chip;
717 break;
20147f0d
CYT		 718 case AXP809_ID:
719 axp20x->nr_cells = ARRAY_SIZE(axp809_cells);
720 axp20x->cells = axp809_cells;
721 axp20x->regmap_cfg = &axp22x_regmap_config;
722 axp20x->regmap_irq_chip = &axp809_regmap_irq_chip;
723 break;
af7e9069
JP		 724 default:
725 dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant);
726 return -EINVAL;
727 }
728 dev_info(dev, "AXP20x variant %s found\n",
2260a453 729 axp20x_model_names[axp20x->variant]);
af7e9069
JP		 730
731 return 0;
732}
4fd41151 733EXPORT_SYMBOL(axp20x_match_device);
af7e9069 734
4fd41151 735int axp20x_device_probe(struct axp20x_dev *axp20x)
cfb61a41 736{
cfb61a41
CC		 737 int ret;
738
4fd41151 739 ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
cfb61a41 740 IRQF_ONESHOT | IRQF_SHARED, -1,
af7e9069 741 axp20x->regmap_irq_chip,
cfb61a41
CC		 742 &axp20x->regmap_irqc);
743 if (ret) {
4fd41151 744 dev_err(axp20x->dev, "failed to add irq chip: %d\n", ret);
cfb61a41
CC		 745 return ret;
746 }
747
af7e9069 748 ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
2260a453 749 axp20x->nr_cells, NULL, 0, NULL);
cfb61a41
CC		 750
751 if (ret) {
4fd41151
CYT		 752 dev_err(axp20x->dev, "failed to add MFD devices: %d\n", ret);
753 regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
cfb61a41
CC		 754 return ret;
755 }
756
757 if (!pm_power_off) {
758 axp20x_pm_power_off = axp20x;
759 pm_power_off = axp20x_power_off;
760 }
761
4fd41151 762 dev_info(axp20x->dev, "AXP20X driver loaded\n");
cfb61a41
CC		 763
764 return 0;
765}
4fd41151 766EXPORT_SYMBOL(axp20x_device_probe);
cfb61a41 767
4fd41151 768int axp20x_device_remove(struct axp20x_dev *axp20x)
cfb61a41 769{
cfb61a41
CC		 770 if (axp20x == axp20x_pm_power_off) {
771 axp20x_pm_power_off = NULL;
772 pm_power_off = NULL;
773 }
774
775 mfd_remove_devices(axp20x->dev);
4fd41151 776 regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
cfb61a41
CC		 777
778 return 0;
779}
4fd41151 780EXPORT_SYMBOL(axp20x_device_remove);
cfb61a41
CC		 781
782MODULE_DESCRIPTION("PMIC MFD core driver for AXP20X");
783MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
784MODULE_LICENSE("GPL");
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