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cfb61a41 | 1 | /* |
4fd41151 | 2 | * MFD core driver for the X-Powers' Power Management ICs |
cfb61a41 | 3 | * |
af7e9069 JP |
4 | * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK DC-DC |
5 | * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature | |
6 | * as well as configurable GPIOs. | |
cfb61a41 | 7 | * |
4fd41151 CYT |
8 | * This file contains the interface independent core functions. |
9 | * | |
e740235d CYT |
10 | * Copyright (C) 2014 Carlo Caione |
11 | * | |
cfb61a41 CC |
12 | * Author: Carlo Caione <carlo@caione.org> |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | */ | |
18 | ||
19 | #include <linux/err.h> | |
179dc63d | 20 | #include <linux/delay.h> |
cfb61a41 CC |
21 | #include <linux/interrupt.h> |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | #include <linux/regmap.h> | |
cfb61a41 CC |
26 | #include <linux/regulator/consumer.h> |
27 | #include <linux/mfd/axp20x.h> | |
28 | #include <linux/mfd/core.h> | |
29 | #include <linux/of_device.h> | |
af7e9069 | 30 | #include <linux/acpi.h> |
cfb61a41 CC |
31 | |
32 | #define AXP20X_OFF 0x80 | |
33 | ||
c0369698 | 34 | #define AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE 0 |
696f0b3f CYT |
35 | #define AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE BIT(4) |
36 | ||
c31e858b | 37 | static const char * const axp20x_model_names[] = { |
d8d79f8f | 38 | "AXP152", |
af7e9069 JP |
39 | "AXP202", |
40 | "AXP209", | |
f05be589 | 41 | "AXP221", |
02071f0f | 42 | "AXP223", |
af7e9069 | 43 | "AXP288", |
8824ee85 | 44 | "AXP806", |
20147f0d | 45 | "AXP809", |
af7e9069 JP |
46 | }; |
47 | ||
d8d79f8f MS |
48 | static const struct regmap_range axp152_writeable_ranges[] = { |
49 | regmap_reg_range(AXP152_LDO3456_DC1234_CTRL, AXP152_IRQ3_STATE), | |
50 | regmap_reg_range(AXP152_DCDC_MODE, AXP152_PWM1_DUTY_CYCLE), | |
51 | }; | |
52 | ||
53 | static const struct regmap_range axp152_volatile_ranges[] = { | |
54 | regmap_reg_range(AXP152_PWR_OP_MODE, AXP152_PWR_OP_MODE), | |
55 | regmap_reg_range(AXP152_IRQ1_EN, AXP152_IRQ3_STATE), | |
56 | regmap_reg_range(AXP152_GPIO_INPUT, AXP152_GPIO_INPUT), | |
57 | }; | |
58 | ||
59 | static const struct regmap_access_table axp152_writeable_table = { | |
60 | .yes_ranges = axp152_writeable_ranges, | |
61 | .n_yes_ranges = ARRAY_SIZE(axp152_writeable_ranges), | |
62 | }; | |
63 | ||
64 | static const struct regmap_access_table axp152_volatile_table = { | |
65 | .yes_ranges = axp152_volatile_ranges, | |
66 | .n_yes_ranges = ARRAY_SIZE(axp152_volatile_ranges), | |
67 | }; | |
68 | ||
cfb61a41 CC |
69 | static const struct regmap_range axp20x_writeable_ranges[] = { |
70 | regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE), | |
97602370 | 71 | regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2), |
cfb61a41 | 72 | regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES), |
553ed4b5 | 73 | regmap_reg_range(AXP20X_RDC_H, AXP20X_OCV(AXP20X_OCV_MAX)), |
cfb61a41 CC |
74 | }; |
75 | ||
76 | static const struct regmap_range axp20x_volatile_ranges[] = { | |
553ed4b5 BP |
77 | regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_USB_OTG_STATUS), |
78 | regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2), | |
cfb61a41 | 79 | regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE), |
553ed4b5 BP |
80 | regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L), |
81 | regmap_reg_range(AXP20X_GPIO20_SS, AXP20X_GPIO3_CTRL), | |
82 | regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L), | |
cfb61a41 CC |
83 | }; |
84 | ||
85 | static const struct regmap_access_table axp20x_writeable_table = { | |
86 | .yes_ranges = axp20x_writeable_ranges, | |
87 | .n_yes_ranges = ARRAY_SIZE(axp20x_writeable_ranges), | |
88 | }; | |
89 | ||
90 | static const struct regmap_access_table axp20x_volatile_table = { | |
91 | .yes_ranges = axp20x_volatile_ranges, | |
92 | .n_yes_ranges = ARRAY_SIZE(axp20x_volatile_ranges), | |
93 | }; | |
94 | ||
20147f0d | 95 | /* AXP22x ranges are shared with the AXP809, as they cover the same range */ |
f05be589 BB |
96 | static const struct regmap_range axp22x_writeable_ranges[] = { |
97 | regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE), | |
97602370 | 98 | regmap_reg_range(AXP20X_CHRG_CTRL1, AXP22X_CHRG_CTRL3), |
f05be589 BB |
99 | regmap_reg_range(AXP20X_DCDC_MODE, AXP22X_BATLOW_THRES1), |
100 | }; | |
101 | ||
102 | static const struct regmap_range axp22x_volatile_ranges[] = { | |
15093250 | 103 | regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_PWR_OP_MODE), |
f05be589 | 104 | regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE), |
15093250 | 105 | regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE), |
ed7311f0 | 106 | regmap_reg_range(AXP22X_PMIC_TEMP_H, AXP20X_IPSOUT_V_HIGH_L), |
15093250 | 107 | regmap_reg_range(AXP20X_FG_RES, AXP20X_FG_RES), |
f05be589 BB |
108 | }; |
109 | ||
110 | static const struct regmap_access_table axp22x_writeable_table = { | |
111 | .yes_ranges = axp22x_writeable_ranges, | |
112 | .n_yes_ranges = ARRAY_SIZE(axp22x_writeable_ranges), | |
113 | }; | |
114 | ||
115 | static const struct regmap_access_table axp22x_volatile_table = { | |
116 | .yes_ranges = axp22x_volatile_ranges, | |
117 | .n_yes_ranges = ARRAY_SIZE(axp22x_volatile_ranges), | |
118 | }; | |
119 | ||
af7e9069 JP |
120 | static const struct regmap_range axp288_writeable_ranges[] = { |
121 | regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE), | |
122 | regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5), | |
123 | }; | |
124 | ||
125 | static const struct regmap_range axp288_volatile_ranges[] = { | |
cd532166 HG |
126 | regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP288_POWER_REASON), |
127 | regmap_reg_range(AXP288_BC_GLOBAL, AXP288_BC_GLOBAL), | |
128 | regmap_reg_range(AXP288_BC_DET_STAT, AXP288_BC_DET_STAT), | |
af7e9069 | 129 | regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L), |
cd532166 HG |
130 | regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL), |
131 | regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE), | |
132 | regmap_reg_range(AXP288_RT_BATT_V_H, AXP288_RT_BATT_V_L), | |
133 | regmap_reg_range(AXP20X_FG_RES, AXP288_FG_CC_CAP_REG), | |
af7e9069 JP |
134 | }; |
135 | ||
136 | static const struct regmap_access_table axp288_writeable_table = { | |
137 | .yes_ranges = axp288_writeable_ranges, | |
138 | .n_yes_ranges = ARRAY_SIZE(axp288_writeable_ranges), | |
139 | }; | |
140 | ||
141 | static const struct regmap_access_table axp288_volatile_table = { | |
142 | .yes_ranges = axp288_volatile_ranges, | |
143 | .n_yes_ranges = ARRAY_SIZE(axp288_volatile_ranges), | |
144 | }; | |
145 | ||
8824ee85 CYT |
146 | static const struct regmap_range axp806_writeable_ranges[] = { |
147 | regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_DATACACHE(3)), | |
148 | regmap_reg_range(AXP806_PWR_OUT_CTRL1, AXP806_CLDO3_V_CTRL), | |
149 | regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ2_EN), | |
150 | regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE), | |
34d9030b | 151 | regmap_reg_range(AXP806_REG_ADDR_EXT, AXP806_REG_ADDR_EXT), |
8824ee85 CYT |
152 | }; |
153 | ||
154 | static const struct regmap_range axp806_volatile_ranges[] = { | |
155 | regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE), | |
156 | }; | |
157 | ||
158 | static const struct regmap_access_table axp806_writeable_table = { | |
159 | .yes_ranges = axp806_writeable_ranges, | |
160 | .n_yes_ranges = ARRAY_SIZE(axp806_writeable_ranges), | |
161 | }; | |
162 | ||
163 | static const struct regmap_access_table axp806_volatile_table = { | |
164 | .yes_ranges = axp806_volatile_ranges, | |
165 | .n_yes_ranges = ARRAY_SIZE(axp806_volatile_ranges), | |
166 | }; | |
167 | ||
d8d79f8f MS |
168 | static struct resource axp152_pek_resources[] = { |
169 | DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_RIS_EDGE, "PEK_DBR"), | |
170 | DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"), | |
171 | }; | |
172 | ||
cd7cf27b MH |
173 | static struct resource axp20x_ac_power_supply_resources[] = { |
174 | DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"), | |
175 | DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"), | |
176 | DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_OVER_V, "ACIN_OVER_V"), | |
177 | }; | |
178 | ||
cfb61a41 CC |
179 | static struct resource axp20x_pek_resources[] = { |
180 | { | |
181 | .name = "PEK_DBR", | |
182 | .start = AXP20X_IRQ_PEK_RIS_EDGE, | |
183 | .end = AXP20X_IRQ_PEK_RIS_EDGE, | |
184 | .flags = IORESOURCE_IRQ, | |
185 | }, { | |
186 | .name = "PEK_DBF", | |
187 | .start = AXP20X_IRQ_PEK_FAL_EDGE, | |
188 | .end = AXP20X_IRQ_PEK_FAL_EDGE, | |
189 | .flags = IORESOURCE_IRQ, | |
190 | }, | |
191 | }; | |
192 | ||
8de4efda HG |
193 | static struct resource axp20x_usb_power_supply_resources[] = { |
194 | DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"), | |
195 | DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"), | |
196 | DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_VALID, "VBUS_VALID"), | |
197 | DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"), | |
198 | }; | |
199 | ||
ecd98cce HG |
200 | static struct resource axp22x_usb_power_supply_resources[] = { |
201 | DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"), | |
202 | DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"), | |
203 | }; | |
204 | ||
f05be589 BB |
205 | static struct resource axp22x_pek_resources[] = { |
206 | { | |
207 | .name = "PEK_DBR", | |
208 | .start = AXP22X_IRQ_PEK_RIS_EDGE, | |
209 | .end = AXP22X_IRQ_PEK_RIS_EDGE, | |
210 | .flags = IORESOURCE_IRQ, | |
211 | }, { | |
212 | .name = "PEK_DBF", | |
213 | .start = AXP22X_IRQ_PEK_FAL_EDGE, | |
214 | .end = AXP22X_IRQ_PEK_FAL_EDGE, | |
215 | .flags = IORESOURCE_IRQ, | |
216 | }, | |
217 | }; | |
218 | ||
e56e5ad6 BF |
219 | static struct resource axp288_power_button_resources[] = { |
220 | { | |
221 | .name = "PEK_DBR", | |
1af468eb HG |
222 | .start = AXP288_IRQ_POKP, |
223 | .end = AXP288_IRQ_POKP, | |
e56e5ad6 BF |
224 | .flags = IORESOURCE_IRQ, |
225 | }, | |
226 | { | |
227 | .name = "PEK_DBF", | |
1af468eb HG |
228 | .start = AXP288_IRQ_POKN, |
229 | .end = AXP288_IRQ_POKN, | |
e56e5ad6 BF |
230 | .flags = IORESOURCE_IRQ, |
231 | }, | |
232 | }; | |
233 | ||
d6387874 | 234 | static struct resource axp288_fuel_gauge_resources[] = { |
af7e9069 JP |
235 | { |
236 | .start = AXP288_IRQ_QWBTU, | |
237 | .end = AXP288_IRQ_QWBTU, | |
238 | .flags = IORESOURCE_IRQ, | |
239 | }, | |
240 | { | |
241 | .start = AXP288_IRQ_WBTU, | |
242 | .end = AXP288_IRQ_WBTU, | |
243 | .flags = IORESOURCE_IRQ, | |
244 | }, | |
245 | { | |
246 | .start = AXP288_IRQ_QWBTO, | |
247 | .end = AXP288_IRQ_QWBTO, | |
248 | .flags = IORESOURCE_IRQ, | |
249 | }, | |
250 | { | |
251 | .start = AXP288_IRQ_WBTO, | |
252 | .end = AXP288_IRQ_WBTO, | |
253 | .flags = IORESOURCE_IRQ, | |
254 | }, | |
255 | { | |
256 | .start = AXP288_IRQ_WL2, | |
257 | .end = AXP288_IRQ_WL2, | |
258 | .flags = IORESOURCE_IRQ, | |
259 | }, | |
260 | { | |
261 | .start = AXP288_IRQ_WL1, | |
262 | .end = AXP288_IRQ_WL1, | |
263 | .flags = IORESOURCE_IRQ, | |
264 | }, | |
265 | }; | |
266 | ||
20147f0d CYT |
267 | static struct resource axp809_pek_resources[] = { |
268 | { | |
269 | .name = "PEK_DBR", | |
270 | .start = AXP809_IRQ_PEK_RIS_EDGE, | |
271 | .end = AXP809_IRQ_PEK_RIS_EDGE, | |
272 | .flags = IORESOURCE_IRQ, | |
273 | }, { | |
274 | .name = "PEK_DBF", | |
275 | .start = AXP809_IRQ_PEK_FAL_EDGE, | |
276 | .end = AXP809_IRQ_PEK_FAL_EDGE, | |
277 | .flags = IORESOURCE_IRQ, | |
278 | }, | |
279 | }; | |
280 | ||
d8d79f8f MS |
281 | static const struct regmap_config axp152_regmap_config = { |
282 | .reg_bits = 8, | |
283 | .val_bits = 8, | |
284 | .wr_table = &axp152_writeable_table, | |
285 | .volatile_table = &axp152_volatile_table, | |
286 | .max_register = AXP152_PWM1_DUTY_CYCLE, | |
287 | .cache_type = REGCACHE_RBTREE, | |
288 | }; | |
289 | ||
cfb61a41 CC |
290 | static const struct regmap_config axp20x_regmap_config = { |
291 | .reg_bits = 8, | |
292 | .val_bits = 8, | |
293 | .wr_table = &axp20x_writeable_table, | |
294 | .volatile_table = &axp20x_volatile_table, | |
553ed4b5 | 295 | .max_register = AXP20X_OCV(AXP20X_OCV_MAX), |
cfb61a41 CC |
296 | .cache_type = REGCACHE_RBTREE, |
297 | }; | |
298 | ||
f05be589 BB |
299 | static const struct regmap_config axp22x_regmap_config = { |
300 | .reg_bits = 8, | |
301 | .val_bits = 8, | |
302 | .wr_table = &axp22x_writeable_table, | |
303 | .volatile_table = &axp22x_volatile_table, | |
304 | .max_register = AXP22X_BATLOW_THRES1, | |
305 | .cache_type = REGCACHE_RBTREE, | |
306 | }; | |
307 | ||
af7e9069 JP |
308 | static const struct regmap_config axp288_regmap_config = { |
309 | .reg_bits = 8, | |
310 | .val_bits = 8, | |
311 | .wr_table = &axp288_writeable_table, | |
312 | .volatile_table = &axp288_volatile_table, | |
313 | .max_register = AXP288_FG_TUNE5, | |
314 | .cache_type = REGCACHE_RBTREE, | |
315 | }; | |
316 | ||
8824ee85 CYT |
317 | static const struct regmap_config axp806_regmap_config = { |
318 | .reg_bits = 8, | |
319 | .val_bits = 8, | |
320 | .wr_table = &axp806_writeable_table, | |
321 | .volatile_table = &axp806_volatile_table, | |
34d9030b | 322 | .max_register = AXP806_REG_ADDR_EXT, |
8824ee85 CYT |
323 | .cache_type = REGCACHE_RBTREE, |
324 | }; | |
325 | ||
af7e9069 JP |
326 | #define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask) \ |
327 | [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) } | |
cfb61a41 | 328 | |
d8d79f8f MS |
329 | static const struct regmap_irq axp152_regmap_irqs[] = { |
330 | INIT_REGMAP_IRQ(AXP152, LDO0IN_CONNECT, 0, 6), | |
331 | INIT_REGMAP_IRQ(AXP152, LDO0IN_REMOVAL, 0, 5), | |
332 | INIT_REGMAP_IRQ(AXP152, ALDO0IN_CONNECT, 0, 3), | |
333 | INIT_REGMAP_IRQ(AXP152, ALDO0IN_REMOVAL, 0, 2), | |
334 | INIT_REGMAP_IRQ(AXP152, DCDC1_V_LOW, 1, 5), | |
335 | INIT_REGMAP_IRQ(AXP152, DCDC2_V_LOW, 1, 4), | |
336 | INIT_REGMAP_IRQ(AXP152, DCDC3_V_LOW, 1, 3), | |
337 | INIT_REGMAP_IRQ(AXP152, DCDC4_V_LOW, 1, 2), | |
338 | INIT_REGMAP_IRQ(AXP152, PEK_SHORT, 1, 1), | |
339 | INIT_REGMAP_IRQ(AXP152, PEK_LONG, 1, 0), | |
340 | INIT_REGMAP_IRQ(AXP152, TIMER, 2, 7), | |
341 | INIT_REGMAP_IRQ(AXP152, PEK_RIS_EDGE, 2, 6), | |
342 | INIT_REGMAP_IRQ(AXP152, PEK_FAL_EDGE, 2, 5), | |
343 | INIT_REGMAP_IRQ(AXP152, GPIO3_INPUT, 2, 3), | |
344 | INIT_REGMAP_IRQ(AXP152, GPIO2_INPUT, 2, 2), | |
345 | INIT_REGMAP_IRQ(AXP152, GPIO1_INPUT, 2, 1), | |
346 | INIT_REGMAP_IRQ(AXP152, GPIO0_INPUT, 2, 0), | |
347 | }; | |
348 | ||
cfb61a41 | 349 | static const struct regmap_irq axp20x_regmap_irqs[] = { |
af7e9069 JP |
350 | INIT_REGMAP_IRQ(AXP20X, ACIN_OVER_V, 0, 7), |
351 | INIT_REGMAP_IRQ(AXP20X, ACIN_PLUGIN, 0, 6), | |
352 | INIT_REGMAP_IRQ(AXP20X, ACIN_REMOVAL, 0, 5), | |
353 | INIT_REGMAP_IRQ(AXP20X, VBUS_OVER_V, 0, 4), | |
354 | INIT_REGMAP_IRQ(AXP20X, VBUS_PLUGIN, 0, 3), | |
355 | INIT_REGMAP_IRQ(AXP20X, VBUS_REMOVAL, 0, 2), | |
356 | INIT_REGMAP_IRQ(AXP20X, VBUS_V_LOW, 0, 1), | |
357 | INIT_REGMAP_IRQ(AXP20X, BATT_PLUGIN, 1, 7), | |
358 | INIT_REGMAP_IRQ(AXP20X, BATT_REMOVAL, 1, 6), | |
359 | INIT_REGMAP_IRQ(AXP20X, BATT_ENT_ACT_MODE, 1, 5), | |
360 | INIT_REGMAP_IRQ(AXP20X, BATT_EXIT_ACT_MODE, 1, 4), | |
361 | INIT_REGMAP_IRQ(AXP20X, CHARG, 1, 3), | |
362 | INIT_REGMAP_IRQ(AXP20X, CHARG_DONE, 1, 2), | |
363 | INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_HIGH, 1, 1), | |
364 | INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_LOW, 1, 0), | |
365 | INIT_REGMAP_IRQ(AXP20X, DIE_TEMP_HIGH, 2, 7), | |
366 | INIT_REGMAP_IRQ(AXP20X, CHARG_I_LOW, 2, 6), | |
367 | INIT_REGMAP_IRQ(AXP20X, DCDC1_V_LONG, 2, 5), | |
368 | INIT_REGMAP_IRQ(AXP20X, DCDC2_V_LONG, 2, 4), | |
369 | INIT_REGMAP_IRQ(AXP20X, DCDC3_V_LONG, 2, 3), | |
370 | INIT_REGMAP_IRQ(AXP20X, PEK_SHORT, 2, 1), | |
371 | INIT_REGMAP_IRQ(AXP20X, PEK_LONG, 2, 0), | |
372 | INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_ON, 3, 7), | |
373 | INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_OFF, 3, 6), | |
374 | INIT_REGMAP_IRQ(AXP20X, VBUS_VALID, 3, 5), | |
375 | INIT_REGMAP_IRQ(AXP20X, VBUS_NOT_VALID, 3, 4), | |
376 | INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_VALID, 3, 3), | |
377 | INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_END, 3, 2), | |
378 | INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL1, 3, 1), | |
379 | INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL2, 3, 0), | |
380 | INIT_REGMAP_IRQ(AXP20X, TIMER, 4, 7), | |
381 | INIT_REGMAP_IRQ(AXP20X, PEK_RIS_EDGE, 4, 6), | |
382 | INIT_REGMAP_IRQ(AXP20X, PEK_FAL_EDGE, 4, 5), | |
383 | INIT_REGMAP_IRQ(AXP20X, GPIO3_INPUT, 4, 3), | |
384 | INIT_REGMAP_IRQ(AXP20X, GPIO2_INPUT, 4, 2), | |
385 | INIT_REGMAP_IRQ(AXP20X, GPIO1_INPUT, 4, 1), | |
386 | INIT_REGMAP_IRQ(AXP20X, GPIO0_INPUT, 4, 0), | |
387 | }; | |
388 | ||
f05be589 BB |
389 | static const struct regmap_irq axp22x_regmap_irqs[] = { |
390 | INIT_REGMAP_IRQ(AXP22X, ACIN_OVER_V, 0, 7), | |
391 | INIT_REGMAP_IRQ(AXP22X, ACIN_PLUGIN, 0, 6), | |
392 | INIT_REGMAP_IRQ(AXP22X, ACIN_REMOVAL, 0, 5), | |
393 | INIT_REGMAP_IRQ(AXP22X, VBUS_OVER_V, 0, 4), | |
394 | INIT_REGMAP_IRQ(AXP22X, VBUS_PLUGIN, 0, 3), | |
395 | INIT_REGMAP_IRQ(AXP22X, VBUS_REMOVAL, 0, 2), | |
396 | INIT_REGMAP_IRQ(AXP22X, VBUS_V_LOW, 0, 1), | |
397 | INIT_REGMAP_IRQ(AXP22X, BATT_PLUGIN, 1, 7), | |
398 | INIT_REGMAP_IRQ(AXP22X, BATT_REMOVAL, 1, 6), | |
399 | INIT_REGMAP_IRQ(AXP22X, BATT_ENT_ACT_MODE, 1, 5), | |
400 | INIT_REGMAP_IRQ(AXP22X, BATT_EXIT_ACT_MODE, 1, 4), | |
401 | INIT_REGMAP_IRQ(AXP22X, CHARG, 1, 3), | |
402 | INIT_REGMAP_IRQ(AXP22X, CHARG_DONE, 1, 2), | |
403 | INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_HIGH, 1, 1), | |
404 | INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_LOW, 1, 0), | |
405 | INIT_REGMAP_IRQ(AXP22X, DIE_TEMP_HIGH, 2, 7), | |
406 | INIT_REGMAP_IRQ(AXP22X, PEK_SHORT, 2, 1), | |
407 | INIT_REGMAP_IRQ(AXP22X, PEK_LONG, 2, 0), | |
408 | INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL1, 3, 1), | |
409 | INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL2, 3, 0), | |
410 | INIT_REGMAP_IRQ(AXP22X, TIMER, 4, 7), | |
411 | INIT_REGMAP_IRQ(AXP22X, PEK_RIS_EDGE, 4, 6), | |
412 | INIT_REGMAP_IRQ(AXP22X, PEK_FAL_EDGE, 4, 5), | |
413 | INIT_REGMAP_IRQ(AXP22X, GPIO1_INPUT, 4, 1), | |
414 | INIT_REGMAP_IRQ(AXP22X, GPIO0_INPUT, 4, 0), | |
415 | }; | |
416 | ||
af7e9069 JP |
417 | /* some IRQs are compatible with axp20x models */ |
418 | static const struct regmap_irq axp288_regmap_irqs[] = { | |
ff3bbc5c JP |
419 | INIT_REGMAP_IRQ(AXP288, VBUS_FALL, 0, 2), |
420 | INIT_REGMAP_IRQ(AXP288, VBUS_RISE, 0, 3), | |
421 | INIT_REGMAP_IRQ(AXP288, OV, 0, 4), | |
8b44e678 HG |
422 | INIT_REGMAP_IRQ(AXP288, FALLING_ALT, 0, 5), |
423 | INIT_REGMAP_IRQ(AXP288, RISING_ALT, 0, 6), | |
424 | INIT_REGMAP_IRQ(AXP288, OV_ALT, 0, 7), | |
af7e9069 | 425 | |
ff3bbc5c JP |
426 | INIT_REGMAP_IRQ(AXP288, DONE, 1, 2), |
427 | INIT_REGMAP_IRQ(AXP288, CHARGING, 1, 3), | |
af7e9069 JP |
428 | INIT_REGMAP_IRQ(AXP288, SAFE_QUIT, 1, 4), |
429 | INIT_REGMAP_IRQ(AXP288, SAFE_ENTER, 1, 5), | |
ff3bbc5c JP |
430 | INIT_REGMAP_IRQ(AXP288, ABSENT, 1, 6), |
431 | INIT_REGMAP_IRQ(AXP288, APPEND, 1, 7), | |
af7e9069 JP |
432 | |
433 | INIT_REGMAP_IRQ(AXP288, QWBTU, 2, 0), | |
434 | INIT_REGMAP_IRQ(AXP288, WBTU, 2, 1), | |
435 | INIT_REGMAP_IRQ(AXP288, QWBTO, 2, 2), | |
ff3bbc5c | 436 | INIT_REGMAP_IRQ(AXP288, WBTO, 2, 3), |
af7e9069 JP |
437 | INIT_REGMAP_IRQ(AXP288, QCBTU, 2, 4), |
438 | INIT_REGMAP_IRQ(AXP288, CBTU, 2, 5), | |
439 | INIT_REGMAP_IRQ(AXP288, QCBTO, 2, 6), | |
440 | INIT_REGMAP_IRQ(AXP288, CBTO, 2, 7), | |
441 | ||
442 | INIT_REGMAP_IRQ(AXP288, WL2, 3, 0), | |
443 | INIT_REGMAP_IRQ(AXP288, WL1, 3, 1), | |
444 | INIT_REGMAP_IRQ(AXP288, GPADC, 3, 2), | |
445 | INIT_REGMAP_IRQ(AXP288, OT, 3, 7), | |
446 | ||
447 | INIT_REGMAP_IRQ(AXP288, GPIO0, 4, 0), | |
448 | INIT_REGMAP_IRQ(AXP288, GPIO1, 4, 1), | |
449 | INIT_REGMAP_IRQ(AXP288, POKO, 4, 2), | |
450 | INIT_REGMAP_IRQ(AXP288, POKL, 4, 3), | |
451 | INIT_REGMAP_IRQ(AXP288, POKS, 4, 4), | |
452 | INIT_REGMAP_IRQ(AXP288, POKN, 4, 5), | |
453 | INIT_REGMAP_IRQ(AXP288, POKP, 4, 6), | |
ff3bbc5c | 454 | INIT_REGMAP_IRQ(AXP288, TIMER, 4, 7), |
af7e9069 JP |
455 | |
456 | INIT_REGMAP_IRQ(AXP288, MV_CHNG, 5, 0), | |
457 | INIT_REGMAP_IRQ(AXP288, BC_USB_CHNG, 5, 1), | |
cfb61a41 CC |
458 | }; |
459 | ||
8824ee85 CYT |
460 | static const struct regmap_irq axp806_regmap_irqs[] = { |
461 | INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV1, 0, 0), | |
462 | INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV2, 0, 1), | |
463 | INIT_REGMAP_IRQ(AXP806, DCDCA_V_LOW, 0, 3), | |
464 | INIT_REGMAP_IRQ(AXP806, DCDCB_V_LOW, 0, 4), | |
465 | INIT_REGMAP_IRQ(AXP806, DCDCC_V_LOW, 0, 5), | |
466 | INIT_REGMAP_IRQ(AXP806, DCDCD_V_LOW, 0, 6), | |
467 | INIT_REGMAP_IRQ(AXP806, DCDCE_V_LOW, 0, 7), | |
468 | INIT_REGMAP_IRQ(AXP806, PWROK_LONG, 1, 0), | |
469 | INIT_REGMAP_IRQ(AXP806, PWROK_SHORT, 1, 1), | |
470 | INIT_REGMAP_IRQ(AXP806, WAKEUP, 1, 4), | |
471 | INIT_REGMAP_IRQ(AXP806, PWROK_FALL, 1, 5), | |
472 | INIT_REGMAP_IRQ(AXP806, PWROK_RISE, 1, 6), | |
473 | }; | |
474 | ||
20147f0d CYT |
475 | static const struct regmap_irq axp809_regmap_irqs[] = { |
476 | INIT_REGMAP_IRQ(AXP809, ACIN_OVER_V, 0, 7), | |
477 | INIT_REGMAP_IRQ(AXP809, ACIN_PLUGIN, 0, 6), | |
478 | INIT_REGMAP_IRQ(AXP809, ACIN_REMOVAL, 0, 5), | |
479 | INIT_REGMAP_IRQ(AXP809, VBUS_OVER_V, 0, 4), | |
480 | INIT_REGMAP_IRQ(AXP809, VBUS_PLUGIN, 0, 3), | |
481 | INIT_REGMAP_IRQ(AXP809, VBUS_REMOVAL, 0, 2), | |
482 | INIT_REGMAP_IRQ(AXP809, VBUS_V_LOW, 0, 1), | |
483 | INIT_REGMAP_IRQ(AXP809, BATT_PLUGIN, 1, 7), | |
484 | INIT_REGMAP_IRQ(AXP809, BATT_REMOVAL, 1, 6), | |
485 | INIT_REGMAP_IRQ(AXP809, BATT_ENT_ACT_MODE, 1, 5), | |
486 | INIT_REGMAP_IRQ(AXP809, BATT_EXIT_ACT_MODE, 1, 4), | |
487 | INIT_REGMAP_IRQ(AXP809, CHARG, 1, 3), | |
488 | INIT_REGMAP_IRQ(AXP809, CHARG_DONE, 1, 2), | |
489 | INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH, 2, 7), | |
490 | INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH_END, 2, 6), | |
491 | INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW, 2, 5), | |
492 | INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW_END, 2, 4), | |
493 | INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH, 2, 3), | |
494 | INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH_END, 2, 2), | |
495 | INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW, 2, 1), | |
496 | INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW_END, 2, 0), | |
497 | INIT_REGMAP_IRQ(AXP809, DIE_TEMP_HIGH, 3, 7), | |
498 | INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL1, 3, 1), | |
499 | INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL2, 3, 0), | |
500 | INIT_REGMAP_IRQ(AXP809, TIMER, 4, 7), | |
501 | INIT_REGMAP_IRQ(AXP809, PEK_RIS_EDGE, 4, 6), | |
502 | INIT_REGMAP_IRQ(AXP809, PEK_FAL_EDGE, 4, 5), | |
503 | INIT_REGMAP_IRQ(AXP809, PEK_SHORT, 4, 4), | |
504 | INIT_REGMAP_IRQ(AXP809, PEK_LONG, 4, 3), | |
505 | INIT_REGMAP_IRQ(AXP809, PEK_OVER_OFF, 4, 2), | |
506 | INIT_REGMAP_IRQ(AXP809, GPIO1_INPUT, 4, 1), | |
507 | INIT_REGMAP_IRQ(AXP809, GPIO0_INPUT, 4, 0), | |
508 | }; | |
509 | ||
d8d79f8f MS |
510 | static const struct regmap_irq_chip axp152_regmap_irq_chip = { |
511 | .name = "axp152_irq_chip", | |
512 | .status_base = AXP152_IRQ1_STATE, | |
513 | .ack_base = AXP152_IRQ1_STATE, | |
514 | .mask_base = AXP152_IRQ1_EN, | |
515 | .mask_invert = true, | |
516 | .init_ack_masked = true, | |
517 | .irqs = axp152_regmap_irqs, | |
518 | .num_irqs = ARRAY_SIZE(axp152_regmap_irqs), | |
519 | .num_regs = 3, | |
520 | }; | |
521 | ||
cfb61a41 CC |
522 | static const struct regmap_irq_chip axp20x_regmap_irq_chip = { |
523 | .name = "axp20x_irq_chip", | |
524 | .status_base = AXP20X_IRQ1_STATE, | |
525 | .ack_base = AXP20X_IRQ1_STATE, | |
526 | .mask_base = AXP20X_IRQ1_EN, | |
af7e9069 JP |
527 | .mask_invert = true, |
528 | .init_ack_masked = true, | |
cfb61a41 CC |
529 | .irqs = axp20x_regmap_irqs, |
530 | .num_irqs = ARRAY_SIZE(axp20x_regmap_irqs), | |
af7e9069 JP |
531 | .num_regs = 5, |
532 | ||
533 | }; | |
534 | ||
f05be589 BB |
535 | static const struct regmap_irq_chip axp22x_regmap_irq_chip = { |
536 | .name = "axp22x_irq_chip", | |
537 | .status_base = AXP20X_IRQ1_STATE, | |
538 | .ack_base = AXP20X_IRQ1_STATE, | |
539 | .mask_base = AXP20X_IRQ1_EN, | |
540 | .mask_invert = true, | |
541 | .init_ack_masked = true, | |
542 | .irqs = axp22x_regmap_irqs, | |
543 | .num_irqs = ARRAY_SIZE(axp22x_regmap_irqs), | |
544 | .num_regs = 5, | |
545 | }; | |
546 | ||
af7e9069 JP |
547 | static const struct regmap_irq_chip axp288_regmap_irq_chip = { |
548 | .name = "axp288_irq_chip", | |
549 | .status_base = AXP20X_IRQ1_STATE, | |
550 | .ack_base = AXP20X_IRQ1_STATE, | |
551 | .mask_base = AXP20X_IRQ1_EN, | |
cfb61a41 CC |
552 | .mask_invert = true, |
553 | .init_ack_masked = true, | |
af7e9069 JP |
554 | .irqs = axp288_regmap_irqs, |
555 | .num_irqs = ARRAY_SIZE(axp288_regmap_irqs), | |
556 | .num_regs = 6, | |
557 | ||
cfb61a41 CC |
558 | }; |
559 | ||
8824ee85 CYT |
560 | static const struct regmap_irq_chip axp806_regmap_irq_chip = { |
561 | .name = "axp806", | |
562 | .status_base = AXP20X_IRQ1_STATE, | |
563 | .ack_base = AXP20X_IRQ1_STATE, | |
564 | .mask_base = AXP20X_IRQ1_EN, | |
565 | .mask_invert = true, | |
566 | .init_ack_masked = true, | |
567 | .irqs = axp806_regmap_irqs, | |
568 | .num_irqs = ARRAY_SIZE(axp806_regmap_irqs), | |
569 | .num_regs = 2, | |
570 | }; | |
571 | ||
20147f0d CYT |
572 | static const struct regmap_irq_chip axp809_regmap_irq_chip = { |
573 | .name = "axp809", | |
574 | .status_base = AXP20X_IRQ1_STATE, | |
575 | .ack_base = AXP20X_IRQ1_STATE, | |
576 | .mask_base = AXP20X_IRQ1_EN, | |
577 | .mask_invert = true, | |
578 | .init_ack_masked = true, | |
579 | .irqs = axp809_regmap_irqs, | |
580 | .num_irqs = ARRAY_SIZE(axp809_regmap_irqs), | |
581 | .num_regs = 5, | |
582 | }; | |
583 | ||
cfb61a41 CC |
584 | static struct mfd_cell axp20x_cells[] = { |
585 | { | |
b419c16b MR |
586 | .name = "axp20x-gpio", |
587 | .of_compatible = "x-powers,axp209-gpio", | |
588 | }, { | |
8de4efda HG |
589 | .name = "axp20x-pek", |
590 | .num_resources = ARRAY_SIZE(axp20x_pek_resources), | |
591 | .resources = axp20x_pek_resources, | |
cfb61a41 | 592 | }, { |
8de4efda | 593 | .name = "axp20x-regulator", |
4d5e5c34 QS |
594 | }, { |
595 | .name = "axp20x-adc", | |
b4aeceb6 QS |
596 | }, { |
597 | .name = "axp20x-battery-power-supply", | |
598 | .of_compatible = "x-powers,axp209-battery-power-supply", | |
cd7cf27b MH |
599 | }, { |
600 | .name = "axp20x-ac-power-supply", | |
601 | .of_compatible = "x-powers,axp202-ac-power-supply", | |
602 | .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources), | |
603 | .resources = axp20x_ac_power_supply_resources, | |
8de4efda HG |
604 | }, { |
605 | .name = "axp20x-usb-power-supply", | |
606 | .of_compatible = "x-powers,axp202-usb-power-supply", | |
607 | .num_resources = ARRAY_SIZE(axp20x_usb_power_supply_resources), | |
608 | .resources = axp20x_usb_power_supply_resources, | |
cfb61a41 CC |
609 | }, |
610 | }; | |
611 | ||
4c650561 QS |
612 | static struct mfd_cell axp221_cells[] = { |
613 | { | |
614 | .name = "axp20x-pek", | |
615 | .num_resources = ARRAY_SIZE(axp22x_pek_resources), | |
616 | .resources = axp22x_pek_resources, | |
617 | }, { | |
618 | .name = "axp20x-regulator", | |
4d5e5c34 QS |
619 | }, { |
620 | .name = "axp22x-adc" | |
95c4f531 QS |
621 | }, { |
622 | .name = "axp20x-ac-power-supply", | |
623 | .of_compatible = "x-powers,axp221-ac-power-supply", | |
624 | .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources), | |
625 | .resources = axp20x_ac_power_supply_resources, | |
b4aeceb6 QS |
626 | }, { |
627 | .name = "axp20x-battery-power-supply", | |
628 | .of_compatible = "x-powers,axp221-battery-power-supply", | |
4c650561 QS |
629 | }, { |
630 | .name = "axp20x-usb-power-supply", | |
631 | .of_compatible = "x-powers,axp221-usb-power-supply", | |
632 | .num_resources = ARRAY_SIZE(axp22x_usb_power_supply_resources), | |
633 | .resources = axp22x_usb_power_supply_resources, | |
634 | }, | |
635 | }; | |
636 | ||
637 | static struct mfd_cell axp223_cells[] = { | |
f05be589 BB |
638 | { |
639 | .name = "axp20x-pek", | |
640 | .num_resources = ARRAY_SIZE(axp22x_pek_resources), | |
641 | .resources = axp22x_pek_resources, | |
4d5e5c34 QS |
642 | }, { |
643 | .name = "axp22x-adc", | |
b4aeceb6 QS |
644 | }, { |
645 | .name = "axp20x-battery-power-supply", | |
646 | .of_compatible = "x-powers,axp221-battery-power-supply", | |
6d4fa89d CYT |
647 | }, { |
648 | .name = "axp20x-regulator", | |
95c4f531 QS |
649 | }, { |
650 | .name = "axp20x-ac-power-supply", | |
651 | .of_compatible = "x-powers,axp221-ac-power-supply", | |
652 | .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources), | |
653 | .resources = axp20x_ac_power_supply_resources, | |
ecd98cce HG |
654 | }, { |
655 | .name = "axp20x-usb-power-supply", | |
4c650561 | 656 | .of_compatible = "x-powers,axp223-usb-power-supply", |
ecd98cce HG |
657 | .num_resources = ARRAY_SIZE(axp22x_usb_power_supply_resources), |
658 | .resources = axp22x_usb_power_supply_resources, | |
f05be589 BB |
659 | }, |
660 | }; | |
661 | ||
d8d79f8f MS |
662 | static struct mfd_cell axp152_cells[] = { |
663 | { | |
664 | .name = "axp20x-pek", | |
665 | .num_resources = ARRAY_SIZE(axp152_pek_resources), | |
666 | .resources = axp152_pek_resources, | |
667 | }, | |
668 | }; | |
669 | ||
af7e9069 JP |
670 | static struct resource axp288_adc_resources[] = { |
671 | { | |
672 | .name = "GPADC", | |
673 | .start = AXP288_IRQ_GPADC, | |
674 | .end = AXP288_IRQ_GPADC, | |
675 | .flags = IORESOURCE_IRQ, | |
676 | }, | |
677 | }; | |
678 | ||
bdb01f78 RP |
679 | static struct resource axp288_extcon_resources[] = { |
680 | { | |
681 | .start = AXP288_IRQ_VBUS_FALL, | |
682 | .end = AXP288_IRQ_VBUS_FALL, | |
683 | .flags = IORESOURCE_IRQ, | |
684 | }, | |
685 | { | |
686 | .start = AXP288_IRQ_VBUS_RISE, | |
687 | .end = AXP288_IRQ_VBUS_RISE, | |
688 | .flags = IORESOURCE_IRQ, | |
689 | }, | |
690 | { | |
691 | .start = AXP288_IRQ_MV_CHNG, | |
692 | .end = AXP288_IRQ_MV_CHNG, | |
693 | .flags = IORESOURCE_IRQ, | |
694 | }, | |
695 | { | |
696 | .start = AXP288_IRQ_BC_USB_CHNG, | |
697 | .end = AXP288_IRQ_BC_USB_CHNG, | |
698 | .flags = IORESOURCE_IRQ, | |
699 | }, | |
700 | }; | |
701 | ||
af7e9069 JP |
702 | static struct resource axp288_charger_resources[] = { |
703 | { | |
704 | .start = AXP288_IRQ_OV, | |
705 | .end = AXP288_IRQ_OV, | |
706 | .flags = IORESOURCE_IRQ, | |
707 | }, | |
708 | { | |
709 | .start = AXP288_IRQ_DONE, | |
710 | .end = AXP288_IRQ_DONE, | |
711 | .flags = IORESOURCE_IRQ, | |
712 | }, | |
713 | { | |
714 | .start = AXP288_IRQ_CHARGING, | |
715 | .end = AXP288_IRQ_CHARGING, | |
716 | .flags = IORESOURCE_IRQ, | |
717 | }, | |
718 | { | |
719 | .start = AXP288_IRQ_SAFE_QUIT, | |
720 | .end = AXP288_IRQ_SAFE_QUIT, | |
721 | .flags = IORESOURCE_IRQ, | |
722 | }, | |
723 | { | |
724 | .start = AXP288_IRQ_SAFE_ENTER, | |
725 | .end = AXP288_IRQ_SAFE_ENTER, | |
726 | .flags = IORESOURCE_IRQ, | |
727 | }, | |
728 | { | |
729 | .start = AXP288_IRQ_QCBTU, | |
730 | .end = AXP288_IRQ_QCBTU, | |
731 | .flags = IORESOURCE_IRQ, | |
732 | }, | |
733 | { | |
734 | .start = AXP288_IRQ_CBTU, | |
735 | .end = AXP288_IRQ_CBTU, | |
736 | .flags = IORESOURCE_IRQ, | |
737 | }, | |
738 | { | |
739 | .start = AXP288_IRQ_QCBTO, | |
740 | .end = AXP288_IRQ_QCBTO, | |
741 | .flags = IORESOURCE_IRQ, | |
742 | }, | |
743 | { | |
744 | .start = AXP288_IRQ_CBTO, | |
745 | .end = AXP288_IRQ_CBTO, | |
746 | .flags = IORESOURCE_IRQ, | |
747 | }, | |
748 | }; | |
749 | ||
750 | static struct mfd_cell axp288_cells[] = { | |
751 | { | |
752 | .name = "axp288_adc", | |
753 | .num_resources = ARRAY_SIZE(axp288_adc_resources), | |
754 | .resources = axp288_adc_resources, | |
755 | }, | |
bdb01f78 RP |
756 | { |
757 | .name = "axp288_extcon", | |
758 | .num_resources = ARRAY_SIZE(axp288_extcon_resources), | |
759 | .resources = axp288_extcon_resources, | |
760 | }, | |
af7e9069 JP |
761 | { |
762 | .name = "axp288_charger", | |
763 | .num_resources = ARRAY_SIZE(axp288_charger_resources), | |
764 | .resources = axp288_charger_resources, | |
765 | }, | |
766 | { | |
d6387874 TB |
767 | .name = "axp288_fuel_gauge", |
768 | .num_resources = ARRAY_SIZE(axp288_fuel_gauge_resources), | |
769 | .resources = axp288_fuel_gauge_resources, | |
af7e9069 | 770 | }, |
e56e5ad6 BF |
771 | { |
772 | .name = "axp20x-pek", | |
773 | .num_resources = ARRAY_SIZE(axp288_power_button_resources), | |
774 | .resources = axp288_power_button_resources, | |
775 | }, | |
d8139f63 AL |
776 | { |
777 | .name = "axp288_pmic_acpi", | |
778 | }, | |
af7e9069 JP |
779 | }; |
780 | ||
8824ee85 CYT |
781 | static struct mfd_cell axp806_cells[] = { |
782 | { | |
783 | .id = 2, | |
784 | .name = "axp20x-regulator", | |
785 | }, | |
786 | }; | |
787 | ||
20147f0d CYT |
788 | static struct mfd_cell axp809_cells[] = { |
789 | { | |
790 | .name = "axp20x-pek", | |
791 | .num_resources = ARRAY_SIZE(axp809_pek_resources), | |
792 | .resources = axp809_pek_resources, | |
793 | }, { | |
8824ee85 | 794 | .id = 1, |
20147f0d CYT |
795 | .name = "axp20x-regulator", |
796 | }, | |
797 | }; | |
798 | ||
cfb61a41 CC |
799 | static struct axp20x_dev *axp20x_pm_power_off; |
800 | static void axp20x_power_off(void) | |
801 | { | |
af7e9069 JP |
802 | if (axp20x_pm_power_off->variant == AXP288_ID) |
803 | return; | |
804 | ||
cfb61a41 CC |
805 | regmap_write(axp20x_pm_power_off->regmap, AXP20X_OFF_CTRL, |
806 | AXP20X_OFF); | |
179dc63d HG |
807 | |
808 | /* Give capacitors etc. time to drain to avoid kernel panic msg. */ | |
809 | msleep(500); | |
cfb61a41 CC |
810 | } |
811 | ||
4fd41151 | 812 | int axp20x_match_device(struct axp20x_dev *axp20x) |
af7e9069 | 813 | { |
e47a3cf7 | 814 | struct device *dev = axp20x->dev; |
af7e9069 JP |
815 | const struct acpi_device_id *acpi_id; |
816 | const struct of_device_id *of_id; | |
817 | ||
818 | if (dev->of_node) { | |
af7acc3d | 819 | of_id = of_match_device(dev->driver->of_match_table, dev); |
af7e9069 JP |
820 | if (!of_id) { |
821 | dev_err(dev, "Unable to match OF ID\n"); | |
822 | return -ENODEV; | |
823 | } | |
2260a453 | 824 | axp20x->variant = (long)of_id->data; |
af7e9069 JP |
825 | } else { |
826 | acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev); | |
827 | if (!acpi_id || !acpi_id->driver_data) { | |
828 | dev_err(dev, "Unable to match ACPI ID and data\n"); | |
829 | return -ENODEV; | |
830 | } | |
2260a453 | 831 | axp20x->variant = (long)acpi_id->driver_data; |
af7e9069 JP |
832 | } |
833 | ||
834 | switch (axp20x->variant) { | |
d8d79f8f MS |
835 | case AXP152_ID: |
836 | axp20x->nr_cells = ARRAY_SIZE(axp152_cells); | |
837 | axp20x->cells = axp152_cells; | |
838 | axp20x->regmap_cfg = &axp152_regmap_config; | |
839 | axp20x->regmap_irq_chip = &axp152_regmap_irq_chip; | |
840 | break; | |
af7e9069 JP |
841 | case AXP202_ID: |
842 | case AXP209_ID: | |
843 | axp20x->nr_cells = ARRAY_SIZE(axp20x_cells); | |
844 | axp20x->cells = axp20x_cells; | |
845 | axp20x->regmap_cfg = &axp20x_regmap_config; | |
846 | axp20x->regmap_irq_chip = &axp20x_regmap_irq_chip; | |
847 | break; | |
f05be589 | 848 | case AXP221_ID: |
4c650561 QS |
849 | axp20x->nr_cells = ARRAY_SIZE(axp221_cells); |
850 | axp20x->cells = axp221_cells; | |
851 | axp20x->regmap_cfg = &axp22x_regmap_config; | |
852 | axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip; | |
853 | break; | |
02071f0f | 854 | case AXP223_ID: |
4c650561 QS |
855 | axp20x->nr_cells = ARRAY_SIZE(axp223_cells); |
856 | axp20x->cells = axp223_cells; | |
f05be589 BB |
857 | axp20x->regmap_cfg = &axp22x_regmap_config; |
858 | axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip; | |
859 | break; | |
af7e9069 JP |
860 | case AXP288_ID: |
861 | axp20x->cells = axp288_cells; | |
862 | axp20x->nr_cells = ARRAY_SIZE(axp288_cells); | |
863 | axp20x->regmap_cfg = &axp288_regmap_config; | |
864 | axp20x->regmap_irq_chip = &axp288_regmap_irq_chip; | |
0a5454c9 | 865 | axp20x->irq_flags = IRQF_TRIGGER_LOW; |
af7e9069 | 866 | break; |
8824ee85 CYT |
867 | case AXP806_ID: |
868 | axp20x->nr_cells = ARRAY_SIZE(axp806_cells); | |
869 | axp20x->cells = axp806_cells; | |
870 | axp20x->regmap_cfg = &axp806_regmap_config; | |
871 | axp20x->regmap_irq_chip = &axp806_regmap_irq_chip; | |
872 | break; | |
20147f0d CYT |
873 | case AXP809_ID: |
874 | axp20x->nr_cells = ARRAY_SIZE(axp809_cells); | |
875 | axp20x->cells = axp809_cells; | |
876 | axp20x->regmap_cfg = &axp22x_regmap_config; | |
877 | axp20x->regmap_irq_chip = &axp809_regmap_irq_chip; | |
878 | break; | |
af7e9069 JP |
879 | default: |
880 | dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant); | |
881 | return -EINVAL; | |
882 | } | |
883 | dev_info(dev, "AXP20x variant %s found\n", | |
2260a453 | 884 | axp20x_model_names[axp20x->variant]); |
af7e9069 JP |
885 | |
886 | return 0; | |
887 | } | |
4fd41151 | 888 | EXPORT_SYMBOL(axp20x_match_device); |
af7e9069 | 889 | |
4fd41151 | 890 | int axp20x_device_probe(struct axp20x_dev *axp20x) |
cfb61a41 | 891 | { |
cfb61a41 CC |
892 | int ret; |
893 | ||
696f0b3f CYT |
894 | /* |
895 | * The AXP806 supports either master/standalone or slave mode. | |
896 | * Slave mode allows sharing the serial bus, even with multiple | |
897 | * AXP806 which all have the same hardware address. | |
898 | * | |
899 | * This is done with extra "serial interface address extension", | |
900 | * or AXP806_BUS_ADDR_EXT, and "register address extension", or | |
901 | * AXP806_REG_ADDR_EXT, registers. The former is read-only, with | |
902 | * 1 bit customizable at the factory, and 1 bit depending on the | |
903 | * state of an external pin. The latter is writable. The device | |
904 | * will only respond to operations to its other registers when | |
905 | * the these device addressing bits (in the upper 4 bits of the | |
906 | * registers) match. | |
907 | * | |
c0369698 RIL |
908 | * By default we support an AXP806 chained to an AXP809 in slave |
909 | * mode. Boards which use an AXP806 in master mode can set the | |
910 | * property "x-powers,master-mode" to override the default. | |
696f0b3f | 911 | */ |
c0369698 RIL |
912 | if (axp20x->variant == AXP806_ID) { |
913 | if (of_property_read_bool(axp20x->dev->of_node, | |
914 | "x-powers,master-mode")) | |
915 | regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT, | |
916 | AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE); | |
917 | else | |
918 | regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT, | |
919 | AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE); | |
920 | } | |
696f0b3f | 921 | |
4fd41151 | 922 | ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq, |
0a5454c9 HG |
923 | IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags, |
924 | -1, axp20x->regmap_irq_chip, &axp20x->regmap_irqc); | |
cfb61a41 | 925 | if (ret) { |
4fd41151 | 926 | dev_err(axp20x->dev, "failed to add irq chip: %d\n", ret); |
cfb61a41 CC |
927 | return ret; |
928 | } | |
929 | ||
af7e9069 | 930 | ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells, |
2260a453 | 931 | axp20x->nr_cells, NULL, 0, NULL); |
cfb61a41 CC |
932 | |
933 | if (ret) { | |
4fd41151 CYT |
934 | dev_err(axp20x->dev, "failed to add MFD devices: %d\n", ret); |
935 | regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc); | |
cfb61a41 CC |
936 | return ret; |
937 | } | |
938 | ||
939 | if (!pm_power_off) { | |
940 | axp20x_pm_power_off = axp20x; | |
941 | pm_power_off = axp20x_power_off; | |
942 | } | |
943 | ||
4fd41151 | 944 | dev_info(axp20x->dev, "AXP20X driver loaded\n"); |
cfb61a41 CC |
945 | |
946 | return 0; | |
947 | } | |
4fd41151 | 948 | EXPORT_SYMBOL(axp20x_device_probe); |
cfb61a41 | 949 | |
4fd41151 | 950 | int axp20x_device_remove(struct axp20x_dev *axp20x) |
cfb61a41 | 951 | { |
cfb61a41 CC |
952 | if (axp20x == axp20x_pm_power_off) { |
953 | axp20x_pm_power_off = NULL; | |
954 | pm_power_off = NULL; | |
955 | } | |
956 | ||
957 | mfd_remove_devices(axp20x->dev); | |
4fd41151 | 958 | regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc); |
cfb61a41 CC |
959 | |
960 | return 0; | |
961 | } | |
4fd41151 | 962 | EXPORT_SYMBOL(axp20x_device_remove); |
cfb61a41 CC |
963 | |
964 | MODULE_DESCRIPTION("PMIC MFD core driver for AXP20X"); | |
965 | MODULE_AUTHOR("Carlo Caione <carlo@caione.org>"); | |
966 | MODULE_LICENSE("GPL"); |