[mirror_ubuntu-hirsute-kernel.git] / drivers / mfd / exynos-lpass.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2015 - 2016 Samsung Electronics Co., Ltd.
 *
 * Authors: Inha Song <ideal.song@samsung.com>
 *          Sylwester Nawrocki <s.nawrocki@samsung.com>
 *
 * Samsung Exynos SoC series Low Power Audio Subsystem driver.
 *
 * This module provides regmap for the Top SFR region and instantiates
 * devices for IP blocks like DMAC, I2S, UART.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/soc/samsung/exynos-regs-pmu.h>
#include <linux/types.h>

/* LPASS Top register definitions */
#define SFR_LPASS_CORE_SW_RESET		0x08
#define  LPASS_SB_SW_RESET		BIT(11)
#define  LPASS_UART_SW_RESET		BIT(10)
#define  LPASS_PCM_SW_RESET		BIT(9)
#define  LPASS_I2S_SW_RESET		BIT(8)
#define  LPASS_WDT1_SW_RESET		BIT(4)
#define  LPASS_WDT0_SW_RESET		BIT(3)
#define  LPASS_TIMER_SW_RESET		BIT(2)
#define  LPASS_MEM_SW_RESET		BIT(1)
#define  LPASS_DMA_SW_RESET		BIT(0)

#define SFR_LPASS_INTR_CA5_MASK		0x48
#define SFR_LPASS_INTR_CPU_MASK		0x58
#define  LPASS_INTR_APM			BIT(9)
#define  LPASS_INTR_MIF			BIT(8)
#define  LPASS_INTR_TIMER		BIT(7)
#define  LPASS_INTR_DMA			BIT(6)
#define  LPASS_INTR_GPIO		BIT(5)
#define  LPASS_INTR_I2S			BIT(4)
#define  LPASS_INTR_PCM			BIT(3)
#define  LPASS_INTR_SLIMBUS		BIT(2)
#define  LPASS_INTR_UART		BIT(1)
#define  LPASS_INTR_SFR			BIT(0)

struct exynos_lpass {
	/* pointer to the LPASS TOP regmap */
	struct regmap *top;
	struct clk *sfr0_clk;
};

static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
{
	unsigned int val = 0;

	regmap_read(lpass->top, SFR_LPASS_CORE_SW_RESET, &val);

	val &= ~mask;
	regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);

	usleep_range(100, 150);

	val |= mask;
	regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);
}

static void exynos_lpass_enable(struct exynos_lpass *lpass)
{
	clk_prepare_enable(lpass->sfr0_clk);

	/* Unmask SFR, DMA and I2S interrupt */
	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK,
		     LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);

	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK,
		     LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S |
		     LPASS_INTR_UART);

	exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET);
	exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET);
	exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET);
	exynos_lpass_core_sw_reset(lpass, LPASS_UART_SW_RESET);
}

static void exynos_lpass_disable(struct exynos_lpass *lpass)
{
	/* Mask any unmasked IP interrupt sources */
	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);

	clk_disable_unprepare(lpass->sfr0_clk);
}

static const struct regmap_config exynos_lpass_reg_conf = {
	.reg_bits	= 32,
	.reg_stride	= 4,
	.val_bits	= 32,
	.max_register	= 0xfc,
	.fast_io	= true,
};

static int exynos_lpass_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct exynos_lpass *lpass;
	void __iomem *base_top;
	struct resource *res;

	lpass = devm_kzalloc(dev, sizeof(*lpass), GFP_KERNEL);
	if (!lpass)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base_top = devm_ioremap_resource(dev, res);
	if (IS_ERR(base_top))
		return PTR_ERR(base_top);

	lpass->sfr0_clk = devm_clk_get(dev, "sfr0_ctrl");
	if (IS_ERR(lpass->sfr0_clk))
		return PTR_ERR(lpass->sfr0_clk);

	lpass->top = regmap_init_mmio(dev, base_top,
					&exynos_lpass_reg_conf);
	if (IS_ERR(lpass->top)) {
		dev_err(dev, "LPASS top regmap initialization failed\n");
		return PTR_ERR(lpass->top);
	}

	platform_set_drvdata(pdev, lpass);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);
	exynos_lpass_enable(lpass);

	return devm_of_platform_populate(dev);
}

static int exynos_lpass_remove(struct platform_device *pdev)
{
	struct exynos_lpass *lpass = platform_get_drvdata(pdev);

	exynos_lpass_disable(lpass);
	pm_runtime_disable(&pdev->dev);
	if (!pm_runtime_status_suspended(&pdev->dev))
		exynos_lpass_disable(lpass);
	regmap_exit(lpass->top);

	return 0;
}

static int __maybe_unused exynos_lpass_suspend(struct device *dev)
{
	struct exynos_lpass *lpass = dev_get_drvdata(dev);

	exynos_lpass_disable(lpass);

	return 0;
}

static int __maybe_unused exynos_lpass_resume(struct device *dev)
{
	struct exynos_lpass *lpass = dev_get_drvdata(dev);

	exynos_lpass_enable(lpass);

	return 0;
}

static const struct dev_pm_ops lpass_pm_ops = {
	SET_RUNTIME_PM_OPS(exynos_lpass_suspend, exynos_lpass_resume, NULL)
	SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
				     pm_runtime_force_resume)
};

static const struct of_device_id exynos_lpass_of_match[] = {
	{ .compatible = "samsung,exynos5433-lpass" },
	{ },
};
MODULE_DEVICE_TABLE(of, exynos_lpass_of_match);

static struct platform_driver exynos_lpass_driver = {
	.driver = {
		.name		= "exynos-lpass",
		.pm		= &lpass_pm_ops,
		.of_match_table	= exynos_lpass_of_match,
	},
	.probe	= exynos_lpass_probe,
	.remove	= exynos_lpass_remove,
};
module_platform_driver(exynos_lpass_driver);

MODULE_DESCRIPTION("Samsung Low Power Audio Subsystem driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
c9fd3ce1	1	// SPDX-License-Identifier: GPL-2.0-only
c695abab SN	2	/*
	3	* Copyright (C) 2015 - 2016 Samsung Electronics Co., Ltd.
	4	*
	5	* Authors: Inha Song <ideal.song@samsung.com>
	6	* Sylwester Nawrocki <s.nawrocki@samsung.com>
	7	*
	8	* Samsung Exynos SoC series Low Power Audio Subsystem driver.
	9	*
	10	* This module provides regmap for the Top SFR region and instantiates
	11	* devices for IP blocks like DMAC, I2S, UART.
c695abab SN	12	*/
c695abab SN	13
8f1be5bd	14	#include <linux/clk.h>
c695abab SN	15	#include <linux/delay.h>
	16	#include <linux/io.h>
	17	#include <linux/module.h>
	18	#include <linux/mfd/syscon.h>
c695abab SN	19	#include <linux/of.h>
	20	#include <linux/of_platform.h>
	21	#include <linux/platform_device.h>
90f44717	22	#include <linux/pm_runtime.h>
c695abab	23	#include <linux/regmap.h>
f7f6c060	24	#include <linux/soc/samsung/exynos-regs-pmu.h>
c695abab SN	25	#include <linux/types.h>
	26
	27	/* LPASS Top register definitions */
	28	#define SFR_LPASS_CORE_SW_RESET 0x08
	29	#define LPASS_SB_SW_RESET BIT(11)
	30	#define LPASS_UART_SW_RESET BIT(10)
	31	#define LPASS_PCM_SW_RESET BIT(9)
	32	#define LPASS_I2S_SW_RESET BIT(8)
	33	#define LPASS_WDT1_SW_RESET BIT(4)
	34	#define LPASS_WDT0_SW_RESET BIT(3)
	35	#define LPASS_TIMER_SW_RESET BIT(2)
	36	#define LPASS_MEM_SW_RESET BIT(1)
	37	#define LPASS_DMA_SW_RESET BIT(0)
	38
	39	#define SFR_LPASS_INTR_CA5_MASK 0x48
	40	#define SFR_LPASS_INTR_CPU_MASK 0x58
	41	#define LPASS_INTR_APM BIT(9)
	42	#define LPASS_INTR_MIF BIT(8)
	43	#define LPASS_INTR_TIMER BIT(7)
	44	#define LPASS_INTR_DMA BIT(6)
	45	#define LPASS_INTR_GPIO BIT(5)
	46	#define LPASS_INTR_I2S BIT(4)
	47	#define LPASS_INTR_PCM BIT(3)
	48	#define LPASS_INTR_SLIMBUS BIT(2)
	49	#define LPASS_INTR_UART BIT(1)
	50	#define LPASS_INTR_SFR BIT(0)
	51
	52	struct exynos_lpass {
c695abab SN	53	/* pointer to the LPASS TOP regmap */
c695abab SN	54	struct regmap *top;
8f1be5bd	55	struct clk *sfr0_clk;
c695abab SN	56	};
	57
	58	static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
	59	{
	60	unsigned int val = 0;
	61
	62	regmap_read(lpass->top, SFR_LPASS_CORE_SW_RESET, &val);
	63
	64	val &= ~mask;
	65	regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);
	66
	67	usleep_range(100, 150);
	68
	69	val \|= mask;
	70	regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);
	71	}
	72
	73	static void exynos_lpass_enable(struct exynos_lpass *lpass)
	74	{
8f1be5bd MS	75	clk_prepare_enable(lpass->sfr0_clk);
8f1be5bd MS	76
c695abab SN	77	/* Unmask SFR, DMA and I2S interrupt */
	78	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK,
	79	LPASS_INTR_SFR \| LPASS_INTR_DMA \| LPASS_INTR_I2S);
	80
	81	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK,
3f2d347e BS	82	LPASS_INTR_SFR \| LPASS_INTR_DMA \| LPASS_INTR_I2S \|
3f2d347e BS	83	LPASS_INTR_UART);
c695abab	84
c695abab SN	85	exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET);
	86	exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET);
	87	exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET);
3f2d347e	88	exynos_lpass_core_sw_reset(lpass, LPASS_UART_SW_RESET);
c695abab SN	89	}
	90
	91	static void exynos_lpass_disable(struct exynos_lpass *lpass)
	92	{
	93	/* Mask any unmasked IP interrupt sources */
	94	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
	95	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
8f1be5bd MS	96
8f1be5bd MS	97	clk_disable_unprepare(lpass->sfr0_clk);
c695abab SN	98	}
	99
	100	static const struct regmap_config exynos_lpass_reg_conf = {
	101	.reg_bits = 32,
	102	.reg_stride = 4,
	103	.val_bits = 32,
	104	.max_register = 0xfc,
	105	.fast_io = true,
	106	};
	107
	108	static int exynos_lpass_probe(struct platform_device *pdev)
	109	{
	110	struct device *dev = &pdev->dev;
	111	struct exynos_lpass *lpass;
	112	void __iomem *base_top;
	113	struct resource *res;
	114
	115	lpass = devm_kzalloc(dev, sizeof(*lpass), GFP_KERNEL);
	116	if (!lpass)
	117	return -ENOMEM;
	118
	119	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	120	base_top = devm_ioremap_resource(dev, res);
	121	if (IS_ERR(base_top))
	122	return PTR_ERR(base_top);
	123
8f1be5bd MS	124	lpass->sfr0_clk = devm_clk_get(dev, "sfr0_ctrl");
	125	if (IS_ERR(lpass->sfr0_clk))
	126	return PTR_ERR(lpass->sfr0_clk);
	127
c695abab SN	128	lpass->top = regmap_init_mmio(dev, base_top,
	129	&exynos_lpass_reg_conf);
	130	if (IS_ERR(lpass->top)) {
	131	dev_err(dev, "LPASS top regmap initialization failed\n");
	132	return PTR_ERR(lpass->top);
	133	}
	134
c695abab	135	platform_set_drvdata(pdev, lpass);
90f44717 MS	136	pm_runtime_set_active(dev);
90f44717 MS	137	pm_runtime_enable(dev);
c695abab SN	138	exynos_lpass_enable(lpass);
c695abab SN	139
11ee55d9	140	return devm_of_platform_populate(dev);
c695abab SN	141	}
c695abab SN	142
c414df12 MS	143	static int exynos_lpass_remove(struct platform_device *pdev)
	144	{
	145	struct exynos_lpass *lpass = platform_get_drvdata(pdev);
	146
	147	exynos_lpass_disable(lpass);
90f44717 MS	148	pm_runtime_disable(&pdev->dev);
	149	if (!pm_runtime_status_suspended(&pdev->dev))
	150	exynos_lpass_disable(lpass);
c414df12 MS	151	regmap_exit(lpass->top);
	152
	153	return 0;
	154	}
	155
22a96b85	156	static int __maybe_unused exynos_lpass_suspend(struct device *dev)
c695abab SN	157	{
	158	struct exynos_lpass *lpass = dev_get_drvdata(dev);
	159
	160	exynos_lpass_disable(lpass);
	161
	162	return 0;
	163	}
	164
22a96b85	165	static int __maybe_unused exynos_lpass_resume(struct device *dev)
c695abab SN	166	{
	167	struct exynos_lpass *lpass = dev_get_drvdata(dev);
	168
	169	exynos_lpass_enable(lpass);
	170
	171	return 0;
	172	}
c695abab	173
90f44717 MS	174	static const struct dev_pm_ops lpass_pm_ops = {
	175	SET_RUNTIME_PM_OPS(exynos_lpass_suspend, exynos_lpass_resume, NULL)
	176	SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
	177	pm_runtime_force_resume)
	178	};
c695abab SN	179
	180	static const struct of_device_id exynos_lpass_of_match[] = {
	181	{ .compatible = "samsung,exynos5433-lpass" },
	182	{ },
	183	};
	184	MODULE_DEVICE_TABLE(of, exynos_lpass_of_match);
	185
	186	static struct platform_driver exynos_lpass_driver = {
	187	.driver = {
	188	.name = "exynos-lpass",
	189	.pm = &lpass_pm_ops,
	190	.of_match_table = exynos_lpass_of_match,
	191	},
	192	.probe = exynos_lpass_probe,
c414df12	193	.remove = exynos_lpass_remove,
c695abab SN	194	};
	195	module_platform_driver(exynos_lpass_driver);
	196
	197	MODULE_DESCRIPTION("Samsung Low Power Audio Subsystem driver");
	198	MODULE_LICENSE("GPL v2");