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1 | /* |
2 | * Copyright (C) 2015 - 2016 Samsung Electronics Co., Ltd. | |
3 | * | |
4 | * Authors: Inha Song <ideal.song@samsung.com> | |
5 | * Sylwester Nawrocki <s.nawrocki@samsung.com> | |
6 | * | |
7 | * Samsung Exynos SoC series Low Power Audio Subsystem driver. | |
8 | * | |
9 | * This module provides regmap for the Top SFR region and instantiates | |
10 | * devices for IP blocks like DMAC, I2S, UART. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 and | |
14 | * only version 2 as published by the Free Software Foundation. | |
15 | */ | |
16 | ||
17 | #include <linux/delay.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/mfd/syscon.h> | |
c695abab SN |
21 | #include <linux/of.h> |
22 | #include <linux/of_platform.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/regmap.h> | |
f7f6c060 | 25 | #include <linux/soc/samsung/exynos-regs-pmu.h> |
c695abab SN |
26 | #include <linux/types.h> |
27 | ||
28 | /* LPASS Top register definitions */ | |
29 | #define SFR_LPASS_CORE_SW_RESET 0x08 | |
30 | #define LPASS_SB_SW_RESET BIT(11) | |
31 | #define LPASS_UART_SW_RESET BIT(10) | |
32 | #define LPASS_PCM_SW_RESET BIT(9) | |
33 | #define LPASS_I2S_SW_RESET BIT(8) | |
34 | #define LPASS_WDT1_SW_RESET BIT(4) | |
35 | #define LPASS_WDT0_SW_RESET BIT(3) | |
36 | #define LPASS_TIMER_SW_RESET BIT(2) | |
37 | #define LPASS_MEM_SW_RESET BIT(1) | |
38 | #define LPASS_DMA_SW_RESET BIT(0) | |
39 | ||
40 | #define SFR_LPASS_INTR_CA5_MASK 0x48 | |
41 | #define SFR_LPASS_INTR_CPU_MASK 0x58 | |
42 | #define LPASS_INTR_APM BIT(9) | |
43 | #define LPASS_INTR_MIF BIT(8) | |
44 | #define LPASS_INTR_TIMER BIT(7) | |
45 | #define LPASS_INTR_DMA BIT(6) | |
46 | #define LPASS_INTR_GPIO BIT(5) | |
47 | #define LPASS_INTR_I2S BIT(4) | |
48 | #define LPASS_INTR_PCM BIT(3) | |
49 | #define LPASS_INTR_SLIMBUS BIT(2) | |
50 | #define LPASS_INTR_UART BIT(1) | |
51 | #define LPASS_INTR_SFR BIT(0) | |
52 | ||
53 | struct exynos_lpass { | |
c695abab SN |
54 | /* pointer to the LPASS TOP regmap */ |
55 | struct regmap *top; | |
56 | }; | |
57 | ||
58 | static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask) | |
59 | { | |
60 | unsigned int val = 0; | |
61 | ||
62 | regmap_read(lpass->top, SFR_LPASS_CORE_SW_RESET, &val); | |
63 | ||
64 | val &= ~mask; | |
65 | regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val); | |
66 | ||
67 | usleep_range(100, 150); | |
68 | ||
69 | val |= mask; | |
70 | regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val); | |
71 | } | |
72 | ||
73 | static void exynos_lpass_enable(struct exynos_lpass *lpass) | |
74 | { | |
75 | /* Unmask SFR, DMA and I2S interrupt */ | |
76 | regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, | |
77 | LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S); | |
78 | ||
79 | regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, | |
80 | LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S); | |
81 | ||
c695abab SN |
82 | exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET); |
83 | exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET); | |
84 | exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET); | |
85 | } | |
86 | ||
87 | static void exynos_lpass_disable(struct exynos_lpass *lpass) | |
88 | { | |
89 | /* Mask any unmasked IP interrupt sources */ | |
90 | regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0); | |
91 | regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0); | |
c695abab SN |
92 | } |
93 | ||
94 | static const struct regmap_config exynos_lpass_reg_conf = { | |
95 | .reg_bits = 32, | |
96 | .reg_stride = 4, | |
97 | .val_bits = 32, | |
98 | .max_register = 0xfc, | |
99 | .fast_io = true, | |
100 | }; | |
101 | ||
102 | static int exynos_lpass_probe(struct platform_device *pdev) | |
103 | { | |
104 | struct device *dev = &pdev->dev; | |
105 | struct exynos_lpass *lpass; | |
106 | void __iomem *base_top; | |
107 | struct resource *res; | |
108 | ||
109 | lpass = devm_kzalloc(dev, sizeof(*lpass), GFP_KERNEL); | |
110 | if (!lpass) | |
111 | return -ENOMEM; | |
112 | ||
113 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
114 | base_top = devm_ioremap_resource(dev, res); | |
115 | if (IS_ERR(base_top)) | |
116 | return PTR_ERR(base_top); | |
117 | ||
118 | lpass->top = regmap_init_mmio(dev, base_top, | |
119 | &exynos_lpass_reg_conf); | |
120 | if (IS_ERR(lpass->top)) { | |
121 | dev_err(dev, "LPASS top regmap initialization failed\n"); | |
122 | return PTR_ERR(lpass->top); | |
123 | } | |
124 | ||
c695abab SN |
125 | platform_set_drvdata(pdev, lpass); |
126 | exynos_lpass_enable(lpass); | |
127 | ||
128 | return of_platform_populate(dev->of_node, NULL, NULL, dev); | |
129 | } | |
130 | ||
22a96b85 | 131 | static int __maybe_unused exynos_lpass_suspend(struct device *dev) |
c695abab SN |
132 | { |
133 | struct exynos_lpass *lpass = dev_get_drvdata(dev); | |
134 | ||
135 | exynos_lpass_disable(lpass); | |
136 | ||
137 | return 0; | |
138 | } | |
139 | ||
22a96b85 | 140 | static int __maybe_unused exynos_lpass_resume(struct device *dev) |
c695abab SN |
141 | { |
142 | struct exynos_lpass *lpass = dev_get_drvdata(dev); | |
143 | ||
144 | exynos_lpass_enable(lpass); | |
145 | ||
146 | return 0; | |
147 | } | |
c695abab SN |
148 | |
149 | static SIMPLE_DEV_PM_OPS(lpass_pm_ops, exynos_lpass_suspend, | |
150 | exynos_lpass_resume); | |
151 | ||
152 | static const struct of_device_id exynos_lpass_of_match[] = { | |
153 | { .compatible = "samsung,exynos5433-lpass" }, | |
154 | { }, | |
155 | }; | |
156 | MODULE_DEVICE_TABLE(of, exynos_lpass_of_match); | |
157 | ||
158 | static struct platform_driver exynos_lpass_driver = { | |
159 | .driver = { | |
160 | .name = "exynos-lpass", | |
161 | .pm = &lpass_pm_ops, | |
162 | .of_match_table = exynos_lpass_of_match, | |
163 | }, | |
164 | .probe = exynos_lpass_probe, | |
165 | }; | |
166 | module_platform_driver(exynos_lpass_driver); | |
167 | ||
168 | MODULE_DESCRIPTION("Samsung Low Power Audio Subsystem driver"); | |
169 | MODULE_LICENSE("GPL v2"); |