[mirror_ubuntu-artful-kernel.git] / drivers / mfd / intel_soc_pmic_bxtwc.c

/*
 * MFD core driver for Intel Broxton Whiskey Cove PMIC
 *
 * Copyright (C) 2015 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <linux/module.h>
#include <linux/acpi.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/mfd/intel_bxtwc.h>
#include <asm/intel_pmc_ipc.h>

/* PMIC device registers */
#define REG_ADDR_MASK		0xFF00
#define REG_ADDR_SHIFT		8
#define REG_OFFSET_MASK		0xFF

/* Interrupt Status Registers */
#define BXTWC_IRQLVL1		0x4E02
#define BXTWC_PWRBTNIRQ		0x4E03

#define BXTWC_THRM0IRQ		0x4E04
#define BXTWC_THRM1IRQ		0x4E05
#define BXTWC_THRM2IRQ		0x4E06
#define BXTWC_BCUIRQ		0x4E07
#define BXTWC_ADCIRQ		0x4E08
#define BXTWC_CHGR0IRQ		0x4E09
#define BXTWC_CHGR1IRQ		0x4E0A
#define BXTWC_GPIOIRQ0		0x4E0B
#define BXTWC_GPIOIRQ1		0x4E0C
#define BXTWC_CRITIRQ		0x4E0D
#define BXTWC_TMUIRQ		0x4FB6

/* Interrupt MASK Registers */
#define BXTWC_MIRQLVL1		0x4E0E
#define BXTWC_MPWRTNIRQ		0x4E0F

#define BXTWC_MIRQLVL1_MCHGR	BIT(5)

#define BXTWC_MTHRM0IRQ		0x4E12
#define BXTWC_MTHRM1IRQ		0x4E13
#define BXTWC_MTHRM2IRQ		0x4E14
#define BXTWC_MBCUIRQ		0x4E15
#define BXTWC_MADCIRQ		0x4E16
#define BXTWC_MCHGR0IRQ		0x4E17
#define BXTWC_MCHGR1IRQ		0x4E18
#define BXTWC_MGPIO0IRQ		0x4E19
#define BXTWC_MGPIO1IRQ		0x4E1A
#define BXTWC_MCRITIRQ		0x4E1B
#define BXTWC_MTMUIRQ		0x4FB7

/* Whiskey Cove PMIC share same ACPI ID between different platforms */
#define BROXTON_PMIC_WC_HRV	4

/* Manage in two IRQ chips since mask registers are not consecutive */
enum bxtwc_irqs {
	/* Level 1 */
	BXTWC_PWRBTN_LVL1_IRQ = 0,
	BXTWC_TMU_LVL1_IRQ,
	BXTWC_THRM_LVL1_IRQ,
	BXTWC_BCU_LVL1_IRQ,
	BXTWC_ADC_LVL1_IRQ,
	BXTWC_CHGR_LVL1_IRQ,
	BXTWC_GPIO_LVL1_IRQ,
	BXTWC_CRIT_LVL1_IRQ,

	/* Level 2 */
	BXTWC_PWRBTN_IRQ,
};

enum bxtwc_irqs_level2 {
	/* Level 2 */
	BXTWC_THRM0_IRQ = 0,
	BXTWC_THRM1_IRQ,
	BXTWC_THRM2_IRQ,
	BXTWC_BCU_IRQ,
	BXTWC_ADC_IRQ,
	BXTWC_USBC_IRQ,
	BXTWC_CHGR0_IRQ,
	BXTWC_CHGR1_IRQ,
	BXTWC_GPIO0_IRQ,
	BXTWC_GPIO1_IRQ,
	BXTWC_CRIT_IRQ,
	BXTWC_TMU_IRQ,
};

static const struct regmap_irq bxtwc_regmap_irqs[] = {
	REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)),
	REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)),
	REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)),
	REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)),
	REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)),
	REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)),
	REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)),
	REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)),
	REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 1, 0x03),
};

static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
	REGMAP_IRQ_REG(BXTWC_THRM0_IRQ, 0, 0xff),
	REGMAP_IRQ_REG(BXTWC_THRM1_IRQ, 1, 0xbf),
	REGMAP_IRQ_REG(BXTWC_THRM2_IRQ, 2, 0xff),
	REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 3, 0x1f),
	REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 4, 0xff),
	REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 5, BIT(5)),
	REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 5, 0x1f),
	REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 6, 0x1f),
	REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 7, 0xff),
	REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 8, 0x3f),
	REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 9, 0x03),
};

static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
	REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
};

static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
	.name = "bxtwc_irq_chip",
	.status_base = BXTWC_IRQLVL1,
	.mask_base = BXTWC_MIRQLVL1,
	.irqs = bxtwc_regmap_irqs,
	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs),
	.num_regs = 2,
};

static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = {
	.name = "bxtwc_irq_chip_level2",
	.status_base = BXTWC_THRM0IRQ,
	.mask_base = BXTWC_MTHRM0IRQ,
	.irqs = bxtwc_regmap_irqs_level2,
	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_level2),
	.num_regs = 10,
};

static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
	.name = "bxtwc_irq_chip_tmu",
	.status_base = BXTWC_TMUIRQ,
	.mask_base = BXTWC_MTMUIRQ,
	.irqs = bxtwc_regmap_irqs_tmu,
	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_tmu),
	.num_regs = 1,
};

static struct resource gpio_resources[] = {
	DEFINE_RES_IRQ_NAMED(BXTWC_GPIO0_IRQ, "GPIO0"),
	DEFINE_RES_IRQ_NAMED(BXTWC_GPIO1_IRQ, "GPIO1"),
};

static struct resource adc_resources[] = {
	DEFINE_RES_IRQ_NAMED(BXTWC_ADC_IRQ, "ADC"),
};

static struct resource usbc_resources[] = {
	DEFINE_RES_IRQ(BXTWC_USBC_IRQ),
};

static struct resource charger_resources[] = {
	DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "CHARGER"),
	DEFINE_RES_IRQ_NAMED(BXTWC_CHGR1_IRQ, "CHARGER1"),
};

static struct resource thermal_resources[] = {
	DEFINE_RES_IRQ(BXTWC_THRM0_IRQ),
	DEFINE_RES_IRQ(BXTWC_THRM1_IRQ),
	DEFINE_RES_IRQ(BXTWC_THRM2_IRQ),
};

static struct resource bcu_resources[] = {
	DEFINE_RES_IRQ_NAMED(BXTWC_BCU_IRQ, "BCU"),
};

static struct resource tmu_resources[] = {
	DEFINE_RES_IRQ_NAMED(BXTWC_TMU_IRQ, "TMU"),
};

static struct mfd_cell bxt_wc_dev[] = {
	{
		.name = "bxt_wcove_gpadc",
		.num_resources = ARRAY_SIZE(adc_resources),
		.resources = adc_resources,
	},
	{
		.name = "bxt_wcove_thermal",
		.num_resources = ARRAY_SIZE(thermal_resources),
		.resources = thermal_resources,
	},
	{
		.name = "bxt_wcove_usbc",
		.num_resources = ARRAY_SIZE(usbc_resources),
		.resources = usbc_resources,
	},
	{
		.name = "bxt_wcove_ext_charger",
		.num_resources = ARRAY_SIZE(charger_resources),
		.resources = charger_resources,
	},
	{
		.name = "bxt_wcove_bcu",
		.num_resources = ARRAY_SIZE(bcu_resources),
		.resources = bcu_resources,
	},
	{
		.name = "bxt_wcove_tmu",
		.num_resources = ARRAY_SIZE(tmu_resources),
		.resources = tmu_resources,
	},

	{
		.name = "bxt_wcove_gpio",
		.num_resources = ARRAY_SIZE(gpio_resources),
		.resources = gpio_resources,
	},
	{
		.name = "bxt_wcove_region",
	},
};

static int regmap_ipc_byte_reg_read(void *context, unsigned int reg,
				    unsigned int *val)
{
	int ret;
	int i2c_addr;
	u8 ipc_in[2];
	u8 ipc_out[4];
	struct intel_soc_pmic *pmic = context;

	if (reg & REG_ADDR_MASK)
		i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
	else {
		i2c_addr = BXTWC_DEVICE1_ADDR;
		if (!i2c_addr) {
			dev_err(pmic->dev, "I2C address not set\n");
			return -EINVAL;
		}
	}
	reg &= REG_OFFSET_MASK;

	ipc_in[0] = reg;
	ipc_in[1] = i2c_addr;
	ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
			PMC_IPC_PMIC_ACCESS_READ,
			ipc_in, sizeof(ipc_in), (u32 *)ipc_out, 1);
	if (ret) {
		dev_err(pmic->dev, "Failed to read from PMIC\n");
		return ret;
	}
	*val = ipc_out[0];

	return 0;
}

static int regmap_ipc_byte_reg_write(void *context, unsigned int reg,
				       unsigned int val)
{
	int ret;
	int i2c_addr;
	u8 ipc_in[3];
	struct intel_soc_pmic *pmic = context;

	if (reg & REG_ADDR_MASK)
		i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
	else {
		i2c_addr = BXTWC_DEVICE1_ADDR;
		if (!i2c_addr) {
			dev_err(pmic->dev, "I2C address not set\n");
			return -EINVAL;
		}
	}
	reg &= REG_OFFSET_MASK;

	ipc_in[0] = reg;
	ipc_in[1] = i2c_addr;
	ipc_in[2] = val;
	ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
			PMC_IPC_PMIC_ACCESS_WRITE,
			ipc_in, sizeof(ipc_in), NULL, 0);
	if (ret) {
		dev_err(pmic->dev, "Failed to write to PMIC\n");
		return ret;
	}

	return 0;
}

/* sysfs interfaces to r/w PMIC registers, required by initial script */
static unsigned long bxtwc_reg_addr;
static ssize_t bxtwc_reg_show(struct device *dev,
		struct device_attribute *attr, char *buf)
{
	return sprintf(buf, "0x%lx\n", bxtwc_reg_addr);
}

static ssize_t bxtwc_reg_store(struct device *dev,
	struct device_attribute *attr, const char *buf, size_t count)
{
	if (kstrtoul(buf, 0, &bxtwc_reg_addr)) {
		dev_err(dev, "Invalid register address\n");
		return -EINVAL;
	}
	return (ssize_t)count;
}

static ssize_t bxtwc_val_show(struct device *dev,
		struct device_attribute *attr, char *buf)
{
	int ret;
	unsigned int val;
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val);
	if (ret < 0) {
		dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr);
		return -EIO;
	}

	return sprintf(buf, "0x%02x\n", val);
}

static ssize_t bxtwc_val_store(struct device *dev,
	struct device_attribute *attr, const char *buf, size_t count)
{
	int ret;
	unsigned int val;
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	ret = kstrtouint(buf, 0, &val);
	if (ret)
		return ret;

	ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val);
	if (ret) {
		dev_err(dev, "Failed to write value 0x%02x to address 0x%lx",
			val, bxtwc_reg_addr);
		return -EIO;
	}
	return count;
}

static DEVICE_ATTR(addr, S_IWUSR | S_IRUSR, bxtwc_reg_show, bxtwc_reg_store);
static DEVICE_ATTR(val, S_IWUSR | S_IRUSR, bxtwc_val_show, bxtwc_val_store);
static struct attribute *bxtwc_attrs[] = {
	&dev_attr_addr.attr,
	&dev_attr_val.attr,
	NULL
};

static const struct attribute_group bxtwc_group = {
	.attrs = bxtwc_attrs,
};

static const struct regmap_config bxtwc_regmap_config = {
	.reg_bits = 16,
	.val_bits = 8,
	.reg_write = regmap_ipc_byte_reg_write,
	.reg_read = regmap_ipc_byte_reg_read,
};

static int bxtwc_probe(struct platform_device *pdev)
{
	int ret;
	acpi_handle handle;
	acpi_status status;
	unsigned long long hrv;
	struct intel_soc_pmic *pmic;

	handle = ACPI_HANDLE(&pdev->dev);
	status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv);
	if (ACPI_FAILURE(status)) {
		dev_err(&pdev->dev, "Failed to get PMIC hardware revision\n");
		return -ENODEV;
	}
	if (hrv != BROXTON_PMIC_WC_HRV) {
		dev_err(&pdev->dev, "Invalid PMIC hardware revision: %llu\n",
			hrv);
		return -ENODEV;
	}

	pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
	if (!pmic)
		return -ENOMEM;

	ret = platform_get_irq(pdev, 0);
	if (ret < 0) {
		dev_err(&pdev->dev, "Invalid IRQ\n");
		return ret;
	}
	pmic->irq = ret;

	dev_set_drvdata(&pdev->dev, pmic);
	pmic->dev = &pdev->dev;

	pmic->regmap = devm_regmap_init(&pdev->dev, NULL, pmic,
					&bxtwc_regmap_config);
	if (IS_ERR(pmic->regmap)) {
		ret = PTR_ERR(pmic->regmap);
		dev_err(&pdev->dev, "Failed to initialise regmap: %d\n", ret);
		return ret;
	}

	ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
				  IRQF_ONESHOT | IRQF_SHARED,
				  0, &bxtwc_regmap_irq_chip,
				  &pmic->irq_chip_data);
	if (ret) {
		dev_err(&pdev->dev, "Failed to add IRQ chip\n");
		return ret;
	}

	ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
				  IRQF_ONESHOT | IRQF_SHARED,
				  0, &bxtwc_regmap_irq_chip_level2,
				  &pmic->irq_chip_data_level2);
	if (ret) {
		dev_err(&pdev->dev, "Failed to add secondary IRQ chip\n");
		goto err_irq_chip_level2;
	}

	ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
				  IRQF_ONESHOT | IRQF_SHARED,
				  0, &bxtwc_regmap_irq_chip_tmu,
				  &pmic->irq_chip_data_tmu);
	if (ret) {
		dev_err(&pdev->dev, "Failed to add TMU IRQ chip\n");
		goto err_irq_chip_tmu;
	}

	ret = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
			      ARRAY_SIZE(bxt_wc_dev), NULL, 0,
			      NULL);
	if (ret) {
		dev_err(&pdev->dev, "Failed to add devices\n");
		goto err_mfd;
	}

	ret = sysfs_create_group(&pdev->dev.kobj, &bxtwc_group);
	if (ret) {
		dev_err(&pdev->dev, "Failed to create sysfs group %d\n", ret);
		goto err_sysfs;
	}

	/*
	 * There is known hw bug. Upon reset BIT 5 of register
	 * BXTWC_CHGR_LVL1_IRQ is 0 which is the expected value. However,
	 * later it's set to 1(masked) automatically by hardware. So we
	 * have the software workaround here to unmaksed it in order to let
	 * charger interrutp work.
	 */
	regmap_update_bits(pmic->regmap, BXTWC_MIRQLVL1,
				BXTWC_MIRQLVL1_MCHGR, 0);

	return 0;

err_sysfs:
	mfd_remove_devices(&pdev->dev);
err_mfd:
	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_tmu);
err_irq_chip_tmu:
	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
err_irq_chip_level2:
	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);

	return ret;
}

static int bxtwc_remove(struct platform_device *pdev)
{
	struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);

	sysfs_remove_group(&pdev->dev.kobj, &bxtwc_group);
	mfd_remove_devices(&pdev->dev);
	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_tmu);

	return 0;
}

static void bxtwc_shutdown(struct platform_device *pdev)
{
	struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);

	disable_irq(pmic->irq);
}

#ifdef CONFIG_PM_SLEEP
static int bxtwc_suspend(struct device *dev)
{
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	disable_irq(pmic->irq);

	return 0;
}

static int bxtwc_resume(struct device *dev)
{
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	enable_irq(pmic->irq);
	return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume);

static const struct acpi_device_id bxtwc_acpi_ids[] = {
	{ "INT34D3", },
	{ }
};
MODULE_DEVICE_TABLE(acpi, bxtwc_acpi_ids);

static struct platform_driver bxtwc_driver = {
	.probe = bxtwc_probe,
	.remove	= bxtwc_remove,
	.shutdown = bxtwc_shutdown,
	.driver	= {
		.name	= "BXTWC PMIC",
		.pm     = &bxtwc_pm_ops,
		.acpi_match_table = ACPI_PTR(bxtwc_acpi_ids),
	},
};

module_platform_driver(bxtwc_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Qipeng Zha<qipeng.zha@intel.com>");
Commit	Line	Data
39d047c0 QZ	1	/*
	2	* MFD core driver for Intel Broxton Whiskey Cove PMIC
	3	*
	4	* Copyright (C) 2015 Intel Corporation. All rights reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/acpi.h>
	18	#include <linux/err.h>
	19	#include <linux/delay.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/kernel.h>
	22	#include <linux/mfd/core.h>
	23	#include <linux/mfd/intel_bxtwc.h>
	24	#include <asm/intel_pmc_ipc.h>
	25
	26	/* PMIC device registers */
	27	#define REG_ADDR_MASK 0xFF00
	28	#define REG_ADDR_SHIFT 8
	29	#define REG_OFFSET_MASK 0xFF
	30
	31	/* Interrupt Status Registers */
	32	#define BXTWC_IRQLVL1 0x4E02
	33	#define BXTWC_PWRBTNIRQ 0x4E03
	34
	35	#define BXTWC_THRM0IRQ 0x4E04
	36	#define BXTWC_THRM1IRQ 0x4E05
	37	#define BXTWC_THRM2IRQ 0x4E06
	38	#define BXTWC_BCUIRQ 0x4E07
	39	#define BXTWC_ADCIRQ 0x4E08
	40	#define BXTWC_CHGR0IRQ 0x4E09
	41	#define BXTWC_CHGR1IRQ 0x4E0A
	42	#define BXTWC_GPIOIRQ0 0x4E0B
	43	#define BXTWC_GPIOIRQ1 0x4E0C
	44	#define BXTWC_CRITIRQ 0x4E0D
957ae509	45	#define BXTWC_TMUIRQ 0x4FB6
39d047c0 QZ	46
	47	/* Interrupt MASK Registers */
	48	#define BXTWC_MIRQLVL1 0x4E0E
	49	#define BXTWC_MPWRTNIRQ 0x4E0F
	50
9c6235c8 BG	51	#define BXTWC_MIRQLVL1_MCHGR BIT(5)
9c6235c8 BG	52
39d047c0 QZ	53	#define BXTWC_MTHRM0IRQ 0x4E12
	54	#define BXTWC_MTHRM1IRQ 0x4E13
	55	#define BXTWC_MTHRM2IRQ 0x4E14
	56	#define BXTWC_MBCUIRQ 0x4E15
	57	#define BXTWC_MADCIRQ 0x4E16
	58	#define BXTWC_MCHGR0IRQ 0x4E17
	59	#define BXTWC_MCHGR1IRQ 0x4E18
	60	#define BXTWC_MGPIO0IRQ 0x4E19
	61	#define BXTWC_MGPIO1IRQ 0x4E1A
	62	#define BXTWC_MCRITIRQ 0x4E1B
957ae509	63	#define BXTWC_MTMUIRQ 0x4FB7
39d047c0 QZ	64
	65	/* Whiskey Cove PMIC share same ACPI ID between different platforms */
	66	#define BROXTON_PMIC_WC_HRV 4
	67
	68	/* Manage in two IRQ chips since mask registers are not consecutive */
	69	enum bxtwc_irqs {
	70	/* Level 1 */
	71	BXTWC_PWRBTN_LVL1_IRQ = 0,
	72	BXTWC_TMU_LVL1_IRQ,
	73	BXTWC_THRM_LVL1_IRQ,
	74	BXTWC_BCU_LVL1_IRQ,
	75	BXTWC_ADC_LVL1_IRQ,
	76	BXTWC_CHGR_LVL1_IRQ,
	77	BXTWC_GPIO_LVL1_IRQ,
	78	BXTWC_CRIT_LVL1_IRQ,
	79
	80	/* Level 2 */
	81	BXTWC_PWRBTN_IRQ,
	82	};
	83
	84	enum bxtwc_irqs_level2 {
	85	/* Level 2 */
	86	BXTWC_THRM0_IRQ = 0,
	87	BXTWC_THRM1_IRQ,
	88	BXTWC_THRM2_IRQ,
	89	BXTWC_BCU_IRQ,
	90	BXTWC_ADC_IRQ,
96007020	91	BXTWC_USBC_IRQ,
39d047c0 QZ	92	BXTWC_CHGR0_IRQ,
	93	BXTWC_CHGR1_IRQ,
	94	BXTWC_GPIO0_IRQ,
	95	BXTWC_GPIO1_IRQ,
	96	BXTWC_CRIT_IRQ,
957ae509	97	BXTWC_TMU_IRQ,
39d047c0 QZ	98	};
	99
	100	static const struct regmap_irq bxtwc_regmap_irqs[] = {
	101	REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)),
	102	REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)),
	103	REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)),
	104	REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)),
	105	REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)),
	106	REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)),
	107	REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)),
	108	REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)),
	109	REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 1, 0x03),
	110	};
	111
	112	static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
	113	REGMAP_IRQ_REG(BXTWC_THRM0_IRQ, 0, 0xff),
	114	REGMAP_IRQ_REG(BXTWC_THRM1_IRQ, 1, 0xbf),
	115	REGMAP_IRQ_REG(BXTWC_THRM2_IRQ, 2, 0xff),
	116	REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 3, 0x1f),
	117	REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 4, 0xff),
96007020 HK	118	REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 5, BIT(5)),
96007020 HK	119	REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 5, 0x1f),
39d047c0 QZ	120	REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 6, 0x1f),
	121	REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 7, 0xff),
	122	REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 8, 0x3f),
	123	REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 9, 0x03),
	124	};
	125
957ae509 NB	126	static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
	127	REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
	128	};
	129
39d047c0 QZ	130	static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
	131	.name = "bxtwc_irq_chip",
	132	.status_base = BXTWC_IRQLVL1,
	133	.mask_base = BXTWC_MIRQLVL1,
	134	.irqs = bxtwc_regmap_irqs,
	135	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs),
	136	.num_regs = 2,
	137	};
	138
	139	static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = {
	140	.name = "bxtwc_irq_chip_level2",
	141	.status_base = BXTWC_THRM0IRQ,
	142	.mask_base = BXTWC_MTHRM0IRQ,
	143	.irqs = bxtwc_regmap_irqs_level2,
	144	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_level2),
	145	.num_regs = 10,
	146	};
	147
957ae509 NB	148	static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
	149	.name = "bxtwc_irq_chip_tmu",
	150	.status_base = BXTWC_TMUIRQ,
	151	.mask_base = BXTWC_MTMUIRQ,
	152	.irqs = bxtwc_regmap_irqs_tmu,
	153	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_tmu),
	154	.num_regs = 1,
	155	};
	156
39d047c0 QZ	157	static struct resource gpio_resources[] = {
	158	DEFINE_RES_IRQ_NAMED(BXTWC_GPIO0_IRQ, "GPIO0"),
	159	DEFINE_RES_IRQ_NAMED(BXTWC_GPIO1_IRQ, "GPIO1"),
	160	};
	161
	162	static struct resource adc_resources[] = {
	163	DEFINE_RES_IRQ_NAMED(BXTWC_ADC_IRQ, "ADC"),
	164	};
	165
9c6235c8	166	static struct resource usbc_resources[] = {
96007020	167	DEFINE_RES_IRQ(BXTWC_USBC_IRQ),
9c6235c8 BG	168	};
9c6235c8 BG	169
39d047c0 QZ	170	static struct resource charger_resources[] = {
	171	DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "CHARGER"),
	172	DEFINE_RES_IRQ_NAMED(BXTWC_CHGR1_IRQ, "CHARGER1"),
	173	};
	174
	175	static struct resource thermal_resources[] = {
	176	DEFINE_RES_IRQ(BXTWC_THRM0_IRQ),
	177	DEFINE_RES_IRQ(BXTWC_THRM1_IRQ),
	178	DEFINE_RES_IRQ(BXTWC_THRM2_IRQ),
	179	};
	180
	181	static struct resource bcu_resources[] = {
	182	DEFINE_RES_IRQ_NAMED(BXTWC_BCU_IRQ, "BCU"),
	183	};
	184
957ae509 NB	185	static struct resource tmu_resources[] = {
	186	DEFINE_RES_IRQ_NAMED(BXTWC_TMU_IRQ, "TMU"),
	187	};
	188
39d047c0 QZ	189	static struct mfd_cell bxt_wc_dev[] = {
	190	{
	191	.name = "bxt_wcove_gpadc",
	192	.num_resources = ARRAY_SIZE(adc_resources),
	193	.resources = adc_resources,
	194	},
	195	{
	196	.name = "bxt_wcove_thermal",
	197	.num_resources = ARRAY_SIZE(thermal_resources),
	198	.resources = thermal_resources,
	199	},
9c6235c8 BG	200	{
	201	.name = "bxt_wcove_usbc",
	202	.num_resources = ARRAY_SIZE(usbc_resources),
	203	.resources = usbc_resources,
	204	},
39d047c0 QZ	205	{
	206	.name = "bxt_wcove_ext_charger",
	207	.num_resources = ARRAY_SIZE(charger_resources),
	208	.resources = charger_resources,
	209	},
	210	{
	211	.name = "bxt_wcove_bcu",
	212	.num_resources = ARRAY_SIZE(bcu_resources),
	213	.resources = bcu_resources,
	214	},
957ae509 NB	215	{
	216	.name = "bxt_wcove_tmu",
	217	.num_resources = ARRAY_SIZE(tmu_resources),
	218	.resources = tmu_resources,
	219	},
	220
39d047c0 QZ	221	{
	222	.name = "bxt_wcove_gpio",
	223	.num_resources = ARRAY_SIZE(gpio_resources),
	224	.resources = gpio_resources,
	225	},
	226	{
	227	.name = "bxt_wcove_region",
	228	},
	229	};
	230
	231	static int regmap_ipc_byte_reg_read(void *context, unsigned int reg,
	232	unsigned int *val)
	233	{
	234	int ret;
	235	int i2c_addr;
	236	u8 ipc_in[2];
	237	u8 ipc_out[4];
	238	struct intel_soc_pmic *pmic = context;
	239
	240	if (reg & REG_ADDR_MASK)
	241	i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
	242	else {
	243	i2c_addr = BXTWC_DEVICE1_ADDR;
	244	if (!i2c_addr) {
	245	dev_err(pmic->dev, "I2C address not set\n");
	246	return -EINVAL;
	247	}
	248	}
	249	reg &= REG_OFFSET_MASK;
	250
	251	ipc_in[0] = reg;
	252	ipc_in[1] = i2c_addr;
	253	ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
	254	PMC_IPC_PMIC_ACCESS_READ,
	255	ipc_in, sizeof(ipc_in), (u32 *)ipc_out, 1);
	256	if (ret) {
	257	dev_err(pmic->dev, "Failed to read from PMIC\n");
	258	return ret;
	259	}
	260	*val = ipc_out[0];
	261
	262	return 0;
	263	}
	264
	265	static int regmap_ipc_byte_reg_write(void *context, unsigned int reg,
	266	unsigned int val)
	267	{
	268	int ret;
	269	int i2c_addr;
	270	u8 ipc_in[3];
	271	struct intel_soc_pmic *pmic = context;
	272
	273	if (reg & REG_ADDR_MASK)
	274	i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
	275	else {
	276	i2c_addr = BXTWC_DEVICE1_ADDR;
	277	if (!i2c_addr) {
	278	dev_err(pmic->dev, "I2C address not set\n");
	279	return -EINVAL;
	280	}
	281	}
	282	reg &= REG_OFFSET_MASK;
	283
	284	ipc_in[0] = reg;
285	ipc_in[1] = i2c_addr;
286	ipc_in[2] = val;
287	ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
288	PMC_IPC_PMIC_ACCESS_WRITE,
289	ipc_in, sizeof(ipc_in), NULL, 0);
290	if (ret) {
291	dev_err(pmic->dev, "Failed to write to PMIC\n");
292	return ret;
293	}
294
295	return 0;
296	}
297
298	/* sysfs interfaces to r/w PMIC registers, required by initial script */
299	static unsigned long bxtwc_reg_addr;
300	static ssize_t bxtwc_reg_show(struct device *dev,
301	struct device_attribute attr, char buf)
302	{
303	return sprintf(buf, "0x%lx\n", bxtwc_reg_addr);
304	}
305
306	static ssize_t bxtwc_reg_store(struct device *dev,
307	struct device_attribute attr, const char buf, size_t count)
308	{
309	if (kstrtoul(buf, 0, &bxtwc_reg_addr)) {
310	dev_err(dev, "Invalid register address\n");
311	return -EINVAL;
312	}
313	return (ssize_t)count;
314	}
315
316	static ssize_t bxtwc_val_show(struct device *dev,
317	struct device_attribute attr, char buf)
318	{
319	int ret;
320	unsigned int val;
321	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
322
323	ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val);
324	if (ret < 0) {
325	dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr);
326	return -EIO;
327	}
328
329	return sprintf(buf, "0x%02x\n", val);
330	}
331
332	static ssize_t bxtwc_val_store(struct device *dev,
333	struct device_attribute attr, const char buf, size_t count)
334	{
335	int ret;
336	unsigned int val;
337	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
338
f3a654c5 DC	339	ret = kstrtouint(buf, 0, &val);
	340	if (ret)
	341	return ret;
39d047c0 QZ	342
	343	ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val);
	344	if (ret) {
	345	dev_err(dev, "Failed to write value 0x%02x to address 0x%lx",
	346	val, bxtwc_reg_addr);
	347	return -EIO;
	348	}
	349	return count;
	350	}
	351
	352	static DEVICE_ATTR(addr, S_IWUSR \| S_IRUSR, bxtwc_reg_show, bxtwc_reg_store);
	353	static DEVICE_ATTR(val, S_IWUSR \| S_IRUSR, bxtwc_val_show, bxtwc_val_store);
	354	static struct attribute *bxtwc_attrs[] = {
	355	&dev_attr_addr.attr,
	356	&dev_attr_val.attr,
	357	NULL
	358	};
	359
	360	static const struct attribute_group bxtwc_group = {
	361	.attrs = bxtwc_attrs,
	362	};
	363
	364	static const struct regmap_config bxtwc_regmap_config = {
	365	.reg_bits = 16,
	366	.val_bits = 8,
	367	.reg_write = regmap_ipc_byte_reg_write,
	368	.reg_read = regmap_ipc_byte_reg_read,
	369	};
	370
	371	static int bxtwc_probe(struct platform_device *pdev)
	372	{
	373	int ret;
	374	acpi_handle handle;
	375	acpi_status status;
	376	unsigned long long hrv;
	377	struct intel_soc_pmic *pmic;
	378
	379	handle = ACPI_HANDLE(&pdev->dev);
	380	status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv);
	381	if (ACPI_FAILURE(status)) {
	382	dev_err(&pdev->dev, "Failed to get PMIC hardware revision\n");
	383	return -ENODEV;
	384	}
	385	if (hrv != BROXTON_PMIC_WC_HRV) {
	386	dev_err(&pdev->dev, "Invalid PMIC hardware revision: %llu\n",
	387	hrv);
	388	return -ENODEV;
	389	}
	390
	391	pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
	392	if (!pmic)
	393	return -ENOMEM;
	394
	395	ret = platform_get_irq(pdev, 0);
	396	if (ret < 0) {
	397	dev_err(&pdev->dev, "Invalid IRQ\n");
	398	return ret;
	399	}
	400	pmic->irq = ret;
	401
	402	dev_set_drvdata(&pdev->dev, pmic);
	403	pmic->dev = &pdev->dev;
	404
	405	pmic->regmap = devm_regmap_init(&pdev->dev, NULL, pmic,
406	&bxtwc_regmap_config);
407	if (IS_ERR(pmic->regmap)) {
408	ret = PTR_ERR(pmic->regmap);
409	dev_err(&pdev->dev, "Failed to initialise regmap: %d\n", ret);
410	return ret;
411	}
412
413	ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
414	IRQF_ONESHOT \| IRQF_SHARED,
415	0, &bxtwc_regmap_irq_chip,
416	&pmic->irq_chip_data);
417	if (ret) {
418	dev_err(&pdev->dev, "Failed to add IRQ chip\n");
419	return ret;
420	}
421
422	ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
423	IRQF_ONESHOT \| IRQF_SHARED,
424	0, &bxtwc_regmap_irq_chip_level2,
425	&pmic->irq_chip_data_level2);
426	if (ret) {
427	dev_err(&pdev->dev, "Failed to add secondary IRQ chip\n");
428	goto err_irq_chip_level2;
429	}
430
957ae509 NB	431	ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
	432	IRQF_ONESHOT \| IRQF_SHARED,
	433	0, &bxtwc_regmap_irq_chip_tmu,
	434	&pmic->irq_chip_data_tmu);
	435	if (ret) {
	436	dev_err(&pdev->dev, "Failed to add TMU IRQ chip\n");
	437	goto err_irq_chip_tmu;
	438	}
	439
39d047c0 QZ	440	ret = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
	441	ARRAY_SIZE(bxt_wc_dev), NULL, 0,
	442	NULL);
	443	if (ret) {
	444	dev_err(&pdev->dev, "Failed to add devices\n");
	445	goto err_mfd;
	446	}
	447
	448	ret = sysfs_create_group(&pdev->dev.kobj, &bxtwc_group);
	449	if (ret) {
	450	dev_err(&pdev->dev, "Failed to create sysfs group %d\n", ret);
	451	goto err_sysfs;
	452	}
	453
9c6235c8 BG	454	/*
	455	* There is known hw bug. Upon reset BIT 5 of register
	456	* BXTWC_CHGR_LVL1_IRQ is 0 which is the expected value. However,
	457	* later it's set to 1(masked) automatically by hardware. So we
	458	* have the software workaround here to unmaksed it in order to let
	459	* charger interrutp work.
	460	*/
	461	regmap_update_bits(pmic->regmap, BXTWC_MIRQLVL1,
	462	BXTWC_MIRQLVL1_MCHGR, 0);
	463
39d047c0 QZ	464	return 0;
	465
	466	err_sysfs:
	467	mfd_remove_devices(&pdev->dev);
	468	err_mfd:
957ae509 NB	469	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_tmu);
957ae509 NB	470	err_irq_chip_tmu:
39d047c0 QZ	471	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
	472	err_irq_chip_level2:
	473	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
	474
	475	return ret;
	476	}
	477
	478	static int bxtwc_remove(struct platform_device *pdev)
	479	{
	480	struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);
	481
	482	sysfs_remove_group(&pdev->dev.kobj, &bxtwc_group);
	483	mfd_remove_devices(&pdev->dev);
	484	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
	485	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
957ae509	486	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_tmu);
39d047c0 QZ	487
	488	return 0;
	489	}
	490
	491	static void bxtwc_shutdown(struct platform_device *pdev)
	492	{
	493	struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);
	494
	495	disable_irq(pmic->irq);
	496	}
	497
	498	#ifdef CONFIG_PM_SLEEP
	499	static int bxtwc_suspend(struct device *dev)
	500	{
	501	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
	502
	503	disable_irq(pmic->irq);
	504
	505	return 0;
	506	}
	507
	508	static int bxtwc_resume(struct device *dev)
	509	{
	510	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
	511
	512	enable_irq(pmic->irq);
	513	return 0;
	514	}
	515	#endif
	516	static SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume);
	517
	518	static const struct acpi_device_id bxtwc_acpi_ids[] = {
	519	{ "INT34D3", },
	520	{ }
	521	};
f57576e7	522	MODULE_DEVICE_TABLE(acpi, bxtwc_acpi_ids);
39d047c0 QZ	523
	524	static struct platform_driver bxtwc_driver = {
	525	.probe = bxtwc_probe,
	526	.remove = bxtwc_remove,
	527	.shutdown = bxtwc_shutdown,
	528	.driver = {
	529	.name = "BXTWC PMIC",
	530	.pm = &bxtwc_pm_ops,
	531	.acpi_match_table = ACPI_PTR(bxtwc_acpi_ids),
	532	},
	533	};
	534
	535	module_platform_driver(bxtwc_driver);
	536
	537	MODULE_LICENSE("GPL v2");
	538	MODULE_AUTHOR("Qipeng Zha<qipeng.zha@intel.com>");