[mirror_ubuntu-bionic-kernel.git] / drivers / mfd / intel_soc_pmic_bxtwc.c

/*
 * MFD core driver for Intel Broxton Whiskey Cove PMIC
 *
 * Copyright (C) 2015 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <linux/module.h>
#include <linux/acpi.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/mfd/intel_soc_pmic_bxtwc.h>
#include <asm/intel_pmc_ipc.h>

/* PMIC device registers */
#define REG_ADDR_MASK		0xFF00
#define REG_ADDR_SHIFT		8
#define REG_OFFSET_MASK		0xFF

/* Interrupt Status Registers */
#define BXTWC_IRQLVL1		0x4E02
#define BXTWC_PWRBTNIRQ		0x4E03

#define BXTWC_THRM0IRQ		0x4E04
#define BXTWC_THRM1IRQ		0x4E05
#define BXTWC_THRM2IRQ		0x4E06
#define BXTWC_BCUIRQ		0x4E07
#define BXTWC_ADCIRQ		0x4E08
#define BXTWC_CHGR0IRQ		0x4E09
#define BXTWC_CHGR1IRQ		0x4E0A
#define BXTWC_GPIOIRQ0		0x4E0B
#define BXTWC_GPIOIRQ1		0x4E0C
#define BXTWC_CRITIRQ		0x4E0D
#define BXTWC_TMUIRQ		0x4FB6

/* Interrupt MASK Registers */
#define BXTWC_MIRQLVL1		0x4E0E
#define BXTWC_MPWRTNIRQ		0x4E0F

#define BXTWC_MIRQLVL1_MCHGR	BIT(5)

#define BXTWC_MTHRM0IRQ		0x4E12
#define BXTWC_MTHRM1IRQ		0x4E13
#define BXTWC_MTHRM2IRQ		0x4E14
#define BXTWC_MBCUIRQ		0x4E15
#define BXTWC_MADCIRQ		0x4E16
#define BXTWC_MCHGR0IRQ		0x4E17
#define BXTWC_MCHGR1IRQ		0x4E18
#define BXTWC_MGPIO0IRQ		0x4E19
#define BXTWC_MGPIO1IRQ		0x4E1A
#define BXTWC_MCRITIRQ		0x4E1B
#define BXTWC_MTMUIRQ		0x4FB7

/* Whiskey Cove PMIC share same ACPI ID between different platforms */
#define BROXTON_PMIC_WC_HRV	4

/* Manage in two IRQ chips since mask registers are not consecutive */
enum bxtwc_irqs {
	/* Level 1 */
	BXTWC_PWRBTN_LVL1_IRQ = 0,
	BXTWC_TMU_LVL1_IRQ,
	BXTWC_THRM_LVL1_IRQ,
	BXTWC_BCU_LVL1_IRQ,
	BXTWC_ADC_LVL1_IRQ,
	BXTWC_CHGR_LVL1_IRQ,
	BXTWC_GPIO_LVL1_IRQ,
	BXTWC_CRIT_LVL1_IRQ,

	/* Level 2 */
	BXTWC_PWRBTN_IRQ,
};

enum bxtwc_irqs_level2 {
	/* Level 2 */
	BXTWC_THRM0_IRQ = 0,
	BXTWC_THRM1_IRQ,
	BXTWC_THRM2_IRQ,
	BXTWC_BCU_IRQ,
	BXTWC_ADC_IRQ,
	BXTWC_USBC_IRQ,
	BXTWC_CHGR0_IRQ,
	BXTWC_CHGR1_IRQ,
	BXTWC_GPIO0_IRQ,
	BXTWC_GPIO1_IRQ,
	BXTWC_CRIT_IRQ,
	BXTWC_TMU_IRQ,
};

static const struct regmap_irq bxtwc_regmap_irqs[] = {
	REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)),
	REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)),
	REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)),
	REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)),
	REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)),
	REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)),
	REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)),
	REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)),
	REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 1, 0x03),
};

static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
	REGMAP_IRQ_REG(BXTWC_THRM0_IRQ, 0, 0xff),
	REGMAP_IRQ_REG(BXTWC_THRM1_IRQ, 1, 0xbf),
	REGMAP_IRQ_REG(BXTWC_THRM2_IRQ, 2, 0xff),
	REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 3, 0x1f),
	REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 4, 0xff),
	REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 5, BIT(5)),
	REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 5, 0x1f),
	REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 6, 0x1f),
	REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 7, 0xff),
	REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 8, 0x3f),
	REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 9, 0x03),
};

static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
	REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
};

static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
	.name = "bxtwc_irq_chip",
	.status_base = BXTWC_IRQLVL1,
	.mask_base = BXTWC_MIRQLVL1,
	.irqs = bxtwc_regmap_irqs,
	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs),
	.num_regs = 2,
};

static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = {
	.name = "bxtwc_irq_chip_level2",
	.status_base = BXTWC_THRM0IRQ,
	.mask_base = BXTWC_MTHRM0IRQ,
	.irqs = bxtwc_regmap_irqs_level2,
	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_level2),
	.num_regs = 10,
};

static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
	.name = "bxtwc_irq_chip_tmu",
	.status_base = BXTWC_TMUIRQ,
	.mask_base = BXTWC_MTMUIRQ,
	.irqs = bxtwc_regmap_irqs_tmu,
	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_tmu),
	.num_regs = 1,
};

static struct resource gpio_resources[] = {
	DEFINE_RES_IRQ_NAMED(BXTWC_GPIO0_IRQ, "GPIO0"),
	DEFINE_RES_IRQ_NAMED(BXTWC_GPIO1_IRQ, "GPIO1"),
};

static struct resource adc_resources[] = {
	DEFINE_RES_IRQ_NAMED(BXTWC_ADC_IRQ, "ADC"),
};

static struct resource usbc_resources[] = {
	DEFINE_RES_IRQ(BXTWC_USBC_IRQ),
};

static struct resource charger_resources[] = {
	DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "CHARGER"),
	DEFINE_RES_IRQ_NAMED(BXTWC_CHGR1_IRQ, "CHARGER1"),
};

static struct resource thermal_resources[] = {
	DEFINE_RES_IRQ(BXTWC_THRM0_IRQ),
	DEFINE_RES_IRQ(BXTWC_THRM1_IRQ),
	DEFINE_RES_IRQ(BXTWC_THRM2_IRQ),
};

static struct resource bcu_resources[] = {
	DEFINE_RES_IRQ_NAMED(BXTWC_BCU_IRQ, "BCU"),
};

static struct resource tmu_resources[] = {
	DEFINE_RES_IRQ_NAMED(BXTWC_TMU_IRQ, "TMU"),
};

static struct mfd_cell bxt_wc_dev[] = {
	{
		.name = "bxt_wcove_gpadc",
		.num_resources = ARRAY_SIZE(adc_resources),
		.resources = adc_resources,
	},
	{
		.name = "bxt_wcove_thermal",
		.num_resources = ARRAY_SIZE(thermal_resources),
		.resources = thermal_resources,
	},
	{
		.name = "bxt_wcove_usbc",
		.num_resources = ARRAY_SIZE(usbc_resources),
		.resources = usbc_resources,
	},
	{
		.name = "bxt_wcove_ext_charger",
		.num_resources = ARRAY_SIZE(charger_resources),
		.resources = charger_resources,
	},
	{
		.name = "bxt_wcove_bcu",
		.num_resources = ARRAY_SIZE(bcu_resources),
		.resources = bcu_resources,
	},
	{
		.name = "bxt_wcove_tmu",
		.num_resources = ARRAY_SIZE(tmu_resources),
		.resources = tmu_resources,
	},

	{
		.name = "bxt_wcove_gpio",
		.num_resources = ARRAY_SIZE(gpio_resources),
		.resources = gpio_resources,
	},
	{
		.name = "bxt_wcove_region",
	},
};

static int regmap_ipc_byte_reg_read(void *context, unsigned int reg,
				    unsigned int *val)
{
	int ret;
	int i2c_addr;
	u8 ipc_in[2];
	u8 ipc_out[4];
	struct intel_soc_pmic *pmic = context;

	if (!pmic)
		return -EINVAL;

	if (reg & REG_ADDR_MASK)
		i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
	else
		i2c_addr = BXTWC_DEVICE1_ADDR;

	reg &= REG_OFFSET_MASK;

	ipc_in[0] = reg;
	ipc_in[1] = i2c_addr;
	ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
			PMC_IPC_PMIC_ACCESS_READ,
			ipc_in, sizeof(ipc_in), (u32 *)ipc_out, 1);
	if (ret) {
		dev_err(pmic->dev, "Failed to read from PMIC\n");
		return ret;
	}
	*val = ipc_out[0];

	return 0;
}

static int regmap_ipc_byte_reg_write(void *context, unsigned int reg,
				       unsigned int val)
{
	int ret;
	int i2c_addr;
	u8 ipc_in[3];
	struct intel_soc_pmic *pmic = context;

	if (!pmic)
		return -EINVAL;

	if (reg & REG_ADDR_MASK)
		i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
	else
		i2c_addr = BXTWC_DEVICE1_ADDR;

	reg &= REG_OFFSET_MASK;

	ipc_in[0] = reg;
	ipc_in[1] = i2c_addr;
	ipc_in[2] = val;
	ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
			PMC_IPC_PMIC_ACCESS_WRITE,
			ipc_in, sizeof(ipc_in), NULL, 0);
	if (ret) {
		dev_err(pmic->dev, "Failed to write to PMIC\n");
		return ret;
	}

	return 0;
}

/* sysfs interfaces to r/w PMIC registers, required by initial script */
static unsigned long bxtwc_reg_addr;
static ssize_t bxtwc_reg_show(struct device *dev,
		struct device_attribute *attr, char *buf)
{
	return sprintf(buf, "0x%lx\n", bxtwc_reg_addr);
}

static ssize_t bxtwc_reg_store(struct device *dev,
	struct device_attribute *attr, const char *buf, size_t count)
{
	if (kstrtoul(buf, 0, &bxtwc_reg_addr)) {
		dev_err(dev, "Invalid register address\n");
		return -EINVAL;
	}
	return (ssize_t)count;
}

static ssize_t bxtwc_val_show(struct device *dev,
		struct device_attribute *attr, char *buf)
{
	int ret;
	unsigned int val;
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val);
	if (ret < 0) {
		dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr);
		return -EIO;
	}

	return sprintf(buf, "0x%02x\n", val);
}

static ssize_t bxtwc_val_store(struct device *dev,
	struct device_attribute *attr, const char *buf, size_t count)
{
	int ret;
	unsigned int val;
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	ret = kstrtouint(buf, 0, &val);
	if (ret)
		return ret;

	ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val);
	if (ret) {
		dev_err(dev, "Failed to write value 0x%02x to address 0x%lx",
			val, bxtwc_reg_addr);
		return -EIO;
	}
	return count;
}

static DEVICE_ATTR(addr, S_IWUSR | S_IRUSR, bxtwc_reg_show, bxtwc_reg_store);
static DEVICE_ATTR(val, S_IWUSR | S_IRUSR, bxtwc_val_show, bxtwc_val_store);
static struct attribute *bxtwc_attrs[] = {
	&dev_attr_addr.attr,
	&dev_attr_val.attr,
	NULL
};

static const struct attribute_group bxtwc_group = {
	.attrs = bxtwc_attrs,
};

static const struct regmap_config bxtwc_regmap_config = {
	.reg_bits = 16,
	.val_bits = 8,
	.reg_write = regmap_ipc_byte_reg_write,
	.reg_read = regmap_ipc_byte_reg_read,
};

static int bxtwc_probe(struct platform_device *pdev)
{
	int ret;
	acpi_handle handle;
	acpi_status status;
	unsigned long long hrv;
	struct intel_soc_pmic *pmic;

	handle = ACPI_HANDLE(&pdev->dev);
	status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv);
	if (ACPI_FAILURE(status)) {
		dev_err(&pdev->dev, "Failed to get PMIC hardware revision\n");
		return -ENODEV;
	}
	if (hrv != BROXTON_PMIC_WC_HRV) {
		dev_err(&pdev->dev, "Invalid PMIC hardware revision: %llu\n",
			hrv);
		return -ENODEV;
	}

	pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
	if (!pmic)
		return -ENOMEM;

	ret = platform_get_irq(pdev, 0);
	if (ret < 0) {
		dev_err(&pdev->dev, "Invalid IRQ\n");
		return ret;
	}
	pmic->irq = ret;

	dev_set_drvdata(&pdev->dev, pmic);
	pmic->dev = &pdev->dev;

	pmic->regmap = devm_regmap_init(&pdev->dev, NULL, pmic,
					&bxtwc_regmap_config);
	if (IS_ERR(pmic->regmap)) {
		ret = PTR_ERR(pmic->regmap);
		dev_err(&pdev->dev, "Failed to initialise regmap: %d\n", ret);
		return ret;
	}

	ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
				  IRQF_ONESHOT | IRQF_SHARED,
				  0, &bxtwc_regmap_irq_chip,
				  &pmic->irq_chip_data);
	if (ret) {
		dev_err(&pdev->dev, "Failed to add IRQ chip\n");
		return ret;
	}

	ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
				  IRQF_ONESHOT | IRQF_SHARED,
				  0, &bxtwc_regmap_irq_chip_level2,
				  &pmic->irq_chip_data_level2);
	if (ret) {
		dev_err(&pdev->dev, "Failed to add secondary IRQ chip\n");
		goto err_irq_chip_level2;
	}

	ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
				  IRQF_ONESHOT | IRQF_SHARED,
				  0, &bxtwc_regmap_irq_chip_tmu,
				  &pmic->irq_chip_data_tmu);
	if (ret) {
		dev_err(&pdev->dev, "Failed to add TMU IRQ chip\n");
		goto err_irq_chip_tmu;
	}

	ret = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
			      ARRAY_SIZE(bxt_wc_dev), NULL, 0,
			      NULL);
	if (ret) {
		dev_err(&pdev->dev, "Failed to add devices\n");
		goto err_mfd;
	}

	ret = sysfs_create_group(&pdev->dev.kobj, &bxtwc_group);
	if (ret) {
		dev_err(&pdev->dev, "Failed to create sysfs group %d\n", ret);
		goto err_sysfs;
	}

	/*
	 * There is known hw bug. Upon reset BIT 5 of register
	 * BXTWC_CHGR_LVL1_IRQ is 0 which is the expected value. However,
	 * later it's set to 1(masked) automatically by hardware. So we
	 * have the software workaround here to unmaksed it in order to let
	 * charger interrutp work.
	 */
	regmap_update_bits(pmic->regmap, BXTWC_MIRQLVL1,
				BXTWC_MIRQLVL1_MCHGR, 0);

	return 0;

err_sysfs:
	mfd_remove_devices(&pdev->dev);
err_mfd:
	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_tmu);
err_irq_chip_tmu:
	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
err_irq_chip_level2:
	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);

	return ret;
}

static int bxtwc_remove(struct platform_device *pdev)
{
	struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);

	sysfs_remove_group(&pdev->dev.kobj, &bxtwc_group);
	mfd_remove_devices(&pdev->dev);
	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_tmu);

	return 0;
}

static void bxtwc_shutdown(struct platform_device *pdev)
{
	struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);

	disable_irq(pmic->irq);
}

#ifdef CONFIG_PM_SLEEP
static int bxtwc_suspend(struct device *dev)
{
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	disable_irq(pmic->irq);

	return 0;
}

static int bxtwc_resume(struct device *dev)
{
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	enable_irq(pmic->irq);
	return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume);

static const struct acpi_device_id bxtwc_acpi_ids[] = {
	{ "INT34D3", },
	{ }
};
MODULE_DEVICE_TABLE(acpi, bxtwc_acpi_ids);

static struct platform_driver bxtwc_driver = {
	.probe = bxtwc_probe,
	.remove	= bxtwc_remove,
	.shutdown = bxtwc_shutdown,
	.driver	= {
		.name	= "BXTWC PMIC",
		.pm     = &bxtwc_pm_ops,
		.acpi_match_table = ACPI_PTR(bxtwc_acpi_ids),
	},
};

module_platform_driver(bxtwc_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Qipeng Zha<qipeng.zha@intel.com>");
Commit	Line	Data
39d047c0 QZ	1	/*
	2	* MFD core driver for Intel Broxton Whiskey Cove PMIC
	3	*
	4	* Copyright (C) 2015 Intel Corporation. All rights reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/acpi.h>
	18	#include <linux/err.h>
	19	#include <linux/delay.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/kernel.h>
	22	#include <linux/mfd/core.h>
f1e34ad8	23	#include <linux/mfd/intel_soc_pmic.h>
0c227c51	24	#include <linux/mfd/intel_soc_pmic_bxtwc.h>
39d047c0 QZ	25	#include <asm/intel_pmc_ipc.h>
	26
	27	/* PMIC device registers */
	28	#define REG_ADDR_MASK 0xFF00
	29	#define REG_ADDR_SHIFT 8
	30	#define REG_OFFSET_MASK 0xFF
	31
	32	/* Interrupt Status Registers */
	33	#define BXTWC_IRQLVL1 0x4E02
	34	#define BXTWC_PWRBTNIRQ 0x4E03
	35
	36	#define BXTWC_THRM0IRQ 0x4E04
	37	#define BXTWC_THRM1IRQ 0x4E05
	38	#define BXTWC_THRM2IRQ 0x4E06
	39	#define BXTWC_BCUIRQ 0x4E07
	40	#define BXTWC_ADCIRQ 0x4E08
	41	#define BXTWC_CHGR0IRQ 0x4E09
	42	#define BXTWC_CHGR1IRQ 0x4E0A
	43	#define BXTWC_GPIOIRQ0 0x4E0B
	44	#define BXTWC_GPIOIRQ1 0x4E0C
	45	#define BXTWC_CRITIRQ 0x4E0D
957ae509	46	#define BXTWC_TMUIRQ 0x4FB6
39d047c0 QZ	47
	48	/* Interrupt MASK Registers */
	49	#define BXTWC_MIRQLVL1 0x4E0E
	50	#define BXTWC_MPWRTNIRQ 0x4E0F
	51
9c6235c8 BG	52	#define BXTWC_MIRQLVL1_MCHGR BIT(5)
9c6235c8 BG	53
39d047c0 QZ	54	#define BXTWC_MTHRM0IRQ 0x4E12
	55	#define BXTWC_MTHRM1IRQ 0x4E13
	56	#define BXTWC_MTHRM2IRQ 0x4E14
	57	#define BXTWC_MBCUIRQ 0x4E15
	58	#define BXTWC_MADCIRQ 0x4E16
	59	#define BXTWC_MCHGR0IRQ 0x4E17
	60	#define BXTWC_MCHGR1IRQ 0x4E18
	61	#define BXTWC_MGPIO0IRQ 0x4E19
	62	#define BXTWC_MGPIO1IRQ 0x4E1A
	63	#define BXTWC_MCRITIRQ 0x4E1B
957ae509	64	#define BXTWC_MTMUIRQ 0x4FB7
39d047c0 QZ	65
	66	/* Whiskey Cove PMIC share same ACPI ID between different platforms */
	67	#define BROXTON_PMIC_WC_HRV 4
	68
	69	/* Manage in two IRQ chips since mask registers are not consecutive */
	70	enum bxtwc_irqs {
	71	/* Level 1 */
	72	BXTWC_PWRBTN_LVL1_IRQ = 0,
	73	BXTWC_TMU_LVL1_IRQ,
	74	BXTWC_THRM_LVL1_IRQ,
	75	BXTWC_BCU_LVL1_IRQ,
	76	BXTWC_ADC_LVL1_IRQ,
	77	BXTWC_CHGR_LVL1_IRQ,
	78	BXTWC_GPIO_LVL1_IRQ,
	79	BXTWC_CRIT_LVL1_IRQ,
	80
	81	/* Level 2 */
	82	BXTWC_PWRBTN_IRQ,
	83	};
	84
	85	enum bxtwc_irqs_level2 {
	86	/* Level 2 */
	87	BXTWC_THRM0_IRQ = 0,
	88	BXTWC_THRM1_IRQ,
	89	BXTWC_THRM2_IRQ,
	90	BXTWC_BCU_IRQ,
	91	BXTWC_ADC_IRQ,
96007020	92	BXTWC_USBC_IRQ,
39d047c0 QZ	93	BXTWC_CHGR0_IRQ,
	94	BXTWC_CHGR1_IRQ,
	95	BXTWC_GPIO0_IRQ,
	96	BXTWC_GPIO1_IRQ,
	97	BXTWC_CRIT_IRQ,
957ae509	98	BXTWC_TMU_IRQ,
39d047c0 QZ	99	};
	100
	101	static const struct regmap_irq bxtwc_regmap_irqs[] = {
	102	REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)),
	103	REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)),
	104	REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)),
	105	REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)),
	106	REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)),
	107	REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)),
	108	REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)),
	109	REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)),
	110	REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 1, 0x03),
	111	};
	112
	113	static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
	114	REGMAP_IRQ_REG(BXTWC_THRM0_IRQ, 0, 0xff),
	115	REGMAP_IRQ_REG(BXTWC_THRM1_IRQ, 1, 0xbf),
	116	REGMAP_IRQ_REG(BXTWC_THRM2_IRQ, 2, 0xff),
	117	REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 3, 0x1f),
	118	REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 4, 0xff),
96007020 HK	119	REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 5, BIT(5)),
96007020 HK	120	REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 5, 0x1f),
39d047c0 QZ	121	REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 6, 0x1f),
	122	REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 7, 0xff),
	123	REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 8, 0x3f),
	124	REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 9, 0x03),
	125	};
	126
957ae509 NB	127	static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
	128	REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
	129	};
	130
39d047c0 QZ	131	static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
	132	.name = "bxtwc_irq_chip",
	133	.status_base = BXTWC_IRQLVL1,
	134	.mask_base = BXTWC_MIRQLVL1,
	135	.irqs = bxtwc_regmap_irqs,
	136	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs),
	137	.num_regs = 2,
	138	};
	139
	140	static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = {
	141	.name = "bxtwc_irq_chip_level2",
	142	.status_base = BXTWC_THRM0IRQ,
	143	.mask_base = BXTWC_MTHRM0IRQ,
	144	.irqs = bxtwc_regmap_irqs_level2,
	145	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_level2),
	146	.num_regs = 10,
	147	};
	148
957ae509 NB	149	static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
	150	.name = "bxtwc_irq_chip_tmu",
	151	.status_base = BXTWC_TMUIRQ,
	152	.mask_base = BXTWC_MTMUIRQ,
	153	.irqs = bxtwc_regmap_irqs_tmu,
	154	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_tmu),
	155	.num_regs = 1,
	156	};
	157
39d047c0 QZ	158	static struct resource gpio_resources[] = {
	159	DEFINE_RES_IRQ_NAMED(BXTWC_GPIO0_IRQ, "GPIO0"),
	160	DEFINE_RES_IRQ_NAMED(BXTWC_GPIO1_IRQ, "GPIO1"),
	161	};
	162
	163	static struct resource adc_resources[] = {
	164	DEFINE_RES_IRQ_NAMED(BXTWC_ADC_IRQ, "ADC"),
	165	};
	166
9c6235c8	167	static struct resource usbc_resources[] = {
96007020	168	DEFINE_RES_IRQ(BXTWC_USBC_IRQ),
9c6235c8 BG	169	};
9c6235c8 BG	170
39d047c0 QZ	171	static struct resource charger_resources[] = {
	172	DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "CHARGER"),
	173	DEFINE_RES_IRQ_NAMED(BXTWC_CHGR1_IRQ, "CHARGER1"),
	174	};
	175
	176	static struct resource thermal_resources[] = {
	177	DEFINE_RES_IRQ(BXTWC_THRM0_IRQ),
	178	DEFINE_RES_IRQ(BXTWC_THRM1_IRQ),
	179	DEFINE_RES_IRQ(BXTWC_THRM2_IRQ),
	180	};
	181
	182	static struct resource bcu_resources[] = {
	183	DEFINE_RES_IRQ_NAMED(BXTWC_BCU_IRQ, "BCU"),
	184	};
	185
957ae509 NB	186	static struct resource tmu_resources[] = {
	187	DEFINE_RES_IRQ_NAMED(BXTWC_TMU_IRQ, "TMU"),
	188	};
	189
39d047c0 QZ	190	static struct mfd_cell bxt_wc_dev[] = {
	191	{
	192	.name = "bxt_wcove_gpadc",
	193	.num_resources = ARRAY_SIZE(adc_resources),
	194	.resources = adc_resources,
	195	},
	196	{
	197	.name = "bxt_wcove_thermal",
	198	.num_resources = ARRAY_SIZE(thermal_resources),
	199	.resources = thermal_resources,
	200	},
9c6235c8 BG	201	{
	202	.name = "bxt_wcove_usbc",
	203	.num_resources = ARRAY_SIZE(usbc_resources),
	204	.resources = usbc_resources,
	205	},
39d047c0 QZ	206	{
	207	.name = "bxt_wcove_ext_charger",
	208	.num_resources = ARRAY_SIZE(charger_resources),
	209	.resources = charger_resources,
	210	},
	211	{
	212	.name = "bxt_wcove_bcu",
	213	.num_resources = ARRAY_SIZE(bcu_resources),
	214	.resources = bcu_resources,
	215	},
957ae509 NB	216	{
	217	.name = "bxt_wcove_tmu",
	218	.num_resources = ARRAY_SIZE(tmu_resources),
	219	.resources = tmu_resources,
	220	},
	221
39d047c0 QZ	222	{
	223	.name = "bxt_wcove_gpio",
	224	.num_resources = ARRAY_SIZE(gpio_resources),
	225	.resources = gpio_resources,
	226	},
	227	{
	228	.name = "bxt_wcove_region",
	229	},
	230	};
	231
	232	static int regmap_ipc_byte_reg_read(void *context, unsigned int reg,
	233	unsigned int *val)
	234	{
	235	int ret;
	236	int i2c_addr;
	237	u8 ipc_in[2];
	238	u8 ipc_out[4];
	239	struct intel_soc_pmic *pmic = context;
	240
b4ccc4d2 KS	241	if (!pmic)
	242	return -EINVAL;
	243
39d047c0 QZ	244	if (reg & REG_ADDR_MASK)
39d047c0 QZ	245	i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
b4ccc4d2	246	else
39d047c0	247	i2c_addr = BXTWC_DEVICE1_ADDR;
b4ccc4d2	248
39d047c0 QZ	249	reg &= REG_OFFSET_MASK;
	250
	251	ipc_in[0] = reg;
	252	ipc_in[1] = i2c_addr;
	253	ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
	254	PMC_IPC_PMIC_ACCESS_READ,
	255	ipc_in, sizeof(ipc_in), (u32 *)ipc_out, 1);
	256	if (ret) {
	257	dev_err(pmic->dev, "Failed to read from PMIC\n");
	258	return ret;
	259	}
	260	*val = ipc_out[0];
	261
	262	return 0;
	263	}
	264
	265	static int regmap_ipc_byte_reg_write(void *context, unsigned int reg,
	266	unsigned int val)
	267	{
	268	int ret;
	269	int i2c_addr;
	270	u8 ipc_in[3];
	271	struct intel_soc_pmic *pmic = context;
	272
b4ccc4d2 KS	273	if (!pmic)
	274	return -EINVAL;
	275
39d047c0 QZ	276	if (reg & REG_ADDR_MASK)
39d047c0 QZ	277	i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
b4ccc4d2	278	else
39d047c0	279	i2c_addr = BXTWC_DEVICE1_ADDR;
b4ccc4d2	280
39d047c0 QZ	281	reg &= REG_OFFSET_MASK;
	282
	283	ipc_in[0] = reg;
	284	ipc_in[1] = i2c_addr;
	285	ipc_in[2] = val;
	286	ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
	287	PMC_IPC_PMIC_ACCESS_WRITE,
	288	ipc_in, sizeof(ipc_in), NULL, 0);
	289	if (ret) {
	290	dev_err(pmic->dev, "Failed to write to PMIC\n");
	291	return ret;
	292	}
	293
	294	return 0;
	295	}
	296
	297	/* sysfs interfaces to r/w PMIC registers, required by initial script */
	298	static unsigned long bxtwc_reg_addr;
	299	static ssize_t bxtwc_reg_show(struct device *dev,
	300	struct device_attribute attr, char buf)
	301	{
	302	return sprintf(buf, "0x%lx\n", bxtwc_reg_addr);
	303	}
	304
	305	static ssize_t bxtwc_reg_store(struct device *dev,
	306	struct device_attribute attr, const char buf, size_t count)
	307	{
	308	if (kstrtoul(buf, 0, &bxtwc_reg_addr)) {
	309	dev_err(dev, "Invalid register address\n");
	310	return -EINVAL;
	311	}
	312	return (ssize_t)count;
	313	}
	314
	315	static ssize_t bxtwc_val_show(struct device *dev,
	316	struct device_attribute attr, char buf)
	317	{
	318	int ret;
	319	unsigned int val;
	320	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
	321
	322	ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val);
	323	if (ret < 0) {
	324	dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr);
	325	return -EIO;
	326	}
	327
	328	return sprintf(buf, "0x%02x\n", val);
	329	}
	330
	331	static ssize_t bxtwc_val_store(struct device *dev,
	332	struct device_attribute attr, const char buf, size_t count)
	333	{
	334	int ret;
	335	unsigned int val;
	336	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
	337
f3a654c5 DC	338	ret = kstrtouint(buf, 0, &val);
	339	if (ret)
	340	return ret;
39d047c0 QZ	341
	342	ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val);
	343	if (ret) {
	344	dev_err(dev, "Failed to write value 0x%02x to address 0x%lx",
	345	val, bxtwc_reg_addr);
	346	return -EIO;
	347	}
	348	return count;
	349	}
	350
	351	static DEVICE_ATTR(addr, S_IWUSR \| S_IRUSR, bxtwc_reg_show, bxtwc_reg_store);
	352	static DEVICE_ATTR(val, S_IWUSR \| S_IRUSR, bxtwc_val_show, bxtwc_val_store);
	353	static struct attribute *bxtwc_attrs[] = {
	354	&dev_attr_addr.attr,
	355	&dev_attr_val.attr,
	356	NULL
	357	};
	358
	359	static const struct attribute_group bxtwc_group = {
	360	.attrs = bxtwc_attrs,
	361	};
	362
	363	static const struct regmap_config bxtwc_regmap_config = {
	364	.reg_bits = 16,
	365	.val_bits = 8,
	366	.reg_write = regmap_ipc_byte_reg_write,
	367	.reg_read = regmap_ipc_byte_reg_read,
	368	};
	369
	370	static int bxtwc_probe(struct platform_device *pdev)
	371	{
	372	int ret;
	373	acpi_handle handle;
	374	acpi_status status;
	375	unsigned long long hrv;
	376	struct intel_soc_pmic *pmic;
	377
	378	handle = ACPI_HANDLE(&pdev->dev);
	379	status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv);
	380	if (ACPI_FAILURE(status)) {
	381	dev_err(&pdev->dev, "Failed to get PMIC hardware revision\n");
	382	return -ENODEV;
	383	}
	384	if (hrv != BROXTON_PMIC_WC_HRV) {
	385	dev_err(&pdev->dev, "Invalid PMIC hardware revision: %llu\n",
	386	hrv);
	387	return -ENODEV;
	388	}
	389
	390	pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
	391	if (!pmic)
	392	return -ENOMEM;
	393
	394	ret = platform_get_irq(pdev, 0);
	395	if (ret < 0) {
	396	dev_err(&pdev->dev, "Invalid IRQ\n");
	397	return ret;
	398	}
	399	pmic->irq = ret;
	400
	401	dev_set_drvdata(&pdev->dev, pmic);
	402	pmic->dev = &pdev->dev;
	403
	404	pmic->regmap = devm_regmap_init(&pdev->dev, NULL, pmic,
405	&bxtwc_regmap_config);
406	if (IS_ERR(pmic->regmap)) {
407	ret = PTR_ERR(pmic->regmap);
408	dev_err(&pdev->dev, "Failed to initialise regmap: %d\n", ret);
409	return ret;
410	}
411
412	ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
413	IRQF_ONESHOT \| IRQF_SHARED,
414	0, &bxtwc_regmap_irq_chip,
415	&pmic->irq_chip_data);
416	if (ret) {
417	dev_err(&pdev->dev, "Failed to add IRQ chip\n");
418	return ret;
419	}
420
421	ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
422	IRQF_ONESHOT \| IRQF_SHARED,
423	0, &bxtwc_regmap_irq_chip_level2,
424	&pmic->irq_chip_data_level2);
425	if (ret) {
426	dev_err(&pdev->dev, "Failed to add secondary IRQ chip\n");
427	goto err_irq_chip_level2;
428	}
429
957ae509 NB	430	ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
	431	IRQF_ONESHOT \| IRQF_SHARED,
	432	0, &bxtwc_regmap_irq_chip_tmu,
	433	&pmic->irq_chip_data_tmu);
	434	if (ret) {
	435	dev_err(&pdev->dev, "Failed to add TMU IRQ chip\n");
	436	goto err_irq_chip_tmu;
	437	}
	438
39d047c0 QZ	439	ret = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
	440	ARRAY_SIZE(bxt_wc_dev), NULL, 0,
	441	NULL);
	442	if (ret) {
	443	dev_err(&pdev->dev, "Failed to add devices\n");
	444	goto err_mfd;
	445	}
	446
	447	ret = sysfs_create_group(&pdev->dev.kobj, &bxtwc_group);
	448	if (ret) {
	449	dev_err(&pdev->dev, "Failed to create sysfs group %d\n", ret);
	450	goto err_sysfs;
	451	}
	452
9c6235c8 BG	453	/*
	454	* There is known hw bug. Upon reset BIT 5 of register
	455	* BXTWC_CHGR_LVL1_IRQ is 0 which is the expected value. However,
	456	* later it's set to 1(masked) automatically by hardware. So we
	457	* have the software workaround here to unmaksed it in order to let
	458	* charger interrutp work.
	459	*/
	460	regmap_update_bits(pmic->regmap, BXTWC_MIRQLVL1,
	461	BXTWC_MIRQLVL1_MCHGR, 0);
	462
39d047c0 QZ	463	return 0;
	464
	465	err_sysfs:
	466	mfd_remove_devices(&pdev->dev);
	467	err_mfd:
957ae509 NB	468	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_tmu);
957ae509 NB	469	err_irq_chip_tmu:
39d047c0 QZ	470	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
	471	err_irq_chip_level2:
	472	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
	473
	474	return ret;
	475	}
	476
	477	static int bxtwc_remove(struct platform_device *pdev)
	478	{
	479	struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);
	480
	481	sysfs_remove_group(&pdev->dev.kobj, &bxtwc_group);
	482	mfd_remove_devices(&pdev->dev);
	483	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
	484	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
957ae509	485	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_tmu);
39d047c0 QZ	486
	487	return 0;
	488	}
	489
	490	static void bxtwc_shutdown(struct platform_device *pdev)
	491	{
	492	struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);
	493
	494	disable_irq(pmic->irq);
	495	}
	496
	497	#ifdef CONFIG_PM_SLEEP
	498	static int bxtwc_suspend(struct device *dev)
	499	{
	500	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
	501
	502	disable_irq(pmic->irq);
	503
	504	return 0;
	505	}
	506
	507	static int bxtwc_resume(struct device *dev)
	508	{
	509	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
	510
	511	enable_irq(pmic->irq);
	512	return 0;
	513	}
	514	#endif
	515	static SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume);
	516
	517	static const struct acpi_device_id bxtwc_acpi_ids[] = {
	518	{ "INT34D3", },
	519	{ }
	520	};
f57576e7	521	MODULE_DEVICE_TABLE(acpi, bxtwc_acpi_ids);
39d047c0 QZ	522
	523	static struct platform_driver bxtwc_driver = {
	524	.probe = bxtwc_probe,
	525	.remove = bxtwc_remove,
	526	.shutdown = bxtwc_shutdown,
	527	.driver = {
	528	.name = "BXTWC PMIC",
	529	.pm = &bxtwc_pm_ops,
	530	.acpi_match_table = ACPI_PTR(bxtwc_acpi_ids),
	531	},
	532	};
	533
	534	module_platform_driver(bxtwc_driver);
	535
	536	MODULE_LICENSE("GPL v2");
	537	MODULE_AUTHOR("Qipeng Zha<qipeng.zha@intel.com>");