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91f4debf LPC |
1 | /* |
2 | * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> | |
3 | * JZ4740 SoC ADC driver | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | * | |
10 | * You should have received a copy of the GNU General Public License along | |
11 | * with this program; if not, write to the Free Software Foundation, Inc., | |
12 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
13 | * | |
14 | * This driver synchronizes access to the JZ4740 ADC core between the | |
15 | * JZ4740 battery and hwmon drivers. | |
16 | */ | |
17 | ||
18 | #include <linux/err.h> | |
fa860403 | 19 | #include <linux/io.h> |
91f4debf LPC |
20 | #include <linux/irq.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/spinlock.h> | |
27 | ||
28 | #include <linux/clk.h> | |
29 | #include <linux/mfd/core.h> | |
30 | ||
31 | #include <linux/jz4740-adc.h> | |
32 | ||
33 | ||
34 | #define JZ_REG_ADC_ENABLE 0x00 | |
35 | #define JZ_REG_ADC_CFG 0x04 | |
36 | #define JZ_REG_ADC_CTRL 0x08 | |
37 | #define JZ_REG_ADC_STATUS 0x0c | |
38 | ||
39 | #define JZ_REG_ADC_TOUCHSCREEN_BASE 0x10 | |
40 | #define JZ_REG_ADC_BATTERY_BASE 0x1c | |
41 | #define JZ_REG_ADC_HWMON_BASE 0x20 | |
42 | ||
43 | #define JZ_ADC_ENABLE_TOUCH BIT(2) | |
44 | #define JZ_ADC_ENABLE_BATTERY BIT(1) | |
45 | #define JZ_ADC_ENABLE_ADCIN BIT(0) | |
46 | ||
47 | enum { | |
48 | JZ_ADC_IRQ_ADCIN = 0, | |
49 | JZ_ADC_IRQ_BATTERY, | |
50 | JZ_ADC_IRQ_TOUCH, | |
51 | JZ_ADC_IRQ_PENUP, | |
52 | JZ_ADC_IRQ_PENDOWN, | |
53 | }; | |
54 | ||
55 | struct jz4740_adc { | |
56 | struct resource *mem; | |
57 | void __iomem *base; | |
58 | ||
59 | int irq; | |
914e6d4e | 60 | struct irq_chip_generic *gc; |
91f4debf LPC |
61 | |
62 | struct clk *clk; | |
63 | atomic_t clk_ref; | |
64 | ||
65 | spinlock_t lock; | |
66 | }; | |
67 | ||
91f4debf LPC |
68 | static void jz4740_adc_irq_demux(unsigned int irq, struct irq_desc *desc) |
69 | { | |
914e6d4e | 70 | struct irq_chip_generic *gc = irq_desc_get_handler_data(desc); |
91f4debf LPC |
71 | uint8_t status; |
72 | unsigned int i; | |
73 | ||
914e6d4e | 74 | status = readb(gc->reg_base + JZ_REG_ADC_STATUS); |
91f4debf LPC |
75 | |
76 | for (i = 0; i < 5; ++i) { | |
77 | if (status & BIT(i)) | |
914e6d4e | 78 | generic_handle_irq(gc->irq_base + i); |
91f4debf LPC |
79 | } |
80 | } | |
81 | ||
82 | ||
83 | /* Refcounting for the ADC clock is done in here instead of in the clock | |
84 | * framework, because it is the only clock which is shared between multiple | |
85 | * devices and thus is the only clock which needs refcounting */ | |
86 | static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc) | |
87 | { | |
88 | if (atomic_inc_return(&adc->clk_ref) == 1) | |
89 | clk_enable(adc->clk); | |
90 | } | |
91 | ||
92 | static inline void jz4740_adc_clk_disable(struct jz4740_adc *adc) | |
93 | { | |
94 | if (atomic_dec_return(&adc->clk_ref) == 0) | |
95 | clk_disable(adc->clk); | |
96 | } | |
97 | ||
98 | static inline void jz4740_adc_set_enabled(struct jz4740_adc *adc, int engine, | |
99 | bool enabled) | |
100 | { | |
101 | unsigned long flags; | |
102 | uint8_t val; | |
103 | ||
104 | spin_lock_irqsave(&adc->lock, flags); | |
105 | ||
106 | val = readb(adc->base + JZ_REG_ADC_ENABLE); | |
107 | if (enabled) | |
108 | val |= BIT(engine); | |
109 | else | |
f9c28019 | 110 | val &= ~BIT(engine); |
91f4debf LPC |
111 | writeb(val, adc->base + JZ_REG_ADC_ENABLE); |
112 | ||
113 | spin_unlock_irqrestore(&adc->lock, flags); | |
114 | } | |
115 | ||
116 | static int jz4740_adc_cell_enable(struct platform_device *pdev) | |
117 | { | |
118 | struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent); | |
119 | ||
120 | jz4740_adc_clk_enable(adc); | |
121 | jz4740_adc_set_enabled(adc, pdev->id, true); | |
122 | ||
123 | return 0; | |
124 | } | |
125 | ||
126 | static int jz4740_adc_cell_disable(struct platform_device *pdev) | |
127 | { | |
128 | struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent); | |
129 | ||
130 | jz4740_adc_set_enabled(adc, pdev->id, false); | |
131 | jz4740_adc_clk_disable(adc); | |
132 | ||
133 | return 0; | |
134 | } | |
135 | ||
136 | int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val) | |
137 | { | |
138 | struct jz4740_adc *adc = dev_get_drvdata(dev); | |
139 | unsigned long flags; | |
140 | uint32_t cfg; | |
141 | ||
142 | if (!adc) | |
143 | return -ENODEV; | |
144 | ||
145 | spin_lock_irqsave(&adc->lock, flags); | |
146 | ||
147 | cfg = readl(adc->base + JZ_REG_ADC_CFG); | |
148 | ||
149 | cfg &= ~mask; | |
150 | cfg |= val; | |
151 | ||
152 | writel(cfg, adc->base + JZ_REG_ADC_CFG); | |
153 | ||
154 | spin_unlock_irqrestore(&adc->lock, flags); | |
155 | ||
156 | return 0; | |
157 | } | |
158 | EXPORT_SYMBOL_GPL(jz4740_adc_set_config); | |
159 | ||
160 | static struct resource jz4740_hwmon_resources[] = { | |
161 | { | |
162 | .start = JZ_ADC_IRQ_ADCIN, | |
163 | .flags = IORESOURCE_IRQ, | |
164 | }, | |
165 | { | |
166 | .start = JZ_REG_ADC_HWMON_BASE, | |
167 | .end = JZ_REG_ADC_HWMON_BASE + 3, | |
168 | .flags = IORESOURCE_MEM, | |
169 | }, | |
170 | }; | |
171 | ||
172 | static struct resource jz4740_battery_resources[] = { | |
173 | { | |
174 | .start = JZ_ADC_IRQ_BATTERY, | |
175 | .flags = IORESOURCE_IRQ, | |
176 | }, | |
177 | { | |
178 | .start = JZ_REG_ADC_BATTERY_BASE, | |
179 | .end = JZ_REG_ADC_BATTERY_BASE + 3, | |
180 | .flags = IORESOURCE_MEM, | |
181 | }, | |
182 | }; | |
183 | ||
aa05c9cf | 184 | static struct mfd_cell jz4740_adc_cells[] = { |
91f4debf LPC |
185 | { |
186 | .id = 0, | |
187 | .name = "jz4740-hwmon", | |
188 | .num_resources = ARRAY_SIZE(jz4740_hwmon_resources), | |
189 | .resources = jz4740_hwmon_resources, | |
91f4debf LPC |
190 | |
191 | .enable = jz4740_adc_cell_enable, | |
192 | .disable = jz4740_adc_cell_disable, | |
193 | }, | |
194 | { | |
195 | .id = 1, | |
196 | .name = "jz4740-battery", | |
197 | .num_resources = ARRAY_SIZE(jz4740_battery_resources), | |
198 | .resources = jz4740_battery_resources, | |
91f4debf LPC |
199 | |
200 | .enable = jz4740_adc_cell_enable, | |
201 | .disable = jz4740_adc_cell_disable, | |
202 | }, | |
203 | }; | |
204 | ||
f791be49 | 205 | static int jz4740_adc_probe(struct platform_device *pdev) |
91f4debf | 206 | { |
914e6d4e LPC |
207 | struct irq_chip_generic *gc; |
208 | struct irq_chip_type *ct; | |
91f4debf LPC |
209 | struct jz4740_adc *adc; |
210 | struct resource *mem_base; | |
914e6d4e LPC |
211 | int ret; |
212 | int irq_base; | |
91f4debf | 213 | |
931cbaf3 | 214 | adc = devm_kzalloc(&pdev->dev, sizeof(*adc), GFP_KERNEL); |
789133b7 AL |
215 | if (!adc) { |
216 | dev_err(&pdev->dev, "Failed to allocate driver structure\n"); | |
217 | return -ENOMEM; | |
218 | } | |
91f4debf LPC |
219 | |
220 | adc->irq = platform_get_irq(pdev, 0); | |
221 | if (adc->irq < 0) { | |
222 | ret = adc->irq; | |
223 | dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret); | |
931cbaf3 | 224 | return ret; |
91f4debf LPC |
225 | } |
226 | ||
914e6d4e LPC |
227 | irq_base = platform_get_irq(pdev, 1); |
228 | if (irq_base < 0) { | |
931cbaf3 DN |
229 | dev_err(&pdev->dev, "Failed to get irq base: %d\n", irq_base); |
230 | return irq_base; | |
91f4debf LPC |
231 | } |
232 | ||
233 | mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
234 | if (!mem_base) { | |
91f4debf | 235 | dev_err(&pdev->dev, "Failed to get platform mmio resource\n"); |
931cbaf3 | 236 | return -ENOENT; |
91f4debf LPC |
237 | } |
238 | ||
239 | /* Only request the shared registers for the MFD driver */ | |
240 | adc->mem = request_mem_region(mem_base->start, JZ_REG_ADC_STATUS, | |
241 | pdev->name); | |
242 | if (!adc->mem) { | |
91f4debf | 243 | dev_err(&pdev->dev, "Failed to request mmio memory region\n"); |
931cbaf3 | 244 | return -EBUSY; |
91f4debf LPC |
245 | } |
246 | ||
247 | adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem)); | |
248 | if (!adc->base) { | |
249 | ret = -EBUSY; | |
250 | dev_err(&pdev->dev, "Failed to ioremap mmio memory\n"); | |
251 | goto err_release_mem_region; | |
252 | } | |
253 | ||
254 | adc->clk = clk_get(&pdev->dev, "adc"); | |
255 | if (IS_ERR(adc->clk)) { | |
256 | ret = PTR_ERR(adc->clk); | |
257 | dev_err(&pdev->dev, "Failed to get clock: %d\n", ret); | |
258 | goto err_iounmap; | |
259 | } | |
260 | ||
261 | spin_lock_init(&adc->lock); | |
262 | atomic_set(&adc->clk_ref, 0); | |
263 | ||
264 | platform_set_drvdata(pdev, adc); | |
265 | ||
914e6d4e LPC |
266 | gc = irq_alloc_generic_chip("INTC", 1, irq_base, adc->base, |
267 | handle_level_irq); | |
268 | ||
269 | ct = gc->chip_types; | |
270 | ct->regs.mask = JZ_REG_ADC_CTRL; | |
271 | ct->regs.ack = JZ_REG_ADC_STATUS; | |
272 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
273 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
6fcb8a3a | 274 | ct->chip.irq_ack = irq_gc_ack_set_bit; |
914e6d4e LPC |
275 | |
276 | irq_setup_generic_chip(gc, IRQ_MSK(5), 0, 0, IRQ_NOPROBE | IRQ_LEVEL); | |
277 | ||
278 | adc->gc = gc; | |
91f4debf | 279 | |
914e6d4e | 280 | irq_set_handler_data(adc->irq, gc); |
d5bb1221 | 281 | irq_set_chained_handler(adc->irq, jz4740_adc_irq_demux); |
91f4debf LPC |
282 | |
283 | writeb(0x00, adc->base + JZ_REG_ADC_ENABLE); | |
284 | writeb(0xff, adc->base + JZ_REG_ADC_CTRL); | |
285 | ||
48736c80 | 286 | ret = mfd_add_devices(&pdev->dev, 0, jz4740_adc_cells, |
0848c94f MB |
287 | ARRAY_SIZE(jz4740_adc_cells), mem_base, |
288 | irq_base, NULL); | |
48736c80 AL |
289 | if (ret < 0) |
290 | goto err_clk_put; | |
91f4debf | 291 | |
48736c80 AL |
292 | return 0; |
293 | ||
294 | err_clk_put: | |
295 | clk_put(adc->clk); | |
91f4debf LPC |
296 | err_iounmap: |
297 | platform_set_drvdata(pdev, NULL); | |
298 | iounmap(adc->base); | |
299 | err_release_mem_region: | |
300 | release_mem_region(adc->mem->start, resource_size(adc->mem)); | |
91f4debf LPC |
301 | return ret; |
302 | } | |
303 | ||
4740f73f | 304 | static int jz4740_adc_remove(struct platform_device *pdev) |
91f4debf LPC |
305 | { |
306 | struct jz4740_adc *adc = platform_get_drvdata(pdev); | |
307 | ||
308 | mfd_remove_devices(&pdev->dev); | |
309 | ||
914e6d4e LPC |
310 | irq_remove_generic_chip(adc->gc, IRQ_MSK(5), IRQ_NOPROBE | IRQ_LEVEL, 0); |
311 | kfree(adc->gc); | |
d5bb1221 TG |
312 | irq_set_handler_data(adc->irq, NULL); |
313 | irq_set_chained_handler(adc->irq, NULL); | |
91f4debf LPC |
314 | |
315 | iounmap(adc->base); | |
316 | release_mem_region(adc->mem->start, resource_size(adc->mem)); | |
317 | ||
318 | clk_put(adc->clk); | |
319 | ||
320 | platform_set_drvdata(pdev, NULL); | |
321 | ||
91f4debf LPC |
322 | return 0; |
323 | } | |
324 | ||
429c9ecc | 325 | static struct platform_driver jz4740_adc_driver = { |
91f4debf | 326 | .probe = jz4740_adc_probe, |
84449216 | 327 | .remove = jz4740_adc_remove, |
91f4debf LPC |
328 | .driver = { |
329 | .name = "jz4740-adc", | |
330 | .owner = THIS_MODULE, | |
331 | }, | |
332 | }; | |
333 | ||
65349d60 | 334 | module_platform_driver(jz4740_adc_driver); |
91f4debf LPC |
335 | |
336 | MODULE_DESCRIPTION("JZ4740 SoC ADC driver"); | |
337 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); | |
338 | MODULE_LICENSE("GPL"); | |
339 | MODULE_ALIAS("platform:jz4740-adc"); |