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mfd: lpc_ich: Remove useless comments in core part
[mirror_ubuntu-bionic-kernel.git] / drivers / mfd / lpc_ich.c
CommitLineData
4630b130
AS		 1/*
2 * lpc_ich.c - LPC interface for Intel ICH
3 *
4 * LPC bridge function of the Intel ICH contains many other
5 * functional units, such as Interrupt controllers, Timers,
6 * Power Management, System Management, GPIO, RTC, and LPC
7 * Configuration Registers.
8 *
9 * This driver is derived from lpc_sch.
10
11 * Copyright (c) 2011 Extreme Engineering Solution, Inc.
12 * Author: Aaron Sierra <asierra@xes-inc.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License 2 as published
16 * by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
4630b130
AS		 23 * This driver supports the following I/O Controller hubs:
24 * (See the intel documentation on http://developer.intel.com.)
25 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
26 * document number 290687-002, 298242-027: 82801BA (ICH2)
27 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
28 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
29 * document number 290744-001, 290745-025: 82801DB (ICH4)
30 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
31 * document number 273599-001, 273645-002: 82801E (C-ICH)
32 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
33 * document number 300641-004, 300884-013: 6300ESB
34 * document number 301473-002, 301474-026: 82801F (ICH6)
35 * document number 313082-001, 313075-006: 631xESB, 632xESB
36 * document number 307013-003, 307014-024: 82801G (ICH7)
37 * document number 322896-001, 322897-001: NM10
38 * document number 313056-003, 313057-017: 82801H (ICH8)
39 * document number 316972-004, 316973-012: 82801I (ICH9)
40 * document number 319973-002, 319974-002: 82801J (ICH10)
41 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
42 * document number 320066-003, 320257-008: EP80597 (IICH)
43 * document number 324645-001, 324646-001: Cougar Point (CPT)
4630b130
AS		 44 */
45
46#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
47
4630b130
AS		 48#include <linux/kernel.h>
49#include <linux/module.h>
50#include <linux/errno.h>
51#include <linux/acpi.h>
52#include <linux/pci.h>
53#include <linux/mfd/core.h>
54#include <linux/mfd/lpc_ich.h>
420b54de 55#include <linux/platform_data/itco_wdt.h>
4630b130
AS		 56
57#define ACPIBASE 0x40
58#define ACPIBASE_GPE_OFF 0x28
59#define ACPIBASE_GPE_END 0x2f
887c8ec7
AS		 60#define ACPIBASE_SMI_OFF 0x30
61#define ACPIBASE_SMI_END 0x33
eb71d4de
PT		 62#define ACPIBASE_PMC_OFF 0x08
63#define ACPIBASE_PMC_END 0x0c
887c8ec7
AS		 64#define ACPIBASE_TCO_OFF 0x60
65#define ACPIBASE_TCO_END 0x7f
eb71d4de 66#define ACPICTRL_PMCBASE 0x44
4630b130 67
887c8ec7
AS		 68#define ACPIBASE_GCS_OFF 0x3410
69#define ACPIBASE_GCS_END 0x3414
70
ff00d7a3
MW		 71#define SPIBASE_BYT 0x54
72#define SPIBASE_BYT_SZ 512
73#define SPIBASE_BYT_EN BIT(1)
74
75#define SPIBASE_LPT 0x3800
76#define SPIBASE_LPT_SZ 512
77#define BCR 0xdc
78#define BCR_WPD BIT(0)
79
87eb832a
MW		 80#define SPIBASE_APL_SZ 4096
81
01560f6b
AS		 82#define GPIOBASE_ICH0 0x58
83#define GPIOCTRL_ICH0 0x5C
84#define GPIOBASE_ICH6 0x48
85#define GPIOCTRL_ICH6 0x4C
4630b130 86
887c8ec7
AS		 87#define RCBABASE 0xf0
88
89#define wdt_io_res(i) wdt_res(0, i)
90#define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
91#define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
92
01560f6b
AS		 93struct lpc_ich_priv {
94 int chipset;
429b941a
PT		 95
96 int abase; /* ACPI base */
eb71d4de 97 int actrl_pbase; /* ACPI control or PMC base */
429b941a
PT		 98 int gbase; /* GPIO base */
99 int gctrl; /* GPIO control */
100
eb71d4de
PT		 101 int abase_save; /* Cached ACPI base value */
102 int actrl_pbase_save; /* Cached ACPI control or PMC base value */
429b941a 103 int gctrl_save; /* Cached GPIO control value */
01560f6b 104};
4630b130 105
887c8ec7
AS		 106static struct resource wdt_ich_res[] = {
107 /* ACPI - TCO */
108 {
109 .flags = IORESOURCE_IO,
110 },
111 /* ACPI - SMI */
112 {
113 .flags = IORESOURCE_IO,
114 },
eb71d4de 115 /* GCS or PMC */
887c8ec7
AS		 116 {
117 .flags = IORESOURCE_MEM,
118 },
119};
120
4630b130
AS		 121static struct resource gpio_ich_res[] = {
122 /* GPIO */
123 {
124 .flags = IORESOURCE_IO,
125 },
126 /* ACPI - GPE0 */
127 {
128 .flags = IORESOURCE_IO,
129 },
130};
131
ff00d7a3
MW		 132static struct resource intel_spi_res[] = {
133 {
134 .flags = IORESOURCE_MEM,
135 }
136};
137
3dab794f
AS		 138static struct mfd_cell lpc_ich_wdt_cell = {
139 .name = "iTCO_wdt",
140 .num_resources = ARRAY_SIZE(wdt_ich_res),
141 .resources = wdt_ich_res,
142 .ignore_resource_conflicts = true,
4630b130
AS		 143};
144
3dab794f
AS		 145static struct mfd_cell lpc_ich_gpio_cell = {
146 .name = "gpio_ich",
147 .num_resources = ARRAY_SIZE(gpio_ich_res),
148 .resources = gpio_ich_res,
149 .ignore_resource_conflicts = true,
4630b130
AS		 150};
151
ff00d7a3
MW		 152
153static struct mfd_cell lpc_ich_spi_cell = {
154 .name = "intel-spi",
155 .num_resources = ARRAY_SIZE(intel_spi_res),
156 .resources = intel_spi_res,
157 .ignore_resource_conflicts = true,
158};
159
4630b130
AS		 160/* chipset related info */
161enum lpc_chipsets {
162 LPC_ICH = 0, /* ICH */
163 LPC_ICH0, /* ICH0 */
164 LPC_ICH2, /* ICH2 */
165 LPC_ICH2M, /* ICH2-M */
166 LPC_ICH3, /* ICH3-S */
167 LPC_ICH3M, /* ICH3-M */
168 LPC_ICH4, /* ICH4 */
169 LPC_ICH4M, /* ICH4-M */
170 LPC_CICH, /* C-ICH */
171 LPC_ICH5, /* ICH5 & ICH5R */
172 LPC_6300ESB, /* 6300ESB */
173 LPC_ICH6, /* ICH6 & ICH6R */
174 LPC_ICH6M, /* ICH6-M */
175 LPC_ICH6W, /* ICH6W & ICH6RW */
176 LPC_631XESB, /* 631xESB/632xESB */
177 LPC_ICH7, /* ICH7 & ICH7R */
178 LPC_ICH7DH, /* ICH7DH */
179 LPC_ICH7M, /* ICH7-M & ICH7-U */
180 LPC_ICH7MDH, /* ICH7-M DH */
181 LPC_NM10, /* NM10 */
182 LPC_ICH8, /* ICH8 & ICH8R */
183 LPC_ICH8DH, /* ICH8DH */
184 LPC_ICH8DO, /* ICH8DO */
185 LPC_ICH8M, /* ICH8M */
186 LPC_ICH8ME, /* ICH8M-E */
187 LPC_ICH9, /* ICH9 */
188 LPC_ICH9R, /* ICH9R */
189 LPC_ICH9DH, /* ICH9DH */
190 LPC_ICH9DO, /* ICH9DO */
191 LPC_ICH9M, /* ICH9M */
192 LPC_ICH9ME, /* ICH9M-E */
193 LPC_ICH10, /* ICH10 */
194 LPC_ICH10R, /* ICH10R */
195 LPC_ICH10D, /* ICH10D */
196 LPC_ICH10DO, /* ICH10DO */
197 LPC_PCH, /* PCH Desktop Full Featured */
198 LPC_PCHM, /* PCH Mobile Full Featured */
199 LPC_P55, /* P55 */
200 LPC_PM55, /* PM55 */
201 LPC_H55, /* H55 */
202 LPC_QM57, /* QM57 */
203 LPC_H57, /* H57 */
204 LPC_HM55, /* HM55 */
205 LPC_Q57, /* Q57 */
206 LPC_HM57, /* HM57 */
207 LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */
208 LPC_QS57, /* QS57 */
209 LPC_3400, /* 3400 */
210 LPC_3420, /* 3420 */
211 LPC_3450, /* 3450 */
212 LPC_EP80579, /* EP80579 */
213 LPC_CPT, /* Cougar Point */
214 LPC_CPTD, /* Cougar Point Desktop */
215 LPC_CPTM, /* Cougar Point Mobile */
216 LPC_PBG, /* Patsburg */
217 LPC_DH89XXCC, /* DH89xxCC */
218 LPC_PPT, /* Panther Point */
219 LPC_LPT, /* Lynx Point */
7fb9c1a4 220 LPC_LPT_LP, /* Lynx Point-LP */
6e6680e3 221 LPC_WBG, /* Wellsburg */
8477128f 222 LPC_AVN, /* Avoton SoC */
6111ec70 223 LPC_BAYTRAIL, /* Bay Trail SoC */
283aae8a 224 LPC_COLETO, /* Coleto Creek */
5e90169c 225 LPC_WPT_LP, /* Wildcat Point-LP */
ff0c9da0 226 LPC_BRASWELL, /* Braswell SoC */
6223a309 227 LPC_LEWISBURG, /* Lewisburg */
fea31042 228 LPC_9S, /* 9 Series */
87eb832a 229 LPC_APL, /* Apollo Lake SoC */
4630b130
AS		 230};
231
a1ca138f 232static struct lpc_ich_info lpc_chipset_info[] = {
4630b130
AS		 233 [LPC_ICH] = {
234 .name = "ICH",
887c8ec7 235 .iTCO_version = 1,
4630b130
AS		 236 },
237 [LPC_ICH0] = {
238 .name = "ICH0",
887c8ec7 239 .iTCO_version = 1,
4630b130
AS		 240 },
241 [LPC_ICH2] = {
242 .name = "ICH2",
887c8ec7 243 .iTCO_version = 1,
4630b130
AS		 244 },
245 [LPC_ICH2M] = {
246 .name = "ICH2-M",
887c8ec7 247 .iTCO_version = 1,
4630b130
AS		 248 },
249 [LPC_ICH3] = {
250 .name = "ICH3-S",
887c8ec7 251 .iTCO_version = 1,
4630b130
AS		 252 },
253 [LPC_ICH3M] = {
254 .name = "ICH3-M",
887c8ec7 255 .iTCO_version = 1,
4630b130
AS		 256 },
257 [LPC_ICH4] = {
258 .name = "ICH4",
887c8ec7 259 .iTCO_version = 1,
4630b130
AS		 260 },
261 [LPC_ICH4M] = {
262 .name = "ICH4-M",
887c8ec7 263 .iTCO_version = 1,
4630b130
AS		 264 },
265 [LPC_CICH] = {
266 .name = "C-ICH",
887c8ec7 267 .iTCO_version = 1,
4630b130
AS		 268 },
269 [LPC_ICH5] = {
270 .name = "ICH5 or ICH5R",
887c8ec7 271 .iTCO_version = 1,
4630b130
AS		 272 },
273 [LPC_6300ESB] = {
274 .name = "6300ESB",
887c8ec7 275 .iTCO_version = 1,
4630b130
AS		 276 },
277 [LPC_ICH6] = {
278 .name = "ICH6 or ICH6R",
887c8ec7 279 .iTCO_version = 2,
4630b130
AS		 280 .gpio_version = ICH_V6_GPIO,
281 },
282 [LPC_ICH6M] = {
283 .name = "ICH6-M",
887c8ec7 284 .iTCO_version = 2,
4630b130
AS		 285 .gpio_version = ICH_V6_GPIO,
286 },
287 [LPC_ICH6W] = {
288 .name = "ICH6W or ICH6RW",
887c8ec7 289 .iTCO_version = 2,
4630b130
AS		 290 .gpio_version = ICH_V6_GPIO,
291 },
292 [LPC_631XESB] = {
293 .name = "631xESB/632xESB",
887c8ec7 294 .iTCO_version = 2,
4630b130
AS		 295 .gpio_version = ICH_V6_GPIO,
296 },
297 [LPC_ICH7] = {
298 .name = "ICH7 or ICH7R",
887c8ec7 299 .iTCO_version = 2,
4630b130
AS		 300 .gpio_version = ICH_V7_GPIO,
301 },
302 [LPC_ICH7DH] = {
303 .name = "ICH7DH",
887c8ec7 304 .iTCO_version = 2,
4630b130
AS		 305 .gpio_version = ICH_V7_GPIO,
306 },
307 [LPC_ICH7M] = {
308 .name = "ICH7-M or ICH7-U",
887c8ec7 309 .iTCO_version = 2,
4630b130
AS		 310 .gpio_version = ICH_V7_GPIO,
311 },
312 [LPC_ICH7MDH] = {
313 .name = "ICH7-M DH",
887c8ec7 314 .iTCO_version = 2,
4630b130
AS		 315 .gpio_version = ICH_V7_GPIO,
316 },
317 [LPC_NM10] = {
318 .name = "NM10",
887c8ec7 319 .iTCO_version = 2,
117bbfe2 320 .gpio_version = ICH_V7_GPIO,
4630b130
AS		 321 },
322 [LPC_ICH8] = {
323 .name = "ICH8 or ICH8R",
887c8ec7 324 .iTCO_version = 2,
4630b130
AS		 325 .gpio_version = ICH_V7_GPIO,
326 },
327 [LPC_ICH8DH] = {
328 .name = "ICH8DH",
887c8ec7 329 .iTCO_version = 2,
4630b130
AS		 330 .gpio_version = ICH_V7_GPIO,
331 },
332 [LPC_ICH8DO] = {
333 .name = "ICH8DO",
887c8ec7 334 .iTCO_version = 2,
4630b130
AS		 335 .gpio_version = ICH_V7_GPIO,
336 },
337 [LPC_ICH8M] = {
338 .name = "ICH8M",
887c8ec7 339 .iTCO_version = 2,
4630b130
AS		 340 .gpio_version = ICH_V7_GPIO,
341 },
342 [LPC_ICH8ME] = {
343 .name = "ICH8M-E",
887c8ec7 344 .iTCO_version = 2,
4630b130
AS		 345 .gpio_version = ICH_V7_GPIO,
346 },
347 [LPC_ICH9] = {
348 .name = "ICH9",
887c8ec7 349 .iTCO_version = 2,
4630b130
AS		 350 .gpio_version = ICH_V9_GPIO,
351 },
352 [LPC_ICH9R] = {
353 .name = "ICH9R",
887c8ec7 354 .iTCO_version = 2,
4630b130
AS		 355 .gpio_version = ICH_V9_GPIO,
356 },
357 [LPC_ICH9DH] = {
358 .name = "ICH9DH",
887c8ec7 359 .iTCO_version = 2,
4630b130
AS		 360 .gpio_version = ICH_V9_GPIO,
361 },
362 [LPC_ICH9DO] = {
363 .name = "ICH9DO",
887c8ec7 364 .iTCO_version = 2,
4630b130
AS		 365 .gpio_version = ICH_V9_GPIO,
366 },
367 [LPC_ICH9M] = {
368 .name = "ICH9M",
887c8ec7 369 .iTCO_version = 2,
4630b130
AS		 370 .gpio_version = ICH_V9_GPIO,
371 },
372 [LPC_ICH9ME] = {
373 .name = "ICH9M-E",
887c8ec7 374 .iTCO_version = 2,
4630b130
AS		 375 .gpio_version = ICH_V9_GPIO,
376 },
377 [LPC_ICH10] = {
378 .name = "ICH10",
887c8ec7 379 .iTCO_version = 2,
4630b130
AS		 380 .gpio_version = ICH_V10CONS_GPIO,
381 },
382 [LPC_ICH10R] = {
383 .name = "ICH10R",
887c8ec7 384 .iTCO_version = 2,
4630b130
AS		 385 .gpio_version = ICH_V10CONS_GPIO,
386 },
387 [LPC_ICH10D] = {
388 .name = "ICH10D",
887c8ec7 389 .iTCO_version = 2,
4630b130
AS		 390 .gpio_version = ICH_V10CORP_GPIO,
391 },
392 [LPC_ICH10DO] = {
393 .name = "ICH10DO",
887c8ec7 394 .iTCO_version = 2,
4630b130
AS		 395 .gpio_version = ICH_V10CORP_GPIO,
396 },
397 [LPC_PCH] = {
398 .name = "PCH Desktop Full Featured",
887c8ec7 399 .iTCO_version = 2,
4630b130
AS		 400 .gpio_version = ICH_V5_GPIO,
401 },
402 [LPC_PCHM] = {
403 .name = "PCH Mobile Full Featured",
887c8ec7 404 .iTCO_version = 2,
4630b130
AS		 405 .gpio_version = ICH_V5_GPIO,
406 },
407 [LPC_P55] = {
408 .name = "P55",
887c8ec7 409 .iTCO_version = 2,
4630b130
AS		 410 .gpio_version = ICH_V5_GPIO,
411 },
412 [LPC_PM55] = {
413 .name = "PM55",
887c8ec7 414 .iTCO_version = 2,
4630b130
AS		 415 .gpio_version = ICH_V5_GPIO,
416 },
417 [LPC_H55] = {
418 .name = "H55",
887c8ec7 419 .iTCO_version = 2,
4630b130
AS		 420 .gpio_version = ICH_V5_GPIO,
421 },
422 [LPC_QM57] = {
423 .name = "QM57",
887c8ec7 424 .iTCO_version = 2,
4630b130
AS		 425 .gpio_version = ICH_V5_GPIO,
426 },
427 [LPC_H57] = {
428 .name = "H57",
887c8ec7 429 .iTCO_version = 2,
4630b130
AS		 430 .gpio_version = ICH_V5_GPIO,
431 },
432 [LPC_HM55] = {
433 .name = "HM55",
887c8ec7 434 .iTCO_version = 2,
4630b130
AS		 435 .gpio_version = ICH_V5_GPIO,
436 },
437 [LPC_Q57] = {
438 .name = "Q57",
887c8ec7 439 .iTCO_version = 2,
4630b130
AS		 440 .gpio_version = ICH_V5_GPIO,
441 },
442 [LPC_HM57] = {
443 .name = "HM57",
887c8ec7 444 .iTCO_version = 2,
4630b130
AS		 445 .gpio_version = ICH_V5_GPIO,
446 },
447 [LPC_PCHMSFF] = {
448 .name = "PCH Mobile SFF Full Featured",
887c8ec7 449 .iTCO_version = 2,
4630b130
AS		 450 .gpio_version = ICH_V5_GPIO,
451 },
452 [LPC_QS57] = {
453 .name = "QS57",
887c8ec7 454 .iTCO_version = 2,
4630b130
AS		 455 .gpio_version = ICH_V5_GPIO,
456 },
457 [LPC_3400] = {
458 .name = "3400",
887c8ec7 459 .iTCO_version = 2,
4630b130
AS		 460 .gpio_version = ICH_V5_GPIO,
461 },
462 [LPC_3420] = {
463 .name = "3420",
887c8ec7 464 .iTCO_version = 2,
4630b130
AS		 465 .gpio_version = ICH_V5_GPIO,
466 },
467 [LPC_3450] = {
468 .name = "3450",
887c8ec7 469 .iTCO_version = 2,
4630b130
AS		 470 .gpio_version = ICH_V5_GPIO,
471 },
472 [LPC_EP80579] = {
473 .name = "EP80579",
887c8ec7 474 .iTCO_version = 2,
4630b130
AS		 475 },
476 [LPC_CPT] = {
477 .name = "Cougar Point",
887c8ec7 478 .iTCO_version = 2,
4630b130
AS		 479 .gpio_version = ICH_V5_GPIO,
480 },
481 [LPC_CPTD] = {
482 .name = "Cougar Point Desktop",
887c8ec7 483 .iTCO_version = 2,
4630b130
AS		 484 .gpio_version = ICH_V5_GPIO,
485 },
486 [LPC_CPTM] = {
487 .name = "Cougar Point Mobile",
887c8ec7 488 .iTCO_version = 2,
4630b130
AS		 489 .gpio_version = ICH_V5_GPIO,
490 },
491 [LPC_PBG] = {
492 .name = "Patsburg",
887c8ec7 493 .iTCO_version = 2,
4630b130
AS		 494 },
495 [LPC_DH89XXCC] = {
496 .name = "DH89xxCC",
887c8ec7 497 .iTCO_version = 2,
4630b130
AS		 498 },
499 [LPC_PPT] = {
500 .name = "Panther Point",
887c8ec7 501 .iTCO_version = 2,
62cf2cdb 502 .gpio_version = ICH_V5_GPIO,
4630b130
AS		 503 },
504 [LPC_LPT] = {
505 .name = "Lynx Point",
887c8ec7 506 .iTCO_version = 2,
e420d6a1 507 .gpio_version = ICH_V5_GPIO,
ff00d7a3 508 .spi_type = INTEL_SPI_LPT,
4630b130 509 },
7fb9c1a4
JR		 510 [LPC_LPT_LP] = {
511 .name = "Lynx Point_LP",
512 .iTCO_version = 2,
ff00d7a3 513 .spi_type = INTEL_SPI_LPT,
7fb9c1a4 514 },
6e6680e3
JR		 515 [LPC_WBG] = {
516 .name = "Wellsburg",
517 .iTCO_version = 2,
518 },
8477128f
JR		 519 [LPC_AVN] = {
520 .name = "Avoton SoC",
c48cf598 521 .iTCO_version = 3,
facd9939 522 .gpio_version = AVOTON_GPIO,
8477128f 523 },
6111ec70
PT		 524 [LPC_BAYTRAIL] = {
525 .name = "Bay Trail SoC",
526 .iTCO_version = 3,
ff00d7a3 527 .spi_type = INTEL_SPI_BYT,
6111ec70 528 },
283aae8a
SH		 529 [LPC_COLETO] = {
530 .name = "Coleto Creek",
531 .iTCO_version = 2,
532 },
5e90169c 533 [LPC_WPT_LP] = {
a8822df9 534 .name = "Wildcat Point_LP",
5e90169c 535 .iTCO_version = 2,
ff00d7a3 536 .spi_type = INTEL_SPI_LPT,
5e90169c 537 },
ff0c9da0
AC		 538 [LPC_BRASWELL] = {
539 .name = "Braswell SoC",
540 .iTCO_version = 3,
ff00d7a3 541 .spi_type = INTEL_SPI_BYT,
ff0c9da0 542 },
6223a309
AY		 543 [LPC_LEWISBURG] = {
544 .name = "Lewisburg",
545 .iTCO_version = 2,
546 },
fea31042
JR		 547 [LPC_9S] = {
548 .name = "9 Series",
549 .iTCO_version = 2,
e420d6a1 550 .gpio_version = ICH_V5_GPIO,
fea31042 551 },
87eb832a
MW		 552 [LPC_APL] = {
553 .name = "Apollo Lake SoC",
554 .spi_type = INTEL_SPI_BXT,
555 },
4630b130
AS		 556};
557
558/*
559 * This data only exists for exporting the supported PCI ids
560 * via MODULE_DEVICE_TABLE. We do not actually register a
561 * pci_driver, because the I/O Controller Hub has also other
562 * functions that probably will be registered by other drivers.
563 */
36fcd06c 564static const struct pci_device_id lpc_ich_ids[] = {
aec9038e
AS		 565 { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL},
566 { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
567 { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
568 { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
569 { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
570 { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
571 { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
572 { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
573 { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
574 { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
575 { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
576 { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
577 { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
578 { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
579 { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
580 { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
581 { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
582 { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
583 { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
584 { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
585 { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
586 { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
587 { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
588 { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
589 { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
590 { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
591 { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
592 { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
593 { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
594 { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
595 { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
596 { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
597 { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
598 { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
599 { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
600 { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
601 { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
602 { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
603 { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
604 { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
605 { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
606 { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
607 { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
608 { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
609 { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
610 { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
611 { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
612 { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
613 { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
614 { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
615 { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
616 { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
617 { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
618 { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
619 { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
620 { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
621 { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
622 { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
623 { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
624 { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
625 { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
626 { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
627 { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
628 { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
629 { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
630 { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
631 { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN},
632 { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN},
633 { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN},
634 { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN},
635 { PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL},
636 { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
637 { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO},
4630b130
AS		 638 { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
639 { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
640 { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
641 { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
72715757 642 { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
4630b130
AS		 643 { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
644 { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
645 { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
646 { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
4630b130
AS		 647 { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
648 { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
649 { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
650 { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
651 { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
652 { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
653 { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
654 { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
655 { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
656 { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
657 { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
658 { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
659 { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
660 { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
661 { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
662 { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
663 { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
664 { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
665 { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
666 { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
667 { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
4630b130 668 { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
72715757 669 { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
4630b130 670 { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
4630b130 671 { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
72715757 672 { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
4630b130 673 { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
72715757 674 { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
4630b130
AS		 675 { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
676 { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
677 { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
4630b130
AS		 678 { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
679 { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
72715757 680 { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
4630b130 681 { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
72715757
AS		 682 { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
683 { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
684 { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
4630b130 685 { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
72715757 686 { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
4630b130 687 { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
4630b130
AS		 688 { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
689 { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
690 { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
691 { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
692 { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
693 { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
694 { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
695 { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
696 { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
697 { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
698 { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
699 { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
700 { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
701 { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
702 { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
703 { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
87eb832a 704 { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
4630b130
AS		 705 { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
706 { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
707 { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
708 { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
709 { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
710 { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
711 { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
712 { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
713 { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
714 { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
715 { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
716 { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
717 { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
718 { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
719 { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
720 { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
721 { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
722 { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
723 { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
724 { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
725 { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
726 { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
727 { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
728 { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
729 { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
730 { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
731 { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
732 { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
733 { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
734 { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
735 { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
736 { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
aec9038e
AS		 737 { PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S},
738 { PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S},
739 { PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S},
740 { PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S},
741 { PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S},
6e6680e3
JR		 742 { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG},
743 { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG},
744 { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG},
745 { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG},
746 { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG},
747 { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG},
748 { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG},
749 { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG},
750 { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG},
751 { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG},
752 { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG},
753 { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG},
754 { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG},
755 { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG},
756 { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG},
757 { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG},
758 { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG},
759 { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG},
760 { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG},
761 { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG},
762 { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG},
763 { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG},
764 { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG},
765 { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG},
766 { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG},
767 { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG},
768 { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG},
769 { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG},
770 { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG},
771 { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG},
772 { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG},
773 { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG},
aec9038e
AS		 774 { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP},
775 { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP},
776 { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP},
777 { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP},
778 { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP},
779 { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP},
780 { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP},
781 { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP},
5e90169c
JR		 782 { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP},
783 { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP},
784 { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP},
785 { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP},
786 { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP},
787 { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP},
788 { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP},
6223a309
AY		 789 { PCI_VDEVICE(INTEL, 0xa1c1), LPC_LEWISBURG},
790 { PCI_VDEVICE(INTEL, 0xa1c2), LPC_LEWISBURG},
791 { PCI_VDEVICE(INTEL, 0xa1c3), LPC_LEWISBURG},
792 { PCI_VDEVICE(INTEL, 0xa1c4), LPC_LEWISBURG},
793 { PCI_VDEVICE(INTEL, 0xa1c5), LPC_LEWISBURG},
794 { PCI_VDEVICE(INTEL, 0xa1c6), LPC_LEWISBURG},
795 { PCI_VDEVICE(INTEL, 0xa1c7), LPC_LEWISBURG},
796 { PCI_VDEVICE(INTEL, 0xa242), LPC_LEWISBURG},
797 { PCI_VDEVICE(INTEL, 0xa243), LPC_LEWISBURG},
4630b130
AS		 798 { 0, }, /* End of list */
799};
800MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
801
802static void lpc_ich_restore_config_space(struct pci_dev *dev)
803{
01560f6b
AS		 804 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
805
eb71d4de
PT		 806 if (priv->abase_save >= 0) {
807 pci_write_config_byte(dev, priv->abase, priv->abase_save);
808 priv->abase_save = -1;
809 }
810
811 if (priv->actrl_pbase_save >= 0) {
812 pci_write_config_byte(dev, priv->actrl_pbase,
813 priv->actrl_pbase_save);
814 priv->actrl_pbase_save = -1;
4630b130
AS		 815 }
816
429b941a
PT		 817 if (priv->gctrl_save >= 0) {
818 pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save);
819 priv->gctrl_save = -1;
4630b130
AS		 820 }
821}
822
f791be49 823static void lpc_ich_enable_acpi_space(struct pci_dev *dev)
4630b130 824{
01560f6b 825 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
4630b130
AS		 826 u8 reg_save;
827
eb71d4de
PT		 828 switch (lpc_chipset_info[priv->chipset].iTCO_version) {
829 case 3:
830 /*
831 * Some chipsets (eg Avoton) enable the ACPI space in the
832 * ACPI BASE register.
833 */
834 pci_read_config_byte(dev, priv->abase, &reg_save);
835 pci_write_config_byte(dev, priv->abase, reg_save | 0x2);
836 priv->abase_save = reg_save;
837 break;
838 default:
839 /*
840 * Most chipsets enable the ACPI space in the ACPI control
841 * register.
842 */
843 pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
844 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80);
845 priv->actrl_pbase_save = reg_save;
846 break;
847 }
4630b130
AS		 848}
849
f791be49 850static void lpc_ich_enable_gpio_space(struct pci_dev *dev)
4630b130 851{
01560f6b 852 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
4630b130
AS		 853 u8 reg_save;
854
429b941a
PT		 855 pci_read_config_byte(dev, priv->gctrl, &reg_save);
856 pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10);
857 priv->gctrl_save = reg_save;
4630b130
AS		 858}
859
eb71d4de
PT		 860static void lpc_ich_enable_pmc_space(struct pci_dev *dev)
861{
862 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
863 u8 reg_save;
864
865 pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
866 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2);
867
868 priv->actrl_pbase_save = reg_save;
869}
870
420b54de 871static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev)
4630b130 872{
420b54de 873 struct itco_wdt_platform_data *pdata;
01560f6b 874 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
420b54de 875 struct lpc_ich_info *info;
3dab794f 876 struct mfd_cell *cell = &lpc_ich_wdt_cell;
420b54de
MF		 877
878 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
879 if (!pdata)
880 return -ENOMEM;
881
882 info = &lpc_chipset_info[priv->chipset];
883
884 pdata->version = info->iTCO_version;
885 strlcpy(pdata->name, info->name, sizeof(pdata->name));
886
887 cell->platform_data = pdata;
888 cell->pdata_size = sizeof(*pdata);
889 return 0;
890}
891
892static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev)
893{
894 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
3dab794f 895 struct mfd_cell *cell = &lpc_ich_gpio_cell;
01560f6b
AS		 896
897 cell->platform_data = &lpc_chipset_info[priv->chipset];
4630b130
AS		 898 cell->pdata_size = sizeof(struct lpc_ich_info);
899}
900
4f600ada
JD		 901/*
902 * We don't check for resource conflict globally. There are 2 or 3 independent
903 * GPIO groups and it's enough to have access to one of these to instantiate
904 * the device.
905 */
f791be49 906static int lpc_ich_check_conflict_gpio(struct resource *res)
4f600ada
JD		 907{
908 int ret;
909 u8 use_gpio = 0;
910
911 if (resource_size(res) >= 0x50 &&
912 !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))
913 use_gpio |= 1 << 2;
914
915 if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))
916 use_gpio |= 1 << 1;
917
918 ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");
919 if (!ret)
920 use_gpio |= 1 << 0;
921
922 return use_gpio ? use_gpio : ret;
923}
924
01560f6b 925static int lpc_ich_init_gpio(struct pci_dev *dev)
4630b130 926{
01560f6b 927 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
4630b130
AS		 928 u32 base_addr_cfg;
929 u32 base_addr;
930 int ret;
931 bool acpi_conflict = false;
932 struct resource *res;
933
934 /* Setup power management base register */
429b941a 935 pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
4630b130
AS		 936 base_addr = base_addr_cfg & 0x0000ff80;
937 if (!base_addr) {
0c418844 938 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
3dab794f 939 lpc_ich_gpio_cell.num_resources--;
4630b130
AS		 940 goto gpe0_done;
941 }
942
943 res = &gpio_ich_res[ICH_RES_GPE0];
944 res->start = base_addr + ACPIBASE_GPE_OFF;
945 res->end = base_addr + ACPIBASE_GPE_END;
946 ret = acpi_check_resource_conflict(res);
947 if (ret) {
948 /*
949 * This isn't fatal for the GPIO, but we have to make sure that
950 * the platform_device subsystem doesn't see this resource
951 * or it will register an invalid region.
952 */
3dab794f 953 lpc_ich_gpio_cell.num_resources--;
4630b130
AS		 954 acpi_conflict = true;
955 } else {
956 lpc_ich_enable_acpi_space(dev);
957 }
958
959gpe0_done:
960 /* Setup GPIO base register */
429b941a 961 pci_read_config_dword(dev, priv->gbase, &base_addr_cfg);
4630b130
AS		 962 base_addr = base_addr_cfg & 0x0000ff80;
963 if (!base_addr) {
0c418844 964 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
4630b130
AS		 965 ret = -ENODEV;
966 goto gpio_done;
967 }
968
969 /* Older devices provide fewer GPIO and have a smaller resource size. */
970 res = &gpio_ich_res[ICH_RES_GPIO];
971 res->start = base_addr;
01560f6b 972 switch (lpc_chipset_info[priv->chipset].gpio_version) {
4630b130
AS		 973 case ICH_V5_GPIO:
974 case ICH_V10CORP_GPIO:
975 res->end = res->start + 128 - 1;
976 break;
977 default:
978 res->end = res->start + 64 - 1;
979 break;
980 }
981
4f600ada
JD		 982 ret = lpc_ich_check_conflict_gpio(res);
983 if (ret < 0) {
4630b130
AS		 984 /* this isn't necessarily fatal for the GPIO */
985 acpi_conflict = true;
986 goto gpio_done;
987 }
01560f6b 988 lpc_chipset_info[priv->chipset].use_gpio = ret;
4630b130
AS		 989 lpc_ich_enable_gpio_space(dev);
990
420b54de 991 lpc_ich_finalize_gpio_cell(dev);
1abf25a2 992 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
3dab794f 993 &lpc_ich_gpio_cell, 1, NULL, 0, NULL);
4630b130
AS		 994
995gpio_done:
996 if (acpi_conflict)
997 pr_warn("Resource conflict(s) found affecting %s\n",
3dab794f 998 lpc_ich_gpio_cell.name);
4630b130
AS		 999 return ret;
1000}
1001
01560f6b 1002static int lpc_ich_init_wdt(struct pci_dev *dev)
887c8ec7 1003{
01560f6b 1004 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
887c8ec7
AS		 1005 u32 base_addr_cfg;
1006 u32 base_addr;
1007 int ret;
887c8ec7
AS		 1008 struct resource *res;
1009
3413f702
MW		 1010 /* If we have ACPI based watchdog use that instead */
1011 if (acpi_has_watchdog())
1012 return -ENODEV;
1013
887c8ec7 1014 /* Setup power management base register */
429b941a 1015 pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
887c8ec7
AS		 1016 base_addr = base_addr_cfg & 0x0000ff80;
1017 if (!base_addr) {
0c418844 1018 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
887c8ec7
AS		 1019 ret = -ENODEV;
1020 goto wdt_done;
1021 }
1022
1023 res = wdt_io_res(ICH_RES_IO_TCO);
1024 res->start = base_addr + ACPIBASE_TCO_OFF;
1025 res->end = base_addr + ACPIBASE_TCO_END;
887c8ec7
AS		 1026
1027 res = wdt_io_res(ICH_RES_IO_SMI);
1028 res->start = base_addr + ACPIBASE_SMI_OFF;
1029 res->end = base_addr + ACPIBASE_SMI_END;
092369ef 1030
887c8ec7
AS		 1031 lpc_ich_enable_acpi_space(dev);
1032
1033 /*
eb71d4de 1034 * iTCO v2:
887c8ec7
AS		 1035 * Get the Memory-Mapped GCS register. To get access to it
1036 * we have to read RCBA from PCI Config space 0xf0 and use
1037 * it as base. GCS = RCBA + ICH6_GCS(0x3410).
eb71d4de
PT		 1038 *
1039 * iTCO v3:
1040 * Get the Power Management Configuration register. To get access
1041 * to it we have to read the PMC BASE from config space and address
1042 * the register at offset 0x8.
887c8ec7 1043 */
01560f6b 1044 if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {
e294bc91 1045 /* Don't register iomem for TCO ver 1 */
3dab794f 1046 lpc_ich_wdt_cell.num_resources--;
eb71d4de 1047 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) {
887c8ec7
AS		 1048 pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
1049 base_addr = base_addr_cfg & 0xffffc000;
1050 if (!(base_addr_cfg & 1)) {
0c418844
PB		 1051 dev_notice(&dev->dev, "RCBA is disabled by "
1052 "hardware/BIOS, device disabled\n");
887c8ec7
AS		 1053 ret = -ENODEV;
1054 goto wdt_done;
1055 }
eb71d4de 1056 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
887c8ec7
AS		 1057 res->start = base_addr + ACPIBASE_GCS_OFF;
1058 res->end = base_addr + ACPIBASE_GCS_END;
eb71d4de
PT		 1059 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) {
1060 lpc_ich_enable_pmc_space(dev);
1061 pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg);
1062 base_addr = base_addr_cfg & 0xfffffe00;
1063
1064 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1065 res->start = base_addr + ACPIBASE_PMC_OFF;
1066 res->end = base_addr + ACPIBASE_PMC_END;
887c8ec7
AS		 1067 }
1068
420b54de
MF		 1069 ret = lpc_ich_finalize_wdt_cell(dev);
1070 if (ret)
1071 goto wdt_done;
1072
1abf25a2 1073 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
3dab794f 1074 &lpc_ich_wdt_cell, 1, NULL, 0, NULL);
887c8ec7
AS		 1075
1076wdt_done:
887c8ec7
AS		 1077 return ret;
1078}
1079
ff00d7a3
MW		 1080static int lpc_ich_init_spi(struct pci_dev *dev)
1081{
1082 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1083 struct resource *res = &intel_spi_res[0];
1084 struct intel_spi_boardinfo *info;
1085 u32 spi_base, rcba, bcr;
1086
1087 info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);
1088 if (!info)
1089 return -ENOMEM;
1090
1091 info->type = lpc_chipset_info[priv->chipset].spi_type;
1092
1093 switch (info->type) {
1094 case INTEL_SPI_BYT:
1095 pci_read_config_dword(dev, SPIBASE_BYT, &spi_base);
1096 if (spi_base & SPIBASE_BYT_EN) {
1097 res->start = spi_base & ~(SPIBASE_BYT_SZ - 1);
1098 res->end = res->start + SPIBASE_BYT_SZ - 1;
1099 }
1100 break;
1101
1102 case INTEL_SPI_LPT:
1103 pci_read_config_dword(dev, RCBABASE, &rcba);
1104 if (rcba & 1) {
1105 spi_base = round_down(rcba, SPIBASE_LPT_SZ);
1106 res->start = spi_base + SPIBASE_LPT;
1107 res->end = res->start + SPIBASE_LPT_SZ - 1;
1108
1109 /*
1110 * Try to make the flash chip writeable now by
1111 * setting BCR_WPD. It it fails we tell the driver
1112 * that it can only read the chip.
1113 */
1114 pci_read_config_dword(dev, BCR, &bcr);
1115 if (!(bcr & BCR_WPD)) {
1116 bcr |= BCR_WPD;
1117 pci_write_config_dword(dev, BCR, bcr);
1118 pci_read_config_dword(dev, BCR, &bcr);
1119 }
1120 info->writeable = !!(bcr & BCR_WPD);
1121 }
1122 break;
1123
87eb832a
MW		 1124 case INTEL_SPI_BXT: {
1125 unsigned int p2sb = PCI_DEVFN(13, 0);
1126 unsigned int spi = PCI_DEVFN(13, 2);
1127 struct pci_bus *bus = dev->bus;
1128
1129 /*
1130 * The P2SB is hidden by BIOS and we need to unhide it in
1131 * order to read BAR of the SPI flash device. Once that is
1132 * done we hide it again.
1133 */
1134 pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x0);
1135 pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0,
1136 &spi_base);
1137 if (spi_base != ~0) {
1138 res->start = spi_base & 0xfffffff0;
1139 res->end = res->start + SPIBASE_APL_SZ - 1;
1140
1141 pci_bus_read_config_dword(bus, spi, BCR, &bcr);
1142 if (!(bcr & BCR_WPD)) {
1143 bcr |= BCR_WPD;
1144 pci_bus_write_config_dword(bus, spi, BCR, bcr);
1145 pci_bus_read_config_dword(bus, spi, BCR, &bcr);
1146 }
1147 info->writeable = !!(bcr & BCR_WPD);
1148 }
1149
1150 pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1);
1151 break;
1152 }
1153
ff00d7a3
MW		 1154 default:
1155 return -EINVAL;
1156 }
1157
1158 if (!res->start)
1159 return -ENODEV;
1160
1161 lpc_ich_spi_cell.platform_data = info;
1162 lpc_ich_spi_cell.pdata_size = sizeof(*info);
1163
1164 return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE,
1165 &lpc_ich_spi_cell, 1, NULL, 0, NULL);
1166}
1167
f791be49 1168static int lpc_ich_probe(struct pci_dev *dev,
4630b130
AS		 1169 const struct pci_device_id *id)
1170{
01560f6b 1171 struct lpc_ich_priv *priv;
4630b130
AS		 1172 int ret;
1173 bool cell_added = false;
1174
ff7109fa
AS		 1175 priv = devm_kzalloc(&dev->dev,
1176 sizeof(struct lpc_ich_priv), GFP_KERNEL);
01560f6b
AS		 1177 if (!priv)
1178 return -ENOMEM;
1179
1180 priv->chipset = id->driver_data;
01560f6b 1181
eb71d4de
PT		 1182 priv->actrl_pbase_save = -1;
1183 priv->abase_save = -1;
1184
429b941a 1185 priv->abase = ACPIBASE;
eb71d4de 1186 priv->actrl_pbase = ACPICTRL_PMCBASE;
429b941a
PT		 1187
1188 priv->gctrl_save = -1;
01560f6b 1189 if (priv->chipset <= LPC_ICH5) {
429b941a
PT		 1190 priv->gbase = GPIOBASE_ICH0;
1191 priv->gctrl = GPIOCTRL_ICH0;
01560f6b 1192 } else {
429b941a
PT		 1193 priv->gbase = GPIOBASE_ICH6;
1194 priv->gctrl = GPIOCTRL_ICH6;
01560f6b
AS		 1195 }
1196
1197 pci_set_drvdata(dev, priv);
1198
f0776b8c
PT		 1199 if (lpc_chipset_info[priv->chipset].iTCO_version) {
1200 ret = lpc_ich_init_wdt(dev);
1201 if (!ret)
1202 cell_added = true;
1203 }
887c8ec7 1204
f0776b8c
PT		 1205 if (lpc_chipset_info[priv->chipset].gpio_version) {
1206 ret = lpc_ich_init_gpio(dev);
1207 if (!ret)
1208 cell_added = true;
1209 }
4630b130 1210
ff00d7a3
MW		 1211 if (lpc_chipset_info[priv->chipset].spi_type) {
1212 ret = lpc_ich_init_spi(dev);
1213 if (!ret)
1214 cell_added = true;
1215 }
1216
4630b130
AS		 1217 /*
1218 * We only care if at least one or none of the cells registered
1219 * successfully.
1220 */
1221 if (!cell_added) {
0c418844 1222 dev_warn(&dev->dev, "No MFD cells added\n");
4630b130
AS		 1223 lpc_ich_restore_config_space(dev);
1224 return -ENODEV;
1225 }
1226
1227 return 0;
1228}
1229
4740f73f 1230static void lpc_ich_remove(struct pci_dev *dev)
4630b130
AS		 1231{
1232 mfd_remove_devices(&dev->dev);
1233 lpc_ich_restore_config_space(dev);
1234}
1235
1236static struct pci_driver lpc_ich_driver = {
1237 .name = "lpc_ich",
1238 .id_table = lpc_ich_ids,
1239 .probe = lpc_ich_probe,
84449216 1240 .remove = lpc_ich_remove,
4630b130
AS		 1241};
1242
b4d0fe9c 1243module_pci_driver(lpc_ich_driver);
4630b130
AS		 1244
1245MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
1246MODULE_DESCRIPTION("LPC interface for Intel ICH");
1247MODULE_LICENSE("GPL");
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