[mirror_ubuntu-bionic-kernel.git] / drivers / mfd / max77620.c

/*
 * Maxim MAX77620 MFD Driver
 *
 * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
 *
 * Author:
 *	Laxman Dewangan <ldewangan@nvidia.com>
 *	Chaitanya Bandi <bandik@nvidia.com>
 *	Mallikarjun Kasoju <mkasoju@nvidia.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/****************** Teminology used in driver ********************
 * Here are some terminology used from datasheet for quick reference:
 * Flexible Power Sequence (FPS):
 * The Flexible Power Sequencer (FPS) allows each regulator to power up under
 * hardware or software control. Additionally, each regulator can power on
 * independently or among a group of other regulators with an adjustable
 * power-up and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can
 * be programmed to be part of a sequence allowing external regulators to be
 * sequenced along with internal regulators. 32KHz clock can be programmed to
 * be part of a sequence.
 * There is 3 FPS confguration registers and all resources are configured to
 * any of these FPS or no FPS.
 */

#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/mfd/max77620.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>

static struct resource gpio_resources[] = {
	DEFINE_RES_IRQ(MAX77620_IRQ_TOP_GPIO),
};

static struct resource power_resources[] = {
	DEFINE_RES_IRQ(MAX77620_IRQ_LBT_MBATLOW),
};

static struct resource rtc_resources[] = {
	DEFINE_RES_IRQ(MAX77620_IRQ_TOP_RTC),
};

static struct resource thermal_resources[] = {
	DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM1),
	DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM2),
};

static const struct regmap_irq max77620_top_irqs[] = {
	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GLBL, 0, MAX77620_IRQ_TOP_GLBL_MASK),
	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_SD, 0, MAX77620_IRQ_TOP_SD_MASK),
	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_LDO, 0, MAX77620_IRQ_TOP_LDO_MASK),
	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GPIO, 0, MAX77620_IRQ_TOP_GPIO_MASK),
	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_RTC, 0, MAX77620_IRQ_TOP_RTC_MASK),
	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_32K, 0, MAX77620_IRQ_TOP_32K_MASK),
	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_ONOFF, 0, MAX77620_IRQ_TOP_ONOFF_MASK),
	REGMAP_IRQ_REG(MAX77620_IRQ_LBT_MBATLOW, 1, MAX77620_IRQ_LBM_MASK),
	REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM1, 1, MAX77620_IRQ_TJALRM1_MASK),
	REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM2, 1, MAX77620_IRQ_TJALRM2_MASK),
};

static const struct mfd_cell max77620_children[] = {
	{ .name = "max77620-pinctrl", },
	{ .name = "max77620-clock", },
	{ .name = "max77620-pmic", },
	{ .name = "max77620-watchdog", },
	{
		.name = "max77620-gpio",
		.resources = gpio_resources,
		.num_resources = ARRAY_SIZE(gpio_resources),
	}, {
		.name = "max77620-rtc",
		.resources = rtc_resources,
		.num_resources = ARRAY_SIZE(rtc_resources),
	}, {
		.name = "max77620-power",
		.resources = power_resources,
		.num_resources = ARRAY_SIZE(power_resources),
	}, {
		.name = "max77620-thermal",
		.resources = thermal_resources,
		.num_resources = ARRAY_SIZE(thermal_resources),
	},
};

static const struct mfd_cell max20024_children[] = {
	{ .name = "max20024-pinctrl", },
	{ .name = "max77620-clock", },
	{ .name = "max20024-pmic", },
	{ .name = "max77620-watchdog", },
	{
		.name = "max77620-gpio",
		.resources = gpio_resources,
		.num_resources = ARRAY_SIZE(gpio_resources),
	}, {
		.name = "max77620-rtc",
		.resources = rtc_resources,
		.num_resources = ARRAY_SIZE(rtc_resources),
	}, {
		.name = "max20024-power",
		.resources = power_resources,
		.num_resources = ARRAY_SIZE(power_resources),
	},
};

static struct regmap_irq_chip max77620_top_irq_chip = {
	.name = "max77620-top",
	.irqs = max77620_top_irqs,
	.num_irqs = ARRAY_SIZE(max77620_top_irqs),
	.num_regs = 2,
	.status_base = MAX77620_REG_IRQTOP,
	.mask_base = MAX77620_REG_IRQTOPM,
};

static const struct regmap_range max77620_readable_ranges[] = {
	regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
};

static const struct regmap_access_table max77620_readable_table = {
	.yes_ranges = max77620_readable_ranges,
	.n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges),
};

static const struct regmap_range max20024_readable_ranges[] = {
	regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
	regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD),
};

static const struct regmap_access_table max20024_readable_table = {
	.yes_ranges = max20024_readable_ranges,
	.n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges),
};

static const struct regmap_range max77620_writable_ranges[] = {
	regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
};

static const struct regmap_access_table max77620_writable_table = {
	.yes_ranges = max77620_writable_ranges,
	.n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges),
};

static const struct regmap_range max77620_cacheable_ranges[] = {
	regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3),
	regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3),
};

static const struct regmap_access_table max77620_volatile_table = {
	.no_ranges = max77620_cacheable_ranges,
	.n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges),
};

static const struct regmap_config max77620_regmap_config = {
	.name = "power-slave",
	.reg_bits = 8,
	.val_bits = 8,
	.max_register = MAX77620_REG_DVSSD4 + 1,
	.cache_type = REGCACHE_RBTREE,
	.rd_table = &max77620_readable_table,
	.wr_table = &max77620_writable_table,
	.volatile_table = &max77620_volatile_table,
};

static const struct regmap_config max20024_regmap_config = {
	.name = "power-slave",
	.reg_bits = 8,
	.val_bits = 8,
	.max_register = MAX20024_REG_MAX_ADD + 1,
	.cache_type = REGCACHE_RBTREE,
	.rd_table = &max20024_readable_table,
	.wr_table = &max77620_writable_table,
	.volatile_table = &max77620_volatile_table,
};

/* max77620_get_fps_period_reg_value:  Get FPS bit field value from
 *				       requested periods.
 * MAX77620 supports the FPS period of 40, 80, 160, 320, 540, 1280, 2560
 * and 5120 microseconds. MAX20024 supports the FPS period of 20, 40, 80,
 * 160, 320, 540, 1280 and 2560 microseconds.
 * The FPS register has 3 bits field to set the FPS period as
 * bits		max77620		max20024
 * 000		40			20
 * 001		80			40
 * :::
*/
static int max77620_get_fps_period_reg_value(struct max77620_chip *chip,
					     int tperiod)
{
	int fps_min_period;
	int i;

	switch (chip->chip_id) {
	case MAX20024:
		fps_min_period = MAX20024_FPS_PERIOD_MIN_US;
		break;
	case MAX77620:
		fps_min_period = MAX77620_FPS_PERIOD_MIN_US;
	default:
		return -EINVAL;
	}

	for (i = 0; i < 7; i++) {
		if (fps_min_period >= tperiod)
			return i;
		fps_min_period *= 2;
	}

	return i;
}

/* max77620_config_fps: Configure FPS configuration registers
 *			based on platform specific information.
 */
static int max77620_config_fps(struct max77620_chip *chip,
			       struct device_node *fps_np)
{
	struct device *dev = chip->dev;
	unsigned int mask = 0, config = 0;
	u32 fps_max_period;
	u32 param_val;
	int tperiod, fps_id;
	int ret;
	char fps_name[10];

	switch (chip->chip_id) {
	case MAX20024:
		fps_max_period = MAX20024_FPS_PERIOD_MAX_US;
		break;
	case MAX77620:
		fps_max_period = MAX77620_FPS_PERIOD_MAX_US;
	default:
		return -EINVAL;
	}

	for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
		sprintf(fps_name, "fps%d", fps_id);
		if (!strcmp(fps_np->name, fps_name))
			break;
	}

	if (fps_id == MAX77620_FPS_COUNT) {
		dev_err(dev, "FPS node name %s is not valid\n", fps_np->name);
		return -EINVAL;
	}

	ret = of_property_read_u32(fps_np, "maxim,shutdown-fps-time-period-us",
				   &param_val);
	if (!ret) {
		mask |= MAX77620_FPS_TIME_PERIOD_MASK;
		chip->shutdown_fps_period[fps_id] = min(param_val,
							fps_max_period);
		tperiod = max77620_get_fps_period_reg_value(chip,
				chip->shutdown_fps_period[fps_id]);
		config |= tperiod << MAX77620_FPS_TIME_PERIOD_SHIFT;
	}

	ret = of_property_read_u32(fps_np, "maxim,suspend-fps-time-period-us",
				   &param_val);
	if (!ret)
		chip->suspend_fps_period[fps_id] = min(param_val,
						       fps_max_period);

	ret = of_property_read_u32(fps_np, "maxim,fps-event-source",
				   &param_val);
	if (!ret) {
		if (param_val > 2) {
			dev_err(dev, "FPS%d event-source invalid\n", fps_id);
			return -EINVAL;
		}
		mask |= MAX77620_FPS_EN_SRC_MASK;
		config |= param_val << MAX77620_FPS_EN_SRC_SHIFT;
		if (param_val == 2) {
			mask |= MAX77620_FPS_ENFPS_SW_MASK;
			config |= MAX77620_FPS_ENFPS_SW;
		}
	}

	if (!chip->sleep_enable && !chip->enable_global_lpm) {
		ret = of_property_read_u32(fps_np,
				"maxim,device-state-on-disabled-event",
				&param_val);
		if (!ret) {
			if (param_val == 0)
				chip->sleep_enable = true;
			else if (param_val == 1)
				chip->enable_global_lpm = true;
		}
	}

	ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
				 mask, config);
	if (ret < 0) {
		dev_err(dev, "Failed to update FPS CFG: %d\n", ret);
		return ret;
	}

	return 0;
}

static int max77620_initialise_fps(struct max77620_chip *chip)
{
	struct device *dev = chip->dev;
	struct device_node *fps_np, *fps_child;
	u8 config;
	int fps_id;
	int ret;

	for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
		chip->shutdown_fps_period[fps_id] = -1;
		chip->suspend_fps_period[fps_id] = -1;
	}

	fps_np = of_get_child_by_name(dev->of_node, "fps");
	if (!fps_np)
		goto skip_fps;

	for_each_child_of_node(fps_np, fps_child) {
		ret = max77620_config_fps(chip, fps_child);
		if (ret < 0)
			return ret;
	}

	config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0;
	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
				 MAX77620_ONOFFCNFG2_SLP_LPM_MSK, config);
	if (ret < 0) {
		dev_err(dev, "Failed to update SLP_LPM: %d\n", ret);
		return ret;
	}

skip_fps:
	/* Enable wake on EN0 pin */
	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
				 MAX77620_ONOFFCNFG2_WK_EN0,
				 MAX77620_ONOFFCNFG2_WK_EN0);
	if (ret < 0) {
		dev_err(dev, "Failed to update WK_EN0: %d\n", ret);
		return ret;
	}

	/* For MAX20024, SLPEN will be POR reset if CLRSE is b11 */
	if ((chip->chip_id == MAX20024) && chip->sleep_enable) {
		config = MAX77620_ONOFFCNFG1_SLPEN | MAX20024_ONOFFCNFG1_CLRSE;
		ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
					 config, config);
		if (ret < 0) {
			dev_err(dev, "Failed to update SLPEN: %d\n", ret);
			return ret;
		}
	}

	return 0;
}

static int max77620_read_es_version(struct max77620_chip *chip)
{
	unsigned int val;
	u8 cid_val[6];
	int i;
	int ret;

	for (i = MAX77620_REG_CID0; i <= MAX77620_REG_CID5; i++) {
		ret = regmap_read(chip->rmap, i, &val);
		if (ret < 0) {
			dev_err(chip->dev, "Failed to read CID: %d\n", ret);
			return ret;
		}
		dev_dbg(chip->dev, "CID%d: 0x%02x\n",
			i - MAX77620_REG_CID0, val);
		cid_val[i - MAX77620_REG_CID0] = val;
	}

	/* CID4 is OTP Version  and CID5 is ES version */
	dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%X\n",
		 cid_val[4], MAX77620_CID5_DIDM(cid_val[5]));

	return ret;
}

static int max77620_probe(struct i2c_client *client,
			  const struct i2c_device_id *id)
{
	const struct regmap_config *rmap_config;
	struct max77620_chip *chip;
	const struct mfd_cell *mfd_cells;
	int n_mfd_cells;
	int ret;

	chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	i2c_set_clientdata(client, chip);
	chip->dev = &client->dev;
	chip->irq_base = -1;
	chip->chip_irq = client->irq;
	chip->chip_id = (enum max77620_chip_id)id->driver_data;

	switch (chip->chip_id) {
	case MAX77620:
		mfd_cells = max77620_children;
		n_mfd_cells = ARRAY_SIZE(max77620_children);
		rmap_config = &max77620_regmap_config;
		break;
	case MAX20024:
		mfd_cells = max20024_children;
		n_mfd_cells = ARRAY_SIZE(max20024_children);
		rmap_config = &max20024_regmap_config;
		break;
	default:
		dev_err(chip->dev, "ChipID is invalid %d\n", chip->chip_id);
		return -EINVAL;
	}

	chip->rmap = devm_regmap_init_i2c(client, rmap_config);
	if (IS_ERR(chip->rmap)) {
		ret = PTR_ERR(chip->rmap);
		dev_err(chip->dev, "Failed to intialise regmap: %d\n", ret);
		return ret;
	}

	ret = max77620_read_es_version(chip);
	if (ret < 0)
		return ret;

	ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq,
				       IRQF_ONESHOT | IRQF_SHARED,
				       chip->irq_base, &max77620_top_irq_chip,
				       &chip->top_irq_data);
	if (ret < 0) {
		dev_err(chip->dev, "Failed to add regmap irq: %d\n", ret);
		return ret;
	}

	ret = max77620_initialise_fps(chip);
	if (ret < 0)
		return ret;

	ret =  devm_mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE,
				    mfd_cells, n_mfd_cells, NULL, 0,
				    regmap_irq_get_domain(chip->top_irq_data));
	if (ret < 0) {
		dev_err(chip->dev, "Failed to add MFD children: %d\n", ret);
		return ret;
	}

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int max77620_set_fps_period(struct max77620_chip *chip,
				   int fps_id, int time_period)
{
	int period = max77620_get_fps_period_reg_value(chip, time_period);
	int ret;

	ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
				 MAX77620_FPS_TIME_PERIOD_MASK,
				 period << MAX77620_FPS_TIME_PERIOD_SHIFT);
	if (ret < 0) {
		dev_err(chip->dev, "Failed to update FPS period: %d\n", ret);
		return ret;
	}

	return 0;
}

static int max77620_i2c_suspend(struct device *dev)
{
	struct max77620_chip *chip = dev_get_drvdata(dev);
	struct i2c_client *client = to_i2c_client(dev);
	unsigned int config;
	int fps;
	int ret;

	for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
		if (chip->suspend_fps_period[fps] < 0)
			continue;

		ret = max77620_set_fps_period(chip, fps,
					      chip->suspend_fps_period[fps]);
		if (ret < 0)
			return ret;
	}

	/*
	 * For MAX20024: No need to configure SLPEN on suspend as
	 * it will be configured on Init.
	 */
	if (chip->chip_id == MAX20024)
		goto out;

	config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0;
	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
				 MAX77620_ONOFFCNFG1_SLPEN,
				 config);
	if (ret < 0) {
		dev_err(dev, "Failed to configure sleep in suspend: %d\n", ret);
		return ret;
	}

	/* Disable WK_EN0 */
	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
				 MAX77620_ONOFFCNFG2_WK_EN0, 0);
	if (ret < 0) {
		dev_err(dev, "Failed to configure WK_EN in suspend: %d\n", ret);
		return ret;
	}

out:
	disable_irq(client->irq);

	return 0;
}

static int max77620_i2c_resume(struct device *dev)
{
	struct max77620_chip *chip = dev_get_drvdata(dev);
	struct i2c_client *client = to_i2c_client(dev);
	int ret;
	int fps;

	for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
		if (chip->shutdown_fps_period[fps] < 0)
			continue;

		ret = max77620_set_fps_period(chip, fps,
					      chip->shutdown_fps_period[fps]);
		if (ret < 0)
			return ret;
	}

	/*
	 * For MAX20024: No need to configure WKEN0 on resume as
	 * it is configured on Init.
	 */
	if (chip->chip_id == MAX20024)
		goto out;

	/* Enable WK_EN0 */
	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
				 MAX77620_ONOFFCNFG2_WK_EN0,
				 MAX77620_ONOFFCNFG2_WK_EN0);
	if (ret < 0) {
		dev_err(dev, "Failed to configure WK_EN0 n resume: %d\n", ret);
		return ret;
	}

out:
	enable_irq(client->irq);

	return 0;
}
#endif

static const struct i2c_device_id max77620_id[] = {
	{"max77620", MAX77620},
	{"max20024", MAX20024},
	{},
};

static const struct dev_pm_ops max77620_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(max77620_i2c_suspend, max77620_i2c_resume)
};

static struct i2c_driver max77620_driver = {
	.driver = {
		.name = "max77620",
		.pm = &max77620_pm_ops,
	},
	.probe = max77620_probe,
	.id_table = max77620_id,
};
builtin_i2c_driver(max77620_driver);
Commit	Line	Data
327156c5 LD	1	/*
	2	* Maxim MAX77620 MFD Driver
	3	*
	4	* Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
	5	*
	6	* Author:
	7	* Laxman Dewangan <ldewangan@nvidia.com>
	8	* Chaitanya Bandi <bandik@nvidia.com>
	9	* Mallikarjun Kasoju <mkasoju@nvidia.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	/**************** Teminology used in driver ******************
	17	* Here are some terminology used from datasheet for quick reference:
	18	* Flexible Power Sequence (FPS):
	19	* The Flexible Power Sequencer (FPS) allows each regulator to power up under
	20	* hardware or software control. Additionally, each regulator can power on
	21	* independently or among a group of other regulators with an adjustable
	22	* power-up and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can
	23	* be programmed to be part of a sequence allowing external regulators to be
	24	* sequenced along with internal regulators. 32KHz clock can be programmed to
	25	* be part of a sequence.
	26	* There is 3 FPS confguration registers and all resources are configured to
	27	* any of these FPS or no FPS.
	28	*/
	29
	30	#include <linux/i2c.h>
	31	#include <linux/interrupt.h>
	32	#include <linux/mfd/core.h>
	33	#include <linux/mfd/max77620.h>
c1fe7c45	34	#include <linux/init.h>
327156c5 LD	35	#include <linux/of.h>
	36	#include <linux/of_device.h>
	37	#include <linux/regmap.h>
	38	#include <linux/slab.h>
	39
	40	static struct resource gpio_resources[] = {
	41	DEFINE_RES_IRQ(MAX77620_IRQ_TOP_GPIO),
	42	};
	43
	44	static struct resource power_resources[] = {
	45	DEFINE_RES_IRQ(MAX77620_IRQ_LBT_MBATLOW),
	46	};
	47
	48	static struct resource rtc_resources[] = {
	49	DEFINE_RES_IRQ(MAX77620_IRQ_TOP_RTC),
	50	};
	51
	52	static struct resource thermal_resources[] = {
	53	DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM1),
	54	DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM2),
	55	};
	56
	57	static const struct regmap_irq max77620_top_irqs[] = {
	58	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GLBL, 0, MAX77620_IRQ_TOP_GLBL_MASK),
	59	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_SD, 0, MAX77620_IRQ_TOP_SD_MASK),
	60	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_LDO, 0, MAX77620_IRQ_TOP_LDO_MASK),
	61	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GPIO, 0, MAX77620_IRQ_TOP_GPIO_MASK),
	62	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_RTC, 0, MAX77620_IRQ_TOP_RTC_MASK),
	63	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_32K, 0, MAX77620_IRQ_TOP_32K_MASK),
	64	REGMAP_IRQ_REG(MAX77620_IRQ_TOP_ONOFF, 0, MAX77620_IRQ_TOP_ONOFF_MASK),
	65	REGMAP_IRQ_REG(MAX77620_IRQ_LBT_MBATLOW, 1, MAX77620_IRQ_LBM_MASK),
	66	REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM1, 1, MAX77620_IRQ_TJALRM1_MASK),
	67	REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM2, 1, MAX77620_IRQ_TJALRM2_MASK),
	68	};
	69
	70	static const struct mfd_cell max77620_children[] = {
	71	{ .name = "max77620-pinctrl", },
	72	{ .name = "max77620-clock", },
	73	{ .name = "max77620-pmic", },
	74	{ .name = "max77620-watchdog", },
	75	{
	76	.name = "max77620-gpio",
	77	.resources = gpio_resources,
	78	.num_resources = ARRAY_SIZE(gpio_resources),
	79	}, {
	80	.name = "max77620-rtc",
	81	.resources = rtc_resources,
	82	.num_resources = ARRAY_SIZE(rtc_resources),
	83	}, {
	84	.name = "max77620-power",
	85	.resources = power_resources,
	86	.num_resources = ARRAY_SIZE(power_resources),
	87	}, {
	88	.name = "max77620-thermal",
	89	.resources = thermal_resources,
	90	.num_resources = ARRAY_SIZE(thermal_resources),
	91	},
	92	};
	93
	94	static const struct mfd_cell max20024_children[] = {
	95	{ .name = "max20024-pinctrl", },
	96	{ .name = "max77620-clock", },
	97	{ .name = "max20024-pmic", },
	98	{ .name = "max77620-watchdog", },
99	{
100	.name = "max77620-gpio",
101	.resources = gpio_resources,
102	.num_resources = ARRAY_SIZE(gpio_resources),
103	}, {
104	.name = "max77620-rtc",
105	.resources = rtc_resources,
106	.num_resources = ARRAY_SIZE(rtc_resources),
107	}, {
108	.name = "max20024-power",
109	.resources = power_resources,
110	.num_resources = ARRAY_SIZE(power_resources),
111	},
112	};
113
114	static struct regmap_irq_chip max77620_top_irq_chip = {
115	.name = "max77620-top",
116	.irqs = max77620_top_irqs,
117	.num_irqs = ARRAY_SIZE(max77620_top_irqs),
118	.num_regs = 2,
119	.status_base = MAX77620_REG_IRQTOP,
120	.mask_base = MAX77620_REG_IRQTOPM,
121	};
122
123	static const struct regmap_range max77620_readable_ranges[] = {
124	regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
125	};
126
127	static const struct regmap_access_table max77620_readable_table = {
128	.yes_ranges = max77620_readable_ranges,
129	.n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges),
130	};
131
132	static const struct regmap_range max20024_readable_ranges[] = {
133	regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
134	regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD),
135	};
136
137	static const struct regmap_access_table max20024_readable_table = {
138	.yes_ranges = max20024_readable_ranges,
139	.n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges),
140	};
141
142	static const struct regmap_range max77620_writable_ranges[] = {
143	regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
144	};
145
146	static const struct regmap_access_table max77620_writable_table = {
147	.yes_ranges = max77620_writable_ranges,
148	.n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges),
149	};
150
151	static const struct regmap_range max77620_cacheable_ranges[] = {
152	regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3),
153	regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3),
154	};
155
156	static const struct regmap_access_table max77620_volatile_table = {
157	.no_ranges = max77620_cacheable_ranges,
158	.n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges),
159	};
160
161	static const struct regmap_config max77620_regmap_config = {
162	.name = "power-slave",
163	.reg_bits = 8,
164	.val_bits = 8,
165	.max_register = MAX77620_REG_DVSSD4 + 1,
166	.cache_type = REGCACHE_RBTREE,
167	.rd_table = &max77620_readable_table,
168	.wr_table = &max77620_writable_table,
169	.volatile_table = &max77620_volatile_table,
170	};
171
172	static const struct regmap_config max20024_regmap_config = {
173	.name = "power-slave",
174	.reg_bits = 8,
175	.val_bits = 8,
176	.max_register = MAX20024_REG_MAX_ADD + 1,
177	.cache_type = REGCACHE_RBTREE,
178	.rd_table = &max20024_readable_table,
179	.wr_table = &max77620_writable_table,
180	.volatile_table = &max77620_volatile_table,
181	};
182
183	/* max77620_get_fps_period_reg_value: Get FPS bit field value from
184	* requested periods.
185	* MAX77620 supports the FPS period of 40, 80, 160, 320, 540, 1280, 2560
186	* and 5120 microseconds. MAX20024 supports the FPS period of 20, 40, 80,
187	* 160, 320, 540, 1280 and 2560 microseconds.
188	* The FPS register has 3 bits field to set the FPS period as
189	* bits max77620 max20024
190	* 000 40 20
191	* 001 80 40
192	* :::
193	*/
194	static int max77620_get_fps_period_reg_value(struct max77620_chip *chip,
195	int tperiod)
196	{
197	int fps_min_period;
198	int i;
199
200	switch (chip->chip_id) {
201	case MAX20024:
202	fps_min_period = MAX20024_FPS_PERIOD_MIN_US;
203	break;
204	case MAX77620:
205	fps_min_period = MAX77620_FPS_PERIOD_MIN_US;
206	default:
207	return -EINVAL;
208	}
209
210	for (i = 0; i < 7; i++) {
211	if (fps_min_period >= tperiod)
212	return i;
213	fps_min_period *= 2;
214	}
215
216	return i;
217	}
218
219	/* max77620_config_fps: Configure FPS configuration registers
220	* based on platform specific information.
221	*/
222	static int max77620_config_fps(struct max77620_chip *chip,
223	struct device_node *fps_np)
224	{
225	struct device *dev = chip->dev;
226	unsigned int mask = 0, config = 0;
227	u32 fps_max_period;
228	u32 param_val;
229	int tperiod, fps_id;
230	int ret;
231	char fps_name[10];
232
233	switch (chip->chip_id) {
234	case MAX20024:
235	fps_max_period = MAX20024_FPS_PERIOD_MAX_US;
236	break;
237	case MAX77620:
238	fps_max_period = MAX77620_FPS_PERIOD_MAX_US;
239	default:
240	return -EINVAL;
241	}
242
243	for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
244	sprintf(fps_name, "fps%d", fps_id);
245	if (!strcmp(fps_np->name, fps_name))
246	break;
247	}
248
249	if (fps_id == MAX77620_FPS_COUNT) {
250	dev_err(dev, "FPS node name %s is not valid\n", fps_np->name);
251	return -EINVAL;
252	}
253
254	ret = of_property_read_u32(fps_np, "maxim,shutdown-fps-time-period-us",
255	&param_val);
256	if (!ret) {
257	mask \|= MAX77620_FPS_TIME_PERIOD_MASK;
258	chip->shutdown_fps_period[fps_id] = min(param_val,
259	fps_max_period);
260	tperiod = max77620_get_fps_period_reg_value(chip,
261	chip->shutdown_fps_period[fps_id]);
262	config \|= tperiod << MAX77620_FPS_TIME_PERIOD_SHIFT;
263	}
264
265	ret = of_property_read_u32(fps_np, "maxim,suspend-fps-time-period-us",
266	&param_val);
267	if (!ret)
268	chip->suspend_fps_period[fps_id] = min(param_val,
269	fps_max_period);
270
271	ret = of_property_read_u32(fps_np, "maxim,fps-event-source",
272	&param_val);
273	if (!ret) {
274	if (param_val > 2) {
275	dev_err(dev, "FPS%d event-source invalid\n", fps_id);
276	return -EINVAL;
277	}
278	mask \|= MAX77620_FPS_EN_SRC_MASK;
279	config \|= param_val << MAX77620_FPS_EN_SRC_SHIFT;
280	if (param_val == 2) {
281	mask \|= MAX77620_FPS_ENFPS_SW_MASK;
282	config \|= MAX77620_FPS_ENFPS_SW;
283	}
284	}
285
286	if (!chip->sleep_enable && !chip->enable_global_lpm) {
287	ret = of_property_read_u32(fps_np,
288	"maxim,device-state-on-disabled-event",
289	&param_val);
290	if (!ret) {
291	if (param_val == 0)
292	chip->sleep_enable = true;
293	else if (param_val == 1)
294	chip->enable_global_lpm = true;
295	}
296	}
297
298	ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
299	mask, config);
300	if (ret < 0) {
301	dev_err(dev, "Failed to update FPS CFG: %d\n", ret);
302	return ret;
303	}
304
305	return 0;
306	}
307
308	static int max77620_initialise_fps(struct max77620_chip *chip)
309	{
310	struct device *dev = chip->dev;
311	struct device_node fps_np, fps_child;
312	u8 config;
313	int fps_id;
314	int ret;
315
316	for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
317	chip->shutdown_fps_period[fps_id] = -1;
318	chip->suspend_fps_period[fps_id] = -1;
319	}
320
321	fps_np = of_get_child_by_name(dev->of_node, "fps");
322	if (!fps_np)
323	goto skip_fps;
324
325	for_each_child_of_node(fps_np, fps_child) {
326	ret = max77620_config_fps(chip, fps_child);
327	if (ret < 0)
328	return ret;
329	}
330
331	config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0;
332	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
333	MAX77620_ONOFFCNFG2_SLP_LPM_MSK, config);
334	if (ret < 0) {
335	dev_err(dev, "Failed to update SLP_LPM: %d\n", ret);
336	return ret;
337	}
338
339	skip_fps:
340	/* Enable wake on EN0 pin */
341	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
342	MAX77620_ONOFFCNFG2_WK_EN0,
343	MAX77620_ONOFFCNFG2_WK_EN0);
344	if (ret < 0) {
345	dev_err(dev, "Failed to update WK_EN0: %d\n", ret);
346	return ret;
347	}
348
349	/* For MAX20024, SLPEN will be POR reset if CLRSE is b11 */
350	if ((chip->chip_id == MAX20024) && chip->sleep_enable) {
351	config = MAX77620_ONOFFCNFG1_SLPEN \| MAX20024_ONOFFCNFG1_CLRSE;
352	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
353	config, config);
354	if (ret < 0) {
355	dev_err(dev, "Failed to update SLPEN: %d\n", ret);
356	return ret;
357	}
358	}
359
360	return 0;
361	}
362
363	static int max77620_read_es_version(struct max77620_chip *chip)
364	{
365	unsigned int val;
366	u8 cid_val[6];
367	int i;
368	int ret;
369
370	for (i = MAX77620_REG_CID0; i <= MAX77620_REG_CID5; i++) {
371	ret = regmap_read(chip->rmap, i, &val);
372	if (ret < 0) {
373	dev_err(chip->dev, "Failed to read CID: %d\n", ret);
374	return ret;
375	}
376	dev_dbg(chip->dev, "CID%d: 0x%02x\n",
377	i - MAX77620_REG_CID0, val);
378	cid_val[i - MAX77620_REG_CID0] = val;
379	}
380
381	/* CID4 is OTP Version and CID5 is ES version */
382	dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%X\n",
383	cid_val[4], MAX77620_CID5_DIDM(cid_val[5]));
384
385	return ret;
386	}
387
388	static int max77620_probe(struct i2c_client *client,
389	const struct i2c_device_id *id)
390	{
391	const struct regmap_config *rmap_config;
392	struct max77620_chip *chip;
393	const struct mfd_cell *mfd_cells;
394	int n_mfd_cells;
395	int ret;
396
397	chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
398	if (!chip)
399	return -ENOMEM;
400
401	i2c_set_clientdata(client, chip);
402	chip->dev = &client->dev;
403	chip->irq_base = -1;
404	chip->chip_irq = client->irq;
405	chip->chip_id = (enum max77620_chip_id)id->driver_data;
406
407	switch (chip->chip_id) {
408	case MAX77620:
409	mfd_cells = max77620_children;
410	n_mfd_cells = ARRAY_SIZE(max77620_children);
411	rmap_config = &max77620_regmap_config;
412	break;
413	case MAX20024:
414	mfd_cells = max20024_children;
415	n_mfd_cells = ARRAY_SIZE(max20024_children);
416	rmap_config = &max20024_regmap_config;
417	break;
418	default:
419	dev_err(chip->dev, "ChipID is invalid %d\n", chip->chip_id);
420	return -EINVAL;
421	}
422
423	chip->rmap = devm_regmap_init_i2c(client, rmap_config);
424	if (IS_ERR(chip->rmap)) {
425	ret = PTR_ERR(chip->rmap);
426	dev_err(chip->dev, "Failed to intialise regmap: %d\n", ret);
427	return ret;
428	}
429
430	ret = max77620_read_es_version(chip);
431	if (ret < 0)
432	return ret;
433
434	ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq,
435	IRQF_ONESHOT \| IRQF_SHARED,
436	chip->irq_base, &max77620_top_irq_chip,
437	&chip->top_irq_data);
438	if (ret < 0) {
439	dev_err(chip->dev, "Failed to add regmap irq: %d\n", ret);
440	return ret;
441	}
442
443	ret = max77620_initialise_fps(chip);
444	if (ret < 0)
445	return ret;
446
447	ret = devm_mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE,
448	mfd_cells, n_mfd_cells, NULL, 0,
449	regmap_irq_get_domain(chip->top_irq_data));
450	if (ret < 0) {
451	dev_err(chip->dev, "Failed to add MFD children: %d\n", ret);
452	return ret;
453	}
454
455	return 0;
456	}
457
458	#ifdef CONFIG_PM_SLEEP
459	static int max77620_set_fps_period(struct max77620_chip *chip,
460	int fps_id, int time_period)
461	{
462	int period = max77620_get_fps_period_reg_value(chip, time_period);
463	int ret;
464
465	ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
466	MAX77620_FPS_TIME_PERIOD_MASK,
467	period << MAX77620_FPS_TIME_PERIOD_SHIFT);
468	if (ret < 0) {
469	dev_err(chip->dev, "Failed to update FPS period: %d\n", ret);
470	return ret;
471	}
472
473	return 0;
474	}
475
476	static int max77620_i2c_suspend(struct device *dev)
477	{
478	struct max77620_chip *chip = dev_get_drvdata(dev);
479	struct i2c_client *client = to_i2c_client(dev);
480	unsigned int config;
481	int fps;
482	int ret;
483
484	for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
485	if (chip->suspend_fps_period[fps] < 0)
486	continue;
487
488	ret = max77620_set_fps_period(chip, fps,
489	chip->suspend_fps_period[fps]);
490	if (ret < 0)
491	return ret;
492	}
493
494	/*
495	* For MAX20024: No need to configure SLPEN on suspend as
496	* it will be configured on Init.
497	*/
498	if (chip->chip_id == MAX20024)
499	goto out;
500
501	config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0;
502	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
503	MAX77620_ONOFFCNFG1_SLPEN,
504	config);
505	if (ret < 0) {
506	dev_err(dev, "Failed to configure sleep in suspend: %d\n", ret);
507	return ret;
508	}
509
510	/* Disable WK_EN0 */
511	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
512	MAX77620_ONOFFCNFG2_WK_EN0, 0);
513	if (ret < 0) {
514	dev_err(dev, "Failed to configure WK_EN in suspend: %d\n", ret);
515	return ret;
516	}
517
518	out:
519	disable_irq(client->irq);
520
521	return 0;
522	}
523
524	static int max77620_i2c_resume(struct device *dev)
525	{
526	struct max77620_chip *chip = dev_get_drvdata(dev);
527	struct i2c_client *client = to_i2c_client(dev);
528	int ret;
529	int fps;
530
531	for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
532	if (chip->shutdown_fps_period[fps] < 0)
533	continue;
534
535	ret = max77620_set_fps_period(chip, fps,
536	chip->shutdown_fps_period[fps]);
537	if (ret < 0)
538	return ret;
539	}
540
541	/*
542	* For MAX20024: No need to configure WKEN0 on resume as
543	* it is configured on Init.
544	*/
545	if (chip->chip_id == MAX20024)
546	goto out;
547
548	/* Enable WK_EN0 */
549	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
550	MAX77620_ONOFFCNFG2_WK_EN0,
551	MAX77620_ONOFFCNFG2_WK_EN0);
552	if (ret < 0) {
553	dev_err(dev, "Failed to configure WK_EN0 n resume: %d\n", ret);
554	return ret;
555	}
556
557	out:
558	enable_irq(client->irq);
559
560	return 0;
561	}
562	#endif
563
564	static const struct i2c_device_id max77620_id[] = {
565	{"max77620", MAX77620},
566	{"max20024", MAX20024},
567	{},
568	};
327156c5 LD	569
	570	static const struct dev_pm_ops max77620_pm_ops = {
	571	SET_SYSTEM_SLEEP_PM_OPS(max77620_i2c_suspend, max77620_i2c_resume)
	572	};
	573
	574	static struct i2c_driver max77620_driver = {
	575	.driver = {
	576	.name = "max77620",
	577	.pm = &max77620_pm_ops,
	578	},
	579	.probe = max77620_probe,
	580	.id_table = max77620_id,
	581	};
c1fe7c45	582	builtin_i2c_driver(max77620_driver);