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[mirror_ubuntu-hirsute-kernel.git] / drivers / mfd / max77620.c
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d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
327156c5
LD		 2/*
3 * Maxim MAX77620 MFD Driver
4 *
5 * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Laxman Dewangan <ldewangan@nvidia.com>
9 * Chaitanya Bandi <bandik@nvidia.com>
10 * Mallikarjun Kasoju <mkasoju@nvidia.com>
327156c5
LD		 11 */
12
13/****************** Teminology used in driver ********************
14 * Here are some terminology used from datasheet for quick reference:
15 * Flexible Power Sequence (FPS):
16 * The Flexible Power Sequencer (FPS) allows each regulator to power up under
17 * hardware or software control. Additionally, each regulator can power on
18 * independently or among a group of other regulators with an adjustable
19 * power-up and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can
20 * be programmed to be part of a sequence allowing external regulators to be
21 * sequenced along with internal regulators. 32KHz clock can be programmed to
22 * be part of a sequence.
23 * There is 3 FPS confguration registers and all resources are configured to
24 * any of these FPS or no FPS.
25 */
26
27#include <linux/i2c.h>
28#include <linux/interrupt.h>
29#include <linux/mfd/core.h>
30#include <linux/mfd/max77620.h>
c1fe7c45 31#include <linux/init.h>
327156c5
LD		 32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/regmap.h>
35#include <linux/slab.h>
36
744b1310
DO		 37static struct max77620_chip *max77620_scratch;
38
2be59755 39static const struct resource gpio_resources[] = {
327156c5
LD		 40 DEFINE_RES_IRQ(MAX77620_IRQ_TOP_GPIO),
41};
42
2be59755 43static const struct resource power_resources[] = {
327156c5
LD		 44 DEFINE_RES_IRQ(MAX77620_IRQ_LBT_MBATLOW),
45};
46
2be59755 47static const struct resource rtc_resources[] = {
327156c5
LD		 48 DEFINE_RES_IRQ(MAX77620_IRQ_TOP_RTC),
49};
50
2be59755 51static const struct resource thermal_resources[] = {
327156c5
LD		 52 DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM1),
53 DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM2),
54};
55
56static const struct regmap_irq max77620_top_irqs[] = {
57 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GLBL, 0, MAX77620_IRQ_TOP_GLBL_MASK),
58 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_SD, 0, MAX77620_IRQ_TOP_SD_MASK),
59 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_LDO, 0, MAX77620_IRQ_TOP_LDO_MASK),
60 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GPIO, 0, MAX77620_IRQ_TOP_GPIO_MASK),
61 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_RTC, 0, MAX77620_IRQ_TOP_RTC_MASK),
62 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_32K, 0, MAX77620_IRQ_TOP_32K_MASK),
63 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_ONOFF, 0, MAX77620_IRQ_TOP_ONOFF_MASK),
64 REGMAP_IRQ_REG(MAX77620_IRQ_LBT_MBATLOW, 1, MAX77620_IRQ_LBM_MASK),
65 REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM1, 1, MAX77620_IRQ_TJALRM1_MASK),
66 REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM2, 1, MAX77620_IRQ_TJALRM2_MASK),
67};
68
69static const struct mfd_cell max77620_children[] = {
70 { .name = "max77620-pinctrl", },
71 { .name = "max77620-clock", },
72 { .name = "max77620-pmic", },
73 { .name = "max77620-watchdog", },
74 {
75 .name = "max77620-gpio",
76 .resources = gpio_resources,
77 .num_resources = ARRAY_SIZE(gpio_resources),
78 }, {
79 .name = "max77620-rtc",
80 .resources = rtc_resources,
81 .num_resources = ARRAY_SIZE(rtc_resources),
82 }, {
83 .name = "max77620-power",
84 .resources = power_resources,
85 .num_resources = ARRAY_SIZE(power_resources),
86 }, {
87 .name = "max77620-thermal",
88 .resources = thermal_resources,
89 .num_resources = ARRAY_SIZE(thermal_resources),
90 },
91};
92
93static const struct mfd_cell max20024_children[] = {
94 { .name = "max20024-pinctrl", },
95 { .name = "max77620-clock", },
96 { .name = "max20024-pmic", },
97 { .name = "max77620-watchdog", },
98 {
99 .name = "max77620-gpio",
100 .resources = gpio_resources,
101 .num_resources = ARRAY_SIZE(gpio_resources),
102 }, {
103 .name = "max77620-rtc",
104 .resources = rtc_resources,
105 .num_resources = ARRAY_SIZE(rtc_resources),
106 }, {
107 .name = "max20024-power",
108 .resources = power_resources,
109 .num_resources = ARRAY_SIZE(power_resources),
110 },
111};
112
4c58f701
DO		 113static const struct mfd_cell max77663_children[] = {
114 { .name = "max77620-pinctrl", },
115 { .name = "max77620-clock", },
116 { .name = "max77663-pmic", },
117 { .name = "max77620-watchdog", },
118 {
119 .name = "max77620-gpio",
120 .resources = gpio_resources,
121 .num_resources = ARRAY_SIZE(gpio_resources),
122 }, {
123 .name = "max77620-rtc",
124 .resources = rtc_resources,
125 .num_resources = ARRAY_SIZE(rtc_resources),
126 }, {
127 .name = "max77663-power",
128 .resources = power_resources,
129 .num_resources = ARRAY_SIZE(power_resources),
130 },
131};
132
327156c5
LD		 133static const struct regmap_range max77620_readable_ranges[] = {
134 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
135};
136
137static const struct regmap_access_table max77620_readable_table = {
138 .yes_ranges = max77620_readable_ranges,
139 .n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges),
140};
141
142static const struct regmap_range max20024_readable_ranges[] = {
143 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
144 regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD),
145};
146
147static const struct regmap_access_table max20024_readable_table = {
148 .yes_ranges = max20024_readable_ranges,
149 .n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges),
150};
151
152static const struct regmap_range max77620_writable_ranges[] = {
153 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
154};
155
156static const struct regmap_access_table max77620_writable_table = {
157 .yes_ranges = max77620_writable_ranges,
158 .n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges),
159};
160
161static const struct regmap_range max77620_cacheable_ranges[] = {
162 regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3),
163 regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3),
164};
165
166static const struct regmap_access_table max77620_volatile_table = {
167 .no_ranges = max77620_cacheable_ranges,
168 .n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges),
169};
170
171static const struct regmap_config max77620_regmap_config = {
172 .name = "power-slave",
173 .reg_bits = 8,
174 .val_bits = 8,
175 .max_register = MAX77620_REG_DVSSD4 + 1,
176 .cache_type = REGCACHE_RBTREE,
177 .rd_table = &max77620_readable_table,
178 .wr_table = &max77620_writable_table,
179 .volatile_table = &max77620_volatile_table,
180};
181
182static const struct regmap_config max20024_regmap_config = {
183 .name = "power-slave",
184 .reg_bits = 8,
185 .val_bits = 8,
186 .max_register = MAX20024_REG_MAX_ADD + 1,
187 .cache_type = REGCACHE_RBTREE,
188 .rd_table = &max20024_readable_table,
189 .wr_table = &max77620_writable_table,
190 .volatile_table = &max77620_volatile_table,
191};
192
4c58f701
DO		 193static const struct regmap_range max77663_readable_ranges[] = {
194 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5),
195};
196
197static const struct regmap_access_table max77663_readable_table = {
198 .yes_ranges = max77663_readable_ranges,
199 .n_yes_ranges = ARRAY_SIZE(max77663_readable_ranges),
200};
201
202static const struct regmap_range max77663_writable_ranges[] = {
203 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5),
204};
205
206static const struct regmap_access_table max77663_writable_table = {
207 .yes_ranges = max77663_writable_ranges,
208 .n_yes_ranges = ARRAY_SIZE(max77663_writable_ranges),
209};
210
211static const struct regmap_config max77663_regmap_config = {
212 .name = "power-slave",
213 .reg_bits = 8,
214 .val_bits = 8,
215 .max_register = MAX77620_REG_CID5 + 1,
216 .cache_type = REGCACHE_RBTREE,
217 .rd_table = &max77663_readable_table,
218 .wr_table = &max77663_writable_table,
219 .volatile_table = &max77620_volatile_table,
220};
221
3df140d1
LD		 222/*
223 * MAX77620 and MAX20024 has the following steps of the interrupt handling
224 * for TOP interrupts:
225 * 1. When interrupt occurs from PMIC, mask the PMIC interrupt by setting GLBLM.
226 * 2. Read IRQTOP and service the interrupt.
227 * 3. Once all interrupts has been checked and serviced, the interrupt service
228 * routine un-masks the hardware interrupt line by clearing GLBLM.
229 */
230static int max77620_irq_global_mask(void *irq_drv_data)
231{
232 struct max77620_chip *chip = irq_drv_data;
233 int ret;
234
235 ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT,
236 MAX77620_GLBLM_MASK, MAX77620_GLBLM_MASK);
237 if (ret < 0)
238 dev_err(chip->dev, "Failed to set GLBLM: %d\n", ret);
239
240 return ret;
241}
242
243static int max77620_irq_global_unmask(void *irq_drv_data)
244{
245 struct max77620_chip *chip = irq_drv_data;
246 int ret;
247
248 ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT,
249 MAX77620_GLBLM_MASK, 0);
250 if (ret < 0)
251 dev_err(chip->dev, "Failed to reset GLBLM: %d\n", ret);
252
253 return ret;
254}
255
256static struct regmap_irq_chip max77620_top_irq_chip = {
257 .name = "max77620-top",
258 .irqs = max77620_top_irqs,
259 .num_irqs = ARRAY_SIZE(max77620_top_irqs),
260 .num_regs = 2,
261 .status_base = MAX77620_REG_IRQTOP,
262 .mask_base = MAX77620_REG_IRQTOPM,
263 .handle_pre_irq = max77620_irq_global_mask,
264 .handle_post_irq = max77620_irq_global_unmask,
265};
266
327156c5
LD		 267/* max77620_get_fps_period_reg_value: Get FPS bit field value from
268 * requested periods.
269 * MAX77620 supports the FPS period of 40, 80, 160, 320, 540, 1280, 2560
270 * and 5120 microseconds. MAX20024 supports the FPS period of 20, 40, 80,
271 * 160, 320, 540, 1280 and 2560 microseconds.
272 * The FPS register has 3 bits field to set the FPS period as
273 * bits max77620 max20024
274 * 000 40 20
275 * 001 80 40
276 * :::
277*/
278static int max77620_get_fps_period_reg_value(struct max77620_chip *chip,
279 int tperiod)
280{
281 int fps_min_period;
282 int i;
283
284 switch (chip->chip_id) {
285 case MAX20024:
286 fps_min_period = MAX20024_FPS_PERIOD_MIN_US;
287 break;
288 case MAX77620:
289 fps_min_period = MAX77620_FPS_PERIOD_MIN_US;
82d8eb40 290 break;
4c58f701
DO		 291 case MAX77663:
292 fps_min_period = MAX20024_FPS_PERIOD_MIN_US;
293 break;
327156c5
LD		 294 default:
295 return -EINVAL;
296 }
297
298 for (i = 0; i < 7; i++) {
299 if (fps_min_period >= tperiod)
300 return i;
301 fps_min_period *= 2;
302 }
303
304 return i;
305}
306
307/* max77620_config_fps: Configure FPS configuration registers
308 * based on platform specific information.
309 */
310static int max77620_config_fps(struct max77620_chip *chip,
311 struct device_node *fps_np)
312{
313 struct device *dev = chip->dev;
314 unsigned int mask = 0, config = 0;
315 u32 fps_max_period;
316 u32 param_val;
317 int tperiod, fps_id;
318 int ret;
319 char fps_name[10];
320
321 switch (chip->chip_id) {
322 case MAX20024:
323 fps_max_period = MAX20024_FPS_PERIOD_MAX_US;
324 break;
325 case MAX77620:
326 fps_max_period = MAX77620_FPS_PERIOD_MAX_US;
82d8eb40 327 break;
4c58f701
DO		 328 case MAX77663:
329 fps_max_period = MAX20024_FPS_PERIOD_MAX_US;
330 break;
327156c5
LD		 331 default:
332 return -EINVAL;
333 }
334
335 for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
336 sprintf(fps_name, "fps%d", fps_id);
38df91cc 337 if (of_node_name_eq(fps_np, fps_name))
327156c5
LD		 338 break;
339 }
340
341 if (fps_id == MAX77620_FPS_COUNT) {
75a11072 342 dev_err(dev, "FPS node name %pOFn is not valid\n", fps_np);
327156c5
LD		 343 return -EINVAL;
344 }
345
346 ret = of_property_read_u32(fps_np, "maxim,shutdown-fps-time-period-us",
347 &param_val);
348 if (!ret) {
349 mask |= MAX77620_FPS_TIME_PERIOD_MASK;
350 chip->shutdown_fps_period[fps_id] = min(param_val,
351 fps_max_period);
352 tperiod = max77620_get_fps_period_reg_value(chip,
353 chip->shutdown_fps_period[fps_id]);
354 config |= tperiod << MAX77620_FPS_TIME_PERIOD_SHIFT;
355 }
356
357 ret = of_property_read_u32(fps_np, "maxim,suspend-fps-time-period-us",
358 &param_val);
359 if (!ret)
360 chip->suspend_fps_period[fps_id] = min(param_val,
361 fps_max_period);
362
363 ret = of_property_read_u32(fps_np, "maxim,fps-event-source",
364 &param_val);
365 if (!ret) {
366 if (param_val > 2) {
367 dev_err(dev, "FPS%d event-source invalid\n", fps_id);
368 return -EINVAL;
369 }
370 mask |= MAX77620_FPS_EN_SRC_MASK;
371 config |= param_val << MAX77620_FPS_EN_SRC_SHIFT;
372 if (param_val == 2) {
373 mask |= MAX77620_FPS_ENFPS_SW_MASK;
374 config |= MAX77620_FPS_ENFPS_SW;
375 }
376 }
377
378 if (!chip->sleep_enable && !chip->enable_global_lpm) {
379 ret = of_property_read_u32(fps_np,
380 "maxim,device-state-on-disabled-event",
381 &param_val);
382 if (!ret) {
383 if (param_val == 0)
384 chip->sleep_enable = true;
385 else if (param_val == 1)
386 chip->enable_global_lpm = true;
387 }
388 }
389
390 ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
391 mask, config);
392 if (ret < 0) {
393 dev_err(dev, "Failed to update FPS CFG: %d\n", ret);
394 return ret;
395 }
396
397 return 0;
398}
399
400static int max77620_initialise_fps(struct max77620_chip *chip)
401{
402 struct device *dev = chip->dev;
403 struct device_node *fps_np, *fps_child;
404 u8 config;
405 int fps_id;
406 int ret;
407
408 for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
409 chip->shutdown_fps_period[fps_id] = -1;
410 chip->suspend_fps_period[fps_id] = -1;
411 }
412
413 fps_np = of_get_child_by_name(dev->of_node, "fps");
414 if (!fps_np)
415 goto skip_fps;
416
417 for_each_child_of_node(fps_np, fps_child) {
418 ret = max77620_config_fps(chip, fps_child);
197df18f
ND		 419 if (ret < 0) {
420 of_node_put(fps_child);
327156c5 421 return ret;
197df18f 422 }
327156c5
LD		 423 }
424
425 config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0;
426 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
427 MAX77620_ONOFFCNFG2_SLP_LPM_MSK, config);
428 if (ret < 0) {
429 dev_err(dev, "Failed to update SLP_LPM: %d\n", ret);
430 return ret;
431 }
432
433skip_fps:
4c58f701
DO		 434 if (chip->chip_id == MAX77663)
435 return 0;
436
327156c5
LD		 437 /* Enable wake on EN0 pin */
438 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
439 MAX77620_ONOFFCNFG2_WK_EN0,
440 MAX77620_ONOFFCNFG2_WK_EN0);
441 if (ret < 0) {
442 dev_err(dev, "Failed to update WK_EN0: %d\n", ret);
443 return ret;
444 }
445
446 /* For MAX20024, SLPEN will be POR reset if CLRSE is b11 */
447 if ((chip->chip_id == MAX20024) && chip->sleep_enable) {
448 config = MAX77620_ONOFFCNFG1_SLPEN | MAX20024_ONOFFCNFG1_CLRSE;
449 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
450 config, config);
451 if (ret < 0) {
452 dev_err(dev, "Failed to update SLPEN: %d\n", ret);
453 return ret;
454 }
455 }
456
457 return 0;
458}
459
460static int max77620_read_es_version(struct max77620_chip *chip)
461{
462 unsigned int val;
463 u8 cid_val[6];
464 int i;
465 int ret;
466
467 for (i = MAX77620_REG_CID0; i <= MAX77620_REG_CID5; i++) {
468 ret = regmap_read(chip->rmap, i, &val);
469 if (ret < 0) {
470 dev_err(chip->dev, "Failed to read CID: %d\n", ret);
471 return ret;
472 }
473 dev_dbg(chip->dev, "CID%d: 0x%02x\n",
474 i - MAX77620_REG_CID0, val);
475 cid_val[i - MAX77620_REG_CID0] = val;
476 }
477
478 /* CID4 is OTP Version and CID5 is ES version */
479 dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%X\n",
480 cid_val[4], MAX77620_CID5_DIDM(cid_val[5]));
481
482 return ret;
483}
484
744b1310
DO		 485static void max77620_pm_power_off(void)
486{
487 struct max77620_chip *chip = max77620_scratch;
488
489 regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
490 MAX77620_ONOFFCNFG1_SFT_RST,
491 MAX77620_ONOFFCNFG1_SFT_RST);
492}
493
327156c5
LD		 494static int max77620_probe(struct i2c_client *client,
495 const struct i2c_device_id *id)
496{
497 const struct regmap_config *rmap_config;
498 struct max77620_chip *chip;
499 const struct mfd_cell *mfd_cells;
500 int n_mfd_cells;
744b1310 501 bool pm_off;
327156c5
LD		 502 int ret;
503
504 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
505 if (!chip)
506 return -ENOMEM;
507
508 i2c_set_clientdata(client, chip);
509 chip->dev = &client->dev;
327156c5
LD		 510 chip->chip_irq = client->irq;
511 chip->chip_id = (enum max77620_chip_id)id->driver_data;
512
513 switch (chip->chip_id) {
514 case MAX77620:
515 mfd_cells = max77620_children;
516 n_mfd_cells = ARRAY_SIZE(max77620_children);
517 rmap_config = &max77620_regmap_config;
518 break;
519 case MAX20024:
520 mfd_cells = max20024_children;
521 n_mfd_cells = ARRAY_SIZE(max20024_children);
522 rmap_config = &max20024_regmap_config;
523 break;
4c58f701
DO		 524 case MAX77663:
525 mfd_cells = max77663_children;
526 n_mfd_cells = ARRAY_SIZE(max77663_children);
527 rmap_config = &max77663_regmap_config;
528 break;
327156c5
LD		 529 default:
530 dev_err(chip->dev, "ChipID is invalid %d\n", chip->chip_id);
531 return -EINVAL;
532 }
533
534 chip->rmap = devm_regmap_init_i2c(client, rmap_config);
535 if (IS_ERR(chip->rmap)) {
536 ret = PTR_ERR(chip->rmap);
9165dabb 537 dev_err(chip->dev, "Failed to initialise regmap: %d\n", ret);
327156c5
LD		 538 return ret;
539 }
540
541 ret = max77620_read_es_version(chip);
542 if (ret < 0)
543 return ret;
544
3df140d1 545 max77620_top_irq_chip.irq_drv_data = chip;
327156c5 546 ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq,
7f0e60c7
TR		 547 IRQF_ONESHOT | IRQF_SHARED, 0,
548 &max77620_top_irq_chip,
327156c5
LD		 549 &chip->top_irq_data);
550 if (ret < 0) {
551 dev_err(chip->dev, "Failed to add regmap irq: %d\n", ret);
552 return ret;
553 }
554
555 ret = max77620_initialise_fps(chip);
556 if (ret < 0)
557 return ret;
558
559 ret = devm_mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE,
560 mfd_cells, n_mfd_cells, NULL, 0,
561 regmap_irq_get_domain(chip->top_irq_data));
562 if (ret < 0) {
563 dev_err(chip->dev, "Failed to add MFD children: %d\n", ret);
564 return ret;
565 }
566
744b1310
DO		 567 pm_off = of_device_is_system_power_controller(client->dev.of_node);
568 if (pm_off && !pm_power_off) {
569 max77620_scratch = chip;
570 pm_power_off = max77620_pm_power_off;
571 }
572
327156c5
LD		 573 return 0;
574}
575
576#ifdef CONFIG_PM_SLEEP
577static int max77620_set_fps_period(struct max77620_chip *chip,
578 int fps_id, int time_period)
579{
580 int period = max77620_get_fps_period_reg_value(chip, time_period);
581 int ret;
582
583 ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
584 MAX77620_FPS_TIME_PERIOD_MASK,
585 period << MAX77620_FPS_TIME_PERIOD_SHIFT);
586 if (ret < 0) {
587 dev_err(chip->dev, "Failed to update FPS period: %d\n", ret);
588 return ret;
589 }
590
591 return 0;
592}
593
594static int max77620_i2c_suspend(struct device *dev)
595{
596 struct max77620_chip *chip = dev_get_drvdata(dev);
597 struct i2c_client *client = to_i2c_client(dev);
598 unsigned int config;
599 int fps;
600 int ret;
601
602 for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
603 if (chip->suspend_fps_period[fps] < 0)
604 continue;
605
606 ret = max77620_set_fps_period(chip, fps,
607 chip->suspend_fps_period[fps]);
608 if (ret < 0)
609 return ret;
610 }
611
612 /*
613 * For MAX20024: No need to configure SLPEN on suspend as
614 * it will be configured on Init.
615 */
616 if (chip->chip_id == MAX20024)
617 goto out;
618
619 config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0;
620 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
621 MAX77620_ONOFFCNFG1_SLPEN,
622 config);
623 if (ret < 0) {
624 dev_err(dev, "Failed to configure sleep in suspend: %d\n", ret);
625 return ret;
626 }
627
4c58f701
DO		 628 if (chip->chip_id == MAX77663)
629 goto out;
630
327156c5
LD		 631 /* Disable WK_EN0 */
632 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
633 MAX77620_ONOFFCNFG2_WK_EN0, 0);
634 if (ret < 0) {
635 dev_err(dev, "Failed to configure WK_EN in suspend: %d\n", ret);
636 return ret;
637 }
638
639out:
640 disable_irq(client->irq);
641
642 return 0;
643}
644
645static int max77620_i2c_resume(struct device *dev)
646{
647 struct max77620_chip *chip = dev_get_drvdata(dev);
648 struct i2c_client *client = to_i2c_client(dev);
649 int ret;
650 int fps;
651
652 for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
653 if (chip->shutdown_fps_period[fps] < 0)
654 continue;
655
656 ret = max77620_set_fps_period(chip, fps,
657 chip->shutdown_fps_period[fps]);
658 if (ret < 0)
659 return ret;
660 }
661
662 /*
663 * For MAX20024: No need to configure WKEN0 on resume as
664 * it is configured on Init.
665 */
4c58f701 666 if (chip->chip_id == MAX20024 || chip->chip_id == MAX77663)
327156c5
LD		 667 goto out;
668
669 /* Enable WK_EN0 */
670 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
671 MAX77620_ONOFFCNFG2_WK_EN0,
672 MAX77620_ONOFFCNFG2_WK_EN0);
673 if (ret < 0) {
674 dev_err(dev, "Failed to configure WK_EN0 n resume: %d\n", ret);
675 return ret;
676 }
677
678out:
679 enable_irq(client->irq);
680
681 return 0;
682}
683#endif
684
685static const struct i2c_device_id max77620_id[] = {
686 {"max77620", MAX77620},
687 {"max20024", MAX20024},
4c58f701 688 {"max77663", MAX77663},
327156c5
LD		 689 {},
690};
327156c5
LD		 691
692static const struct dev_pm_ops max77620_pm_ops = {
693 SET_SYSTEM_SLEEP_PM_OPS(max77620_i2c_suspend, max77620_i2c_resume)
694};
695
696static struct i2c_driver max77620_driver = {
697 .driver = {
698 .name = "max77620",
699 .pm = &max77620_pm_ops,
700 },
701 .probe = max77620_probe,
702 .id_table = max77620_id,
703};
c1fe7c45 704builtin_i2c_driver(max77620_driver);
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