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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lliubbo...
[mirror_ubuntu-bionic-kernel.git] / drivers / mfd / mc13xxx-core.c
CommitLineData
8e005935
UKK		 1/*
2 * Copyright 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * loosely based on an earlier driver that has
6 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
7 *
8 * This program is free software; you can redistribute it and/or modify it under
9 * the terms of the GNU General Public License version 2 as published by the
10 * Free Software Foundation.
11 */
8e005935
UKK		 12
13#include <linux/slab.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/mutex.h>
17#include <linux/interrupt.h>
18#include <linux/spi/spi.h>
19#include <linux/mfd/core.h>
20#include <linux/mfd/mc13xxx.h>
876989d5
SG		 21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/of_gpio.h>
8e005935
UKK		 24
25struct mc13xxx {
26 struct spi_device *spidev;
27 struct mutex lock;
28 int irq;
876989d5 29 int flags;
8e005935
UKK		 30
31 irq_handler_t irqhandler[MC13XXX_NUM_IRQ];
32 void *irqdata[MC13XXX_NUM_IRQ];
fec316d6
UKK		 33
34 int adcflags;
8e005935
UKK		 35};
36
8e005935
UKK		 37#define MC13XXX_IRQSTAT0 0
38#define MC13XXX_IRQSTAT0_ADCDONEI (1 << 0)
39#define MC13XXX_IRQSTAT0_ADCBISDONEI (1 << 1)
40#define MC13XXX_IRQSTAT0_TSI (1 << 2)
41#define MC13783_IRQSTAT0_WHIGHI (1 << 3)
42#define MC13783_IRQSTAT0_WLOWI (1 << 4)
43#define MC13XXX_IRQSTAT0_CHGDETI (1 << 6)
44#define MC13783_IRQSTAT0_CHGOVI (1 << 7)
45#define MC13XXX_IRQSTAT0_CHGREVI (1 << 8)
46#define MC13XXX_IRQSTAT0_CHGSHORTI (1 << 9)
47#define MC13XXX_IRQSTAT0_CCCVI (1 << 10)
48#define MC13XXX_IRQSTAT0_CHGCURRI (1 << 11)
49#define MC13XXX_IRQSTAT0_BPONI (1 << 12)
50#define MC13XXX_IRQSTAT0_LOBATLI (1 << 13)
51#define MC13XXX_IRQSTAT0_LOBATHI (1 << 14)
52#define MC13783_IRQSTAT0_UDPI (1 << 15)
53#define MC13783_IRQSTAT0_USBI (1 << 16)
54#define MC13783_IRQSTAT0_IDI (1 << 19)
55#define MC13783_IRQSTAT0_SE1I (1 << 21)
56#define MC13783_IRQSTAT0_CKDETI (1 << 22)
57#define MC13783_IRQSTAT0_UDMI (1 << 23)
58
59#define MC13XXX_IRQMASK0 1
60#define MC13XXX_IRQMASK0_ADCDONEM MC13XXX_IRQSTAT0_ADCDONEI
61#define MC13XXX_IRQMASK0_ADCBISDONEM MC13XXX_IRQSTAT0_ADCBISDONEI
62#define MC13XXX_IRQMASK0_TSM MC13XXX_IRQSTAT0_TSI
63#define MC13783_IRQMASK0_WHIGHM MC13783_IRQSTAT0_WHIGHI
64#define MC13783_IRQMASK0_WLOWM MC13783_IRQSTAT0_WLOWI
65#define MC13XXX_IRQMASK0_CHGDETM MC13XXX_IRQSTAT0_CHGDETI
66#define MC13783_IRQMASK0_CHGOVM MC13783_IRQSTAT0_CHGOVI
67#define MC13XXX_IRQMASK0_CHGREVM MC13XXX_IRQSTAT0_CHGREVI
68#define MC13XXX_IRQMASK0_CHGSHORTM MC13XXX_IRQSTAT0_CHGSHORTI
69#define MC13XXX_IRQMASK0_CCCVM MC13XXX_IRQSTAT0_CCCVI
70#define MC13XXX_IRQMASK0_CHGCURRM MC13XXX_IRQSTAT0_CHGCURRI
71#define MC13XXX_IRQMASK0_BPONM MC13XXX_IRQSTAT0_BPONI
72#define MC13XXX_IRQMASK0_LOBATLM MC13XXX_IRQSTAT0_LOBATLI
73#define MC13XXX_IRQMASK0_LOBATHM MC13XXX_IRQSTAT0_LOBATHI
74#define MC13783_IRQMASK0_UDPM MC13783_IRQSTAT0_UDPI
75#define MC13783_IRQMASK0_USBM MC13783_IRQSTAT0_USBI
76#define MC13783_IRQMASK0_IDM MC13783_IRQSTAT0_IDI
77#define MC13783_IRQMASK0_SE1M MC13783_IRQSTAT0_SE1I
78#define MC13783_IRQMASK0_CKDETM MC13783_IRQSTAT0_CKDETI
79#define MC13783_IRQMASK0_UDMM MC13783_IRQSTAT0_UDMI
80
81#define MC13XXX_IRQSTAT1 3
82#define MC13XXX_IRQSTAT1_1HZI (1 << 0)
83#define MC13XXX_IRQSTAT1_TODAI (1 << 1)
84#define MC13783_IRQSTAT1_ONOFD1I (1 << 3)
85#define MC13783_IRQSTAT1_ONOFD2I (1 << 4)
86#define MC13783_IRQSTAT1_ONOFD3I (1 << 5)
87#define MC13XXX_IRQSTAT1_SYSRSTI (1 << 6)
88#define MC13XXX_IRQSTAT1_RTCRSTI (1 << 7)
89#define MC13XXX_IRQSTAT1_PCI (1 << 8)
90#define MC13XXX_IRQSTAT1_WARMI (1 << 9)
91#define MC13XXX_IRQSTAT1_MEMHLDI (1 << 10)
92#define MC13783_IRQSTAT1_PWRRDYI (1 << 11)
93#define MC13XXX_IRQSTAT1_THWARNLI (1 << 12)
94#define MC13XXX_IRQSTAT1_THWARNHI (1 << 13)
95#define MC13XXX_IRQSTAT1_CLKI (1 << 14)
96#define MC13783_IRQSTAT1_SEMAFI (1 << 15)
97#define MC13783_IRQSTAT1_MC2BI (1 << 17)
98#define MC13783_IRQSTAT1_HSDETI (1 << 18)
99#define MC13783_IRQSTAT1_HSLI (1 << 19)
100#define MC13783_IRQSTAT1_ALSPTHI (1 << 20)
101#define MC13783_IRQSTAT1_AHSSHORTI (1 << 21)
102
103#define MC13XXX_IRQMASK1 4
104#define MC13XXX_IRQMASK1_1HZM MC13XXX_IRQSTAT1_1HZI
105#define MC13XXX_IRQMASK1_TODAM MC13XXX_IRQSTAT1_TODAI
106#define MC13783_IRQMASK1_ONOFD1M MC13783_IRQSTAT1_ONOFD1I
107#define MC13783_IRQMASK1_ONOFD2M MC13783_IRQSTAT1_ONOFD2I
108#define MC13783_IRQMASK1_ONOFD3M MC13783_IRQSTAT1_ONOFD3I
109#define MC13XXX_IRQMASK1_SYSRSTM MC13XXX_IRQSTAT1_SYSRSTI
110#define MC13XXX_IRQMASK1_RTCRSTM MC13XXX_IRQSTAT1_RTCRSTI
111#define MC13XXX_IRQMASK1_PCM MC13XXX_IRQSTAT1_PCI
112#define MC13XXX_IRQMASK1_WARMM MC13XXX_IRQSTAT1_WARMI
113#define MC13XXX_IRQMASK1_MEMHLDM MC13XXX_IRQSTAT1_MEMHLDI
114#define MC13783_IRQMASK1_PWRRDYM MC13783_IRQSTAT1_PWRRDYI
115#define MC13XXX_IRQMASK1_THWARNLM MC13XXX_IRQSTAT1_THWARNLI
116#define MC13XXX_IRQMASK1_THWARNHM MC13XXX_IRQSTAT1_THWARNHI
117#define MC13XXX_IRQMASK1_CLKM MC13XXX_IRQSTAT1_CLKI
118#define MC13783_IRQMASK1_SEMAFM MC13783_IRQSTAT1_SEMAFI
119#define MC13783_IRQMASK1_MC2BM MC13783_IRQSTAT1_MC2BI
120#define MC13783_IRQMASK1_HSDETM MC13783_IRQSTAT1_HSDETI
121#define MC13783_IRQMASK1_HSLM MC13783_IRQSTAT1_HSLI
122#define MC13783_IRQMASK1_ALSPTHM MC13783_IRQSTAT1_ALSPTHI
123#define MC13783_IRQMASK1_AHSSHORTM MC13783_IRQSTAT1_AHSSHORTI
124
125#define MC13XXX_REVISION 7
126#define MC13XXX_REVISION_REVMETAL (0x07 << 0)
127#define MC13XXX_REVISION_REVFULL (0x03 << 3)
128#define MC13XXX_REVISION_ICID (0x07 << 6)
129#define MC13XXX_REVISION_FIN (0x03 << 9)
130#define MC13XXX_REVISION_FAB (0x03 << 11)
131#define MC13XXX_REVISION_ICIDCODE (0x3f << 13)
132
fec316d6
UKK		 133#define MC13XXX_ADC1 44
134#define MC13XXX_ADC1_ADEN (1 << 0)
135#define MC13XXX_ADC1_RAND (1 << 1)
136#define MC13XXX_ADC1_ADSEL (1 << 3)
137#define MC13XXX_ADC1_ASC (1 << 20)
138#define MC13XXX_ADC1_ADTRIGIGN (1 << 21)
8e005935 139
fec316d6 140#define MC13XXX_ADC2 45
8e005935
UKK		 141
142#define MC13XXX_NUMREGS 0x3f
143
144void mc13xxx_lock(struct mc13xxx *mc13xxx)
145{
146 if (!mutex_trylock(&mc13xxx->lock)) {
147 dev_dbg(&mc13xxx->spidev->dev, "wait for %s from %pf\n",
148 __func__, __builtin_return_address(0));
149
150 mutex_lock(&mc13xxx->lock);
151 }
152 dev_dbg(&mc13xxx->spidev->dev, "%s from %pf\n",
153 __func__, __builtin_return_address(0));
154}
155EXPORT_SYMBOL(mc13xxx_lock);
156
157void mc13xxx_unlock(struct mc13xxx *mc13xxx)
158{
159 dev_dbg(&mc13xxx->spidev->dev, "%s from %pf\n",
160 __func__, __builtin_return_address(0));
161 mutex_unlock(&mc13xxx->lock);
162}
163EXPORT_SYMBOL(mc13xxx_unlock);
164
165#define MC13XXX_REGOFFSET_SHIFT 25
166int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
167{
168 struct spi_transfer t;
169 struct spi_message m;
170 int ret;
171
172 BUG_ON(!mutex_is_locked(&mc13xxx->lock));
173
174 if (offset > MC13XXX_NUMREGS)
175 return -EINVAL;
176
177 *val = offset << MC13XXX_REGOFFSET_SHIFT;
178
179 memset(&t, 0, sizeof(t));
180
181 t.tx_buf = val;
182 t.rx_buf = val;
183 t.len = sizeof(u32);
184
185 spi_message_init(&m);
186 spi_message_add_tail(&t, &m);
187
188 ret = spi_sync(mc13xxx->spidev, &m);
189
190 /* error in message.status implies error return from spi_sync */
191 BUG_ON(!ret && m.status);
192
193 if (ret)
194 return ret;
195
196 *val &= 0xffffff;
197
198 dev_vdbg(&mc13xxx->spidev->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
199
200 return 0;
201}
202EXPORT_SYMBOL(mc13xxx_reg_read);
203
204int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
205{
206 u32 buf;
207 struct spi_transfer t;
208 struct spi_message m;
209 int ret;
210
211 BUG_ON(!mutex_is_locked(&mc13xxx->lock));
212
213 dev_vdbg(&mc13xxx->spidev->dev, "[0x%02x] <- 0x%06x\n", offset, val);
214
215 if (offset > MC13XXX_NUMREGS || val > 0xffffff)
216 return -EINVAL;
217
218 buf = 1 << 31 | offset << MC13XXX_REGOFFSET_SHIFT | val;
219
220 memset(&t, 0, sizeof(t));
221
222 t.tx_buf = &buf;
223 t.rx_buf = &buf;
224 t.len = sizeof(u32);
225
226 spi_message_init(&m);
227 spi_message_add_tail(&t, &m);
228
229 ret = spi_sync(mc13xxx->spidev, &m);
230
231 BUG_ON(!ret && m.status);
232
233 if (ret)
234 return ret;
235
236 return 0;
237}
238EXPORT_SYMBOL(mc13xxx_reg_write);
239
240int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
241 u32 mask, u32 val)
242{
243 int ret;
244 u32 valread;
245
246 BUG_ON(val & ~mask);
247
248 ret = mc13xxx_reg_read(mc13xxx, offset, &valread);
249 if (ret)
250 return ret;
251
252 valread = (valread & ~mask) | val;
253
254 return mc13xxx_reg_write(mc13xxx, offset, valread);
255}
256EXPORT_SYMBOL(mc13xxx_reg_rmw);
257
258int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq)
259{
260 int ret;
261 unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
262 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
263 u32 mask;
264
265 if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
266 return -EINVAL;
267
268 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
269 if (ret)
270 return ret;
271
272 if (mask & irqbit)
273 /* already masked */
274 return 0;
275
276 return mc13xxx_reg_write(mc13xxx, offmask, mask | irqbit);
277}
278EXPORT_SYMBOL(mc13xxx_irq_mask);
279
280int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq)
281{
282 int ret;
283 unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
284 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
285 u32 mask;
286
287 if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
288 return -EINVAL;
289
290 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
291 if (ret)
292 return ret;
293
294 if (!(mask & irqbit))
295 /* already unmasked */
296 return 0;
297
298 return mc13xxx_reg_write(mc13xxx, offmask, mask & ~irqbit);
299}
300EXPORT_SYMBOL(mc13xxx_irq_unmask);
301
302int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
303 int *enabled, int *pending)
304{
305 int ret;
306 unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
307 unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
308 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
309
310 if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
311 return -EINVAL;
312
313 if (enabled) {
314 u32 mask;
315
316 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
317 if (ret)
318 return ret;
319
320 *enabled = mask & irqbit;
321 }
322
323 if (pending) {
324 u32 stat;
325
326 ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
327 if (ret)
328 return ret;
329
330 *pending = stat & irqbit;
331 }
332
333 return 0;
334}
335EXPORT_SYMBOL(mc13xxx_irq_status);
336
337int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq)
338{
339 unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
340 unsigned int val = 1 << (irq < 24 ? irq : irq - 24);
341
342 BUG_ON(irq < 0 || irq >= MC13XXX_NUM_IRQ);
343
344 return mc13xxx_reg_write(mc13xxx, offstat, val);
345}
346EXPORT_SYMBOL(mc13xxx_irq_ack);
347
348int mc13xxx_irq_request_nounmask(struct mc13xxx *mc13xxx, int irq,
349 irq_handler_t handler, const char *name, void *dev)
350{
351 BUG_ON(!mutex_is_locked(&mc13xxx->lock));
352 BUG_ON(!handler);
353
354 if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
355 return -EINVAL;
356
357 if (mc13xxx->irqhandler[irq])
358 return -EBUSY;
359
360 mc13xxx->irqhandler[irq] = handler;
361 mc13xxx->irqdata[irq] = dev;
362
363 return 0;
364}
365EXPORT_SYMBOL(mc13xxx_irq_request_nounmask);
366
367int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
368 irq_handler_t handler, const char *name, void *dev)
369{
370 int ret;
371
372 ret = mc13xxx_irq_request_nounmask(mc13xxx, irq, handler, name, dev);
373 if (ret)
374 return ret;
375
376 ret = mc13xxx_irq_unmask(mc13xxx, irq);
377 if (ret) {
378 mc13xxx->irqhandler[irq] = NULL;
379 mc13xxx->irqdata[irq] = NULL;
380 return ret;
381 }
382
383 return 0;
384}
385EXPORT_SYMBOL(mc13xxx_irq_request);
386
387int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev)
388{
389 int ret;
390 BUG_ON(!mutex_is_locked(&mc13xxx->lock));
391
392 if (irq < 0 || irq >= MC13XXX_NUM_IRQ || !mc13xxx->irqhandler[irq] ||
393 mc13xxx->irqdata[irq] != dev)
394 return -EINVAL;
395
396 ret = mc13xxx_irq_mask(mc13xxx, irq);
397 if (ret)
398 return ret;
399
400 mc13xxx->irqhandler[irq] = NULL;
401 mc13xxx->irqdata[irq] = NULL;
402
403 return 0;
404}
405EXPORT_SYMBOL(mc13xxx_irq_free);
406
407static inline irqreturn_t mc13xxx_irqhandler(struct mc13xxx *mc13xxx, int irq)
408{
409 return mc13xxx->irqhandler[irq](irq, mc13xxx->irqdata[irq]);
410}
411
412/*
413 * returns: number of handled irqs or negative error
414 * locking: holds mc13xxx->lock
415 */
416static int mc13xxx_irq_handle(struct mc13xxx *mc13xxx,
417 unsigned int offstat, unsigned int offmask, int baseirq)
418{
419 u32 stat, mask;
420 int ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
421 int num_handled = 0;
422
423 if (ret)
424 return ret;
425
426 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
427 if (ret)
428 return ret;
429
430 while (stat & ~mask) {
431 int irq = __ffs(stat & ~mask);
432
433 stat &= ~(1 << irq);
434
435 if (likely(mc13xxx->irqhandler[baseirq + irq])) {
436 irqreturn_t handled;
437
438 handled = mc13xxx_irqhandler(mc13xxx, baseirq + irq);
439 if (handled == IRQ_HANDLED)
440 num_handled++;
441 } else {
442 dev_err(&mc13xxx->spidev->dev,
443 "BUG: irq %u but no handler\n",
444 baseirq + irq);
445
446 mask |= 1 << irq;
447
448 ret = mc13xxx_reg_write(mc13xxx, offmask, mask);
449 }
450 }
451
452 return num_handled;
453}
454
455static irqreturn_t mc13xxx_irq_thread(int irq, void *data)
456{
457 struct mc13xxx *mc13xxx = data;
458 irqreturn_t ret;
459 int handled = 0;
460
461 mc13xxx_lock(mc13xxx);
462
463 ret = mc13xxx_irq_handle(mc13xxx, MC13XXX_IRQSTAT0,
464 MC13XXX_IRQMASK0, 0);
465 if (ret > 0)
466 handled = 1;
467
468 ret = mc13xxx_irq_handle(mc13xxx, MC13XXX_IRQSTAT1,
469 MC13XXX_IRQMASK1, 24);
470 if (ret > 0)
471 handled = 1;
472
473 mc13xxx_unlock(mc13xxx);
474
475 return IRQ_RETVAL(handled);
476}
477
478enum mc13xxx_id {
479 MC13XXX_ID_MC13783,
480 MC13XXX_ID_MC13892,
481 MC13XXX_ID_INVALID,
482};
483
bb3149a9 484static const char *mc13xxx_chipname[] = {
8e005935
UKK		 485 [MC13XXX_ID_MC13783] = "mc13783",
486 [MC13XXX_ID_MC13892] = "mc13892",
487};
488
489#define maskval(reg, mask) (((reg) & (mask)) >> __ffs(mask))
490static int mc13xxx_identify(struct mc13xxx *mc13xxx, enum mc13xxx_id *id)
491{
492 u32 icid;
493 u32 revision;
494 const char *name;
495 int ret;
496
497 ret = mc13xxx_reg_read(mc13xxx, 46, &icid);
498 if (ret)
499 return ret;
500
501 icid = (icid >> 6) & 0x7;
502
503 switch (icid) {
504 case 2:
505 *id = MC13XXX_ID_MC13783;
506 name = "mc13783";
507 break;
508 case 7:
509 *id = MC13XXX_ID_MC13892;
510 name = "mc13892";
511 break;
512 default:
513 *id = MC13XXX_ID_INVALID;
514 break;
515 }
516
517 if (*id == MC13XXX_ID_MC13783 || *id == MC13XXX_ID_MC13892) {
518 ret = mc13xxx_reg_read(mc13xxx, MC13XXX_REVISION, &revision);
519 if (ret)
520 return ret;
521
522 dev_info(&mc13xxx->spidev->dev, "%s: rev: %d.%d, "
523 "fin: %d, fab: %d, icid: %d/%d\n",
524 mc13xxx_chipname[*id],
525 maskval(revision, MC13XXX_REVISION_REVFULL),
526 maskval(revision, MC13XXX_REVISION_REVMETAL),
527 maskval(revision, MC13XXX_REVISION_FIN),
528 maskval(revision, MC13XXX_REVISION_FAB),
529 maskval(revision, MC13XXX_REVISION_ICID),
530 maskval(revision, MC13XXX_REVISION_ICIDCODE));
531 }
532
533 if (*id != MC13XXX_ID_INVALID) {
534 const struct spi_device_id *devid =
535 spi_get_device_id(mc13xxx->spidev);
536 if (!devid || devid->driver_data != *id)
537 dev_warn(&mc13xxx->spidev->dev, "device id doesn't "
538 "match auto detection!\n");
539 }
540
541 return 0;
542}
543
544static const char *mc13xxx_get_chipname(struct mc13xxx *mc13xxx)
545{
546 const struct spi_device_id *devid =
547 spi_get_device_id(mc13xxx->spidev);
548
549 if (!devid)
550 return NULL;
551
552 return mc13xxx_chipname[devid->driver_data];
553}
554
8e005935
UKK		 555int mc13xxx_get_flags(struct mc13xxx *mc13xxx)
556{
876989d5 557 return mc13xxx->flags;
8e005935
UKK		 558}
559EXPORT_SYMBOL(mc13xxx_get_flags);
560
fec316d6
UKK		 561#define MC13XXX_ADC1_CHAN0_SHIFT 5
562#define MC13XXX_ADC1_CHAN1_SHIFT 8
8e005935
UKK		 563
564struct mc13xxx_adcdone_data {
565 struct mc13xxx *mc13xxx;
566 struct completion done;
567};
568
fec316d6 569static irqreturn_t mc13xxx_handler_adcdone(int irq, void *data)
8e005935
UKK		 570{
571 struct mc13xxx_adcdone_data *adcdone_data = data;
572
573 mc13xxx_irq_ack(adcdone_data->mc13xxx, irq);
574
575 complete_all(&adcdone_data->done);
576
577 return IRQ_HANDLED;
578}
579
fec316d6 580#define MC13XXX_ADC_WORKING (1 << 0)
8e005935 581
fec316d6 582int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
8e005935
UKK		 583 unsigned int channel, unsigned int *sample)
584{
8e005935
UKK		 585 u32 adc0, adc1, old_adc0;
586 int i, ret;
587 struct mc13xxx_adcdone_data adcdone_data = {
588 .mc13xxx = mc13xxx,
589 };
590 init_completion(&adcdone_data.done);
591
592 dev_dbg(&mc13xxx->spidev->dev, "%s\n", __func__);
593
594 mc13xxx_lock(mc13xxx);
595
fec316d6 596 if (mc13xxx->adcflags & MC13XXX_ADC_WORKING) {
8e005935
UKK		 597 ret = -EBUSY;
598 goto out;
599 }
600
fec316d6 601 mc13xxx->adcflags |= MC13XXX_ADC_WORKING;
8e005935 602
fec316d6 603 mc13xxx_reg_read(mc13xxx, MC13XXX_ADC0, &old_adc0);
8e005935 604
fec316d6
UKK		 605 adc0 = MC13XXX_ADC0_ADINC1 | MC13XXX_ADC0_ADINC2;
606 adc1 = MC13XXX_ADC1_ADEN | MC13XXX_ADC1_ADTRIGIGN | MC13XXX_ADC1_ASC;
8e005935
UKK		 607
608 if (channel > 7)
fec316d6 609 adc1 |= MC13XXX_ADC1_ADSEL;
8e005935
UKK		 610
611 switch (mode) {
fec316d6
UKK		 612 case MC13XXX_ADC_MODE_TS:
613 adc0 |= MC13XXX_ADC0_ADREFEN | MC13XXX_ADC0_TSMOD0 |
614 MC13XXX_ADC0_TSMOD1;
615 adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
8e005935
UKK		 616 break;
617
fec316d6 618 case MC13XXX_ADC_MODE_SINGLE_CHAN:
2161891a 619 adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
fec316d6
UKK		 620 adc1 |= (channel & 0x7) << MC13XXX_ADC1_CHAN0_SHIFT;
621 adc1 |= MC13XXX_ADC1_RAND;
8e005935
UKK		 622 break;
623
fec316d6 624 case MC13XXX_ADC_MODE_MULT_CHAN:
2161891a 625 adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
fec316d6 626 adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
8e005935
UKK		 627 break;
628
629 default:
fec316d6 630 mc13xxx_unlock(mc13xxx);
8e005935
UKK		 631 return -EINVAL;
632 }
633
fec316d6
UKK		 634 dev_dbg(&mc13xxx->spidev->dev, "%s: request irq\n", __func__);
635 mc13xxx_irq_request(mc13xxx, MC13XXX_IRQ_ADCDONE,
636 mc13xxx_handler_adcdone, __func__, &adcdone_data);
637 mc13xxx_irq_ack(mc13xxx, MC13XXX_IRQ_ADCDONE);
8e005935 638
fec316d6
UKK		 639 mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, adc0);
640 mc13xxx_reg_write(mc13xxx, MC13XXX_ADC1, adc1);
8e005935
UKK		 641
642 mc13xxx_unlock(mc13xxx);
643
644 ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
645
646 if (!ret)
647 ret = -ETIMEDOUT;
648
649 mc13xxx_lock(mc13xxx);
650
fec316d6 651 mc13xxx_irq_free(mc13xxx, MC13XXX_IRQ_ADCDONE, &adcdone_data);
8e005935
UKK		 652
653 if (ret > 0)
654 for (i = 0; i < 4; ++i) {
655 ret = mc13xxx_reg_read(mc13xxx,
fec316d6 656 MC13XXX_ADC2, &sample[i]);
8e005935
UKK		 657 if (ret)
658 break;
659 }
660
fec316d6 661 if (mode == MC13XXX_ADC_MODE_TS)
8e005935 662 /* restore TSMOD */
fec316d6 663 mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, old_adc0);
8e005935 664
fec316d6 665 mc13xxx->adcflags &= ~MC13XXX_ADC_WORKING;
8e005935
UKK		 666out:
667 mc13xxx_unlock(mc13xxx);
668
669 return ret;
670}
fec316d6 671EXPORT_SYMBOL_GPL(mc13xxx_adc_do_conversion);
8e005935
UKK		 672
673static int mc13xxx_add_subdevice_pdata(struct mc13xxx *mc13xxx,
c8a03c96 674 const char *format, void *pdata, size_t pdata_size)
8e005935
UKK		 675{
676 char buf[30];
677 const char *name = mc13xxx_get_chipname(mc13xxx);
678
679 struct mfd_cell cell = {
c8a03c96
SO		 680 .platform_data = pdata,
681 .pdata_size = pdata_size,
8e005935
UKK		 682 };
683
684 /* there is no asnprintf in the kernel :-( */
685 if (snprintf(buf, sizeof(buf), format, name) > sizeof(buf))
686 return -E2BIG;
687
688 cell.name = kmemdup(buf, strlen(buf) + 1, GFP_KERNEL);
689 if (!cell.name)
690 return -ENOMEM;
691
692 return mfd_add_devices(&mc13xxx->spidev->dev, -1, &cell, 1, NULL, 0);
693}
694
695static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
696{
c8a03c96 697 return mc13xxx_add_subdevice_pdata(mc13xxx, format, NULL, 0);
8e005935
UKK		 698}
699
876989d5
SG		 700#ifdef CONFIG_OF
701static int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
702{
703 struct device_node *np = mc13xxx->spidev->dev.of_node;
704
705 if (!np)
706 return -ENODEV;
707
708 if (of_get_property(np, "fsl,mc13xxx-uses-adc", NULL))
709 mc13xxx->flags |= MC13XXX_USE_ADC;
710
711 if (of_get_property(np, "fsl,mc13xxx-uses-codec", NULL))
712 mc13xxx->flags |= MC13XXX_USE_CODEC;
713
714 if (of_get_property(np, "fsl,mc13xxx-uses-rtc", NULL))
715 mc13xxx->flags |= MC13XXX_USE_RTC;
716
717 if (of_get_property(np, "fsl,mc13xxx-uses-touch", NULL))
718 mc13xxx->flags |= MC13XXX_USE_TOUCHSCREEN;
719
720 return 0;
721}
722#else
723static inline int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
724{
725 return -ENODEV;
726}
727#endif
728
729static const struct spi_device_id mc13xxx_device_id[] = {
730 {
731 .name = "mc13783",
732 .driver_data = MC13XXX_ID_MC13783,
733 }, {
734 .name = "mc13892",
735 .driver_data = MC13XXX_ID_MC13892,
736 }, {
737 /* sentinel */
738 }
739};
740MODULE_DEVICE_TABLE(spi, mc13xxx_device_id);
741
742static const struct of_device_id mc13xxx_dt_ids[] = {
743 { .compatible = "fsl,mc13783", .data = (void *) MC13XXX_ID_MC13783, },
744 { .compatible = "fsl,mc13892", .data = (void *) MC13XXX_ID_MC13892, },
745 { /* sentinel */ }
746};
747MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
748
8e005935
UKK		 749static int mc13xxx_probe(struct spi_device *spi)
750{
876989d5
SG		 751 const struct of_device_id *of_id;
752 struct spi_driver *sdrv = to_spi_driver(spi->dev.driver);
8e005935
UKK		 753 struct mc13xxx *mc13xxx;
754 struct mc13xxx_platform_data *pdata = dev_get_platdata(&spi->dev);
755 enum mc13xxx_id id;
756 int ret;
757
876989d5
SG		 758 of_id = of_match_device(mc13xxx_dt_ids, &spi->dev);
759 if (of_id)
760 sdrv->id_table = &mc13xxx_device_id[(enum mc13xxx_id) of_id->data];
30fc7ac3 761
8e005935
UKK		 762 mc13xxx = kzalloc(sizeof(*mc13xxx), GFP_KERNEL);
763 if (!mc13xxx)
764 return -ENOMEM;
765
766 dev_set_drvdata(&spi->dev, mc13xxx);
767 spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
768 spi->bits_per_word = 32;
769 spi_setup(spi);
770
771 mc13xxx->spidev = spi;
772
773 mutex_init(&mc13xxx->lock);
774 mc13xxx_lock(mc13xxx);
775
776 ret = mc13xxx_identify(mc13xxx, &id);
777 if (ret || id == MC13XXX_ID_INVALID)
778 goto err_revision;
779
780 /* mask all irqs */
781 ret = mc13xxx_reg_write(mc13xxx, MC13XXX_IRQMASK0, 0x00ffffff);
782 if (ret)
783 goto err_mask;
784
785 ret = mc13xxx_reg_write(mc13xxx, MC13XXX_IRQMASK1, 0x00ffffff);
786 if (ret)
787 goto err_mask;
788
789 ret = request_threaded_irq(spi->irq, NULL, mc13xxx_irq_thread,
790 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13xxx", mc13xxx);
791
792 if (ret) {
793err_mask:
794err_revision:
e1b88eb0 795 mc13xxx_unlock(mc13xxx);
8e005935
UKK		 796 dev_set_drvdata(&spi->dev, NULL);
797 kfree(mc13xxx);
798 return ret;
799 }
800
801 mc13xxx_unlock(mc13xxx);
802
876989d5
SG		 803 if (mc13xxx_probe_flags_dt(mc13xxx) < 0 && pdata)
804 mc13xxx->flags = pdata->flags;
805
806 if (mc13xxx->flags & MC13XXX_USE_ADC)
8e005935
UKK		 807 mc13xxx_add_subdevice(mc13xxx, "%s-adc");
808
876989d5 809 if (mc13xxx->flags & MC13XXX_USE_CODEC)
8e005935
UKK		 810 mc13xxx_add_subdevice(mc13xxx, "%s-codec");
811
876989d5 812 if (mc13xxx->flags & MC13XXX_USE_RTC)
8e005935
UKK		 813 mc13xxx_add_subdevice(mc13xxx, "%s-rtc");
814
876989d5 815 if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
8e005935
UKK		 816 mc13xxx_add_subdevice(mc13xxx, "%s-ts");
817
876989d5
SG		 818 if (pdata) {
819 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-regulator",
820 &pdata->regulators, sizeof(pdata->regulators));
c8a03c96
SO		 821 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-led",
822 pdata->leds, sizeof(*pdata->leds));
30fc7ac3
PR		 823 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-pwrbutton",
824 pdata->buttons, sizeof(*pdata->buttons));
876989d5
SG		 825 } else {
826 mc13xxx_add_subdevice(mc13xxx, "%s-regulator");
827 mc13xxx_add_subdevice(mc13xxx, "%s-led");
828 mc13xxx_add_subdevice(mc13xxx, "%s-pwrbutton");
829 }
30fc7ac3 830
8e005935
UKK		 831 return 0;
832}
833
834static int __devexit mc13xxx_remove(struct spi_device *spi)
835{
836 struct mc13xxx *mc13xxx = dev_get_drvdata(&spi->dev);
837
838 free_irq(mc13xxx->spidev->irq, mc13xxx);
839
840 mfd_remove_devices(&spi->dev);
841
cef92fe6
AL		 842 kfree(mc13xxx);
843
8e005935
UKK		 844 return 0;
845}
846
8e005935
UKK		 847static struct spi_driver mc13xxx_driver = {
848 .id_table = mc13xxx_device_id,
849 .driver = {
850 .name = "mc13xxx",
8e005935 851 .owner = THIS_MODULE,
876989d5 852 .of_match_table = mc13xxx_dt_ids,
8e005935
UKK		 853 },
854 .probe = mc13xxx_probe,
855 .remove = __devexit_p(mc13xxx_remove),
856};
857
858static int __init mc13xxx_init(void)
859{
860 return spi_register_driver(&mc13xxx_driver);
861}
862subsys_initcall(mc13xxx_init);
863
864static void __exit mc13xxx_exit(void)
865{
866 spi_unregister_driver(&mc13xxx_driver);
867}
868module_exit(mc13xxx_exit);
869
870MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
871MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
872MODULE_LICENSE("GPL v2");
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