[mirror_ubuntu-bionic-kernel.git] / drivers / mfd / mt6397-core.c

/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Flora Fu, MediaTek
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/regmap.h>
#include <linux/mfd/core.h>
#include <linux/mfd/mt6397/core.h>
#include <linux/mfd/mt6323/core.h>
#include <linux/mfd/mt6397/registers.h>
#include <linux/mfd/mt6323/registers.h>

#define MT6397_RTC_BASE		0xe000
#define MT6397_RTC_SIZE		0x3e

#define MT6323_CID_CODE		0x23
#define MT6391_CID_CODE		0x91
#define MT6397_CID_CODE		0x97

static const struct resource mt6397_rtc_resources[] = {
	{
		.start = MT6397_RTC_BASE,
		.end   = MT6397_RTC_BASE + MT6397_RTC_SIZE,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = MT6397_IRQ_RTC,
		.end   = MT6397_IRQ_RTC,
		.flags = IORESOURCE_IRQ,
	},
};

static const struct mfd_cell mt6323_devs[] = {
	{
		.name = "mt6323-regulator",
		.of_compatible = "mediatek,mt6323-regulator"
	}, {
		.name = "mt6323-led",
		.of_compatible = "mediatek,mt6323-led"
	},
};

static const struct mfd_cell mt6397_devs[] = {
	{
		.name = "mt6397-rtc",
		.num_resources = ARRAY_SIZE(mt6397_rtc_resources),
		.resources = mt6397_rtc_resources,
		.of_compatible = "mediatek,mt6397-rtc",
	}, {
		.name = "mt6397-regulator",
		.of_compatible = "mediatek,mt6397-regulator",
	}, {
		.name = "mt6397-codec",
		.of_compatible = "mediatek,mt6397-codec",
	}, {
		.name = "mt6397-clk",
		.of_compatible = "mediatek,mt6397-clk",
	}, {
		.name = "mt6397-pinctrl",
		.of_compatible = "mediatek,mt6397-pinctrl",
	},
};

static void mt6397_irq_lock(struct irq_data *data)
{
	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);

	mutex_lock(&mt6397->irqlock);
}

static void mt6397_irq_sync_unlock(struct irq_data *data)
{
	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);

	regmap_write(mt6397->regmap, mt6397->int_con[0],
		     mt6397->irq_masks_cur[0]);
	regmap_write(mt6397->regmap, mt6397->int_con[1],
		     mt6397->irq_masks_cur[1]);

	mutex_unlock(&mt6397->irqlock);
}

static void mt6397_irq_disable(struct irq_data *data)
{
	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
	int shift = data->hwirq & 0xf;
	int reg = data->hwirq >> 4;

	mt6397->irq_masks_cur[reg] &= ~BIT(shift);
}

static void mt6397_irq_enable(struct irq_data *data)
{
	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
	int shift = data->hwirq & 0xf;
	int reg = data->hwirq >> 4;

	mt6397->irq_masks_cur[reg] |= BIT(shift);
}

#ifdef CONFIG_PM_SLEEP
static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
{
	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
	int shift = irq_data->hwirq & 0xf;
	int reg = irq_data->hwirq >> 4;

	if (on)
		mt6397->wake_mask[reg] |= BIT(shift);
	else
		mt6397->wake_mask[reg] &= ~BIT(shift);

	return 0;
}
#else
#define mt6397_irq_set_wake NULL
#endif

static struct irq_chip mt6397_irq_chip = {
	.name = "mt6397-irq",
	.irq_bus_lock = mt6397_irq_lock,
	.irq_bus_sync_unlock = mt6397_irq_sync_unlock,
	.irq_enable = mt6397_irq_enable,
	.irq_disable = mt6397_irq_disable,
	.irq_set_wake = mt6397_irq_set_wake,
};

static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
		int irqbase)
{
	unsigned int status;
	int i, irq, ret;

	ret = regmap_read(mt6397->regmap, reg, &status);
	if (ret) {
		dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
		return;
	}

	for (i = 0; i < 16; i++) {
		if (status & BIT(i)) {
			irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
			if (irq)
				handle_nested_irq(irq);
		}
	}

	regmap_write(mt6397->regmap, reg, status);
}

static irqreturn_t mt6397_irq_thread(int irq, void *data)
{
	struct mt6397_chip *mt6397 = data;

	mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
	mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);

	return IRQ_HANDLED;
}

static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
					irq_hw_number_t hw)
{
	struct mt6397_chip *mt6397 = d->host_data;

	irq_set_chip_data(irq, mt6397);
	irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
	irq_set_nested_thread(irq, 1);
	irq_set_noprobe(irq);

	return 0;
}

static const struct irq_domain_ops mt6397_irq_domain_ops = {
	.map = mt6397_irq_domain_map,
};

static int mt6397_irq_init(struct mt6397_chip *mt6397)
{
	int ret;

	mutex_init(&mt6397->irqlock);

	/* Mask all interrupt sources */
	regmap_write(mt6397->regmap, mt6397->int_con[0], 0x0);
	regmap_write(mt6397->regmap, mt6397->int_con[1], 0x0);

	mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
		MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
	if (!mt6397->irq_domain) {
		dev_err(mt6397->dev, "could not create irq domain\n");
		return -ENOMEM;
	}

	ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL,
		mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397);
	if (ret) {
		dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n",
			mt6397->irq, ret);
		return ret;
	}

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int mt6397_irq_suspend(struct device *dev)
{
	struct mt6397_chip *chip = dev_get_drvdata(dev);

	regmap_write(chip->regmap, chip->int_con[0], chip->wake_mask[0]);
	regmap_write(chip->regmap, chip->int_con[1], chip->wake_mask[1]);

	enable_irq_wake(chip->irq);

	return 0;
}

static int mt6397_irq_resume(struct device *dev)
{
	struct mt6397_chip *chip = dev_get_drvdata(dev);

	regmap_write(chip->regmap, chip->int_con[0], chip->irq_masks_cur[0]);
	regmap_write(chip->regmap, chip->int_con[1], chip->irq_masks_cur[1]);

	disable_irq_wake(chip->irq);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_irq_suspend,
			mt6397_irq_resume);

static int mt6397_probe(struct platform_device *pdev)
{
	int ret;
	unsigned int id;
	struct mt6397_chip *pmic;

	pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
	if (!pmic)
		return -ENOMEM;

	pmic->dev = &pdev->dev;

	/*
	 * mt6397 MFD is child device of soc pmic wrapper.
	 * Regmap is set from its parent.
	 */
	pmic->regmap = dev_get_regmap(pdev->dev.parent, NULL);
	if (!pmic->regmap)
		return -ENODEV;

	platform_set_drvdata(pdev, pmic);

	ret = regmap_read(pmic->regmap, MT6397_CID, &id);
	if (ret) {
		dev_err(pmic->dev, "Failed to read chip id: %d\n", ret);
		return ret;
	}

	pmic->irq = platform_get_irq(pdev, 0);
	if (pmic->irq <= 0)
		return pmic->irq;

	switch (id & 0xff) {
	case MT6323_CID_CODE:
		pmic->int_con[0] = MT6323_INT_CON0;
		pmic->int_con[1] = MT6323_INT_CON1;
		pmic->int_status[0] = MT6323_INT_STATUS0;
		pmic->int_status[1] = MT6323_INT_STATUS1;
		ret = mt6397_irq_init(pmic);
		if (ret)
			return ret;

		ret = devm_mfd_add_devices(&pdev->dev, -1, mt6323_devs,
					   ARRAY_SIZE(mt6323_devs), NULL,
					   0, NULL);
		break;

	case MT6397_CID_CODE:
	case MT6391_CID_CODE:
		pmic->int_con[0] = MT6397_INT_CON0;
		pmic->int_con[1] = MT6397_INT_CON1;
		pmic->int_status[0] = MT6397_INT_STATUS0;
		pmic->int_status[1] = MT6397_INT_STATUS1;
		ret = mt6397_irq_init(pmic);
		if (ret)
			return ret;

		ret = devm_mfd_add_devices(&pdev->dev, -1, mt6397_devs,
					   ARRAY_SIZE(mt6397_devs), NULL,
					   0, NULL);
		break;

	default:
		dev_err(&pdev->dev, "unsupported chip: %d\n", id);
		ret = -ENODEV;
		break;
	}

	if (ret) {
		irq_domain_remove(pmic->irq_domain);
		dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
	}

	return ret;
}

static const struct of_device_id mt6397_of_match[] = {
	{ .compatible = "mediatek,mt6397" },
	{ .compatible = "mediatek,mt6323" },
	{ }
};
MODULE_DEVICE_TABLE(of, mt6397_of_match);

static const struct platform_device_id mt6397_id[] = {
	{ "mt6397", 0 },
	{ },
};
MODULE_DEVICE_TABLE(platform, mt6397_id);

static struct platform_driver mt6397_driver = {
	.probe = mt6397_probe,
	.driver = {
		.name = "mt6397",
		.of_match_table = of_match_ptr(mt6397_of_match),
		.pm = &mt6397_pm_ops,
	},
	.id_table = mt6397_id,
};

module_platform_driver(mt6397_driver);

MODULE_AUTHOR("Flora Fu, MediaTek");
MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
MODULE_LICENSE("GPL");
Commit	Line	Data
6df8dd5c FF	1	/*
	2	* Copyright (c) 2014 MediaTek Inc.
	3	* Author: Flora Fu, MediaTek
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
	15	#include <linux/interrupt.h>
	16	#include <linux/module.h>
	17	#include <linux/of_device.h>
	18	#include <linux/of_irq.h>
	19	#include <linux/regmap.h>
	20	#include <linux/mfd/core.h>
	21	#include <linux/mfd/mt6397/core.h>
44760cf3	22	#include <linux/mfd/mt6323/core.h>
6df8dd5c	23	#include <linux/mfd/mt6397/registers.h>
44760cf3	24	#include <linux/mfd/mt6323/registers.h>
6df8dd5c	25
a5d7ea09 EH	26	#define MT6397_RTC_BASE 0xe000
	27	#define MT6397_RTC_SIZE 0x3e
	28
44760cf3	29	#define MT6323_CID_CODE 0x23
1d2c25ed JC	30	#define MT6391_CID_CODE 0x91
	31	#define MT6397_CID_CODE 0x97
	32
a5d7ea09 EH	33	static const struct resource mt6397_rtc_resources[] = {
	34	{
	35	.start = MT6397_RTC_BASE,
	36	.end = MT6397_RTC_BASE + MT6397_RTC_SIZE,
	37	.flags = IORESOURCE_MEM,
	38	},
	39	{
	40	.start = MT6397_IRQ_RTC,
	41	.end = MT6397_IRQ_RTC,
	42	.flags = IORESOURCE_IRQ,
	43	},
	44	};
	45
44760cf3 JC	46	static const struct mfd_cell mt6323_devs[] = {
	47	{
	48	.name = "mt6323-regulator",
	49	.of_compatible = "mediatek,mt6323-regulator"
040fc9b1	50	}, {
1cb8af8d SW	51	.name = "mt6323-led",
	52	.of_compatible = "mediatek,mt6323-led"
	53	},
44760cf3 JC	54	};
44760cf3 JC	55
6df8dd5c FF	56	static const struct mfd_cell mt6397_devs[] = {
	57	{
	58	.name = "mt6397-rtc",
a5d7ea09 EH	59	.num_resources = ARRAY_SIZE(mt6397_rtc_resources),
a5d7ea09 EH	60	.resources = mt6397_rtc_resources,
6df8dd5c FF	61	.of_compatible = "mediatek,mt6397-rtc",
	62	}, {
	63	.name = "mt6397-regulator",
	64	.of_compatible = "mediatek,mt6397-regulator",
	65	}, {
	66	.name = "mt6397-codec",
	67	.of_compatible = "mediatek,mt6397-codec",
	68	}, {
	69	.name = "mt6397-clk",
	70	.of_compatible = "mediatek,mt6397-clk",
cf55078b HY	71	}, {
	72	.name = "mt6397-pinctrl",
	73	.of_compatible = "mediatek,mt6397-pinctrl",
6df8dd5c FF	74	},
	75	};
	76
	77	static void mt6397_irq_lock(struct irq_data *data)
	78	{
1e84aa44	79	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
6df8dd5c FF	80
	81	mutex_lock(&mt6397->irqlock);
	82	}
	83
	84	static void mt6397_irq_sync_unlock(struct irq_data *data)
	85	{
1e84aa44	86	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
6df8dd5c	87
feec4799 JC	88	regmap_write(mt6397->regmap, mt6397->int_con[0],
	89	mt6397->irq_masks_cur[0]);
	90	regmap_write(mt6397->regmap, mt6397->int_con[1],
	91	mt6397->irq_masks_cur[1]);
6df8dd5c FF	92
	93	mutex_unlock(&mt6397->irqlock);
	94	}
	95
	96	static void mt6397_irq_disable(struct irq_data *data)
	97	{
1e84aa44	98	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
6df8dd5c FF	99	int shift = data->hwirq & 0xf;
	100	int reg = data->hwirq >> 4;
	101
	102	mt6397->irq_masks_cur[reg] &= ~BIT(shift);
	103	}
	104
	105	static void mt6397_irq_enable(struct irq_data *data)
	106	{
1e84aa44	107	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
6df8dd5c FF	108	int shift = data->hwirq & 0xf;
	109	int reg = data->hwirq >> 4;
	110
	111	mt6397->irq_masks_cur[reg] \|= BIT(shift);
	112	}
	113
f3151ab4 HC	114	#ifdef CONFIG_PM_SLEEP
	115	static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
	116	{
	117	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
	118	int shift = irq_data->hwirq & 0xf;
	119	int reg = irq_data->hwirq >> 4;
	120
	121	if (on)
	122	mt6397->wake_mask[reg] \|= BIT(shift);
	123	else
	124	mt6397->wake_mask[reg] &= ~BIT(shift);
	125
	126	return 0;
	127	}
	128	#else
	129	#define mt6397_irq_set_wake NULL
	130	#endif
	131
6df8dd5c FF	132	static struct irq_chip mt6397_irq_chip = {
	133	.name = "mt6397-irq",
	134	.irq_bus_lock = mt6397_irq_lock,
	135	.irq_bus_sync_unlock = mt6397_irq_sync_unlock,
	136	.irq_enable = mt6397_irq_enable,
	137	.irq_disable = mt6397_irq_disable,
f3151ab4	138	.irq_set_wake = mt6397_irq_set_wake,
6df8dd5c FF	139	};
	140
	141	static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
	142	int irqbase)
	143	{
	144	unsigned int status;
	145	int i, irq, ret;
	146
	147	ret = regmap_read(mt6397->regmap, reg, &status);
	148	if (ret) {
	149	dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
	150	return;
	151	}
	152
	153	for (i = 0; i < 16; i++) {
	154	if (status & BIT(i)) {
	155	irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
	156	if (irq)
	157	handle_nested_irq(irq);
	158	}
	159	}
	160
	161	regmap_write(mt6397->regmap, reg, status);
	162	}
	163
	164	static irqreturn_t mt6397_irq_thread(int irq, void *data)
	165	{
	166	struct mt6397_chip *mt6397 = data;
	167
feec4799 JC	168	mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
feec4799 JC	169	mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
6df8dd5c FF	170
	171	return IRQ_HANDLED;
	172	}
	173
	174	static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
	175	irq_hw_number_t hw)
	176	{
	177	struct mt6397_chip *mt6397 = d->host_data;
	178
	179	irq_set_chip_data(irq, mt6397);
	180	irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
	181	irq_set_nested_thread(irq, 1);
6df8dd5c	182	irq_set_noprobe(irq);
6df8dd5c FF	183
	184	return 0;
	185	}
	186
7ce7b26f	187	static const struct irq_domain_ops mt6397_irq_domain_ops = {
6df8dd5c FF	188	.map = mt6397_irq_domain_map,
	189	};
	190
	191	static int mt6397_irq_init(struct mt6397_chip *mt6397)
	192	{
	193	int ret;
	194
	195	mutex_init(&mt6397->irqlock);
	196
	197	/* Mask all interrupt sources */
feec4799 JC	198	regmap_write(mt6397->regmap, mt6397->int_con[0], 0x0);
feec4799 JC	199	regmap_write(mt6397->regmap, mt6397->int_con[1], 0x0);
6df8dd5c FF	200
	201	mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
	202	MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
	203	if (!mt6397->irq_domain) {
	204	dev_err(mt6397->dev, "could not create irq domain\n");
	205	return -ENOMEM;
	206	}
	207
	208	ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL,
	209	mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397);
	210	if (ret) {
	211	dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n",
	212	mt6397->irq, ret);
	213	return ret;
	214	}
	215
	216	return 0;
	217	}
	218
f3151ab4 HC	219	#ifdef CONFIG_PM_SLEEP
	220	static int mt6397_irq_suspend(struct device *dev)
	221	{
	222	struct mt6397_chip *chip = dev_get_drvdata(dev);
	223
feec4799 JC	224	regmap_write(chip->regmap, chip->int_con[0], chip->wake_mask[0]);
feec4799 JC	225	regmap_write(chip->regmap, chip->int_con[1], chip->wake_mask[1]);
f3151ab4 HC	226
	227	enable_irq_wake(chip->irq);
	228
	229	return 0;
	230	}
	231
	232	static int mt6397_irq_resume(struct device *dev)
	233	{
	234	struct mt6397_chip *chip = dev_get_drvdata(dev);
	235
feec4799 JC	236	regmap_write(chip->regmap, chip->int_con[0], chip->irq_masks_cur[0]);
feec4799 JC	237	regmap_write(chip->regmap, chip->int_con[1], chip->irq_masks_cur[1]);
f3151ab4 HC	238
	239	disable_irq_wake(chip->irq);
	240
	241	return 0;
	242	}
	243	#endif
	244
	245	static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_irq_suspend,
	246	mt6397_irq_resume);
	247
6df8dd5c FF	248	static int mt6397_probe(struct platform_device *pdev)
	249	{
	250	int ret;
1d2c25ed JC	251	unsigned int id;
1d2c25ed JC	252	struct mt6397_chip *pmic;
6df8dd5c	253
1d2c25ed JC	254	pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
1d2c25ed JC	255	if (!pmic)
6df8dd5c FF	256	return -ENOMEM;
6df8dd5c FF	257
1d2c25ed	258	pmic->dev = &pdev->dev;
feec4799	259
6df8dd5c FF	260	/*
	261	* mt6397 MFD is child device of soc pmic wrapper.
	262	* Regmap is set from its parent.
	263	*/
1d2c25ed JC	264	pmic->regmap = dev_get_regmap(pdev->dev.parent, NULL);
1d2c25ed JC	265	if (!pmic->regmap)
6df8dd5c FF	266	return -ENODEV;
6df8dd5c FF	267
1d2c25ed JC	268	platform_set_drvdata(pdev, pmic);
	269
	270	ret = regmap_read(pmic->regmap, MT6397_CID, &id);
	271	if (ret) {
	272	dev_err(pmic->dev, "Failed to read chip id: %d\n", ret);
1387ff53	273	return ret;
1d2c25ed JC	274	}
1d2c25ed JC	275
1387ff53 HC	276	pmic->irq = platform_get_irq(pdev, 0);
	277	if (pmic->irq <= 0)
	278	return pmic->irq;
	279
1d2c25ed	280	switch (id & 0xff) {
44760cf3 JC	281	case MT6323_CID_CODE:
	282	pmic->int_con[0] = MT6323_INT_CON0;
	283	pmic->int_con[1] = MT6323_INT_CON1;
	284	pmic->int_status[0] = MT6323_INT_STATUS0;
	285	pmic->int_status[1] = MT6323_INT_STATUS1;
1387ff53 HC	286	ret = mt6397_irq_init(pmic);
	287	if (ret)
	288	return ret;
	289
08e380a5 LD	290	ret = devm_mfd_add_devices(&pdev->dev, -1, mt6323_devs,
	291	ARRAY_SIZE(mt6323_devs), NULL,
	292	0, NULL);
44760cf3 JC	293	break;
44760cf3 JC	294
1d2c25ed JC	295	case MT6397_CID_CODE:
	296	case MT6391_CID_CODE:
	297	pmic->int_con[0] = MT6397_INT_CON0;
	298	pmic->int_con[1] = MT6397_INT_CON1;
	299	pmic->int_status[0] = MT6397_INT_STATUS0;
	300	pmic->int_status[1] = MT6397_INT_STATUS1;
1387ff53 HC	301	ret = mt6397_irq_init(pmic);
	302	if (ret)
	303	return ret;
	304
08e380a5 LD	305	ret = devm_mfd_add_devices(&pdev->dev, -1, mt6397_devs,
	306	ARRAY_SIZE(mt6397_devs), NULL,
	307	0, NULL);
1d2c25ed JC	308	break;
	309
	310	default:
	311	dev_err(&pdev->dev, "unsupported chip: %d\n", id);
	312	ret = -ENODEV;
	313	break;
	314	}
6df8dd5c	315
1d2c25ed JC	316	if (ret) {
1d2c25ed JC	317	irq_domain_remove(pmic->irq_domain);
6df8dd5c	318	dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
1d2c25ed	319	}
6df8dd5c FF	320
	321	return ret;
	322	}
	323
6df8dd5c FF	324	static const struct of_device_id mt6397_of_match[] = {
6df8dd5c FF	325	{ .compatible = "mediatek,mt6397" },
44760cf3	326	{ .compatible = "mediatek,mt6323" },
6df8dd5c FF	327	{ }
	328	};
	329	MODULE_DEVICE_TABLE(of, mt6397_of_match);
	330
e1d9a109 JMC	331	static const struct platform_device_id mt6397_id[] = {
	332	{ "mt6397", 0 },
	333	{ },
	334	};
	335	MODULE_DEVICE_TABLE(platform, mt6397_id);
	336
6df8dd5c FF	337	static struct platform_driver mt6397_driver = {
6df8dd5c FF	338	.probe = mt6397_probe,
6df8dd5c FF	339	.driver = {
	340	.name = "mt6397",
	341	.of_match_table = of_match_ptr(mt6397_of_match),
f3151ab4	342	.pm = &mt6397_pm_ops,
6df8dd5c	343	},
e1d9a109	344	.id_table = mt6397_id,
6df8dd5c FF	345	};
	346
	347	module_platform_driver(mt6397_driver);
	348
	349	MODULE_AUTHOR("Flora Fu, MediaTek");
	350	MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
	351	MODULE_LICENSE("GPL");