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Merge tag 'omapdrm-4.15-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba...
[mirror_ubuntu-bionic-kernel.git] / drivers / mfd / palmas.c
CommitLineData
2945fbc2
GG		 1/*
2 * TI Palmas MFD Driver
3 *
4 * Copyright 2011-2012 Texas Instruments Inc.
5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/slab.h>
19#include <linux/i2c.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22#include <linux/regmap.h>
23#include <linux/err.h>
24#include <linux/mfd/core.h>
25#include <linux/mfd/palmas.h>
1ffb0be3 26#include <linux/of_device.h>
2945fbc2 27
2945fbc2
GG		 28static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
29 {
30 .reg_bits = 8,
31 .val_bits = 8,
32 .max_register = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
33 PALMAS_PRIMARY_SECONDARY_PAD3),
34 },
35 {
36 .reg_bits = 8,
37 .val_bits = 8,
38 .max_register = PALMAS_BASE_TO_REG(PALMAS_GPADC_BASE,
39 PALMAS_GPADC_SMPS_VSEL_MONITORING),
40 },
41 {
42 .reg_bits = 8,
43 .val_bits = 8,
44 .max_register = PALMAS_BASE_TO_REG(PALMAS_TRIM_GPADC_BASE,
45 PALMAS_GPADC_TRIM16),
46 },
47};
48
1c113d83
K		 49static const struct regmap_irq tps65917_irqs[] = {
50 /* INT1 IRQs */
51 [TPS65917_RESERVED1] = {
52 .mask = TPS65917_RESERVED,
53 },
54 [TPS65917_PWRON_IRQ] = {
55 .mask = TPS65917_INT1_STATUS_PWRON,
56 },
57 [TPS65917_LONG_PRESS_KEY_IRQ] = {
58 .mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY,
59 },
60 [TPS65917_RESERVED2] = {
61 .mask = TPS65917_RESERVED,
62 },
63 [TPS65917_PWRDOWN_IRQ] = {
64 .mask = TPS65917_INT1_STATUS_PWRDOWN,
65 },
66 [TPS65917_HOTDIE_IRQ] = {
67 .mask = TPS65917_INT1_STATUS_HOTDIE,
68 },
69 [TPS65917_VSYS_MON_IRQ] = {
70 .mask = TPS65917_INT1_STATUS_VSYS_MON,
71 },
72 [TPS65917_RESERVED3] = {
73 .mask = TPS65917_RESERVED,
74 },
75 /* INT2 IRQs*/
76 [TPS65917_RESERVED4] = {
77 .mask = TPS65917_RESERVED,
78 .reg_offset = 1,
79 },
80 [TPS65917_OTP_ERROR_IRQ] = {
81 .mask = TPS65917_INT2_STATUS_OTP_ERROR,
82 .reg_offset = 1,
83 },
84 [TPS65917_WDT_IRQ] = {
85 .mask = TPS65917_INT2_STATUS_WDT,
86 .reg_offset = 1,
87 },
88 [TPS65917_RESERVED5] = {
89 .mask = TPS65917_RESERVED,
90 .reg_offset = 1,
91 },
92 [TPS65917_RESET_IN_IRQ] = {
93 .mask = TPS65917_INT2_STATUS_RESET_IN,
94 .reg_offset = 1,
95 },
96 [TPS65917_FSD_IRQ] = {
97 .mask = TPS65917_INT2_STATUS_FSD,
98 .reg_offset = 1,
99 },
100 [TPS65917_SHORT_IRQ] = {
101 .mask = TPS65917_INT2_STATUS_SHORT,
102 .reg_offset = 1,
103 },
104 [TPS65917_RESERVED6] = {
105 .mask = TPS65917_RESERVED,
106 .reg_offset = 1,
107 },
108 /* INT3 IRQs */
109 [TPS65917_GPADC_AUTO_0_IRQ] = {
110 .mask = TPS65917_INT3_STATUS_GPADC_AUTO_0,
111 .reg_offset = 2,
112 },
113 [TPS65917_GPADC_AUTO_1_IRQ] = {
114 .mask = TPS65917_INT3_STATUS_GPADC_AUTO_1,
115 .reg_offset = 2,
116 },
117 [TPS65917_GPADC_EOC_SW_IRQ] = {
118 .mask = TPS65917_INT3_STATUS_GPADC_EOC_SW,
119 .reg_offset = 2,
120 },
121 [TPS65917_RESREVED6] = {
122 .mask = TPS65917_RESERVED6,
123 .reg_offset = 2,
124 },
125 [TPS65917_RESERVED7] = {
126 .mask = TPS65917_RESERVED,
127 .reg_offset = 2,
128 },
129 [TPS65917_RESERVED8] = {
130 .mask = TPS65917_RESERVED,
131 .reg_offset = 2,
132 },
133 [TPS65917_RESERVED9] = {
134 .mask = TPS65917_RESERVED,
135 .reg_offset = 2,
136 },
137 [TPS65917_VBUS_IRQ] = {
138 .mask = TPS65917_INT3_STATUS_VBUS,
139 .reg_offset = 2,
140 },
141 /* INT4 IRQs */
142 [TPS65917_GPIO_0_IRQ] = {
143 .mask = TPS65917_INT4_STATUS_GPIO_0,
144 .reg_offset = 3,
145 },
146 [TPS65917_GPIO_1_IRQ] = {
147 .mask = TPS65917_INT4_STATUS_GPIO_1,
148 .reg_offset = 3,
149 },
150 [TPS65917_GPIO_2_IRQ] = {
151 .mask = TPS65917_INT4_STATUS_GPIO_2,
152 .reg_offset = 3,
153 },
154 [TPS65917_GPIO_3_IRQ] = {
155 .mask = TPS65917_INT4_STATUS_GPIO_3,
156 .reg_offset = 3,
157 },
158 [TPS65917_GPIO_4_IRQ] = {
159 .mask = TPS65917_INT4_STATUS_GPIO_4,
160 .reg_offset = 3,
161 },
162 [TPS65917_GPIO_5_IRQ] = {
163 .mask = TPS65917_INT4_STATUS_GPIO_5,
164 .reg_offset = 3,
165 },
166 [TPS65917_GPIO_6_IRQ] = {
167 .mask = TPS65917_INT4_STATUS_GPIO_6,
168 .reg_offset = 3,
169 },
170 [TPS65917_RESERVED10] = {
171 .mask = TPS65917_RESERVED10,
172 .reg_offset = 3,
173 },
174};
175
2945fbc2
GG		 176static const struct regmap_irq palmas_irqs[] = {
177 /* INT1 IRQs */
178 [PALMAS_CHARG_DET_N_VBUS_OVV_IRQ] = {
179 .mask = PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV,
180 },
181 [PALMAS_PWRON_IRQ] = {
182 .mask = PALMAS_INT1_STATUS_PWRON,
183 },
184 [PALMAS_LONG_PRESS_KEY_IRQ] = {
185 .mask = PALMAS_INT1_STATUS_LONG_PRESS_KEY,
186 },
187 [PALMAS_RPWRON_IRQ] = {
188 .mask = PALMAS_INT1_STATUS_RPWRON,
189 },
190 [PALMAS_PWRDOWN_IRQ] = {
191 .mask = PALMAS_INT1_STATUS_PWRDOWN,
192 },
193 [PALMAS_HOTDIE_IRQ] = {
194 .mask = PALMAS_INT1_STATUS_HOTDIE,
195 },
196 [PALMAS_VSYS_MON_IRQ] = {
197 .mask = PALMAS_INT1_STATUS_VSYS_MON,
198 },
199 [PALMAS_VBAT_MON_IRQ] = {
200 .mask = PALMAS_INT1_STATUS_VBAT_MON,
201 },
202 /* INT2 IRQs*/
203 [PALMAS_RTC_ALARM_IRQ] = {
204 .mask = PALMAS_INT2_STATUS_RTC_ALARM,
205 .reg_offset = 1,
206 },
207 [PALMAS_RTC_TIMER_IRQ] = {
208 .mask = PALMAS_INT2_STATUS_RTC_TIMER,
209 .reg_offset = 1,
210 },
211 [PALMAS_WDT_IRQ] = {
212 .mask = PALMAS_INT2_STATUS_WDT,
213 .reg_offset = 1,
214 },
215 [PALMAS_BATREMOVAL_IRQ] = {
216 .mask = PALMAS_INT2_STATUS_BATREMOVAL,
217 .reg_offset = 1,
218 },
219 [PALMAS_RESET_IN_IRQ] = {
220 .mask = PALMAS_INT2_STATUS_RESET_IN,
221 .reg_offset = 1,
222 },
223 [PALMAS_FBI_BB_IRQ] = {
224 .mask = PALMAS_INT2_STATUS_FBI_BB,
225 .reg_offset = 1,
226 },
227 [PALMAS_SHORT_IRQ] = {
228 .mask = PALMAS_INT2_STATUS_SHORT,
229 .reg_offset = 1,
230 },
231 [PALMAS_VAC_ACOK_IRQ] = {
232 .mask = PALMAS_INT2_STATUS_VAC_ACOK,
233 .reg_offset = 1,
234 },
235 /* INT3 IRQs */
236 [PALMAS_GPADC_AUTO_0_IRQ] = {
237 .mask = PALMAS_INT3_STATUS_GPADC_AUTO_0,
238 .reg_offset = 2,
239 },
240 [PALMAS_GPADC_AUTO_1_IRQ] = {
241 .mask = PALMAS_INT3_STATUS_GPADC_AUTO_1,
242 .reg_offset = 2,
243 },
244 [PALMAS_GPADC_EOC_SW_IRQ] = {
245 .mask = PALMAS_INT3_STATUS_GPADC_EOC_SW,
246 .reg_offset = 2,
247 },
248 [PALMAS_GPADC_EOC_RT_IRQ] = {
249 .mask = PALMAS_INT3_STATUS_GPADC_EOC_RT,
250 .reg_offset = 2,
251 },
252 [PALMAS_ID_OTG_IRQ] = {
253 .mask = PALMAS_INT3_STATUS_ID_OTG,
254 .reg_offset = 2,
255 },
256 [PALMAS_ID_IRQ] = {
257 .mask = PALMAS_INT3_STATUS_ID,
258 .reg_offset = 2,
259 },
260 [PALMAS_VBUS_OTG_IRQ] = {
261 .mask = PALMAS_INT3_STATUS_VBUS_OTG,
262 .reg_offset = 2,
263 },
264 [PALMAS_VBUS_IRQ] = {
265 .mask = PALMAS_INT3_STATUS_VBUS,
266 .reg_offset = 2,
267 },
268 /* INT4 IRQs */
269 [PALMAS_GPIO_0_IRQ] = {
270 .mask = PALMAS_INT4_STATUS_GPIO_0,
271 .reg_offset = 3,
272 },
273 [PALMAS_GPIO_1_IRQ] = {
274 .mask = PALMAS_INT4_STATUS_GPIO_1,
275 .reg_offset = 3,
276 },
277 [PALMAS_GPIO_2_IRQ] = {
278 .mask = PALMAS_INT4_STATUS_GPIO_2,
279 .reg_offset = 3,
280 },
281 [PALMAS_GPIO_3_IRQ] = {
282 .mask = PALMAS_INT4_STATUS_GPIO_3,
283 .reg_offset = 3,
284 },
285 [PALMAS_GPIO_4_IRQ] = {
286 .mask = PALMAS_INT4_STATUS_GPIO_4,
287 .reg_offset = 3,
288 },
289 [PALMAS_GPIO_5_IRQ] = {
290 .mask = PALMAS_INT4_STATUS_GPIO_5,
291 .reg_offset = 3,
292 },
293 [PALMAS_GPIO_6_IRQ] = {
294 .mask = PALMAS_INT4_STATUS_GPIO_6,
295 .reg_offset = 3,
296 },
297 [PALMAS_GPIO_7_IRQ] = {
298 .mask = PALMAS_INT4_STATUS_GPIO_7,
299 .reg_offset = 3,
300 },
301};
302
303static struct regmap_irq_chip palmas_irq_chip = {
304 .name = "palmas",
305 .irqs = palmas_irqs,
306 .num_irqs = ARRAY_SIZE(palmas_irqs),
307
308 .num_regs = 4,
309 .irq_reg_stride = 5,
310 .status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
311 PALMAS_INT1_STATUS),
312 .mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
313 PALMAS_INT1_MASK),
314};
315
1c113d83
K		 316static struct regmap_irq_chip tps65917_irq_chip = {
317 .name = "tps65917",
318 .irqs = tps65917_irqs,
319 .num_irqs = ARRAY_SIZE(tps65917_irqs),
320
321 .num_regs = 4,
322 .irq_reg_stride = 5,
323 .status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
324 PALMAS_INT1_STATUS),
325 .mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
326 PALMAS_INT1_MASK),
327};
328
cc01b463
LD		 329int palmas_ext_control_req_config(struct palmas *palmas,
330 enum palmas_external_requestor_id id, int ext_ctrl, bool enable)
331{
cac9e916 332 struct palmas_pmic_driver_data *pmic_ddata = palmas->pmic_ddata;
cc01b463
LD		 333 int preq_mask_bit = 0;
334 int reg_add = 0;
cac9e916 335 int bit_pos, ret;
cc01b463
LD		 336
337 if (!(ext_ctrl & PALMAS_EXT_REQ))
338 return 0;
339
340 if (id >= PALMAS_EXTERNAL_REQSTR_ID_MAX)
341 return 0;
342
343 if (ext_ctrl & PALMAS_EXT_CONTROL_NSLEEP) {
344 reg_add = PALMAS_NSLEEP_RES_ASSIGN;
345 preq_mask_bit = 0;
346 } else if (ext_ctrl & PALMAS_EXT_CONTROL_ENABLE1) {
347 reg_add = PALMAS_ENABLE1_RES_ASSIGN;
348 preq_mask_bit = 1;
349 } else if (ext_ctrl & PALMAS_EXT_CONTROL_ENABLE2) {
350 reg_add = PALMAS_ENABLE2_RES_ASSIGN;
351 preq_mask_bit = 2;
352 }
353
cac9e916
K		 354 bit_pos = pmic_ddata->sleep_req_info[id].bit_pos;
355 reg_add += pmic_ddata->sleep_req_info[id].reg_offset;
cc01b463
LD		 356 if (enable)
357 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
358 reg_add, BIT(bit_pos), BIT(bit_pos));
359 else
360 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
361 reg_add, BIT(bit_pos), 0);
362 if (ret < 0) {
363 dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n",
364 reg_add, ret);
365 return ret;
366 }
367
368 /* Unmask the PREQ */
369 ret = palmas_update_bits(palmas, PALMAS_PMU_CONTROL_BASE,
370 PALMAS_POWER_CTRL, BIT(preq_mask_bit), 0);
371 if (ret < 0) {
372 dev_err(palmas->dev, "POWER_CTRL register update failed %d\n",
373 ret);
374 return ret;
375 }
376 return ret;
377}
378EXPORT_SYMBOL_GPL(palmas_ext_control_req_config);
379
df545d1c 380static int palmas_set_pdata_irq_flag(struct i2c_client *i2c,
9c14ac33
GG		 381 struct palmas_platform_data *pdata)
382{
df545d1c
LD		 383 struct irq_data *irq_data = irq_get_irq_data(i2c->irq);
384 if (!irq_data) {
385 dev_err(&i2c->dev, "Invalid IRQ: %d\n", i2c->irq);
386 return -EINVAL;
387 }
388
389 pdata->irq_flags = irqd_get_trigger_type(irq_data);
390 dev_info(&i2c->dev, "Irq flag is 0x%08x\n", pdata->irq_flags);
391 return 0;
392}
393
394static void palmas_dt_to_pdata(struct i2c_client *i2c,
395 struct palmas_platform_data *pdata)
396{
397 struct device_node *node = i2c->dev.of_node;
9c14ac33
GG		 398 int ret;
399 u32 prop;
400
2154a2b3 401 ret = of_property_read_u32(node, "ti,mux-pad1", &prop);
9c14ac33
GG		 402 if (!ret) {
403 pdata->mux_from_pdata = 1;
404 pdata->pad1 = prop;
405 }
406
2154a2b3 407 ret = of_property_read_u32(node, "ti,mux-pad2", &prop);
9c14ac33
GG		 408 if (!ret) {
409 pdata->mux_from_pdata = 1;
410 pdata->pad2 = prop;
411 }
412
413 /* The default for this register is all masked */
2154a2b3 414 ret = of_property_read_u32(node, "ti,power-ctrl", &prop);
9c14ac33
GG		 415 if (!ret)
416 pdata->power_ctrl = prop;
417 else
418 pdata->power_ctrl = PALMAS_POWER_CTRL_NSLEEP_MASK |
419 PALMAS_POWER_CTRL_ENABLE1_MASK |
420 PALMAS_POWER_CTRL_ENABLE2_MASK;
df545d1c
LD		 421 if (i2c->irq)
422 palmas_set_pdata_irq_flag(i2c, pdata);
b81eec09
BH		 423
424 pdata->pm_off = of_property_read_bool(node,
425 "ti,system-power-controller");
426}
427
428static struct palmas *palmas_dev;
429static void palmas_power_off(void)
430{
431 unsigned int addr;
432 int ret, slave;
85fdaf8e
K		 433 struct device_node *np = palmas_dev->dev->of_node;
434
435 if (of_property_read_bool(np, "ti,palmas-override-powerhold")) {
436 addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
437 PALMAS_PRIMARY_SECONDARY_PAD2);
438 slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE);
439
440 ret = regmap_update_bits(palmas_dev->regmap[slave], addr,
441 PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK, 0);
442 if (ret)
443 dev_err(palmas_dev->dev,
444 "Unable to write PRIMARY_SECONDARY_PAD2 %d\n",
445 ret);
446 }
b81eec09 447
b81eec09
BH		 448 slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
449 addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_DEV_CTRL);
450
451 ret = regmap_update_bits(
452 palmas_dev->regmap[slave],
453 addr,
454 PALMAS_DEV_CTRL_DEV_ON,
455 0);
456
457 if (ret)
458 pr_err("%s: Unable to write to DEV_CTRL_DEV_ON: %d\n",
459 __func__, ret);
9c14ac33
GG		 460}
461
1ffb0be3 462static unsigned int palmas_features = PALMAS_PMIC_FEATURE_SMPS10_BOOST;
4124e6e2 463static unsigned int tps659038_features;
1ffb0be3 464
1c113d83
K		 465struct palmas_driver_data {
466 unsigned int *features;
467 struct regmap_irq_chip *irq_chip;
468};
469
470static struct palmas_driver_data palmas_data = {
471 .features = &palmas_features,
472 .irq_chip = &palmas_irq_chip,
473};
474
475static struct palmas_driver_data tps659038_data = {
476 .features = &tps659038_features,
477 .irq_chip = &palmas_irq_chip,
478};
479
480static struct palmas_driver_data tps65917_data = {
481 .features = &tps659038_features,
482 .irq_chip = &tps65917_irq_chip,
483};
484
1ffb0be3
K		 485static const struct of_device_id of_palmas_match_tbl[] = {
486 {
487 .compatible = "ti,palmas",
1c113d83 488 .data = &palmas_data,
1ffb0be3 489 },
4124e6e2
K		 490 {
491 .compatible = "ti,tps659038",
1c113d83
K		 492 .data = &tps659038_data,
493 },
494 {
495 .compatible = "ti,tps65917",
496 .data = &tps65917_data,
4124e6e2 497 },
1ffb0be3
K		 498 { },
499};
2d8edaf0 500MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);
1ffb0be3 501
f791be49 502static int palmas_i2c_probe(struct i2c_client *i2c,
2945fbc2
GG		 503 const struct i2c_device_id *id)
504{
505 struct palmas *palmas;
506 struct palmas_platform_data *pdata;
1c113d83 507 struct palmas_driver_data *driver_data;
9c14ac33 508 struct device_node *node = i2c->dev.of_node;
2945fbc2 509 int ret = 0, i;
1c113d83 510 unsigned int reg, addr;
2945fbc2 511 int slave;
1ffb0be3 512 const struct of_device_id *match;
2945fbc2
GG		 513
514 pdata = dev_get_platdata(&i2c->dev);
9c14ac33
GG		 515
516 if (node && !pdata) {
517 pdata = devm_kzalloc(&i2c->dev, sizeof(*pdata), GFP_KERNEL);
518
519 if (!pdata)
520 return -ENOMEM;
521
df545d1c 522 palmas_dt_to_pdata(i2c, pdata);
9c14ac33
GG		 523 }
524
2945fbc2
GG		 525 if (!pdata)
526 return -EINVAL;
527
528 palmas = devm_kzalloc(&i2c->dev, sizeof(struct palmas), GFP_KERNEL);
529 if (palmas == NULL)
530 return -ENOMEM;
531
532 i2c_set_clientdata(i2c, palmas);
533 palmas->dev = &i2c->dev;
2945fbc2
GG		 534 palmas->irq = i2c->irq;
535
84195b77 536 match = of_match_device(of_palmas_match_tbl, &i2c->dev);
1ffb0be3
K		 537
538 if (!match)
539 return -ENODATA;
540
1c113d83
K		 541 driver_data = (struct palmas_driver_data *)match->data;
542 palmas->features = *driver_data->features;
1ffb0be3 543
2945fbc2
GG		 544 for (i = 0; i < PALMAS_NUM_CLIENTS; i++) {
545 if (i == 0)
546 palmas->i2c_clients[i] = i2c;
547 else {
548 palmas->i2c_clients[i] =
549 i2c_new_dummy(i2c->adapter,
550 i2c->addr + i);
551 if (!palmas->i2c_clients[i]) {
552 dev_err(palmas->dev,
553 "can't attach client %d\n", i);
554 ret = -ENOMEM;
5e172d75 555 goto err_i2c;
2945fbc2 556 }
c4fbec3c 557 palmas->i2c_clients[i]->dev.of_node = of_node_get(node);
2945fbc2
GG		 558 }
559 palmas->regmap[i] = devm_regmap_init_i2c(palmas->i2c_clients[i],
560 &palmas_regmap_config[i]);
561 if (IS_ERR(palmas->regmap[i])) {
562 ret = PTR_ERR(palmas->regmap[i]);
563 dev_err(palmas->dev,
564 "Failed to allocate regmap %d, err: %d\n",
565 i, ret);
5e172d75 566 goto err_i2c;
2945fbc2
GG		 567 }
568 }
569
ad522f4e
K		 570 if (!palmas->irq) {
571 dev_warn(palmas->dev, "IRQ missing: skipping irq request\n");
572 goto no_irq;
573 }
574
df545d1c
LD		 575 /* Change interrupt line output polarity */
576 if (pdata->irq_flags & IRQ_TYPE_LEVEL_HIGH)
577 reg = PALMAS_POLARITY_CTRL_INT_POLARITY;
578 else
579 reg = 0;
580 ret = palmas_update_bits(palmas, PALMAS_PU_PD_OD_BASE,
581 PALMAS_POLARITY_CTRL, PALMAS_POLARITY_CTRL_INT_POLARITY,
582 reg);
583 if (ret < 0) {
b5b086ab 584 dev_err(palmas->dev, "POLARITY_CTRL update failed: %d\n", ret);
5e172d75 585 goto err_i2c;
df545d1c
LD		 586 }
587
b330f85d
GG		 588 /* Change IRQ into clear on read mode for efficiency */
589 slave = PALMAS_BASE_TO_SLAVE(PALMAS_INTERRUPT_BASE);
590 addr = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE, PALMAS_INT_CTRL);
591 reg = PALMAS_INT_CTRL_INT_CLEAR;
592
593 regmap_write(palmas->regmap[slave], addr, reg);
594
595 ret = regmap_add_irq_chip(palmas->regmap[slave], palmas->irq,
1c113d83
K		 596 IRQF_ONESHOT | pdata->irq_flags, 0,
597 driver_data->irq_chip, &palmas->irq_data);
2945fbc2 598 if (ret < 0)
5e172d75 599 goto err_i2c;
2945fbc2 600
ad522f4e 601no_irq:
2945fbc2
GG		 602 slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE);
603 addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
604 PALMAS_PRIMARY_SECONDARY_PAD1);
605
606 if (pdata->mux_from_pdata) {
607 reg = pdata->pad1;
608 ret = regmap_write(palmas->regmap[slave], addr, reg);
609 if (ret)
3f78decc 610 goto err_irq;
2945fbc2
GG		 611 } else {
612 ret = regmap_read(palmas->regmap[slave], addr, &reg);
613 if (ret)
3f78decc 614 goto err_irq;
2945fbc2
GG		 615 }
616
617 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0))
618 palmas->gpio_muxed |= PALMAS_GPIO_0_MUXED;
619 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK))
620 palmas->gpio_muxed |= PALMAS_GPIO_1_MUXED;
621 else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) ==
622 (2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT))
623 palmas->led_muxed |= PALMAS_LED1_MUXED;
624 else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) ==
625 (3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT))
626 palmas->pwm_muxed |= PALMAS_PWM1_MUXED;
627 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK))
628 palmas->gpio_muxed |= PALMAS_GPIO_2_MUXED;
629 else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) ==
630 (2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT))
631 palmas->led_muxed |= PALMAS_LED2_MUXED;
632 else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) ==
633 (3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT))
634 palmas->pwm_muxed |= PALMAS_PWM2_MUXED;
635 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3))
636 palmas->gpio_muxed |= PALMAS_GPIO_3_MUXED;
637
638 addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
639 PALMAS_PRIMARY_SECONDARY_PAD2);
640
641 if (pdata->mux_from_pdata) {
642 reg = pdata->pad2;
643 ret = regmap_write(palmas->regmap[slave], addr, reg);
644 if (ret)
3f78decc 645 goto err_irq;
2945fbc2
GG		 646 } else {
647 ret = regmap_read(palmas->regmap[slave], addr, &reg);
648 if (ret)
3f78decc 649 goto err_irq;
2945fbc2
GG		 650 }
651
652 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4))
653 palmas->gpio_muxed |= PALMAS_GPIO_4_MUXED;
654 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK))
655 palmas->gpio_muxed |= PALMAS_GPIO_5_MUXED;
656 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6))
657 palmas->gpio_muxed |= PALMAS_GPIO_6_MUXED;
658 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK))
659 palmas->gpio_muxed |= PALMAS_GPIO_7_MUXED;
660
661 dev_info(palmas->dev, "Muxing GPIO %x, PWM %x, LED %x\n",
662 palmas->gpio_muxed, palmas->pwm_muxed,
663 palmas->led_muxed);
664
665 reg = pdata->power_ctrl;
666
667 slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
668 addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_POWER_CTRL);
669
670 ret = regmap_write(palmas->regmap[slave], addr, reg);
671 if (ret)
3f78decc 672 goto err_irq;
2945fbc2 673
9c14ac33
GG		 674 /*
675 * If we are probing with DT do this the DT way and return here
676 * otherwise continue and add devices using mfd helpers.
677 */
678 if (node) {
124e9deb 679 ret = devm_of_platform_populate(&i2c->dev);
b81eec09 680 if (ret < 0) {
9c14ac33 681 goto err_irq;
b81eec09
BH		 682 } else if (pdata->pm_off && !pm_power_off) {
683 palmas_dev = palmas;
684 pm_power_off = palmas_power_off;
b81eec09 685 }
9c14ac33
GG		 686 }
687
2945fbc2
GG		 688 return ret;
689
3f78decc
GG		 690err_irq:
691 regmap_del_irq_chip(palmas->irq, palmas->irq_data);
5e172d75
LD		 692err_i2c:
693 for (i = 1; i < PALMAS_NUM_CLIENTS; i++) {
694 if (palmas->i2c_clients[i])
695 i2c_unregister_device(palmas->i2c_clients[i]);
696 }
2945fbc2
GG		 697 return ret;
698}
699
700static int palmas_i2c_remove(struct i2c_client *i2c)
701{
702 struct palmas *palmas = i2c_get_clientdata(i2c);
5e172d75 703 int i;
2945fbc2 704
2945fbc2
GG		 705 regmap_del_irq_chip(palmas->irq, palmas->irq_data);
706
5e172d75
LD		 707 for (i = 1; i < PALMAS_NUM_CLIENTS; i++) {
708 if (palmas->i2c_clients[i])
709 i2c_unregister_device(palmas->i2c_clients[i]);
710 }
711
7178347e
LD		 712 if (palmas == palmas_dev) {
713 pm_power_off = NULL;
714 palmas_dev = NULL;
715 }
716
2945fbc2
GG		 717 return 0;
718}
719
720static const struct i2c_device_id palmas_i2c_id[] = {
721 { "palmas", },
722 { "twl6035", },
723 { "twl6037", },
724 { "tps65913", },
00ba81c1 725 { /* end */ }
2945fbc2
GG		 726};
727MODULE_DEVICE_TABLE(i2c, palmas_i2c_id);
728
2945fbc2
GG		 729static struct i2c_driver palmas_i2c_driver = {
730 .driver = {
731 .name = "palmas",
732 .of_match_table = of_palmas_match_tbl,
2945fbc2
GG		 733 },
734 .probe = palmas_i2c_probe,
735 .remove = palmas_i2c_remove,
736 .id_table = palmas_i2c_id,
737};
738
739static int __init palmas_i2c_init(void)
740{
741 return i2c_add_driver(&palmas_i2c_driver);
742}
743/* init early so consumer devices can complete system boot */
744subsys_initcall(palmas_i2c_init);
745
746static void __exit palmas_i2c_exit(void)
747{
748 i2c_del_driver(&palmas_i2c_driver);
749}
750module_exit(palmas_i2c_exit);
751
752MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
753MODULE_DESCRIPTION("Palmas chip family multi-function driver");
754MODULE_LICENSE("GPL");
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