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regulator: palmas: Add palmas_pmic_driver_data structure
[mirror_ubuntu-artful-kernel.git] / drivers / mfd / palmas.c
CommitLineData
2945fbc2
GG		 1/*
2 * TI Palmas MFD Driver
3 *
4 * Copyright 2011-2012 Texas Instruments Inc.
5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/slab.h>
19#include <linux/i2c.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22#include <linux/regmap.h>
23#include <linux/err.h>
24#include <linux/mfd/core.h>
25#include <linux/mfd/palmas.h>
1ffb0be3 26#include <linux/of_device.h>
2945fbc2 27
cc01b463
LD		 28#define EXTERNAL_REQUESTOR(_id, _offset, _pos) \
29 [PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \
30 .id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \
31 .reg_offset = _offset, \
32 .bit_pos = _pos, \
33 }
34
35static struct palmas_sleep_requestor_info sleep_req_info[] = {
36 EXTERNAL_REQUESTOR(REGEN1, 0, 0),
37 EXTERNAL_REQUESTOR(REGEN2, 0, 1),
38 EXTERNAL_REQUESTOR(SYSEN1, 0, 2),
39 EXTERNAL_REQUESTOR(SYSEN2, 0, 3),
40 EXTERNAL_REQUESTOR(CLK32KG, 0, 4),
41 EXTERNAL_REQUESTOR(CLK32KGAUDIO, 0, 5),
42 EXTERNAL_REQUESTOR(REGEN3, 0, 6),
43 EXTERNAL_REQUESTOR(SMPS12, 1, 0),
44 EXTERNAL_REQUESTOR(SMPS3, 1, 1),
45 EXTERNAL_REQUESTOR(SMPS45, 1, 2),
46 EXTERNAL_REQUESTOR(SMPS6, 1, 3),
47 EXTERNAL_REQUESTOR(SMPS7, 1, 4),
48 EXTERNAL_REQUESTOR(SMPS8, 1, 5),
49 EXTERNAL_REQUESTOR(SMPS9, 1, 6),
50 EXTERNAL_REQUESTOR(SMPS10, 1, 7),
51 EXTERNAL_REQUESTOR(LDO1, 2, 0),
52 EXTERNAL_REQUESTOR(LDO2, 2, 1),
53 EXTERNAL_REQUESTOR(LDO3, 2, 2),
54 EXTERNAL_REQUESTOR(LDO4, 2, 3),
55 EXTERNAL_REQUESTOR(LDO5, 2, 4),
56 EXTERNAL_REQUESTOR(LDO6, 2, 5),
57 EXTERNAL_REQUESTOR(LDO7, 2, 6),
58 EXTERNAL_REQUESTOR(LDO8, 2, 7),
59 EXTERNAL_REQUESTOR(LDO9, 3, 0),
60 EXTERNAL_REQUESTOR(LDOLN, 3, 1),
61 EXTERNAL_REQUESTOR(LDOUSB, 3, 2),
62};
63
2945fbc2
GG		 64static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
65 {
66 .reg_bits = 8,
67 .val_bits = 8,
68 .max_register = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
69 PALMAS_PRIMARY_SECONDARY_PAD3),
70 },
71 {
72 .reg_bits = 8,
73 .val_bits = 8,
74 .max_register = PALMAS_BASE_TO_REG(PALMAS_GPADC_BASE,
75 PALMAS_GPADC_SMPS_VSEL_MONITORING),
76 },
77 {
78 .reg_bits = 8,
79 .val_bits = 8,
80 .max_register = PALMAS_BASE_TO_REG(PALMAS_TRIM_GPADC_BASE,
81 PALMAS_GPADC_TRIM16),
82 },
83};
84
1c113d83
K		 85static const struct regmap_irq tps65917_irqs[] = {
86 /* INT1 IRQs */
87 [TPS65917_RESERVED1] = {
88 .mask = TPS65917_RESERVED,
89 },
90 [TPS65917_PWRON_IRQ] = {
91 .mask = TPS65917_INT1_STATUS_PWRON,
92 },
93 [TPS65917_LONG_PRESS_KEY_IRQ] = {
94 .mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY,
95 },
96 [TPS65917_RESERVED2] = {
97 .mask = TPS65917_RESERVED,
98 },
99 [TPS65917_PWRDOWN_IRQ] = {
100 .mask = TPS65917_INT1_STATUS_PWRDOWN,
101 },
102 [TPS65917_HOTDIE_IRQ] = {
103 .mask = TPS65917_INT1_STATUS_HOTDIE,
104 },
105 [TPS65917_VSYS_MON_IRQ] = {
106 .mask = TPS65917_INT1_STATUS_VSYS_MON,
107 },
108 [TPS65917_RESERVED3] = {
109 .mask = TPS65917_RESERVED,
110 },
111 /* INT2 IRQs*/
112 [TPS65917_RESERVED4] = {
113 .mask = TPS65917_RESERVED,
114 .reg_offset = 1,
115 },
116 [TPS65917_OTP_ERROR_IRQ] = {
117 .mask = TPS65917_INT2_STATUS_OTP_ERROR,
118 .reg_offset = 1,
119 },
120 [TPS65917_WDT_IRQ] = {
121 .mask = TPS65917_INT2_STATUS_WDT,
122 .reg_offset = 1,
123 },
124 [TPS65917_RESERVED5] = {
125 .mask = TPS65917_RESERVED,
126 .reg_offset = 1,
127 },
128 [TPS65917_RESET_IN_IRQ] = {
129 .mask = TPS65917_INT2_STATUS_RESET_IN,
130 .reg_offset = 1,
131 },
132 [TPS65917_FSD_IRQ] = {
133 .mask = TPS65917_INT2_STATUS_FSD,
134 .reg_offset = 1,
135 },
136 [TPS65917_SHORT_IRQ] = {
137 .mask = TPS65917_INT2_STATUS_SHORT,
138 .reg_offset = 1,
139 },
140 [TPS65917_RESERVED6] = {
141 .mask = TPS65917_RESERVED,
142 .reg_offset = 1,
143 },
144 /* INT3 IRQs */
145 [TPS65917_GPADC_AUTO_0_IRQ] = {
146 .mask = TPS65917_INT3_STATUS_GPADC_AUTO_0,
147 .reg_offset = 2,
148 },
149 [TPS65917_GPADC_AUTO_1_IRQ] = {
150 .mask = TPS65917_INT3_STATUS_GPADC_AUTO_1,
151 .reg_offset = 2,
152 },
153 [TPS65917_GPADC_EOC_SW_IRQ] = {
154 .mask = TPS65917_INT3_STATUS_GPADC_EOC_SW,
155 .reg_offset = 2,
156 },
157 [TPS65917_RESREVED6] = {
158 .mask = TPS65917_RESERVED6,
159 .reg_offset = 2,
160 },
161 [TPS65917_RESERVED7] = {
162 .mask = TPS65917_RESERVED,
163 .reg_offset = 2,
164 },
165 [TPS65917_RESERVED8] = {
166 .mask = TPS65917_RESERVED,
167 .reg_offset = 2,
168 },
169 [TPS65917_RESERVED9] = {
170 .mask = TPS65917_RESERVED,
171 .reg_offset = 2,
172 },
173 [TPS65917_VBUS_IRQ] = {
174 .mask = TPS65917_INT3_STATUS_VBUS,
175 .reg_offset = 2,
176 },
177 /* INT4 IRQs */
178 [TPS65917_GPIO_0_IRQ] = {
179 .mask = TPS65917_INT4_STATUS_GPIO_0,
180 .reg_offset = 3,
181 },
182 [TPS65917_GPIO_1_IRQ] = {
183 .mask = TPS65917_INT4_STATUS_GPIO_1,
184 .reg_offset = 3,
185 },
186 [TPS65917_GPIO_2_IRQ] = {
187 .mask = TPS65917_INT4_STATUS_GPIO_2,
188 .reg_offset = 3,
189 },
190 [TPS65917_GPIO_3_IRQ] = {
191 .mask = TPS65917_INT4_STATUS_GPIO_3,
192 .reg_offset = 3,
193 },
194 [TPS65917_GPIO_4_IRQ] = {
195 .mask = TPS65917_INT4_STATUS_GPIO_4,
196 .reg_offset = 3,
197 },
198 [TPS65917_GPIO_5_IRQ] = {
199 .mask = TPS65917_INT4_STATUS_GPIO_5,
200 .reg_offset = 3,
201 },
202 [TPS65917_GPIO_6_IRQ] = {
203 .mask = TPS65917_INT4_STATUS_GPIO_6,
204 .reg_offset = 3,
205 },
206 [TPS65917_RESERVED10] = {
207 .mask = TPS65917_RESERVED10,
208 .reg_offset = 3,
209 },
210};
211
2945fbc2
GG		 212static const struct regmap_irq palmas_irqs[] = {
213 /* INT1 IRQs */
214 [PALMAS_CHARG_DET_N_VBUS_OVV_IRQ] = {
215 .mask = PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV,
216 },
217 [PALMAS_PWRON_IRQ] = {
218 .mask = PALMAS_INT1_STATUS_PWRON,
219 },
220 [PALMAS_LONG_PRESS_KEY_IRQ] = {
221 .mask = PALMAS_INT1_STATUS_LONG_PRESS_KEY,
222 },
223 [PALMAS_RPWRON_IRQ] = {
224 .mask = PALMAS_INT1_STATUS_RPWRON,
225 },
226 [PALMAS_PWRDOWN_IRQ] = {
227 .mask = PALMAS_INT1_STATUS_PWRDOWN,
228 },
229 [PALMAS_HOTDIE_IRQ] = {
230 .mask = PALMAS_INT1_STATUS_HOTDIE,
231 },
232 [PALMAS_VSYS_MON_IRQ] = {
233 .mask = PALMAS_INT1_STATUS_VSYS_MON,
234 },
235 [PALMAS_VBAT_MON_IRQ] = {
236 .mask = PALMAS_INT1_STATUS_VBAT_MON,
237 },
238 /* INT2 IRQs*/
239 [PALMAS_RTC_ALARM_IRQ] = {
240 .mask = PALMAS_INT2_STATUS_RTC_ALARM,
241 .reg_offset = 1,
242 },
243 [PALMAS_RTC_TIMER_IRQ] = {
244 .mask = PALMAS_INT2_STATUS_RTC_TIMER,
245 .reg_offset = 1,
246 },
247 [PALMAS_WDT_IRQ] = {
248 .mask = PALMAS_INT2_STATUS_WDT,
249 .reg_offset = 1,
250 },
251 [PALMAS_BATREMOVAL_IRQ] = {
252 .mask = PALMAS_INT2_STATUS_BATREMOVAL,
253 .reg_offset = 1,
254 },
255 [PALMAS_RESET_IN_IRQ] = {
256 .mask = PALMAS_INT2_STATUS_RESET_IN,
257 .reg_offset = 1,
258 },
259 [PALMAS_FBI_BB_IRQ] = {
260 .mask = PALMAS_INT2_STATUS_FBI_BB,
261 .reg_offset = 1,
262 },
263 [PALMAS_SHORT_IRQ] = {
264 .mask = PALMAS_INT2_STATUS_SHORT,
265 .reg_offset = 1,
266 },
267 [PALMAS_VAC_ACOK_IRQ] = {
268 .mask = PALMAS_INT2_STATUS_VAC_ACOK,
269 .reg_offset = 1,
270 },
271 /* INT3 IRQs */
272 [PALMAS_GPADC_AUTO_0_IRQ] = {
273 .mask = PALMAS_INT3_STATUS_GPADC_AUTO_0,
274 .reg_offset = 2,
275 },
276 [PALMAS_GPADC_AUTO_1_IRQ] = {
277 .mask = PALMAS_INT3_STATUS_GPADC_AUTO_1,
278 .reg_offset = 2,
279 },
280 [PALMAS_GPADC_EOC_SW_IRQ] = {
281 .mask = PALMAS_INT3_STATUS_GPADC_EOC_SW,
282 .reg_offset = 2,
283 },
284 [PALMAS_GPADC_EOC_RT_IRQ] = {
285 .mask = PALMAS_INT3_STATUS_GPADC_EOC_RT,
286 .reg_offset = 2,
287 },
288 [PALMAS_ID_OTG_IRQ] = {
289 .mask = PALMAS_INT3_STATUS_ID_OTG,
290 .reg_offset = 2,
291 },
292 [PALMAS_ID_IRQ] = {
293 .mask = PALMAS_INT3_STATUS_ID,
294 .reg_offset = 2,
295 },
296 [PALMAS_VBUS_OTG_IRQ] = {
297 .mask = PALMAS_INT3_STATUS_VBUS_OTG,
298 .reg_offset = 2,
299 },
300 [PALMAS_VBUS_IRQ] = {
301 .mask = PALMAS_INT3_STATUS_VBUS,
302 .reg_offset = 2,
303 },
304 /* INT4 IRQs */
305 [PALMAS_GPIO_0_IRQ] = {
306 .mask = PALMAS_INT4_STATUS_GPIO_0,
307 .reg_offset = 3,
308 },
309 [PALMAS_GPIO_1_IRQ] = {
310 .mask = PALMAS_INT4_STATUS_GPIO_1,
311 .reg_offset = 3,
312 },
313 [PALMAS_GPIO_2_IRQ] = {
314 .mask = PALMAS_INT4_STATUS_GPIO_2,
315 .reg_offset = 3,
316 },
317 [PALMAS_GPIO_3_IRQ] = {
318 .mask = PALMAS_INT4_STATUS_GPIO_3,
319 .reg_offset = 3,
320 },
321 [PALMAS_GPIO_4_IRQ] = {
322 .mask = PALMAS_INT4_STATUS_GPIO_4,
323 .reg_offset = 3,
324 },
325 [PALMAS_GPIO_5_IRQ] = {
326 .mask = PALMAS_INT4_STATUS_GPIO_5,
327 .reg_offset = 3,
328 },
329 [PALMAS_GPIO_6_IRQ] = {
330 .mask = PALMAS_INT4_STATUS_GPIO_6,
331 .reg_offset = 3,
332 },
333 [PALMAS_GPIO_7_IRQ] = {
334 .mask = PALMAS_INT4_STATUS_GPIO_7,
335 .reg_offset = 3,
336 },
337};
338
339static struct regmap_irq_chip palmas_irq_chip = {
340 .name = "palmas",
341 .irqs = palmas_irqs,
342 .num_irqs = ARRAY_SIZE(palmas_irqs),
343
344 .num_regs = 4,
345 .irq_reg_stride = 5,
346 .status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
347 PALMAS_INT1_STATUS),
348 .mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
349 PALMAS_INT1_MASK),
350};
351
1c113d83
K		 352static struct regmap_irq_chip tps65917_irq_chip = {
353 .name = "tps65917",
354 .irqs = tps65917_irqs,
355 .num_irqs = ARRAY_SIZE(tps65917_irqs),
356
357 .num_regs = 4,
358 .irq_reg_stride = 5,
359 .status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
360 PALMAS_INT1_STATUS),
361 .mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
362 PALMAS_INT1_MASK),
363};
364
cc01b463
LD		 365int palmas_ext_control_req_config(struct palmas *palmas,
366 enum palmas_external_requestor_id id, int ext_ctrl, bool enable)
367{
368 int preq_mask_bit = 0;
369 int reg_add = 0;
370 int bit_pos;
371 int ret;
372
373 if (!(ext_ctrl & PALMAS_EXT_REQ))
374 return 0;
375
376 if (id >= PALMAS_EXTERNAL_REQSTR_ID_MAX)
377 return 0;
378
379 if (ext_ctrl & PALMAS_EXT_CONTROL_NSLEEP) {
380 reg_add = PALMAS_NSLEEP_RES_ASSIGN;
381 preq_mask_bit = 0;
382 } else if (ext_ctrl & PALMAS_EXT_CONTROL_ENABLE1) {
383 reg_add = PALMAS_ENABLE1_RES_ASSIGN;
384 preq_mask_bit = 1;
385 } else if (ext_ctrl & PALMAS_EXT_CONTROL_ENABLE2) {
386 reg_add = PALMAS_ENABLE2_RES_ASSIGN;
387 preq_mask_bit = 2;
388 }
389
390 bit_pos = sleep_req_info[id].bit_pos;
391 reg_add += sleep_req_info[id].reg_offset;
392 if (enable)
393 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
394 reg_add, BIT(bit_pos), BIT(bit_pos));
395 else
396 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
397 reg_add, BIT(bit_pos), 0);
398 if (ret < 0) {
399 dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n",
400 reg_add, ret);
401 return ret;
402 }
403
404 /* Unmask the PREQ */
405 ret = palmas_update_bits(palmas, PALMAS_PMU_CONTROL_BASE,
406 PALMAS_POWER_CTRL, BIT(preq_mask_bit), 0);
407 if (ret < 0) {
408 dev_err(palmas->dev, "POWER_CTRL register update failed %d\n",
409 ret);
410 return ret;
411 }
412 return ret;
413}
414EXPORT_SYMBOL_GPL(palmas_ext_control_req_config);
415
df545d1c 416static int palmas_set_pdata_irq_flag(struct i2c_client *i2c,
9c14ac33
GG		 417 struct palmas_platform_data *pdata)
418{
df545d1c
LD		 419 struct irq_data *irq_data = irq_get_irq_data(i2c->irq);
420 if (!irq_data) {
421 dev_err(&i2c->dev, "Invalid IRQ: %d\n", i2c->irq);
422 return -EINVAL;
423 }
424
425 pdata->irq_flags = irqd_get_trigger_type(irq_data);
426 dev_info(&i2c->dev, "Irq flag is 0x%08x\n", pdata->irq_flags);
427 return 0;
428}
429
430static void palmas_dt_to_pdata(struct i2c_client *i2c,
431 struct palmas_platform_data *pdata)
432{
433 struct device_node *node = i2c->dev.of_node;
9c14ac33
GG		 434 int ret;
435 u32 prop;
436
2154a2b3 437 ret = of_property_read_u32(node, "ti,mux-pad1", &prop);
9c14ac33
GG		 438 if (!ret) {
439 pdata->mux_from_pdata = 1;
440 pdata->pad1 = prop;
441 }
442
2154a2b3 443 ret = of_property_read_u32(node, "ti,mux-pad2", &prop);
9c14ac33
GG		 444 if (!ret) {
445 pdata->mux_from_pdata = 1;
446 pdata->pad2 = prop;
447 }
448
449 /* The default for this register is all masked */
2154a2b3 450 ret = of_property_read_u32(node, "ti,power-ctrl", &prop);
9c14ac33
GG		 451 if (!ret)
452 pdata->power_ctrl = prop;
453 else
454 pdata->power_ctrl = PALMAS_POWER_CTRL_NSLEEP_MASK |
455 PALMAS_POWER_CTRL_ENABLE1_MASK |
456 PALMAS_POWER_CTRL_ENABLE2_MASK;
df545d1c
LD		 457 if (i2c->irq)
458 palmas_set_pdata_irq_flag(i2c, pdata);
b81eec09
BH		 459
460 pdata->pm_off = of_property_read_bool(node,
461 "ti,system-power-controller");
462}
463
464static struct palmas *palmas_dev;
465static void palmas_power_off(void)
466{
467 unsigned int addr;
468 int ret, slave;
469
470 if (!palmas_dev)
471 return;
472
473 slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
474 addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_DEV_CTRL);
475
476 ret = regmap_update_bits(
477 palmas_dev->regmap[slave],
478 addr,
479 PALMAS_DEV_CTRL_DEV_ON,
480 0);
481
482 if (ret)
483 pr_err("%s: Unable to write to DEV_CTRL_DEV_ON: %d\n",
484 __func__, ret);
9c14ac33
GG		 485}
486
1ffb0be3 487static unsigned int palmas_features = PALMAS_PMIC_FEATURE_SMPS10_BOOST;
4124e6e2 488static unsigned int tps659038_features;
1ffb0be3 489
1c113d83
K		 490struct palmas_driver_data {
491 unsigned int *features;
492 struct regmap_irq_chip *irq_chip;
493};
494
495static struct palmas_driver_data palmas_data = {
496 .features = &palmas_features,
497 .irq_chip = &palmas_irq_chip,
498};
499
500static struct palmas_driver_data tps659038_data = {
501 .features = &tps659038_features,
502 .irq_chip = &palmas_irq_chip,
503};
504
505static struct palmas_driver_data tps65917_data = {
506 .features = &tps659038_features,
507 .irq_chip = &tps65917_irq_chip,
508};
509
1ffb0be3
K		 510static const struct of_device_id of_palmas_match_tbl[] = {
511 {
512 .compatible = "ti,palmas",
1c113d83 513 .data = &palmas_data,
1ffb0be3 514 },
4124e6e2
K		 515 {
516 .compatible = "ti,tps659038",
1c113d83
K		 517 .data = &tps659038_data,
518 },
519 {
520 .compatible = "ti,tps65917",
521 .data = &tps65917_data,
4124e6e2 522 },
1ffb0be3
K		 523 { },
524};
2d8edaf0 525MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);
1ffb0be3 526
f791be49 527static int palmas_i2c_probe(struct i2c_client *i2c,
2945fbc2
GG		 528 const struct i2c_device_id *id)
529{
530 struct palmas *palmas;
531 struct palmas_platform_data *pdata;
1c113d83 532 struct palmas_driver_data *driver_data;
9c14ac33 533 struct device_node *node = i2c->dev.of_node;
2945fbc2 534 int ret = 0, i;
1c113d83 535 unsigned int reg, addr;
2945fbc2 536 int slave;
1ffb0be3 537 const struct of_device_id *match;
2945fbc2
GG		 538
539 pdata = dev_get_platdata(&i2c->dev);
9c14ac33
GG		 540
541 if (node && !pdata) {
542 pdata = devm_kzalloc(&i2c->dev, sizeof(*pdata), GFP_KERNEL);
543
544 if (!pdata)
545 return -ENOMEM;
546
df545d1c 547 palmas_dt_to_pdata(i2c, pdata);
9c14ac33
GG		 548 }
549
2945fbc2
GG		 550 if (!pdata)
551 return -EINVAL;
552
553 palmas = devm_kzalloc(&i2c->dev, sizeof(struct palmas), GFP_KERNEL);
554 if (palmas == NULL)
555 return -ENOMEM;
556
557 i2c_set_clientdata(i2c, palmas);
558 palmas->dev = &i2c->dev;
2945fbc2
GG		 559 palmas->irq = i2c->irq;
560
84195b77 561 match = of_match_device(of_palmas_match_tbl, &i2c->dev);
1ffb0be3
K		 562
563 if (!match)
564 return -ENODATA;
565
1c113d83
K		 566 driver_data = (struct palmas_driver_data *)match->data;
567 palmas->features = *driver_data->features;
1ffb0be3 568
2945fbc2
GG		 569 for (i = 0; i < PALMAS_NUM_CLIENTS; i++) {
570 if (i == 0)
571 palmas->i2c_clients[i] = i2c;
572 else {
573 palmas->i2c_clients[i] =
574 i2c_new_dummy(i2c->adapter,
575 i2c->addr + i);
576 if (!palmas->i2c_clients[i]) {
577 dev_err(palmas->dev,
578 "can't attach client %d\n", i);
579 ret = -ENOMEM;
5e172d75 580 goto err_i2c;
2945fbc2 581 }
c4fbec3c 582 palmas->i2c_clients[i]->dev.of_node = of_node_get(node);
2945fbc2
GG		 583 }
584 palmas->regmap[i] = devm_regmap_init_i2c(palmas->i2c_clients[i],
585 &palmas_regmap_config[i]);
586 if (IS_ERR(palmas->regmap[i])) {
587 ret = PTR_ERR(palmas->regmap[i]);
588 dev_err(palmas->dev,
589 "Failed to allocate regmap %d, err: %d\n",
590 i, ret);
5e172d75 591 goto err_i2c;
2945fbc2
GG		 592 }
593 }
594
ad522f4e
K		 595 if (!palmas->irq) {
596 dev_warn(palmas->dev, "IRQ missing: skipping irq request\n");
597 goto no_irq;
598 }
599
df545d1c
LD		 600 /* Change interrupt line output polarity */
601 if (pdata->irq_flags & IRQ_TYPE_LEVEL_HIGH)
602 reg = PALMAS_POLARITY_CTRL_INT_POLARITY;
603 else
604 reg = 0;
605 ret = palmas_update_bits(palmas, PALMAS_PU_PD_OD_BASE,
606 PALMAS_POLARITY_CTRL, PALMAS_POLARITY_CTRL_INT_POLARITY,
607 reg);
608 if (ret < 0) {
609 dev_err(palmas->dev, "POLARITY_CTRL updat failed: %d\n", ret);
5e172d75 610 goto err_i2c;
df545d1c
LD		 611 }
612
b330f85d
GG		 613 /* Change IRQ into clear on read mode for efficiency */
614 slave = PALMAS_BASE_TO_SLAVE(PALMAS_INTERRUPT_BASE);
615 addr = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE, PALMAS_INT_CTRL);
616 reg = PALMAS_INT_CTRL_INT_CLEAR;
617
618 regmap_write(palmas->regmap[slave], addr, reg);
619
620 ret = regmap_add_irq_chip(palmas->regmap[slave], palmas->irq,
1c113d83
K		 621 IRQF_ONESHOT | pdata->irq_flags, 0,
622 driver_data->irq_chip, &palmas->irq_data);
2945fbc2 623 if (ret < 0)
5e172d75 624 goto err_i2c;
2945fbc2 625
ad522f4e 626no_irq:
2945fbc2
GG		 627 slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE);
628 addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
629 PALMAS_PRIMARY_SECONDARY_PAD1);
630
631 if (pdata->mux_from_pdata) {
632 reg = pdata->pad1;
633 ret = regmap_write(palmas->regmap[slave], addr, reg);
634 if (ret)
3f78decc 635 goto err_irq;
2945fbc2
GG		 636 } else {
637 ret = regmap_read(palmas->regmap[slave], addr, &reg);
638 if (ret)
3f78decc 639 goto err_irq;
2945fbc2
GG		 640 }
641
642 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0))
643 palmas->gpio_muxed |= PALMAS_GPIO_0_MUXED;
644 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK))
645 palmas->gpio_muxed |= PALMAS_GPIO_1_MUXED;
646 else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) ==
647 (2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT))
648 palmas->led_muxed |= PALMAS_LED1_MUXED;
649 else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) ==
650 (3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT))
651 palmas->pwm_muxed |= PALMAS_PWM1_MUXED;
652 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK))
653 palmas->gpio_muxed |= PALMAS_GPIO_2_MUXED;
654 else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) ==
655 (2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT))
656 palmas->led_muxed |= PALMAS_LED2_MUXED;
657 else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) ==
658 (3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT))
659 palmas->pwm_muxed |= PALMAS_PWM2_MUXED;
660 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3))
661 palmas->gpio_muxed |= PALMAS_GPIO_3_MUXED;
662
663 addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
664 PALMAS_PRIMARY_SECONDARY_PAD2);
665
666 if (pdata->mux_from_pdata) {
667 reg = pdata->pad2;
668 ret = regmap_write(palmas->regmap[slave], addr, reg);
669 if (ret)
3f78decc 670 goto err_irq;
2945fbc2
GG		 671 } else {
672 ret = regmap_read(palmas->regmap[slave], addr, &reg);
673 if (ret)
3f78decc 674 goto err_irq;
2945fbc2
GG		 675 }
676
677 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4))
678 palmas->gpio_muxed |= PALMAS_GPIO_4_MUXED;
679 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK))
680 palmas->gpio_muxed |= PALMAS_GPIO_5_MUXED;
681 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6))
682 palmas->gpio_muxed |= PALMAS_GPIO_6_MUXED;
683 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK))
684 palmas->gpio_muxed |= PALMAS_GPIO_7_MUXED;
685
686 dev_info(palmas->dev, "Muxing GPIO %x, PWM %x, LED %x\n",
687 palmas->gpio_muxed, palmas->pwm_muxed,
688 palmas->led_muxed);
689
690 reg = pdata->power_ctrl;
691
692 slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
693 addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_POWER_CTRL);
694
695 ret = regmap_write(palmas->regmap[slave], addr, reg);
696 if (ret)
3f78decc 697 goto err_irq;
2945fbc2 698
9c14ac33
GG		 699 /*
700 * If we are probing with DT do this the DT way and return here
701 * otherwise continue and add devices using mfd helpers.
702 */
703 if (node) {
704 ret = of_platform_populate(node, NULL, NULL, &i2c->dev);
b81eec09 705 if (ret < 0) {
9c14ac33 706 goto err_irq;
b81eec09
BH		 707 } else if (pdata->pm_off && !pm_power_off) {
708 palmas_dev = palmas;
709 pm_power_off = palmas_power_off;
b81eec09 710 }
9c14ac33
GG		 711 }
712
2945fbc2
GG		 713 return ret;
714
3f78decc
GG		 715err_irq:
716 regmap_del_irq_chip(palmas->irq, palmas->irq_data);
5e172d75
LD		 717err_i2c:
718 for (i = 1; i < PALMAS_NUM_CLIENTS; i++) {
719 if (palmas->i2c_clients[i])
720 i2c_unregister_device(palmas->i2c_clients[i]);
721 }
2945fbc2
GG		 722 return ret;
723}
724
725static int palmas_i2c_remove(struct i2c_client *i2c)
726{
727 struct palmas *palmas = i2c_get_clientdata(i2c);
5e172d75 728 int i;
2945fbc2 729
2945fbc2
GG		 730 regmap_del_irq_chip(palmas->irq, palmas->irq_data);
731
5e172d75
LD		 732 for (i = 1; i < PALMAS_NUM_CLIENTS; i++) {
733 if (palmas->i2c_clients[i])
734 i2c_unregister_device(palmas->i2c_clients[i]);
735 }
736
7178347e
LD		 737 if (palmas == palmas_dev) {
738 pm_power_off = NULL;
739 palmas_dev = NULL;
740 }
741
2945fbc2
GG		 742 return 0;
743}
744
745static const struct i2c_device_id palmas_i2c_id[] = {
746 { "palmas", },
747 { "twl6035", },
748 { "twl6037", },
749 { "tps65913", },
00ba81c1 750 { /* end */ }
2945fbc2
GG		 751};
752MODULE_DEVICE_TABLE(i2c, palmas_i2c_id);
753
2945fbc2
GG		 754static struct i2c_driver palmas_i2c_driver = {
755 .driver = {
756 .name = "palmas",
757 .of_match_table = of_palmas_match_tbl,
758 .owner = THIS_MODULE,
759 },
760 .probe = palmas_i2c_probe,
761 .remove = palmas_i2c_remove,
762 .id_table = palmas_i2c_id,
763};
764
765static int __init palmas_i2c_init(void)
766{
767 return i2c_add_driver(&palmas_i2c_driver);
768}
769/* init early so consumer devices can complete system boot */
770subsys_initcall(palmas_i2c_init);
771
772static void __exit palmas_i2c_exit(void)
773{
774 i2c_del_driver(&palmas_i2c_driver);
775}
776module_exit(palmas_i2c_exit);
777
778MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
779MODULE_DESCRIPTION("Palmas chip family multi-function driver");
780MODULE_LICENSE("GPL");
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