[mirror_ubuntu-bionic-kernel.git] / drivers / mfd / pm8921-core.c

/*
 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#define pr_fmt(fmt) "%s: " fmt, __func__

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/ssbi.h>
#include <linux/of_platform.h>
#include <linux/mfd/core.h>
#include <linux/mfd/pm8xxx/core.h>

#define	SSBI_REG_ADDR_IRQ_BASE		0x1BB

#define	SSBI_REG_ADDR_IRQ_ROOT		(SSBI_REG_ADDR_IRQ_BASE + 0)
#define	SSBI_REG_ADDR_IRQ_M_STATUS1	(SSBI_REG_ADDR_IRQ_BASE + 1)
#define	SSBI_REG_ADDR_IRQ_M_STATUS2	(SSBI_REG_ADDR_IRQ_BASE + 2)
#define	SSBI_REG_ADDR_IRQ_M_STATUS3	(SSBI_REG_ADDR_IRQ_BASE + 3)
#define	SSBI_REG_ADDR_IRQ_M_STATUS4	(SSBI_REG_ADDR_IRQ_BASE + 4)
#define	SSBI_REG_ADDR_IRQ_BLK_SEL	(SSBI_REG_ADDR_IRQ_BASE + 5)
#define	SSBI_REG_ADDR_IRQ_IT_STATUS	(SSBI_REG_ADDR_IRQ_BASE + 6)
#define	SSBI_REG_ADDR_IRQ_CONFIG	(SSBI_REG_ADDR_IRQ_BASE + 7)
#define	SSBI_REG_ADDR_IRQ_RT_STATUS	(SSBI_REG_ADDR_IRQ_BASE + 8)

#define	PM_IRQF_LVL_SEL			0x01	/* level select */
#define	PM_IRQF_MASK_FE			0x02	/* mask falling edge */
#define	PM_IRQF_MASK_RE			0x04	/* mask rising edge */
#define	PM_IRQF_CLR			0x08	/* clear interrupt */
#define	PM_IRQF_BITS_MASK		0x70
#define	PM_IRQF_BITS_SHIFT		4
#define	PM_IRQF_WRITE			0x80

#define	PM_IRQF_MASK_ALL		(PM_IRQF_MASK_FE | \
					PM_IRQF_MASK_RE)

#define REG_HWREV		0x002  /* PMIC4 revision */
#define REG_HWREV_2		0x0E8  /* PMIC4 revision 2 */

#define PM8921_NR_IRQS		256

struct pm_irq_chip {
	struct device		*dev;
	spinlock_t		pm_irq_lock;
	struct irq_domain	*irqdomain;
	unsigned int		num_irqs;
	unsigned int		num_blocks;
	unsigned int		num_masters;
	u8			config[0];
};

struct pm8921 {
	struct device			*dev;
	struct pm_irq_chip		*irq_chip;
};

static int pm8xxx_read_root_irq(const struct pm_irq_chip *chip, u8 *rp)
{
	return pm8xxx_readb(chip->dev, SSBI_REG_ADDR_IRQ_ROOT, rp);
}

static int pm8xxx_read_master_irq(const struct pm_irq_chip *chip, u8 m, u8 *bp)
{
	return pm8xxx_readb(chip->dev,
			SSBI_REG_ADDR_IRQ_M_STATUS1 + m, bp);
}

static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, u8 bp, u8 *ip)
{
	int	rc;

	spin_lock(&chip->pm_irq_lock);
	rc = pm8xxx_writeb(chip->dev, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
	if (rc) {
		pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
		goto bail;
	}

	rc = pm8xxx_readb(chip->dev, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
	if (rc)
		pr_err("Failed Reading Status rc=%d\n", rc);
bail:
	spin_unlock(&chip->pm_irq_lock);
	return rc;
}

static int pm8xxx_config_irq(struct pm_irq_chip *chip, u8 bp, u8 cp)
{
	int	rc;

	spin_lock(&chip->pm_irq_lock);
	rc = pm8xxx_writeb(chip->dev, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
	if (rc) {
		pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
		goto bail;
	}

	cp |= PM_IRQF_WRITE;
	rc = pm8xxx_writeb(chip->dev, SSBI_REG_ADDR_IRQ_CONFIG, cp);
	if (rc)
		pr_err("Failed Configuring IRQ rc=%d\n", rc);
bail:
	spin_unlock(&chip->pm_irq_lock);
	return rc;
}

static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
{
	int pmirq, irq, i, ret = 0;
	u8 bits;

	ret = pm8xxx_read_block_irq(chip, block, &bits);
	if (ret) {
		pr_err("Failed reading %d block ret=%d", block, ret);
		return ret;
	}
	if (!bits) {
		pr_err("block bit set in master but no irqs: %d", block);
		return 0;
	}

	/* Check IRQ bits */
	for (i = 0; i < 8; i++) {
		if (bits & (1 << i)) {
			pmirq = block * 8 + i;
			irq = irq_find_mapping(chip->irqdomain, pmirq);
			generic_handle_irq(irq);
		}
	}
	return 0;
}

static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
{
	u8 blockbits;
	int block_number, i, ret = 0;

	ret = pm8xxx_read_master_irq(chip, master, &blockbits);
	if (ret) {
		pr_err("Failed to read master %d ret=%d\n", master, ret);
		return ret;
	}
	if (!blockbits) {
		pr_err("master bit set in root but no blocks: %d", master);
		return 0;
	}

	for (i = 0; i < 8; i++)
		if (blockbits & (1 << i)) {
			block_number = master * 8 + i;	/* block # */
			ret |= pm8xxx_irq_block_handler(chip, block_number);
		}
	return ret;
}

static void pm8xxx_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
	u8	root;
	int	i, ret, masters = 0;

	chained_irq_enter(irq_chip, desc);

	ret = pm8xxx_read_root_irq(chip, &root);
	if (ret) {
		pr_err("Can't read root status ret=%d\n", ret);
		return;
	}

	/* on pm8xxx series masters start from bit 1 of the root */
	masters = root >> 1;

	/* Read allowed masters for blocks. */
	for (i = 0; i < chip->num_masters; i++)
		if (masters & (1 << i))
			pm8xxx_irq_master_handler(chip, i);

	chained_irq_exit(irq_chip, desc);
}

static void pm8xxx_irq_mask_ack(struct irq_data *d)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	int	irq_bit;
	u8	block, config;

	block = pmirq / 8;
	irq_bit = pmirq % 8;

	config = chip->config[pmirq] | PM_IRQF_MASK_ALL | PM_IRQF_CLR;
	pm8xxx_config_irq(chip, block, config);
}

static void pm8xxx_irq_unmask(struct irq_data *d)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	int	irq_bit;
	u8	block, config;

	block = pmirq / 8;
	irq_bit = pmirq % 8;

	config = chip->config[pmirq];
	pm8xxx_config_irq(chip, block, config);
}

static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	int irq_bit;
	u8 block, config;

	block = pmirq / 8;
	irq_bit  = pmirq % 8;

	chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
							| PM_IRQF_MASK_ALL;
	if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
		if (flow_type & IRQF_TRIGGER_RISING)
			chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
		if (flow_type & IRQF_TRIGGER_FALLING)
			chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
	} else {
		chip->config[pmirq] |= PM_IRQF_LVL_SEL;

		if (flow_type & IRQF_TRIGGER_HIGH)
			chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
		else
			chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
	}

	config = chip->config[pmirq] | PM_IRQF_CLR;
	return pm8xxx_config_irq(chip, block, config);
}

static int pm8xxx_irq_set_wake(struct irq_data *d, unsigned int on)
{
	return 0;
}

static struct irq_chip pm8xxx_irq_chip = {
	.name		= "pm8xxx",
	.irq_mask_ack	= pm8xxx_irq_mask_ack,
	.irq_unmask	= pm8xxx_irq_unmask,
	.irq_set_type	= pm8xxx_irq_set_type,
	.irq_set_wake	= pm8xxx_irq_set_wake,
	.flags		= IRQCHIP_MASK_ON_SUSPEND,
};

/**
 * pm8xxx_get_irq_stat - get the status of the irq line
 * @chip: pointer to identify a pmic irq controller
 * @irq: the irq number
 *
 * The pm8xxx gpio and mpp rely on the interrupt block to read
 * the values on their pins. This function is to facilitate reading
 * the status of a gpio or an mpp line. The caller has to convert the
 * gpio number to irq number.
 *
 * RETURNS:
 * an int indicating the value read on that line
 */
static int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq)
{
	int pmirq, rc;
	u8  block, bits, bit;
	unsigned long flags;
	struct irq_data *irq_data = irq_get_irq_data(irq);

	pmirq = irq_data->hwirq;

	block = pmirq / 8;
	bit = pmirq % 8;

	spin_lock_irqsave(&chip->pm_irq_lock, flags);

	rc = pm8xxx_writeb(chip->dev, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
	if (rc) {
		pr_err("Failed Selecting block irq=%d pmirq=%d blk=%d rc=%d\n",
			irq, pmirq, block, rc);
		goto bail_out;
	}

	rc = pm8xxx_readb(chip->dev, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
	if (rc) {
		pr_err("Failed Configuring irq=%d pmirq=%d blk=%d rc=%d\n",
			irq, pmirq, block, rc);
		goto bail_out;
	}

	rc = (bits & (1 << bit)) ? 1 : 0;

bail_out:
	spin_unlock_irqrestore(&chip->pm_irq_lock, flags);

	return rc;
}

static struct lock_class_key pm8xxx_irq_lock_class;

static int pm8xxx_irq_domain_map(struct irq_domain *d, unsigned int irq,
				   irq_hw_number_t hwirq)
{
	struct pm_irq_chip *chip = d->host_data;

	irq_set_lockdep_class(irq, &pm8xxx_irq_lock_class);
	irq_set_chip_and_handler(irq, &pm8xxx_irq_chip, handle_level_irq);
	irq_set_chip_data(irq, chip);
#ifdef CONFIG_ARM
	set_irq_flags(irq, IRQF_VALID);
#else
	irq_set_noprobe(irq);
#endif
	return 0;
}

static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
	.xlate = irq_domain_xlate_twocell,
	.map = pm8xxx_irq_domain_map,
};

static int pm8921_readb(const struct device *dev, u16 addr, u8 *val)
{
	const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
	const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;

	return ssbi_read(pmic->dev->parent, addr, val, 1);
}

static int pm8921_writeb(const struct device *dev, u16 addr, u8 val)
{
	const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
	const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;

	return ssbi_write(pmic->dev->parent, addr, &val, 1);
}

static int pm8921_read_buf(const struct device *dev, u16 addr, u8 *buf,
									int cnt)
{
	const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
	const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;

	return ssbi_read(pmic->dev->parent, addr, buf, cnt);
}

static int pm8921_write_buf(const struct device *dev, u16 addr, u8 *buf,
									int cnt)
{
	const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
	const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;

	return ssbi_write(pmic->dev->parent, addr, buf, cnt);
}

static int pm8921_read_irq_stat(const struct device *dev, int irq)
{
	const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
	const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;

	return pm8xxx_get_irq_stat(pmic->irq_chip, irq);
}

static struct pm8xxx_drvdata pm8921_drvdata = {
	.pmic_readb		= pm8921_readb,
	.pmic_writeb		= pm8921_writeb,
	.pmic_read_buf		= pm8921_read_buf,
	.pmic_write_buf		= pm8921_write_buf,
	.pmic_read_irq_stat	= pm8921_read_irq_stat,
};

static int pm8921_probe(struct platform_device *pdev)
{
	struct pm8921 *pmic;
	int rc;
	u8 val;
	unsigned int irq;
	u32 rev;
	struct pm_irq_chip *chip;
	unsigned int nirqs = PM8921_NR_IRQS;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	pmic = devm_kzalloc(&pdev->dev, sizeof(struct pm8921), GFP_KERNEL);
	if (!pmic) {
		pr_err("Cannot alloc pm8921 struct\n");
		return -ENOMEM;
	}

	/* Read PMIC chip revision */
	rc = ssbi_read(pdev->dev.parent, REG_HWREV, &val, sizeof(val));
	if (rc) {
		pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
		return rc;
	}
	pr_info("PMIC revision 1: %02X\n", val);
	rev = val;

	/* Read PMIC chip revision 2 */
	rc = ssbi_read(pdev->dev.parent, REG_HWREV_2, &val, sizeof(val));
	if (rc) {
		pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
			REG_HWREV_2, rc);
		return rc;
	}
	pr_info("PMIC revision 2: %02X\n", val);
	rev |= val << BITS_PER_BYTE;

	pmic->dev = &pdev->dev;
	pm8921_drvdata.pm_chip_data = pmic;
	platform_set_drvdata(pdev, &pm8921_drvdata);

	chip = devm_kzalloc(&pdev->dev, sizeof(*chip) +
					sizeof(chip->config[0]) * nirqs,
					GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	pmic->irq_chip = chip;
	chip->dev = &pdev->dev;
	chip->num_irqs = nirqs;
	chip->num_blocks = DIV_ROUND_UP(chip->num_irqs, 8);
	chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
	spin_lock_init(&chip->pm_irq_lock);

	chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node, nirqs,
						&pm8xxx_irq_domain_ops,
						chip);
	if (!chip->irqdomain)
		return -ENODEV;

	irq_set_handler_data(irq, chip);
	irq_set_chained_handler(irq, pm8xxx_irq_handler);
	irq_set_irq_wake(irq, 1);

	rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
	if (rc) {
		irq_set_chained_handler(irq, NULL);
		irq_set_handler_data(irq, NULL);
		irq_domain_remove(chip->irqdomain);
	}

	return rc;
}

static int pm8921_remove_child(struct device *dev, void *unused)
{
	platform_device_unregister(to_platform_device(dev));
	return 0;
}

static int pm8921_remove(struct platform_device *pdev)
{
	int irq = platform_get_irq(pdev, 0);
	struct pm8921 *pmic = pm8921_drvdata.pm_chip_data;
	struct pm_irq_chip *chip = pmic->irq_chip;

	device_for_each_child(&pdev->dev, NULL, pm8921_remove_child);
	irq_set_chained_handler(irq, NULL);
	irq_set_handler_data(irq, NULL);
	irq_domain_remove(chip->irqdomain);

	return 0;
}

static struct platform_driver pm8921_driver = {
	.probe		= pm8921_probe,
	.remove		= pm8921_remove,
	.driver		= {
		.name	= "pm8921-core",
		.owner	= THIS_MODULE,
	},
};

static int __init pm8921_init(void)
{
	return platform_driver_register(&pm8921_driver);
}
subsys_initcall(pm8921_init);

static void __exit pm8921_exit(void)
{
	platform_driver_unregister(&pm8921_driver);
}
module_exit(pm8921_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("PMIC 8921 core driver");
MODULE_VERSION("1.0");
MODULE_ALIAS("platform:pm8921-core");
Commit	Line	Data
cbdb53e1 AD	1	/*
	2	* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 and
	6	* only version 2 as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#define pr_fmt(fmt) "%s: " fmt, __func__
	15
	16	#include <linux/kernel.h>
bc866fc7	17	#include <linux/interrupt.h>
cced3548	18	#include <linux/irqchip/chained_irq.h>
bc866fc7	19	#include <linux/irq.h>
dc1a95cc	20	#include <linux/irqdomain.h>
ef310f4b	21	#include <linux/module.h>
cbdb53e1 AD	22	#include <linux/platform_device.h>
cbdb53e1 AD	23	#include <linux/slab.h>
c013f0a5	24	#include <linux/err.h>
ce44bf5b	25	#include <linux/ssbi.h>
dc1a95cc	26	#include <linux/of_platform.h>
cbdb53e1	27	#include <linux/mfd/core.h>
cbdb53e1	28	#include <linux/mfd/pm8xxx/core.h>
bc866fc7 SB	29
	30	#define SSBI_REG_ADDR_IRQ_BASE 0x1BB
	31
	32	#define SSBI_REG_ADDR_IRQ_ROOT (SSBI_REG_ADDR_IRQ_BASE + 0)
	33	#define SSBI_REG_ADDR_IRQ_M_STATUS1 (SSBI_REG_ADDR_IRQ_BASE + 1)
	34	#define SSBI_REG_ADDR_IRQ_M_STATUS2 (SSBI_REG_ADDR_IRQ_BASE + 2)
	35	#define SSBI_REG_ADDR_IRQ_M_STATUS3 (SSBI_REG_ADDR_IRQ_BASE + 3)
	36	#define SSBI_REG_ADDR_IRQ_M_STATUS4 (SSBI_REG_ADDR_IRQ_BASE + 4)
	37	#define SSBI_REG_ADDR_IRQ_BLK_SEL (SSBI_REG_ADDR_IRQ_BASE + 5)
	38	#define SSBI_REG_ADDR_IRQ_IT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 6)
	39	#define SSBI_REG_ADDR_IRQ_CONFIG (SSBI_REG_ADDR_IRQ_BASE + 7)
	40	#define SSBI_REG_ADDR_IRQ_RT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 8)
	41
	42	#define PM_IRQF_LVL_SEL 0x01 /* level select */
	43	#define PM_IRQF_MASK_FE 0x02 /* mask falling edge */
	44	#define PM_IRQF_MASK_RE 0x04 /* mask rising edge */
	45	#define PM_IRQF_CLR 0x08 /* clear interrupt */
	46	#define PM_IRQF_BITS_MASK 0x70
	47	#define PM_IRQF_BITS_SHIFT 4
	48	#define PM_IRQF_WRITE 0x80
	49
	50	#define PM_IRQF_MASK_ALL (PM_IRQF_MASK_FE \| \
	51	PM_IRQF_MASK_RE)
cbdb53e1 AD	52
	53	#define REG_HWREV 0x002 /* PMIC4 revision */
	54	#define REG_HWREV_2 0x0E8 /* PMIC4 revision 2 */
	55
dc1a95cc SB	56	#define PM8921_NR_IRQS 256
dc1a95cc SB	57
bc866fc7 SB	58	struct pm_irq_chip {
	59	struct device *dev;
	60	spinlock_t pm_irq_lock;
dc1a95cc	61	struct irq_domain *irqdomain;
bc866fc7 SB	62	unsigned int num_irqs;
	63	unsigned int num_blocks;
	64	unsigned int num_masters;
	65	u8 config[0];
	66	};
	67
cbdb53e1 AD	68	struct pm8921 {
cbdb53e1 AD	69	struct device *dev;
c013f0a5	70	struct pm_irq_chip *irq_chip;
cbdb53e1 AD	71	};
cbdb53e1 AD	72
bc866fc7 SB	73	static int pm8xxx_read_root_irq(const struct pm_irq_chip chip, u8 rp)
	74	{
	75	return pm8xxx_readb(chip->dev, SSBI_REG_ADDR_IRQ_ROOT, rp);
	76	}
	77
	78	static int pm8xxx_read_master_irq(const struct pm_irq_chip chip, u8 m, u8 bp)
	79	{
	80	return pm8xxx_readb(chip->dev,
	81	SSBI_REG_ADDR_IRQ_M_STATUS1 + m, bp);
	82	}
	83
	84	static int pm8xxx_read_block_irq(struct pm_irq_chip chip, u8 bp, u8 ip)
	85	{
	86	int rc;
	87
	88	spin_lock(&chip->pm_irq_lock);
	89	rc = pm8xxx_writeb(chip->dev, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
	90	if (rc) {
	91	pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
	92	goto bail;
	93	}
	94
	95	rc = pm8xxx_readb(chip->dev, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
	96	if (rc)
	97	pr_err("Failed Reading Status rc=%d\n", rc);
	98	bail:
	99	spin_unlock(&chip->pm_irq_lock);
	100	return rc;
	101	}
	102
	103	static int pm8xxx_config_irq(struct pm_irq_chip *chip, u8 bp, u8 cp)
	104	{
	105	int rc;
	106
	107	spin_lock(&chip->pm_irq_lock);
	108	rc = pm8xxx_writeb(chip->dev, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
	109	if (rc) {
	110	pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
	111	goto bail;
	112	}
	113
	114	cp \|= PM_IRQF_WRITE;
	115	rc = pm8xxx_writeb(chip->dev, SSBI_REG_ADDR_IRQ_CONFIG, cp);
	116	if (rc)
	117	pr_err("Failed Configuring IRQ rc=%d\n", rc);
	118	bail:
	119	spin_unlock(&chip->pm_irq_lock);
	120	return rc;
	121	}
	122
	123	static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
	124	{
	125	int pmirq, irq, i, ret = 0;
	126	u8 bits;
	127
	128	ret = pm8xxx_read_block_irq(chip, block, &bits);
	129	if (ret) {
	130	pr_err("Failed reading %d block ret=%d", block, ret);
	131	return ret;
	132	}
	133	if (!bits) {
	134	pr_err("block bit set in master but no irqs: %d", block);
	135	return 0;
	136	}
137
138	/* Check IRQ bits */
139	for (i = 0; i < 8; i++) {
140	if (bits & (1 << i)) {
141	pmirq = block * 8 + i;
dc1a95cc	142	irq = irq_find_mapping(chip->irqdomain, pmirq);
bc866fc7 SB	143	generic_handle_irq(irq);
	144	}
	145	}
	146	return 0;
	147	}
	148
	149	static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
	150	{
	151	u8 blockbits;
	152	int block_number, i, ret = 0;
	153
	154	ret = pm8xxx_read_master_irq(chip, master, &blockbits);
	155	if (ret) {
	156	pr_err("Failed to read master %d ret=%d\n", master, ret);
	157	return ret;
	158	}
	159	if (!blockbits) {
	160	pr_err("master bit set in root but no blocks: %d", master);
	161	return 0;
	162	}
	163
	164	for (i = 0; i < 8; i++)
	165	if (blockbits & (1 << i)) {
	166	block_number = master * 8 + i; /* block # */
	167	ret \|= pm8xxx_irq_block_handler(chip, block_number);
	168	}
	169	return ret;
	170	}
	171
	172	static void pm8xxx_irq_handler(unsigned int irq, struct irq_desc *desc)
	173	{
	174	struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
	175	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
	176	u8 root;
	177	int i, ret, masters = 0;
	178
cced3548 SB	179	chained_irq_enter(irq_chip, desc);
cced3548 SB	180
bc866fc7 SB	181	ret = pm8xxx_read_root_irq(chip, &root);
	182	if (ret) {
	183	pr_err("Can't read root status ret=%d\n", ret);
	184	return;
	185	}
	186
	187	/* on pm8xxx series masters start from bit 1 of the root */
	188	masters = root >> 1;
	189
	190	/* Read allowed masters for blocks. */
	191	for (i = 0; i < chip->num_masters; i++)
	192	if (masters & (1 << i))
	193	pm8xxx_irq_master_handler(chip, i);
	194
cced3548	195	chained_irq_exit(irq_chip, desc);
bc866fc7 SB	196	}
	197
	198	static void pm8xxx_irq_mask_ack(struct irq_data *d)
	199	{
	200	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
dc1a95cc SB	201	unsigned int pmirq = irqd_to_hwirq(d);
dc1a95cc SB	202	int irq_bit;
bc866fc7 SB	203	u8 block, config;
	204
	205	block = pmirq / 8;
bc866fc7 SB	206	irq_bit = pmirq % 8;
	207
	208	config = chip->config[pmirq] \| PM_IRQF_MASK_ALL \| PM_IRQF_CLR;
	209	pm8xxx_config_irq(chip, block, config);
	210	}
	211
	212	static void pm8xxx_irq_unmask(struct irq_data *d)
	213	{
	214	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
dc1a95cc SB	215	unsigned int pmirq = irqd_to_hwirq(d);
dc1a95cc SB	216	int irq_bit;
bc866fc7 SB	217	u8 block, config;
	218
	219	block = pmirq / 8;
bc866fc7 SB	220	irq_bit = pmirq % 8;
	221
	222	config = chip->config[pmirq];
	223	pm8xxx_config_irq(chip, block, config);
	224	}
	225
	226	static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
	227	{
	228	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
dc1a95cc SB	229	unsigned int pmirq = irqd_to_hwirq(d);
dc1a95cc SB	230	int irq_bit;
bc866fc7 SB	231	u8 block, config;
	232
	233	block = pmirq / 8;
bc866fc7 SB	234	irq_bit = pmirq % 8;
	235
	236	chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
	237	\| PM_IRQF_MASK_ALL;
	238	if (flow_type & (IRQF_TRIGGER_RISING \| IRQF_TRIGGER_FALLING)) {
	239	if (flow_type & IRQF_TRIGGER_RISING)
	240	chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
	241	if (flow_type & IRQF_TRIGGER_FALLING)
	242	chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
	243	} else {
	244	chip->config[pmirq] \|= PM_IRQF_LVL_SEL;
	245
	246	if (flow_type & IRQF_TRIGGER_HIGH)
	247	chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
	248	else
	249	chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
	250	}
	251
	252	config = chip->config[pmirq] \| PM_IRQF_CLR;
	253	return pm8xxx_config_irq(chip, block, config);
	254	}
	255
	256	static int pm8xxx_irq_set_wake(struct irq_data *d, unsigned int on)
	257	{
	258	return 0;
	259	}
	260
	261	static struct irq_chip pm8xxx_irq_chip = {
	262	.name = "pm8xxx",
	263	.irq_mask_ack = pm8xxx_irq_mask_ack,
	264	.irq_unmask = pm8xxx_irq_unmask,
	265	.irq_set_type = pm8xxx_irq_set_type,
	266	.irq_set_wake = pm8xxx_irq_set_wake,
	267	.flags = IRQCHIP_MASK_ON_SUSPEND,
	268	};
	269
	270	/**
	271	* pm8xxx_get_irq_stat - get the status of the irq line
	272	* @chip: pointer to identify a pmic irq controller
	273	* @irq: the irq number
	274	*
	275	* The pm8xxx gpio and mpp rely on the interrupt block to read
	276	* the values on their pins. This function is to facilitate reading
	277	* the status of a gpio or an mpp line. The caller has to convert the
	278	* gpio number to irq number.
	279	*
	280	* RETURNS:
	281	* an int indicating the value read on that line
	282	*/
	283	static int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq)
	284	{
	285	int pmirq, rc;
	286	u8 block, bits, bit;
	287	unsigned long flags;
dc1a95cc	288	struct irq_data *irq_data = irq_get_irq_data(irq);
bc866fc7	289
dc1a95cc	290	pmirq = irq_data->hwirq;
bc866fc7 SB	291
	292	block = pmirq / 8;
	293	bit = pmirq % 8;
	294
	295	spin_lock_irqsave(&chip->pm_irq_lock, flags);
	296
	297	rc = pm8xxx_writeb(chip->dev, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
	298	if (rc) {
	299	pr_err("Failed Selecting block irq=%d pmirq=%d blk=%d rc=%d\n",
	300	irq, pmirq, block, rc);
	301	goto bail_out;
	302	}
	303
	304	rc = pm8xxx_readb(chip->dev, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
	305	if (rc) {
	306	pr_err("Failed Configuring irq=%d pmirq=%d blk=%d rc=%d\n",
	307	irq, pmirq, block, rc);
	308	goto bail_out;
	309	}
	310
	311	rc = (bits & (1 << bit)) ? 1 : 0;
	312
	313	bail_out:
	314	spin_unlock_irqrestore(&chip->pm_irq_lock, flags);
	315
	316	return rc;
	317	}
	318
dc1a95cc	319	static struct lock_class_key pm8xxx_irq_lock_class;
bc866fc7	320
dc1a95cc SB	321	static int pm8xxx_irq_domain_map(struct irq_domain *d, unsigned int irq,
	322	irq_hw_number_t hwirq)
	323	{
	324	struct pm_irq_chip *chip = d->host_data;
bc866fc7	325
dc1a95cc SB	326	irq_set_lockdep_class(irq, &pm8xxx_irq_lock_class);
	327	irq_set_chip_and_handler(irq, &pm8xxx_irq_chip, handle_level_irq);
	328	irq_set_chip_data(irq, chip);
bc866fc7	329	#ifdef CONFIG_ARM
dc1a95cc	330	set_irq_flags(irq, IRQF_VALID);
bc866fc7	331	#else
dc1a95cc	332	irq_set_noprobe(irq);
bc866fc7	333	#endif
bc866fc7 SB	334	return 0;
	335	}
	336
dc1a95cc SB	337	static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
	338	.xlate = irq_domain_xlate_twocell,
	339	.map = pm8xxx_irq_domain_map,
	340	};
	341
cbdb53e1 AD	342	static int pm8921_readb(const struct device dev, u16 addr, u8 val)
	343	{
	344	const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
	345	const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
	346
ce44bf5b	347	return ssbi_read(pmic->dev->parent, addr, val, 1);
cbdb53e1 AD	348	}
	349
	350	static int pm8921_writeb(const struct device *dev, u16 addr, u8 val)
	351	{
	352	const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
	353	const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
	354
ce44bf5b	355	return ssbi_write(pmic->dev->parent, addr, &val, 1);
cbdb53e1 AD	356	}
	357
	358	static int pm8921_read_buf(const struct device dev, u16 addr, u8 buf,
	359	int cnt)
	360	{
	361	const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
	362	const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
	363
ce44bf5b	364	return ssbi_read(pmic->dev->parent, addr, buf, cnt);
cbdb53e1 AD	365	}
	366
	367	static int pm8921_write_buf(const struct device dev, u16 addr, u8 buf,
	368	int cnt)
	369	{
	370	const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
	371	const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
	372
ce44bf5b	373	return ssbi_write(pmic->dev->parent, addr, buf, cnt);
cbdb53e1 AD	374	}
cbdb53e1 AD	375
c013f0a5 AD	376	static int pm8921_read_irq_stat(const struct device *dev, int irq)
	377	{
	378	const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
	379	const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
	380
	381	return pm8xxx_get_irq_stat(pmic->irq_chip, irq);
	382	}
	383
cbdb53e1 AD	384	static struct pm8xxx_drvdata pm8921_drvdata = {
	385	.pmic_readb = pm8921_readb,
	386	.pmic_writeb = pm8921_writeb,
	387	.pmic_read_buf = pm8921_read_buf,
	388	.pmic_write_buf = pm8921_write_buf,
c013f0a5	389	.pmic_read_irq_stat = pm8921_read_irq_stat,
cbdb53e1 AD	390	};
cbdb53e1 AD	391
f791be49	392	static int pm8921_probe(struct platform_device *pdev)
cbdb53e1	393	{
cbdb53e1 AD	394	struct pm8921 *pmic;
	395	int rc;
	396	u8 val;
dc1a95cc	397	unsigned int irq;
c013f0a5	398	u32 rev;
dc1a95cc SB	399	struct pm_irq_chip *chip;
dc1a95cc SB	400	unsigned int nirqs = PM8921_NR_IRQS;
cbdb53e1	401
dc1a95cc SB	402	irq = platform_get_irq(pdev, 0);
	403	if (irq < 0)
	404	return irq;
cbdb53e1	405
b2cdcfac	406	pmic = devm_kzalloc(&pdev->dev, sizeof(struct pm8921), GFP_KERNEL);
cbdb53e1 AD	407	if (!pmic) {
	408	pr_err("Cannot alloc pm8921 struct\n");
	409	return -ENOMEM;
	410	}
	411
	412	/* Read PMIC chip revision */
ce44bf5b	413	rc = ssbi_read(pdev->dev.parent, REG_HWREV, &val, sizeof(val));
cbdb53e1 AD	414	if (rc) {
cbdb53e1 AD	415	pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
b2cdcfac	416	return rc;
cbdb53e1 AD	417	}
cbdb53e1 AD	418	pr_info("PMIC revision 1: %02X\n", val);
c013f0a5	419	rev = val;
cbdb53e1 AD	420
cbdb53e1 AD	421	/* Read PMIC chip revision 2 */
ce44bf5b	422	rc = ssbi_read(pdev->dev.parent, REG_HWREV_2, &val, sizeof(val));
cbdb53e1 AD	423	if (rc) {
	424	pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
	425	REG_HWREV_2, rc);
b2cdcfac	426	return rc;
cbdb53e1 AD	427	}
cbdb53e1 AD	428	pr_info("PMIC revision 2: %02X\n", val);
c013f0a5	429	rev \|= val << BITS_PER_BYTE;
cbdb53e1 AD	430
	431	pmic->dev = &pdev->dev;
	432	pm8921_drvdata.pm_chip_data = pmic;
	433	platform_set_drvdata(pdev, &pm8921_drvdata);
	434
dc1a95cc SB	435	chip = devm_kzalloc(&pdev->dev, sizeof(*chip) +
	436	sizeof(chip->config[0]) * nirqs,
	437	GFP_KERNEL);
	438	if (!chip)
	439	return -ENOMEM;
	440
	441	pmic->irq_chip = chip;
	442	chip->dev = &pdev->dev;
	443	chip->num_irqs = nirqs;
	444	chip->num_blocks = DIV_ROUND_UP(chip->num_irqs, 8);
	445	chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
	446	spin_lock_init(&chip->pm_irq_lock);
	447
	448	chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node, nirqs,
	449	&pm8xxx_irq_domain_ops,
	450	chip);
	451	if (!chip->irqdomain)
	452	return -ENODEV;
	453
	454	irq_set_handler_data(irq, chip);
	455	irq_set_chained_handler(irq, pm8xxx_irq_handler);
	456	irq_set_irq_wake(irq, 1);
	457
	458	rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
c013f0a5	459	if (rc) {
dc1a95cc SB	460	irq_set_chained_handler(irq, NULL);
	461	irq_set_handler_data(irq, NULL);
	462	irq_domain_remove(chip->irqdomain);
c013f0a5 AD	463	}
c013f0a5 AD	464
dc1a95cc SB	465	return rc;
dc1a95cc SB	466	}
c013f0a5	467
dc1a95cc SB	468	static int pm8921_remove_child(struct device dev, void unused)
	469	{
	470	platform_device_unregister(to_platform_device(dev));
cbdb53e1	471	return 0;
cbdb53e1 AD	472	}
cbdb53e1 AD	473
4740f73f	474	static int pm8921_remove(struct platform_device *pdev)
cbdb53e1	475	{
dc1a95cc SB	476	int irq = platform_get_irq(pdev, 0);
	477	struct pm8921 *pmic = pm8921_drvdata.pm_chip_data;
	478	struct pm_irq_chip *chip = pmic->irq_chip;
	479
	480	device_for_each_child(&pdev->dev, NULL, pm8921_remove_child);
	481	irq_set_chained_handler(irq, NULL);
	482	irq_set_handler_data(irq, NULL);
	483	irq_domain_remove(chip->irqdomain);
cbdb53e1 AD	484
	485	return 0;
	486	}
	487
	488	static struct platform_driver pm8921_driver = {
	489	.probe = pm8921_probe,
84449216	490	.remove = pm8921_remove,
cbdb53e1 AD	491	.driver = {
	492	.name = "pm8921-core",
	493	.owner = THIS_MODULE,
	494	},
	495	};
	496
	497	static int __init pm8921_init(void)
	498	{
	499	return platform_driver_register(&pm8921_driver);
	500	}
	501	subsys_initcall(pm8921_init);
	502
	503	static void __exit pm8921_exit(void)
	504	{
	505	platform_driver_unregister(&pm8921_driver);
	506	}
	507	module_exit(pm8921_exit);
	508
	509	MODULE_LICENSE("GPL v2");
	510	MODULE_DESCRIPTION("PMIC 8921 core driver");
	511	MODULE_VERSION("1.0");
	512	MODULE_ALIAS("platform:pm8921-core");