[mirror_ubuntu-jammy-kernel.git] / drivers / mfd / qcom-pm8xxx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
 */

#define pr_fmt(fmt) "%s: " fmt, __func__

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/ssbi.h>
#include <linux/regmap.h>
#include <linux/of_platform.h>
#include <linux/mfd/core.h>

#define	SSBI_REG_ADDR_IRQ_BASE		0x1BB

#define	SSBI_REG_ADDR_IRQ_ROOT		(SSBI_REG_ADDR_IRQ_BASE + 0)
#define	SSBI_REG_ADDR_IRQ_M_STATUS1	(SSBI_REG_ADDR_IRQ_BASE + 1)
#define	SSBI_REG_ADDR_IRQ_M_STATUS2	(SSBI_REG_ADDR_IRQ_BASE + 2)
#define	SSBI_REG_ADDR_IRQ_M_STATUS3	(SSBI_REG_ADDR_IRQ_BASE + 3)
#define	SSBI_REG_ADDR_IRQ_M_STATUS4	(SSBI_REG_ADDR_IRQ_BASE + 4)
#define	SSBI_REG_ADDR_IRQ_BLK_SEL	(SSBI_REG_ADDR_IRQ_BASE + 5)
#define	SSBI_REG_ADDR_IRQ_IT_STATUS	(SSBI_REG_ADDR_IRQ_BASE + 6)
#define	SSBI_REG_ADDR_IRQ_CONFIG	(SSBI_REG_ADDR_IRQ_BASE + 7)
#define	SSBI_REG_ADDR_IRQ_RT_STATUS	(SSBI_REG_ADDR_IRQ_BASE + 8)

#define	PM8821_SSBI_REG_ADDR_IRQ_BASE	0x100
#define	PM8821_SSBI_REG_ADDR_IRQ_MASTER0 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0x30)
#define	PM8821_SSBI_REG_ADDR_IRQ_MASTER1 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0xb0)
#define	PM8821_SSBI_REG(m, b, offset) \
			((m == 0) ? \
			(PM8821_SSBI_REG_ADDR_IRQ_MASTER0 + b + offset) : \
			(PM8821_SSBI_REG_ADDR_IRQ_MASTER1 + b + offset))
#define	PM8821_SSBI_ADDR_IRQ_ROOT(m, b)		PM8821_SSBI_REG(m, b, 0x0)
#define	PM8821_SSBI_ADDR_IRQ_CLEAR(m, b)	PM8821_SSBI_REG(m, b, 0x01)
#define	PM8821_SSBI_ADDR_IRQ_MASK(m, b)		PM8821_SSBI_REG(m, b, 0x08)
#define	PM8821_SSBI_ADDR_IRQ_RT_STATUS(m, b)	PM8821_SSBI_REG(m, b, 0x0f)

#define	PM8821_BLOCKS_PER_MASTER	7

#define	PM_IRQF_LVL_SEL			0x01	/* level select */
#define	PM_IRQF_MASK_FE			0x02	/* mask falling edge */
#define	PM_IRQF_MASK_RE			0x04	/* mask rising edge */
#define	PM_IRQF_CLR			0x08	/* clear interrupt */
#define	PM_IRQF_BITS_MASK		0x70
#define	PM_IRQF_BITS_SHIFT		4
#define	PM_IRQF_WRITE			0x80

#define	PM_IRQF_MASK_ALL		(PM_IRQF_MASK_FE | \
					PM_IRQF_MASK_RE)

#define REG_HWREV		0x002  /* PMIC4 revision */
#define REG_HWREV_2		0x0E8  /* PMIC4 revision 2 */

#define PM8XXX_NR_IRQS		256
#define PM8821_NR_IRQS		112

struct pm_irq_data {
	int num_irqs;
	struct irq_chip *irq_chip;
	void (*irq_handler)(struct irq_desc *desc);
};

struct pm_irq_chip {
	struct regmap		*regmap;
	spinlock_t		pm_irq_lock;
	struct irq_domain	*irqdomain;
	unsigned int		num_blocks;
	unsigned int		num_masters;
	const struct pm_irq_data *pm_irq_data;
	/* MUST BE AT THE END OF THIS STRUCT */
	u8			config[0];
};

static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp,
				 unsigned int *ip)
{
	int	rc;

	spin_lock(&chip->pm_irq_lock);
	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
	if (rc) {
		pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
		goto bail;
	}

	rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
	if (rc)
		pr_err("Failed Reading Status rc=%d\n", rc);
bail:
	spin_unlock(&chip->pm_irq_lock);
	return rc;
}

static int
pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp)
{
	int	rc;

	spin_lock(&chip->pm_irq_lock);
	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
	if (rc) {
		pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
		goto bail;
	}

	cp |= PM_IRQF_WRITE;
	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp);
	if (rc)
		pr_err("Failed Configuring IRQ rc=%d\n", rc);
bail:
	spin_unlock(&chip->pm_irq_lock);
	return rc;
}

static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
{
	int pmirq, irq, i, ret = 0;
	unsigned int bits;

	ret = pm8xxx_read_block_irq(chip, block, &bits);
	if (ret) {
		pr_err("Failed reading %d block ret=%d", block, ret);
		return ret;
	}
	if (!bits) {
		pr_err("block bit set in master but no irqs: %d", block);
		return 0;
	}

	/* Check IRQ bits */
	for (i = 0; i < 8; i++) {
		if (bits & (1 << i)) {
			pmirq = block * 8 + i;
			irq = irq_find_mapping(chip->irqdomain, pmirq);
			generic_handle_irq(irq);
		}
	}
	return 0;
}

static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
{
	unsigned int blockbits;
	int block_number, i, ret = 0;

	ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master,
			  &blockbits);
	if (ret) {
		pr_err("Failed to read master %d ret=%d\n", master, ret);
		return ret;
	}
	if (!blockbits) {
		pr_err("master bit set in root but no blocks: %d", master);
		return 0;
	}

	for (i = 0; i < 8; i++)
		if (blockbits & (1 << i)) {
			block_number = master * 8 + i;	/* block # */
			ret |= pm8xxx_irq_block_handler(chip, block_number);
		}
	return ret;
}

static void pm8xxx_irq_handler(struct irq_desc *desc)
{
	struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
	unsigned int root;
	int	i, ret, masters = 0;

	chained_irq_enter(irq_chip, desc);

	ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root);
	if (ret) {
		pr_err("Can't read root status ret=%d\n", ret);
		return;
	}

	/* on pm8xxx series masters start from bit 1 of the root */
	masters = root >> 1;

	/* Read allowed masters for blocks. */
	for (i = 0; i < chip->num_masters; i++)
		if (masters & (1 << i))
			pm8xxx_irq_master_handler(chip, i);

	chained_irq_exit(irq_chip, desc);
}

static void pm8821_irq_block_handler(struct pm_irq_chip *chip,
				     int master, int block)
{
	int pmirq, irq, i, ret;
	unsigned int bits;

	ret = regmap_read(chip->regmap,
			  PM8821_SSBI_ADDR_IRQ_ROOT(master, block), &bits);
	if (ret) {
		pr_err("Reading block %d failed ret=%d", block, ret);
		return;
	}

	/* Convert block offset to global block number */
	block += (master * PM8821_BLOCKS_PER_MASTER) - 1;

	/* Check IRQ bits */
	for (i = 0; i < 8; i++) {
		if (bits & BIT(i)) {
			pmirq = block * 8 + i;
			irq = irq_find_mapping(chip->irqdomain, pmirq);
			generic_handle_irq(irq);
		}
	}
}

static inline void pm8821_irq_master_handler(struct pm_irq_chip *chip,
					     int master, u8 master_val)
{
	int block;

	for (block = 1; block < 8; block++)
		if (master_val & BIT(block))
			pm8821_irq_block_handler(chip, master, block);
}

static void pm8821_irq_handler(struct irq_desc *desc)
{
	struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
	unsigned int master;
	int ret;

	chained_irq_enter(irq_chip, desc);
	ret = regmap_read(chip->regmap,
			  PM8821_SSBI_REG_ADDR_IRQ_MASTER0, &master);
	if (ret) {
		pr_err("Failed to read master 0 ret=%d\n", ret);
		goto done;
	}

	/* bits 1 through 7 marks the first 7 blocks in master 0 */
	if (master & GENMASK(7, 1))
		pm8821_irq_master_handler(chip, 0, master);

	/* bit 0 marks if master 1 contains any bits */
	if (!(master & BIT(0)))
		goto done;

	ret = regmap_read(chip->regmap,
			  PM8821_SSBI_REG_ADDR_IRQ_MASTER1, &master);
	if (ret) {
		pr_err("Failed to read master 1 ret=%d\n", ret);
		goto done;
	}

	pm8821_irq_master_handler(chip, 1, master);

done:
	chained_irq_exit(irq_chip, desc);
}

static void pm8xxx_irq_mask_ack(struct irq_data *d)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	u8	block, config;

	block = pmirq / 8;

	config = chip->config[pmirq] | PM_IRQF_MASK_ALL | PM_IRQF_CLR;
	pm8xxx_config_irq(chip, block, config);
}

static void pm8xxx_irq_unmask(struct irq_data *d)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	u8	block, config;

	block = pmirq / 8;

	config = chip->config[pmirq];
	pm8xxx_config_irq(chip, block, config);
}

static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	int irq_bit;
	u8 block, config;

	block = pmirq / 8;
	irq_bit  = pmirq % 8;

	chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
							| PM_IRQF_MASK_ALL;
	if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
		if (flow_type & IRQF_TRIGGER_RISING)
			chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
		if (flow_type & IRQF_TRIGGER_FALLING)
			chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
	} else {
		chip->config[pmirq] |= PM_IRQF_LVL_SEL;

		if (flow_type & IRQF_TRIGGER_HIGH)
			chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
		else
			chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
	}

	config = chip->config[pmirq] | PM_IRQF_CLR;
	return pm8xxx_config_irq(chip, block, config);
}

static int pm8xxx_irq_get_irqchip_state(struct irq_data *d,
					enum irqchip_irq_state which,
					bool *state)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	unsigned int bits;
	int irq_bit;
	u8 block;
	int rc;

	if (which != IRQCHIP_STATE_LINE_LEVEL)
		return -EINVAL;

	block = pmirq / 8;
	irq_bit = pmirq % 8;

	spin_lock(&chip->pm_irq_lock);
	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
	if (rc) {
		pr_err("Failed Selecting Block %d rc=%d\n", block, rc);
		goto bail;
	}

	rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
	if (rc) {
		pr_err("Failed Reading Status rc=%d\n", rc);
		goto bail;
	}

	*state = !!(bits & BIT(irq_bit));
bail:
	spin_unlock(&chip->pm_irq_lock);

	return rc;
}

static struct irq_chip pm8xxx_irq_chip = {
	.name		= "pm8xxx",
	.irq_mask_ack	= pm8xxx_irq_mask_ack,
	.irq_unmask	= pm8xxx_irq_unmask,
	.irq_set_type	= pm8xxx_irq_set_type,
	.irq_get_irqchip_state = pm8xxx_irq_get_irqchip_state,
	.flags		= IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
};

static void pm8xxx_irq_domain_map(struct pm_irq_chip *chip,
				  struct irq_domain *domain, unsigned int irq,
				  irq_hw_number_t hwirq, unsigned int type)
{
	irq_domain_set_info(domain, irq, hwirq, chip->pm_irq_data->irq_chip,
			    chip, handle_level_irq, NULL, NULL);
	irq_set_noprobe(irq);
}

static int pm8xxx_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
				   unsigned int nr_irqs, void *data)
{
	struct pm_irq_chip *chip = domain->host_data;
	struct irq_fwspec *fwspec = data;
	irq_hw_number_t hwirq;
	unsigned int type;
	int ret, i;

	ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
	if (ret)
		return ret;

	for (i = 0; i < nr_irqs; i++)
		pm8xxx_irq_domain_map(chip, domain, virq + i, hwirq + i, type);

	return 0;
}

static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
	.alloc = pm8xxx_irq_domain_alloc,
	.free = irq_domain_free_irqs_common,
	.translate = irq_domain_translate_twocell,
};

static void pm8821_irq_mask_ack(struct irq_data *d)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	u8 block, master;
	int irq_bit, rc;

	block = pmirq / 8;
	master = block / PM8821_BLOCKS_PER_MASTER;
	irq_bit = pmirq % 8;
	block %= PM8821_BLOCKS_PER_MASTER;

	rc = regmap_update_bits(chip->regmap,
				PM8821_SSBI_ADDR_IRQ_MASK(master, block),
				BIT(irq_bit), BIT(irq_bit));
	if (rc) {
		pr_err("Failed to mask IRQ:%d rc=%d\n", pmirq, rc);
		return;
	}

	rc = regmap_update_bits(chip->regmap,
				PM8821_SSBI_ADDR_IRQ_CLEAR(master, block),
				BIT(irq_bit), BIT(irq_bit));
	if (rc)
		pr_err("Failed to CLEAR IRQ:%d rc=%d\n", pmirq, rc);
}

static void pm8821_irq_unmask(struct irq_data *d)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	int irq_bit, rc;
	u8 block, master;

	block = pmirq / 8;
	master = block / PM8821_BLOCKS_PER_MASTER;
	irq_bit = pmirq % 8;
	block %= PM8821_BLOCKS_PER_MASTER;

	rc = regmap_update_bits(chip->regmap,
				PM8821_SSBI_ADDR_IRQ_MASK(master, block),
				BIT(irq_bit), ~BIT(irq_bit));
	if (rc)
		pr_err("Failed to read/write unmask IRQ:%d rc=%d\n", pmirq, rc);

}

static int pm8821_irq_get_irqchip_state(struct irq_data *d,
					enum irqchip_irq_state which,
					bool *state)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	int rc, pmirq = irqd_to_hwirq(d);
	u8 block, irq_bit, master;
	unsigned int bits;

	block = pmirq / 8;
	master = block / PM8821_BLOCKS_PER_MASTER;
	irq_bit = pmirq % 8;
	block %= PM8821_BLOCKS_PER_MASTER;

	rc = regmap_read(chip->regmap,
		PM8821_SSBI_ADDR_IRQ_RT_STATUS(master, block), &bits);
	if (rc) {
		pr_err("Reading Status of IRQ %d failed rc=%d\n", pmirq, rc);
		return rc;
	}

	*state = !!(bits & BIT(irq_bit));

	return rc;
}

static struct irq_chip pm8821_irq_chip = {
	.name		= "pm8821",
	.irq_mask_ack	= pm8821_irq_mask_ack,
	.irq_unmask	= pm8821_irq_unmask,
	.irq_get_irqchip_state = pm8821_irq_get_irqchip_state,
	.flags		= IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
};

static const struct regmap_config ssbi_regmap_config = {
	.reg_bits = 16,
	.val_bits = 8,
	.max_register = 0x3ff,
	.fast_io = true,
	.reg_read = ssbi_reg_read,
	.reg_write = ssbi_reg_write
};

static const struct pm_irq_data pm8xxx_data = {
	.num_irqs = PM8XXX_NR_IRQS,
	.irq_chip = &pm8xxx_irq_chip,
	.irq_handler = pm8xxx_irq_handler,
};

static const struct pm_irq_data pm8821_data = {
	.num_irqs = PM8821_NR_IRQS,
	.irq_chip = &pm8821_irq_chip,
	.irq_handler = pm8821_irq_handler,
};

static const struct of_device_id pm8xxx_id_table[] = {
	{ .compatible = "qcom,pm8018", .data = &pm8xxx_data},
	{ .compatible = "qcom,pm8058", .data = &pm8xxx_data},
	{ .compatible = "qcom,pm8821", .data = &pm8821_data},
	{ .compatible = "qcom,pm8921", .data = &pm8xxx_data},
	{ }
};
MODULE_DEVICE_TABLE(of, pm8xxx_id_table);

static int pm8xxx_probe(struct platform_device *pdev)
{
	const struct pm_irq_data *data;
	struct regmap *regmap;
	int irq, rc;
	unsigned int val;
	u32 rev;
	struct pm_irq_chip *chip;

	data = of_device_get_match_data(&pdev->dev);
	if (!data) {
		dev_err(&pdev->dev, "No matching driver data found\n");
		return -EINVAL;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent,
				  &ssbi_regmap_config);
	if (IS_ERR(regmap))
		return PTR_ERR(regmap);

	/* Read PMIC chip revision */
	rc = regmap_read(regmap, REG_HWREV, &val);
	if (rc) {
		pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
		return rc;
	}
	pr_info("PMIC revision 1: %02X\n", val);
	rev = val;

	/* Read PMIC chip revision 2 */
	rc = regmap_read(regmap, REG_HWREV_2, &val);
	if (rc) {
		pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
			REG_HWREV_2, rc);
		return rc;
	}
	pr_info("PMIC revision 2: %02X\n", val);
	rev |= val << BITS_PER_BYTE;

	chip = devm_kzalloc(&pdev->dev,
			    struct_size(chip, config, data->num_irqs),
			    GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	platform_set_drvdata(pdev, chip);
	chip->regmap = regmap;
	chip->num_blocks = DIV_ROUND_UP(data->num_irqs, 8);
	chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
	chip->pm_irq_data = data;
	spin_lock_init(&chip->pm_irq_lock);

	chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
						data->num_irqs,
						&pm8xxx_irq_domain_ops,
						chip);
	if (!chip->irqdomain)
		return -ENODEV;

	irq_set_chained_handler_and_data(irq, data->irq_handler, chip);
	irq_set_irq_wake(irq, 1);

	rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
	if (rc) {
		irq_set_chained_handler_and_data(irq, NULL, NULL);
		irq_domain_remove(chip->irqdomain);
	}

	return rc;
}

static int pm8xxx_remove_child(struct device *dev, void *unused)
{
	platform_device_unregister(to_platform_device(dev));
	return 0;
}

static int pm8xxx_remove(struct platform_device *pdev)
{
	int irq = platform_get_irq(pdev, 0);
	struct pm_irq_chip *chip = platform_get_drvdata(pdev);

	device_for_each_child(&pdev->dev, NULL, pm8xxx_remove_child);
	irq_set_chained_handler_and_data(irq, NULL, NULL);
	irq_domain_remove(chip->irqdomain);

	return 0;
}

static struct platform_driver pm8xxx_driver = {
	.probe		= pm8xxx_probe,
	.remove		= pm8xxx_remove,
	.driver		= {
		.name	= "pm8xxx-core",
		.of_match_table = pm8xxx_id_table,
	},
};

static int __init pm8xxx_init(void)
{
	return platform_driver_register(&pm8xxx_driver);
}
subsys_initcall(pm8xxx_init);

static void __exit pm8xxx_exit(void)
{
	platform_driver_unregister(&pm8xxx_driver);
}
module_exit(pm8xxx_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("PMIC 8xxx core driver");
MODULE_VERSION("1.0");
MODULE_ALIAS("platform:pm8xxx-core");
Commit	Line	Data
97fb5e8d	1	// SPDX-License-Identifier: GPL-2.0-only
cbdb53e1 AD	2	/*
cbdb53e1 AD	3	* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
cbdb53e1 AD	4	*/
	5
	6	#define pr_fmt(fmt) "%s: " fmt, __func__
	7
	8	#include <linux/kernel.h>
bc866fc7	9	#include <linux/interrupt.h>
cced3548	10	#include <linux/irqchip/chained_irq.h>
bc866fc7	11	#include <linux/irq.h>
dc1a95cc	12	#include <linux/irqdomain.h>
ef310f4b	13	#include <linux/module.h>
cbdb53e1 AD	14	#include <linux/platform_device.h>
cbdb53e1 AD	15	#include <linux/slab.h>
c013f0a5	16	#include <linux/err.h>
ce44bf5b	17	#include <linux/ssbi.h>
e7b81fca	18	#include <linux/regmap.h>
dc1a95cc	19	#include <linux/of_platform.h>
cbdb53e1	20	#include <linux/mfd/core.h>
bc866fc7 SB	21
	22	#define SSBI_REG_ADDR_IRQ_BASE 0x1BB
	23
	24	#define SSBI_REG_ADDR_IRQ_ROOT (SSBI_REG_ADDR_IRQ_BASE + 0)
	25	#define SSBI_REG_ADDR_IRQ_M_STATUS1 (SSBI_REG_ADDR_IRQ_BASE + 1)
	26	#define SSBI_REG_ADDR_IRQ_M_STATUS2 (SSBI_REG_ADDR_IRQ_BASE + 2)
	27	#define SSBI_REG_ADDR_IRQ_M_STATUS3 (SSBI_REG_ADDR_IRQ_BASE + 3)
	28	#define SSBI_REG_ADDR_IRQ_M_STATUS4 (SSBI_REG_ADDR_IRQ_BASE + 4)
	29	#define SSBI_REG_ADDR_IRQ_BLK_SEL (SSBI_REG_ADDR_IRQ_BASE + 5)
	30	#define SSBI_REG_ADDR_IRQ_IT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 6)
	31	#define SSBI_REG_ADDR_IRQ_CONFIG (SSBI_REG_ADDR_IRQ_BASE + 7)
	32	#define SSBI_REG_ADDR_IRQ_RT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 8)
	33
953f432b SK	34	#define PM8821_SSBI_REG_ADDR_IRQ_BASE 0x100
	35	#define PM8821_SSBI_REG_ADDR_IRQ_MASTER0 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0x30)
	36	#define PM8821_SSBI_REG_ADDR_IRQ_MASTER1 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0xb0)
	37	#define PM8821_SSBI_REG(m, b, offset) \
	38	((m == 0) ? \
	39	(PM8821_SSBI_REG_ADDR_IRQ_MASTER0 + b + offset) : \
	40	(PM8821_SSBI_REG_ADDR_IRQ_MASTER1 + b + offset))
	41	#define PM8821_SSBI_ADDR_IRQ_ROOT(m, b) PM8821_SSBI_REG(m, b, 0x0)
	42	#define PM8821_SSBI_ADDR_IRQ_CLEAR(m, b) PM8821_SSBI_REG(m, b, 0x01)
	43	#define PM8821_SSBI_ADDR_IRQ_MASK(m, b) PM8821_SSBI_REG(m, b, 0x08)
	44	#define PM8821_SSBI_ADDR_IRQ_RT_STATUS(m, b) PM8821_SSBI_REG(m, b, 0x0f)
	45
	46	#define PM8821_BLOCKS_PER_MASTER 7
	47
bc866fc7 SB	48	#define PM_IRQF_LVL_SEL 0x01 /* level select */
	49	#define PM_IRQF_MASK_FE 0x02 /* mask falling edge */
	50	#define PM_IRQF_MASK_RE 0x04 /* mask rising edge */
	51	#define PM_IRQF_CLR 0x08 /* clear interrupt */
	52	#define PM_IRQF_BITS_MASK 0x70
	53	#define PM_IRQF_BITS_SHIFT 4
	54	#define PM_IRQF_WRITE 0x80
	55
	56	#define PM_IRQF_MASK_ALL (PM_IRQF_MASK_FE \| \
	57	PM_IRQF_MASK_RE)
cbdb53e1 AD	58
	59	#define REG_HWREV 0x002 /* PMIC4 revision */
	60	#define REG_HWREV_2 0x0E8 /* PMIC4 revision 2 */
	61
40a3a0f2	62	#define PM8XXX_NR_IRQS 256
953f432b	63	#define PM8821_NR_IRQS 112
dc1a95cc	64
3324a7c1 BM	65	struct pm_irq_data {
	66	int num_irqs;
	67	struct irq_chip *irq_chip;
	68	void (irq_handler)(struct irq_desc desc);
	69	};
	70
bc866fc7	71	struct pm_irq_chip {
e7b81fca	72	struct regmap *regmap;
bc866fc7	73	spinlock_t pm_irq_lock;
dc1a95cc	74	struct irq_domain *irqdomain;
bc866fc7 SB	75	unsigned int num_blocks;
bc866fc7 SB	76	unsigned int num_masters;
3324a7c1 BM	77	const struct pm_irq_data *pm_irq_data;
3324a7c1 BM	78	/* MUST BE AT THE END OF THIS STRUCT */
bc866fc7 SB	79	u8 config[0];
	80	};
	81
e7b81fca SB	82	static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp,
e7b81fca SB	83	unsigned int *ip)
bc866fc7 SB	84	{
	85	int rc;
	86
	87	spin_lock(&chip->pm_irq_lock);
e7b81fca	88	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
bc866fc7 SB	89	if (rc) {
	90	pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
	91	goto bail;
	92	}
	93
e7b81fca	94	rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
bc866fc7 SB	95	if (rc)
	96	pr_err("Failed Reading Status rc=%d\n", rc);
	97	bail:
	98	spin_unlock(&chip->pm_irq_lock);
	99	return rc;
	100	}
	101
e7b81fca SB	102	static int
e7b81fca SB	103	pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp)
bc866fc7 SB	104	{
	105	int rc;
	106
	107	spin_lock(&chip->pm_irq_lock);
e7b81fca	108	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
bc866fc7 SB	109	if (rc) {
	110	pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
	111	goto bail;
	112	}
	113
	114	cp \|= PM_IRQF_WRITE;
e7b81fca	115	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp);
bc866fc7 SB	116	if (rc)
	117	pr_err("Failed Configuring IRQ rc=%d\n", rc);
	118	bail:
	119	spin_unlock(&chip->pm_irq_lock);
	120	return rc;
	121	}
	122
	123	static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
	124	{
	125	int pmirq, irq, i, ret = 0;
e7b81fca	126	unsigned int bits;
bc866fc7 SB	127
	128	ret = pm8xxx_read_block_irq(chip, block, &bits);
	129	if (ret) {
	130	pr_err("Failed reading %d block ret=%d", block, ret);
	131	return ret;
	132	}
	133	if (!bits) {
	134	pr_err("block bit set in master but no irqs: %d", block);
	135	return 0;
	136	}
	137
	138	/* Check IRQ bits */
	139	for (i = 0; i < 8; i++) {
	140	if (bits & (1 << i)) {
	141	pmirq = block * 8 + i;
dc1a95cc	142	irq = irq_find_mapping(chip->irqdomain, pmirq);
bc866fc7 SB	143	generic_handle_irq(irq);
	144	}
	145	}
	146	return 0;
	147	}
	148
	149	static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
	150	{
e7b81fca	151	unsigned int blockbits;
bc866fc7 SB	152	int block_number, i, ret = 0;
bc866fc7 SB	153
e7b81fca SB	154	ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master,
e7b81fca SB	155	&blockbits);
bc866fc7 SB	156	if (ret) {
	157	pr_err("Failed to read master %d ret=%d\n", master, ret);
	158	return ret;
	159	}
	160	if (!blockbits) {
	161	pr_err("master bit set in root but no blocks: %d", master);
	162	return 0;
	163	}
	164
	165	for (i = 0; i < 8; i++)
	166	if (blockbits & (1 << i)) {
	167	block_number = master * 8 + i; /* block # */
	168	ret \|= pm8xxx_irq_block_handler(chip, block_number);
	169	}
	170	return ret;
	171	}
	172
bd0b9ac4	173	static void pm8xxx_irq_handler(struct irq_desc *desc)
bc866fc7 SB	174	{
	175	struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
	176	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
e7b81fca	177	unsigned int root;
bc866fc7 SB	178	int i, ret, masters = 0;
bc866fc7 SB	179
cced3548 SB	180	chained_irq_enter(irq_chip, desc);
cced3548 SB	181
e7b81fca	182	ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root);
bc866fc7 SB	183	if (ret) {
	184	pr_err("Can't read root status ret=%d\n", ret);
	185	return;
	186	}
	187
	188	/* on pm8xxx series masters start from bit 1 of the root */
	189	masters = root >> 1;
	190
	191	/* Read allowed masters for blocks. */
	192	for (i = 0; i < chip->num_masters; i++)
	193	if (masters & (1 << i))
	194	pm8xxx_irq_master_handler(chip, i);
	195
cced3548	196	chained_irq_exit(irq_chip, desc);
bc866fc7 SB	197	}
bc866fc7 SB	198
953f432b SK	199	static void pm8821_irq_block_handler(struct pm_irq_chip *chip,
	200	int master, int block)
	201	{
	202	int pmirq, irq, i, ret;
	203	unsigned int bits;
	204
	205	ret = regmap_read(chip->regmap,
	206	PM8821_SSBI_ADDR_IRQ_ROOT(master, block), &bits);
	207	if (ret) {
	208	pr_err("Reading block %d failed ret=%d", block, ret);
	209	return;
	210	}
	211
	212	/* Convert block offset to global block number */
	213	block += (master * PM8821_BLOCKS_PER_MASTER) - 1;
	214
	215	/* Check IRQ bits */
	216	for (i = 0; i < 8; i++) {
	217	if (bits & BIT(i)) {
	218	pmirq = block * 8 + i;
	219	irq = irq_find_mapping(chip->irqdomain, pmirq);
	220	generic_handle_irq(irq);
	221	}
	222	}
	223	}
	224
	225	static inline void pm8821_irq_master_handler(struct pm_irq_chip *chip,
	226	int master, u8 master_val)
	227	{
	228	int block;
	229
	230	for (block = 1; block < 8; block++)
	231	if (master_val & BIT(block))
	232	pm8821_irq_block_handler(chip, master, block);
	233	}
	234
	235	static void pm8821_irq_handler(struct irq_desc *desc)
	236	{
	237	struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
	238	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
	239	unsigned int master;
	240	int ret;
	241
	242	chained_irq_enter(irq_chip, desc);
	243	ret = regmap_read(chip->regmap,
	244	PM8821_SSBI_REG_ADDR_IRQ_MASTER0, &master);
	245	if (ret) {
	246	pr_err("Failed to read master 0 ret=%d\n", ret);
	247	goto done;
	248	}
	249
	250	/* bits 1 through 7 marks the first 7 blocks in master 0 */
	251	if (master & GENMASK(7, 1))
	252	pm8821_irq_master_handler(chip, 0, master);
	253
	254	/* bit 0 marks if master 1 contains any bits */
	255	if (!(master & BIT(0)))
	256	goto done;
	257
	258	ret = regmap_read(chip->regmap,
	259	PM8821_SSBI_REG_ADDR_IRQ_MASTER1, &master);
	260	if (ret) {
	261	pr_err("Failed to read master 1 ret=%d\n", ret);
	262	goto done;
263	}
264
265	pm8821_irq_master_handler(chip, 1, master);
266
267	done:
268	chained_irq_exit(irq_chip, desc);
269	}
270
bc866fc7 SB	271	static void pm8xxx_irq_mask_ack(struct irq_data *d)
	272	{
	273	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
dc1a95cc	274	unsigned int pmirq = irqd_to_hwirq(d);
bc866fc7 SB	275	u8 block, config;
	276
	277	block = pmirq / 8;
bc866fc7 SB	278
	279	config = chip->config[pmirq] \| PM_IRQF_MASK_ALL \| PM_IRQF_CLR;
	280	pm8xxx_config_irq(chip, block, config);
	281	}
	282
	283	static void pm8xxx_irq_unmask(struct irq_data *d)
	284	{
	285	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
dc1a95cc	286	unsigned int pmirq = irqd_to_hwirq(d);
bc866fc7 SB	287	u8 block, config;
	288
	289	block = pmirq / 8;
bc866fc7 SB	290
	291	config = chip->config[pmirq];
	292	pm8xxx_config_irq(chip, block, config);
	293	}
	294
	295	static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
	296	{
	297	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
dc1a95cc SB	298	unsigned int pmirq = irqd_to_hwirq(d);
dc1a95cc SB	299	int irq_bit;
bc866fc7 SB	300	u8 block, config;
	301
	302	block = pmirq / 8;
bc866fc7 SB	303	irq_bit = pmirq % 8;
	304
	305	chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
	306	\| PM_IRQF_MASK_ALL;
	307	if (flow_type & (IRQF_TRIGGER_RISING \| IRQF_TRIGGER_FALLING)) {
	308	if (flow_type & IRQF_TRIGGER_RISING)
	309	chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
	310	if (flow_type & IRQF_TRIGGER_FALLING)
	311	chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
	312	} else {
	313	chip->config[pmirq] \|= PM_IRQF_LVL_SEL;
	314
	315	if (flow_type & IRQF_TRIGGER_HIGH)
	316	chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
	317	else
	318	chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
	319	}
	320
	321	config = chip->config[pmirq] \| PM_IRQF_CLR;
	322	return pm8xxx_config_irq(chip, block, config);
	323	}
	324
f1837e4a BA	325	static int pm8xxx_irq_get_irqchip_state(struct irq_data *d,
	326	enum irqchip_irq_state which,
	327	bool *state)
	328	{
	329	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	330	unsigned int pmirq = irqd_to_hwirq(d);
	331	unsigned int bits;
	332	int irq_bit;
	333	u8 block;
	334	int rc;
	335
	336	if (which != IRQCHIP_STATE_LINE_LEVEL)
	337	return -EINVAL;
	338
	339	block = pmirq / 8;
	340	irq_bit = pmirq % 8;
	341
	342	spin_lock(&chip->pm_irq_lock);
	343	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
	344	if (rc) {
	345	pr_err("Failed Selecting Block %d rc=%d\n", block, rc);
	346	goto bail;
	347	}
	348
	349	rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
	350	if (rc) {
	351	pr_err("Failed Reading Status rc=%d\n", rc);
	352	goto bail;
	353	}
	354
	355	*state = !!(bits & BIT(irq_bit));
	356	bail:
	357	spin_unlock(&chip->pm_irq_lock);
	358
	359	return rc;
	360	}
	361
bc866fc7 SB	362	static struct irq_chip pm8xxx_irq_chip = {
	363	.name = "pm8xxx",
	364	.irq_mask_ack = pm8xxx_irq_mask_ack,
	365	.irq_unmask = pm8xxx_irq_unmask,
	366	.irq_set_type = pm8xxx_irq_set_type,
f1837e4a	367	.irq_get_irqchip_state = pm8xxx_irq_get_irqchip_state,
d2d24ad1	368	.flags = IRQCHIP_MASK_ON_SUSPEND \| IRQCHIP_SKIP_SET_WAKE,
bc866fc7 SB	369	};
bc866fc7 SB	370
3324a7c1 BM	371	static void pm8xxx_irq_domain_map(struct pm_irq_chip *chip,
	372	struct irq_domain *domain, unsigned int irq,
	373	irq_hw_number_t hwirq, unsigned int type)
dc1a95cc	374	{
3324a7c1 BM	375	irq_domain_set_info(domain, irq, hwirq, chip->pm_irq_data->irq_chip,
3324a7c1 BM	376	chip, handle_level_irq, NULL, NULL);
dc1a95cc	377	irq_set_noprobe(irq);
3324a7c1 BM	378	}
	379
	380	static int pm8xxx_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
	381	unsigned int nr_irqs, void *data)
	382	{
	383	struct pm_irq_chip *chip = domain->host_data;
	384	struct irq_fwspec *fwspec = data;
	385	irq_hw_number_t hwirq;
	386	unsigned int type;
	387	int ret, i;
	388
	389	ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
	390	if (ret)
	391	return ret;
	392
	393	for (i = 0; i < nr_irqs; i++)
	394	pm8xxx_irq_domain_map(chip, domain, virq + i, hwirq + i, type);
9bd09f34	395
bc866fc7 SB	396	return 0;
	397	}
	398
dc1a95cc	399	static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
3324a7c1 BM	400	.alloc = pm8xxx_irq_domain_alloc,
	401	.free = irq_domain_free_irqs_common,
	402	.translate = irq_domain_translate_twocell,
dc1a95cc SB	403	};
dc1a95cc SB	404
953f432b SK	405	static void pm8821_irq_mask_ack(struct irq_data *d)
	406	{
	407	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	408	unsigned int pmirq = irqd_to_hwirq(d);
	409	u8 block, master;
	410	int irq_bit, rc;
	411
	412	block = pmirq / 8;
	413	master = block / PM8821_BLOCKS_PER_MASTER;
	414	irq_bit = pmirq % 8;
	415	block %= PM8821_BLOCKS_PER_MASTER;
	416
	417	rc = regmap_update_bits(chip->regmap,
	418	PM8821_SSBI_ADDR_IRQ_MASK(master, block),
	419	BIT(irq_bit), BIT(irq_bit));
	420	if (rc) {
	421	pr_err("Failed to mask IRQ:%d rc=%d\n", pmirq, rc);
	422	return;
	423	}
	424
	425	rc = regmap_update_bits(chip->regmap,
	426	PM8821_SSBI_ADDR_IRQ_CLEAR(master, block),
	427	BIT(irq_bit), BIT(irq_bit));
	428	if (rc)
	429	pr_err("Failed to CLEAR IRQ:%d rc=%d\n", pmirq, rc);
	430	}
	431
	432	static void pm8821_irq_unmask(struct irq_data *d)
	433	{
	434	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	435	unsigned int pmirq = irqd_to_hwirq(d);
	436	int irq_bit, rc;
	437	u8 block, master;
	438
	439	block = pmirq / 8;
	440	master = block / PM8821_BLOCKS_PER_MASTER;
	441	irq_bit = pmirq % 8;
	442	block %= PM8821_BLOCKS_PER_MASTER;
	443
	444	rc = regmap_update_bits(chip->regmap,
	445	PM8821_SSBI_ADDR_IRQ_MASK(master, block),
	446	BIT(irq_bit), ~BIT(irq_bit));
	447	if (rc)
	448	pr_err("Failed to read/write unmask IRQ:%d rc=%d\n", pmirq, rc);
	449
	450	}
	451
	452	static int pm8821_irq_get_irqchip_state(struct irq_data *d,
	453	enum irqchip_irq_state which,
	454	bool *state)
	455	{
	456	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	457	int rc, pmirq = irqd_to_hwirq(d);
	458	u8 block, irq_bit, master;
	459	unsigned int bits;
	460
	461	block = pmirq / 8;
	462	master = block / PM8821_BLOCKS_PER_MASTER;
	463	irq_bit = pmirq % 8;
	464	block %= PM8821_BLOCKS_PER_MASTER;
	465
	466	rc = regmap_read(chip->regmap,
	467	PM8821_SSBI_ADDR_IRQ_RT_STATUS(master, block), &bits);
	468	if (rc) {
469	pr_err("Reading Status of IRQ %d failed rc=%d\n", pmirq, rc);
470	return rc;
471	}
472
473	*state = !!(bits & BIT(irq_bit));
474
475	return rc;
476	}
477
478	static struct irq_chip pm8821_irq_chip = {
479	.name = "pm8821",
480	.irq_mask_ack = pm8821_irq_mask_ack,
481	.irq_unmask = pm8821_irq_unmask,
482	.irq_get_irqchip_state = pm8821_irq_get_irqchip_state,
483	.flags = IRQCHIP_MASK_ON_SUSPEND \| IRQCHIP_SKIP_SET_WAKE,
484	};
485
e7b81fca SB	486	static const struct regmap_config ssbi_regmap_config = {
	487	.reg_bits = 16,
	488	.val_bits = 8,
	489	.max_register = 0x3ff,
	490	.fast_io = true,
	491	.reg_read = ssbi_reg_read,
	492	.reg_write = ssbi_reg_write
	493	};
	494
953f432b SK	495	static const struct pm_irq_data pm8xxx_data = {
953f432b SK	496	.num_irqs = PM8XXX_NR_IRQS,
3324a7c1	497	.irq_chip = &pm8xxx_irq_chip,
953f432b SK	498	.irq_handler = pm8xxx_irq_handler,
	499	};
	500
	501	static const struct pm_irq_data pm8821_data = {
	502	.num_irqs = PM8821_NR_IRQS,
3324a7c1	503	.irq_chip = &pm8821_irq_chip,
953f432b SK	504	.irq_handler = pm8821_irq_handler,
	505	};
	506
40a3a0f2	507	static const struct of_device_id pm8xxx_id_table[] = {
953f432b SK	508	{ .compatible = "qcom,pm8018", .data = &pm8xxx_data},
	509	{ .compatible = "qcom,pm8058", .data = &pm8xxx_data},
	510	{ .compatible = "qcom,pm8821", .data = &pm8821_data},
	511	{ .compatible = "qcom,pm8921", .data = &pm8xxx_data},
c5865a53 SB	512	{ }
c5865a53 SB	513	};
40a3a0f2	514	MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
c5865a53	515
40a3a0f2	516	static int pm8xxx_probe(struct platform_device *pdev)
cbdb53e1	517	{
953f432b	518	const struct pm_irq_data *data;
e7b81fca	519	struct regmap *regmap;
202f7680	520	int irq, rc;
e7b81fca	521	unsigned int val;
c013f0a5	522	u32 rev;
dc1a95cc	523	struct pm_irq_chip *chip;
953f432b SK	524
	525	data = of_device_get_match_data(&pdev->dev);
	526	if (!data) {
	527	dev_err(&pdev->dev, "No matching driver data found\n");
	528	return -EINVAL;
	529	}
cbdb53e1	530
dc1a95cc SB	531	irq = platform_get_irq(pdev, 0);
	532	if (irq < 0)
	533	return irq;
cbdb53e1	534
e7b81fca SB	535	regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent,
	536	&ssbi_regmap_config);
	537	if (IS_ERR(regmap))
	538	return PTR_ERR(regmap);
	539
cbdb53e1	540	/* Read PMIC chip revision */
e7b81fca	541	rc = regmap_read(regmap, REG_HWREV, &val);
cbdb53e1 AD	542	if (rc) {
cbdb53e1 AD	543	pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
b2cdcfac	544	return rc;
cbdb53e1 AD	545	}
cbdb53e1 AD	546	pr_info("PMIC revision 1: %02X\n", val);
c013f0a5	547	rev = val;
cbdb53e1 AD	548
cbdb53e1 AD	549	/* Read PMIC chip revision 2 */
e7b81fca	550	rc = regmap_read(regmap, REG_HWREV_2, &val);
cbdb53e1 AD	551	if (rc) {
	552	pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
	553	REG_HWREV_2, rc);
b2cdcfac	554	return rc;
cbdb53e1 AD	555	}
cbdb53e1 AD	556	pr_info("PMIC revision 2: %02X\n", val);
c013f0a5	557	rev \|= val << BITS_PER_BYTE;
cbdb53e1	558
0ed2dd03 KC	559	chip = devm_kzalloc(&pdev->dev,
0ed2dd03 KC	560	struct_size(chip, config, data->num_irqs),
953f432b	561	GFP_KERNEL);
dc1a95cc SB	562	if (!chip)
	563	return -ENOMEM;
	564
3e87933a	565	platform_set_drvdata(pdev, chip);
e7b81fca	566	chip->regmap = regmap;
3324a7c1	567	chip->num_blocks = DIV_ROUND_UP(data->num_irqs, 8);
dc1a95cc	568	chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
3324a7c1	569	chip->pm_irq_data = data;
dc1a95cc SB	570	spin_lock_init(&chip->pm_irq_lock);
dc1a95cc SB	571
953f432b SK	572	chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
953f432b SK	573	data->num_irqs,
3324a7c1	574	&pm8xxx_irq_domain_ops,
dc1a95cc SB	575	chip);
	576	if (!chip->irqdomain)
	577	return -ENODEV;
	578
953f432b	579	irq_set_chained_handler_and_data(irq, data->irq_handler, chip);
dc1a95cc SB	580	irq_set_irq_wake(irq, 1);
	581
	582	rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
c013f0a5	583	if (rc) {
b79f0438	584	irq_set_chained_handler_and_data(irq, NULL, NULL);
dc1a95cc	585	irq_domain_remove(chip->irqdomain);
c013f0a5 AD	586	}
c013f0a5 AD	587
dc1a95cc SB	588	return rc;
dc1a95cc SB	589	}
c013f0a5	590
40a3a0f2	591	static int pm8xxx_remove_child(struct device dev, void unused)
dc1a95cc SB	592	{
dc1a95cc SB	593	platform_device_unregister(to_platform_device(dev));
cbdb53e1	594	return 0;
cbdb53e1 AD	595	}
cbdb53e1 AD	596
40a3a0f2	597	static int pm8xxx_remove(struct platform_device *pdev)
cbdb53e1	598	{
dc1a95cc	599	int irq = platform_get_irq(pdev, 0);
3e87933a	600	struct pm_irq_chip *chip = platform_get_drvdata(pdev);
dc1a95cc	601
40a3a0f2	602	device_for_each_child(&pdev->dev, NULL, pm8xxx_remove_child);
b79f0438	603	irq_set_chained_handler_and_data(irq, NULL, NULL);
dc1a95cc	604	irq_domain_remove(chip->irqdomain);
cbdb53e1 AD	605
	606	return 0;
	607	}
	608
40a3a0f2 LW	609	static struct platform_driver pm8xxx_driver = {
	610	.probe = pm8xxx_probe,
	611	.remove = pm8xxx_remove,
cbdb53e1	612	.driver = {
40a3a0f2 LW	613	.name = "pm8xxx-core",
40a3a0f2 LW	614	.of_match_table = pm8xxx_id_table,
cbdb53e1 AD	615	},
	616	};
	617
40a3a0f2	618	static int __init pm8xxx_init(void)
cbdb53e1	619	{
40a3a0f2	620	return platform_driver_register(&pm8xxx_driver);
cbdb53e1	621	}
40a3a0f2	622	subsys_initcall(pm8xxx_init);
cbdb53e1	623
40a3a0f2	624	static void __exit pm8xxx_exit(void)
cbdb53e1	625	{
40a3a0f2	626	platform_driver_unregister(&pm8xxx_driver);
cbdb53e1	627	}
40a3a0f2	628	module_exit(pm8xxx_exit);
cbdb53e1 AD	629
cbdb53e1 AD	630	MODULE_LICENSE("GPL v2");
40a3a0f2	631	MODULE_DESCRIPTION("PMIC 8xxx core driver");
cbdb53e1	632	MODULE_VERSION("1.0");
40a3a0f2	633	MODULE_ALIAS("platform:pm8xxx-core");