[mirror_ubuntu-jammy-kernel.git] / drivers / mfd / qcom-pm8xxx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
 */

#define pr_fmt(fmt) "%s: " fmt, __func__

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/ssbi.h>
#include <linux/regmap.h>
#include <linux/of_platform.h>
#include <linux/mfd/core.h>

#define	SSBI_REG_ADDR_IRQ_BASE		0x1BB

#define	SSBI_REG_ADDR_IRQ_ROOT		(SSBI_REG_ADDR_IRQ_BASE + 0)
#define	SSBI_REG_ADDR_IRQ_M_STATUS1	(SSBI_REG_ADDR_IRQ_BASE + 1)
#define	SSBI_REG_ADDR_IRQ_M_STATUS2	(SSBI_REG_ADDR_IRQ_BASE + 2)
#define	SSBI_REG_ADDR_IRQ_M_STATUS3	(SSBI_REG_ADDR_IRQ_BASE + 3)
#define	SSBI_REG_ADDR_IRQ_M_STATUS4	(SSBI_REG_ADDR_IRQ_BASE + 4)
#define	SSBI_REG_ADDR_IRQ_BLK_SEL	(SSBI_REG_ADDR_IRQ_BASE + 5)
#define	SSBI_REG_ADDR_IRQ_IT_STATUS	(SSBI_REG_ADDR_IRQ_BASE + 6)
#define	SSBI_REG_ADDR_IRQ_CONFIG	(SSBI_REG_ADDR_IRQ_BASE + 7)
#define	SSBI_REG_ADDR_IRQ_RT_STATUS	(SSBI_REG_ADDR_IRQ_BASE + 8)

#define	PM8821_SSBI_REG_ADDR_IRQ_BASE	0x100
#define	PM8821_SSBI_REG_ADDR_IRQ_MASTER0 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0x30)
#define	PM8821_SSBI_REG_ADDR_IRQ_MASTER1 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0xb0)
#define	PM8821_SSBI_REG(m, b, offset) \
			((m == 0) ? \
			(PM8821_SSBI_REG_ADDR_IRQ_MASTER0 + b + offset) : \
			(PM8821_SSBI_REG_ADDR_IRQ_MASTER1 + b + offset))
#define	PM8821_SSBI_ADDR_IRQ_ROOT(m, b)		PM8821_SSBI_REG(m, b, 0x0)
#define	PM8821_SSBI_ADDR_IRQ_CLEAR(m, b)	PM8821_SSBI_REG(m, b, 0x01)
#define	PM8821_SSBI_ADDR_IRQ_MASK(m, b)		PM8821_SSBI_REG(m, b, 0x08)
#define	PM8821_SSBI_ADDR_IRQ_RT_STATUS(m, b)	PM8821_SSBI_REG(m, b, 0x0f)

#define	PM8821_BLOCKS_PER_MASTER	7

#define	PM_IRQF_LVL_SEL			0x01	/* level select */
#define	PM_IRQF_MASK_FE			0x02	/* mask falling edge */
#define	PM_IRQF_MASK_RE			0x04	/* mask rising edge */
#define	PM_IRQF_CLR			0x08	/* clear interrupt */
#define	PM_IRQF_BITS_MASK		0x70
#define	PM_IRQF_BITS_SHIFT		4
#define	PM_IRQF_WRITE			0x80

#define	PM_IRQF_MASK_ALL		(PM_IRQF_MASK_FE | \
					PM_IRQF_MASK_RE)

#define REG_HWREV		0x002  /* PMIC4 revision */
#define REG_HWREV_2		0x0E8  /* PMIC4 revision 2 */

#define PM8XXX_NR_IRQS		256
#define PM8821_NR_IRQS		112

struct pm_irq_data {
	int num_irqs;
	struct irq_chip *irq_chip;
	void (*irq_handler)(struct irq_desc *desc);
};

struct pm_irq_chip {
	struct regmap		*regmap;
	spinlock_t		pm_irq_lock;
	struct irq_domain	*irqdomain;
	unsigned int		num_blocks;
	unsigned int		num_masters;
	const struct pm_irq_data *pm_irq_data;
	/* MUST BE AT THE END OF THIS STRUCT */
	u8			config[];
};

static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp,
				 unsigned int *ip)
{
	int	rc;

	spin_lock(&chip->pm_irq_lock);
	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
	if (rc) {
		pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
		goto bail;
	}

	rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
	if (rc)
		pr_err("Failed Reading Status rc=%d\n", rc);
bail:
	spin_unlock(&chip->pm_irq_lock);
	return rc;
}

static int
pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp)
{
	int	rc;

	spin_lock(&chip->pm_irq_lock);
	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
	if (rc) {
		pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
		goto bail;
	}

	cp |= PM_IRQF_WRITE;
	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp);
	if (rc)
		pr_err("Failed Configuring IRQ rc=%d\n", rc);
bail:
	spin_unlock(&chip->pm_irq_lock);
	return rc;
}

static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
{
	int pmirq, i, ret = 0;
	unsigned int bits;

	ret = pm8xxx_read_block_irq(chip, block, &bits);
	if (ret) {
		pr_err("Failed reading %d block ret=%d", block, ret);
		return ret;
	}
	if (!bits) {
		pr_err("block bit set in master but no irqs: %d", block);
		return 0;
	}

	/* Check IRQ bits */
	for (i = 0; i < 8; i++) {
		if (bits & (1 << i)) {
			pmirq = block * 8 + i;
			generic_handle_domain_irq(chip->irqdomain, pmirq);
		}
	}
	return 0;
}

static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
{
	unsigned int blockbits;
	int block_number, i, ret = 0;

	ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master,
			  &blockbits);
	if (ret) {
		pr_err("Failed to read master %d ret=%d\n", master, ret);
		return ret;
	}
	if (!blockbits) {
		pr_err("master bit set in root but no blocks: %d", master);
		return 0;
	}

	for (i = 0; i < 8; i++)
		if (blockbits & (1 << i)) {
			block_number = master * 8 + i;	/* block # */
			ret |= pm8xxx_irq_block_handler(chip, block_number);
		}
	return ret;
}

static void pm8xxx_irq_handler(struct irq_desc *desc)
{
	struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
	unsigned int root;
	int	i, ret, masters = 0;

	chained_irq_enter(irq_chip, desc);

	ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root);
	if (ret) {
		pr_err("Can't read root status ret=%d\n", ret);
		return;
	}

	/* on pm8xxx series masters start from bit 1 of the root */
	masters = root >> 1;

	/* Read allowed masters for blocks. */
	for (i = 0; i < chip->num_masters; i++)
		if (masters & (1 << i))
			pm8xxx_irq_master_handler(chip, i);

	chained_irq_exit(irq_chip, desc);
}

static void pm8821_irq_block_handler(struct pm_irq_chip *chip,
				     int master, int block)
{
	int pmirq, i, ret;
	unsigned int bits;

	ret = regmap_read(chip->regmap,
			  PM8821_SSBI_ADDR_IRQ_ROOT(master, block), &bits);
	if (ret) {
		pr_err("Reading block %d failed ret=%d", block, ret);
		return;
	}

	/* Convert block offset to global block number */
	block += (master * PM8821_BLOCKS_PER_MASTER) - 1;

	/* Check IRQ bits */
	for (i = 0; i < 8; i++) {
		if (bits & BIT(i)) {
			pmirq = block * 8 + i;
			generic_handle_domain_irq(chip->irqdomain, pmirq);
		}
	}
}

static inline void pm8821_irq_master_handler(struct pm_irq_chip *chip,
					     int master, u8 master_val)
{
	int block;

	for (block = 1; block < 8; block++)
		if (master_val & BIT(block))
			pm8821_irq_block_handler(chip, master, block);
}

static void pm8821_irq_handler(struct irq_desc *desc)
{
	struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
	unsigned int master;
	int ret;

	chained_irq_enter(irq_chip, desc);
	ret = regmap_read(chip->regmap,
			  PM8821_SSBI_REG_ADDR_IRQ_MASTER0, &master);
	if (ret) {
		pr_err("Failed to read master 0 ret=%d\n", ret);
		goto done;
	}

	/* bits 1 through 7 marks the first 7 blocks in master 0 */
	if (master & GENMASK(7, 1))
		pm8821_irq_master_handler(chip, 0, master);

	/* bit 0 marks if master 1 contains any bits */
	if (!(master & BIT(0)))
		goto done;

	ret = regmap_read(chip->regmap,
			  PM8821_SSBI_REG_ADDR_IRQ_MASTER1, &master);
	if (ret) {
		pr_err("Failed to read master 1 ret=%d\n", ret);
		goto done;
	}

	pm8821_irq_master_handler(chip, 1, master);

done:
	chained_irq_exit(irq_chip, desc);
}

static void pm8xxx_irq_mask_ack(struct irq_data *d)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	u8	block, config;

	block = pmirq / 8;

	config = chip->config[pmirq] | PM_IRQF_MASK_ALL | PM_IRQF_CLR;
	pm8xxx_config_irq(chip, block, config);
}

static void pm8xxx_irq_unmask(struct irq_data *d)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	u8	block, config;

	block = pmirq / 8;

	config = chip->config[pmirq];
	pm8xxx_config_irq(chip, block, config);
}

static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	int irq_bit;
	u8 block, config;

	block = pmirq / 8;
	irq_bit  = pmirq % 8;

	chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
							| PM_IRQF_MASK_ALL;
	if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
		if (flow_type & IRQF_TRIGGER_RISING)
			chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
		if (flow_type & IRQF_TRIGGER_FALLING)
			chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
	} else {
		chip->config[pmirq] |= PM_IRQF_LVL_SEL;

		if (flow_type & IRQF_TRIGGER_HIGH)
			chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
		else
			chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
	}

	config = chip->config[pmirq] | PM_IRQF_CLR;
	return pm8xxx_config_irq(chip, block, config);
}

static int pm8xxx_irq_get_irqchip_state(struct irq_data *d,
					enum irqchip_irq_state which,
					bool *state)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	unsigned int bits;
	int irq_bit;
	u8 block;
	int rc;

	if (which != IRQCHIP_STATE_LINE_LEVEL)
		return -EINVAL;

	block = pmirq / 8;
	irq_bit = pmirq % 8;

	spin_lock(&chip->pm_irq_lock);
	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
	if (rc) {
		pr_err("Failed Selecting Block %d rc=%d\n", block, rc);
		goto bail;
	}

	rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
	if (rc) {
		pr_err("Failed Reading Status rc=%d\n", rc);
		goto bail;
	}

	*state = !!(bits & BIT(irq_bit));
bail:
	spin_unlock(&chip->pm_irq_lock);

	return rc;
}

static struct irq_chip pm8xxx_irq_chip = {
	.name		= "pm8xxx",
	.irq_mask_ack	= pm8xxx_irq_mask_ack,
	.irq_unmask	= pm8xxx_irq_unmask,
	.irq_set_type	= pm8xxx_irq_set_type,
	.irq_get_irqchip_state = pm8xxx_irq_get_irqchip_state,
	.flags		= IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
};

static void pm8xxx_irq_domain_map(struct pm_irq_chip *chip,
				  struct irq_domain *domain, unsigned int irq,
				  irq_hw_number_t hwirq, unsigned int type)
{
	irq_domain_set_info(domain, irq, hwirq, chip->pm_irq_data->irq_chip,
			    chip, handle_level_irq, NULL, NULL);
	irq_set_noprobe(irq);
}

static int pm8xxx_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
				   unsigned int nr_irqs, void *data)
{
	struct pm_irq_chip *chip = domain->host_data;
	struct irq_fwspec *fwspec = data;
	irq_hw_number_t hwirq;
	unsigned int type;
	int ret, i;

	ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
	if (ret)
		return ret;

	for (i = 0; i < nr_irqs; i++)
		pm8xxx_irq_domain_map(chip, domain, virq + i, hwirq + i, type);

	return 0;
}

static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
	.alloc = pm8xxx_irq_domain_alloc,
	.free = irq_domain_free_irqs_common,
	.translate = irq_domain_translate_twocell,
};

static void pm8821_irq_mask_ack(struct irq_data *d)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	u8 block, master;
	int irq_bit, rc;

	block = pmirq / 8;
	master = block / PM8821_BLOCKS_PER_MASTER;
	irq_bit = pmirq % 8;
	block %= PM8821_BLOCKS_PER_MASTER;

	rc = regmap_update_bits(chip->regmap,
				PM8821_SSBI_ADDR_IRQ_MASK(master, block),
				BIT(irq_bit), BIT(irq_bit));
	if (rc) {
		pr_err("Failed to mask IRQ:%d rc=%d\n", pmirq, rc);
		return;
	}

	rc = regmap_update_bits(chip->regmap,
				PM8821_SSBI_ADDR_IRQ_CLEAR(master, block),
				BIT(irq_bit), BIT(irq_bit));
	if (rc)
		pr_err("Failed to CLEAR IRQ:%d rc=%d\n", pmirq, rc);
}

static void pm8821_irq_unmask(struct irq_data *d)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	int irq_bit, rc;
	u8 block, master;

	block = pmirq / 8;
	master = block / PM8821_BLOCKS_PER_MASTER;
	irq_bit = pmirq % 8;
	block %= PM8821_BLOCKS_PER_MASTER;

	rc = regmap_update_bits(chip->regmap,
				PM8821_SSBI_ADDR_IRQ_MASK(master, block),
				BIT(irq_bit), ~BIT(irq_bit));
	if (rc)
		pr_err("Failed to read/write unmask IRQ:%d rc=%d\n", pmirq, rc);

}

static int pm8821_irq_get_irqchip_state(struct irq_data *d,
					enum irqchip_irq_state which,
					bool *state)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	int rc, pmirq = irqd_to_hwirq(d);
	u8 block, irq_bit, master;
	unsigned int bits;

	block = pmirq / 8;
	master = block / PM8821_BLOCKS_PER_MASTER;
	irq_bit = pmirq % 8;
	block %= PM8821_BLOCKS_PER_MASTER;

	rc = regmap_read(chip->regmap,
		PM8821_SSBI_ADDR_IRQ_RT_STATUS(master, block), &bits);
	if (rc) {
		pr_err("Reading Status of IRQ %d failed rc=%d\n", pmirq, rc);
		return rc;
	}

	*state = !!(bits & BIT(irq_bit));

	return rc;
}

static struct irq_chip pm8821_irq_chip = {
	.name		= "pm8821",
	.irq_mask_ack	= pm8821_irq_mask_ack,
	.irq_unmask	= pm8821_irq_unmask,
	.irq_get_irqchip_state = pm8821_irq_get_irqchip_state,
	.flags		= IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
};

static const struct regmap_config ssbi_regmap_config = {
	.reg_bits = 16,
	.val_bits = 8,
	.max_register = 0x3ff,
	.fast_io = true,
	.reg_read = ssbi_reg_read,
	.reg_write = ssbi_reg_write
};

static const struct pm_irq_data pm8xxx_data = {
	.num_irqs = PM8XXX_NR_IRQS,
	.irq_chip = &pm8xxx_irq_chip,
	.irq_handler = pm8xxx_irq_handler,
};

static const struct pm_irq_data pm8821_data = {
	.num_irqs = PM8821_NR_IRQS,
	.irq_chip = &pm8821_irq_chip,
	.irq_handler = pm8821_irq_handler,
};

static const struct of_device_id pm8xxx_id_table[] = {
	{ .compatible = "qcom,pm8018", .data = &pm8xxx_data},
	{ .compatible = "qcom,pm8058", .data = &pm8xxx_data},
	{ .compatible = "qcom,pm8821", .data = &pm8821_data},
	{ .compatible = "qcom,pm8921", .data = &pm8xxx_data},
	{ }
};
MODULE_DEVICE_TABLE(of, pm8xxx_id_table);

static int pm8xxx_probe(struct platform_device *pdev)
{
	const struct pm_irq_data *data;
	struct regmap *regmap;
	int irq, rc;
	unsigned int val;
	u32 rev;
	struct pm_irq_chip *chip;

	data = of_device_get_match_data(&pdev->dev);
	if (!data) {
		dev_err(&pdev->dev, "No matching driver data found\n");
		return -EINVAL;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent,
				  &ssbi_regmap_config);
	if (IS_ERR(regmap))
		return PTR_ERR(regmap);

	/* Read PMIC chip revision */
	rc = regmap_read(regmap, REG_HWREV, &val);
	if (rc) {
		pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
		return rc;
	}
	pr_info("PMIC revision 1: %02X\n", val);
	rev = val;

	/* Read PMIC chip revision 2 */
	rc = regmap_read(regmap, REG_HWREV_2, &val);
	if (rc) {
		pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
			REG_HWREV_2, rc);
		return rc;
	}
	pr_info("PMIC revision 2: %02X\n", val);
	rev |= val << BITS_PER_BYTE;

	chip = devm_kzalloc(&pdev->dev,
			    struct_size(chip, config, data->num_irqs),
			    GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	platform_set_drvdata(pdev, chip);
	chip->regmap = regmap;
	chip->num_blocks = DIV_ROUND_UP(data->num_irqs, 8);
	chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
	chip->pm_irq_data = data;
	spin_lock_init(&chip->pm_irq_lock);

	chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
						data->num_irqs,
						&pm8xxx_irq_domain_ops,
						chip);
	if (!chip->irqdomain)
		return -ENODEV;

	irq_set_chained_handler_and_data(irq, data->irq_handler, chip);
	irq_set_irq_wake(irq, 1);

	rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
	if (rc) {
		irq_set_chained_handler_and_data(irq, NULL, NULL);
		irq_domain_remove(chip->irqdomain);
	}

	return rc;
}

static int pm8xxx_remove_child(struct device *dev, void *unused)
{
	platform_device_unregister(to_platform_device(dev));
	return 0;
}

static int pm8xxx_remove(struct platform_device *pdev)
{
	int irq = platform_get_irq(pdev, 0);
	struct pm_irq_chip *chip = platform_get_drvdata(pdev);

	device_for_each_child(&pdev->dev, NULL, pm8xxx_remove_child);
	irq_set_chained_handler_and_data(irq, NULL, NULL);
	irq_domain_remove(chip->irqdomain);

	return 0;
}

static struct platform_driver pm8xxx_driver = {
	.probe		= pm8xxx_probe,
	.remove		= pm8xxx_remove,
	.driver		= {
		.name	= "pm8xxx-core",
		.of_match_table = pm8xxx_id_table,
	},
};

static int __init pm8xxx_init(void)
{
	return platform_driver_register(&pm8xxx_driver);
}
subsys_initcall(pm8xxx_init);

static void __exit pm8xxx_exit(void)
{
	platform_driver_unregister(&pm8xxx_driver);
}
module_exit(pm8xxx_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("PMIC 8xxx core driver");
MODULE_VERSION("1.0");
MODULE_ALIAS("platform:pm8xxx-core");
Commit	Line	Data
97fb5e8d	1	// SPDX-License-Identifier: GPL-2.0-only
cbdb53e1 AD	2	/*
cbdb53e1 AD	3	* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
cbdb53e1 AD	4	*/
	5
	6	#define pr_fmt(fmt) "%s: " fmt, __func__
	7
	8	#include <linux/kernel.h>
bc866fc7	9	#include <linux/interrupt.h>
cced3548	10	#include <linux/irqchip/chained_irq.h>
bc866fc7	11	#include <linux/irq.h>
dc1a95cc	12	#include <linux/irqdomain.h>
ef310f4b	13	#include <linux/module.h>
cbdb53e1 AD	14	#include <linux/platform_device.h>
cbdb53e1 AD	15	#include <linux/slab.h>
c013f0a5	16	#include <linux/err.h>
ce44bf5b	17	#include <linux/ssbi.h>
e7b81fca	18	#include <linux/regmap.h>
dc1a95cc	19	#include <linux/of_platform.h>
cbdb53e1	20	#include <linux/mfd/core.h>
bc866fc7 SB	21
	22	#define SSBI_REG_ADDR_IRQ_BASE 0x1BB
	23
	24	#define SSBI_REG_ADDR_IRQ_ROOT (SSBI_REG_ADDR_IRQ_BASE + 0)
	25	#define SSBI_REG_ADDR_IRQ_M_STATUS1 (SSBI_REG_ADDR_IRQ_BASE + 1)
	26	#define SSBI_REG_ADDR_IRQ_M_STATUS2 (SSBI_REG_ADDR_IRQ_BASE + 2)
	27	#define SSBI_REG_ADDR_IRQ_M_STATUS3 (SSBI_REG_ADDR_IRQ_BASE + 3)
	28	#define SSBI_REG_ADDR_IRQ_M_STATUS4 (SSBI_REG_ADDR_IRQ_BASE + 4)
	29	#define SSBI_REG_ADDR_IRQ_BLK_SEL (SSBI_REG_ADDR_IRQ_BASE + 5)
	30	#define SSBI_REG_ADDR_IRQ_IT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 6)
	31	#define SSBI_REG_ADDR_IRQ_CONFIG (SSBI_REG_ADDR_IRQ_BASE + 7)
	32	#define SSBI_REG_ADDR_IRQ_RT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 8)
	33
953f432b SK	34	#define PM8821_SSBI_REG_ADDR_IRQ_BASE 0x100
	35	#define PM8821_SSBI_REG_ADDR_IRQ_MASTER0 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0x30)
	36	#define PM8821_SSBI_REG_ADDR_IRQ_MASTER1 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0xb0)
	37	#define PM8821_SSBI_REG(m, b, offset) \
	38	((m == 0) ? \
	39	(PM8821_SSBI_REG_ADDR_IRQ_MASTER0 + b + offset) : \
	40	(PM8821_SSBI_REG_ADDR_IRQ_MASTER1 + b + offset))
	41	#define PM8821_SSBI_ADDR_IRQ_ROOT(m, b) PM8821_SSBI_REG(m, b, 0x0)
	42	#define PM8821_SSBI_ADDR_IRQ_CLEAR(m, b) PM8821_SSBI_REG(m, b, 0x01)
	43	#define PM8821_SSBI_ADDR_IRQ_MASK(m, b) PM8821_SSBI_REG(m, b, 0x08)
	44	#define PM8821_SSBI_ADDR_IRQ_RT_STATUS(m, b) PM8821_SSBI_REG(m, b, 0x0f)
	45
	46	#define PM8821_BLOCKS_PER_MASTER 7
	47
bc866fc7 SB	48	#define PM_IRQF_LVL_SEL 0x01 /* level select */
	49	#define PM_IRQF_MASK_FE 0x02 /* mask falling edge */
	50	#define PM_IRQF_MASK_RE 0x04 /* mask rising edge */
	51	#define PM_IRQF_CLR 0x08 /* clear interrupt */
	52	#define PM_IRQF_BITS_MASK 0x70
	53	#define PM_IRQF_BITS_SHIFT 4
	54	#define PM_IRQF_WRITE 0x80
	55
	56	#define PM_IRQF_MASK_ALL (PM_IRQF_MASK_FE \| \
	57	PM_IRQF_MASK_RE)
cbdb53e1 AD	58
	59	#define REG_HWREV 0x002 /* PMIC4 revision */
	60	#define REG_HWREV_2 0x0E8 /* PMIC4 revision 2 */
	61
40a3a0f2	62	#define PM8XXX_NR_IRQS 256
953f432b	63	#define PM8821_NR_IRQS 112
dc1a95cc	64
3324a7c1 BM	65	struct pm_irq_data {
	66	int num_irqs;
	67	struct irq_chip *irq_chip;
	68	void (irq_handler)(struct irq_desc desc);
	69	};
	70
bc866fc7	71	struct pm_irq_chip {
e7b81fca	72	struct regmap *regmap;
bc866fc7	73	spinlock_t pm_irq_lock;
dc1a95cc	74	struct irq_domain *irqdomain;
bc866fc7 SB	75	unsigned int num_blocks;
bc866fc7 SB	76	unsigned int num_masters;
3324a7c1 BM	77	const struct pm_irq_data *pm_irq_data;
3324a7c1 BM	78	/* MUST BE AT THE END OF THIS STRUCT */
7235d9e4	79	u8 config[];
bc866fc7 SB	80	};
bc866fc7 SB	81
e7b81fca SB	82	static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp,
e7b81fca SB	83	unsigned int *ip)
bc866fc7 SB	84	{
	85	int rc;
	86
	87	spin_lock(&chip->pm_irq_lock);
e7b81fca	88	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
bc866fc7 SB	89	if (rc) {
	90	pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
	91	goto bail;
	92	}
	93
e7b81fca	94	rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
bc866fc7 SB	95	if (rc)
	96	pr_err("Failed Reading Status rc=%d\n", rc);
	97	bail:
	98	spin_unlock(&chip->pm_irq_lock);
	99	return rc;
	100	}
	101
e7b81fca SB	102	static int
e7b81fca SB	103	pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp)
bc866fc7 SB	104	{
	105	int rc;
	106
	107	spin_lock(&chip->pm_irq_lock);
e7b81fca	108	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
bc866fc7 SB	109	if (rc) {
	110	pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
	111	goto bail;
	112	}
	113
	114	cp \|= PM_IRQF_WRITE;
e7b81fca	115	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp);
bc866fc7 SB	116	if (rc)
	117	pr_err("Failed Configuring IRQ rc=%d\n", rc);
	118	bail:
	119	spin_unlock(&chip->pm_irq_lock);
	120	return rc;
	121	}
	122
	123	static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
	124	{
3b0cccef	125	int pmirq, i, ret = 0;
e7b81fca	126	unsigned int bits;
bc866fc7 SB	127
	128	ret = pm8xxx_read_block_irq(chip, block, &bits);
	129	if (ret) {
	130	pr_err("Failed reading %d block ret=%d", block, ret);
	131	return ret;
	132	}
	133	if (!bits) {
	134	pr_err("block bit set in master but no irqs: %d", block);
	135	return 0;
	136	}
	137
	138	/* Check IRQ bits */
	139	for (i = 0; i < 8; i++) {
	140	if (bits & (1 << i)) {
	141	pmirq = block * 8 + i;
3b0cccef	142	generic_handle_domain_irq(chip->irqdomain, pmirq);
bc866fc7 SB	143	}
	144	}
	145	return 0;
	146	}
	147
	148	static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
	149	{
e7b81fca	150	unsigned int blockbits;
bc866fc7 SB	151	int block_number, i, ret = 0;
bc866fc7 SB	152
e7b81fca SB	153	ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master,
e7b81fca SB	154	&blockbits);
bc866fc7 SB	155	if (ret) {
	156	pr_err("Failed to read master %d ret=%d\n", master, ret);
	157	return ret;
	158	}
	159	if (!blockbits) {
	160	pr_err("master bit set in root but no blocks: %d", master);
	161	return 0;
	162	}
	163
	164	for (i = 0; i < 8; i++)
	165	if (blockbits & (1 << i)) {
	166	block_number = master * 8 + i; /* block # */
	167	ret \|= pm8xxx_irq_block_handler(chip, block_number);
	168	}
	169	return ret;
	170	}
	171
bd0b9ac4	172	static void pm8xxx_irq_handler(struct irq_desc *desc)
bc866fc7 SB	173	{
	174	struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
	175	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
e7b81fca	176	unsigned int root;
bc866fc7 SB	177	int i, ret, masters = 0;
bc866fc7 SB	178
cced3548 SB	179	chained_irq_enter(irq_chip, desc);
cced3548 SB	180
e7b81fca	181	ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root);
bc866fc7 SB	182	if (ret) {
	183	pr_err("Can't read root status ret=%d\n", ret);
	184	return;
	185	}
	186
	187	/* on pm8xxx series masters start from bit 1 of the root */
	188	masters = root >> 1;
	189
	190	/* Read allowed masters for blocks. */
	191	for (i = 0; i < chip->num_masters; i++)
	192	if (masters & (1 << i))
	193	pm8xxx_irq_master_handler(chip, i);
	194
cced3548	195	chained_irq_exit(irq_chip, desc);
bc866fc7 SB	196	}
bc866fc7 SB	197
953f432b SK	198	static void pm8821_irq_block_handler(struct pm_irq_chip *chip,
	199	int master, int block)
	200	{
3b0cccef	201	int pmirq, i, ret;
953f432b SK	202	unsigned int bits;
	203
	204	ret = regmap_read(chip->regmap,
	205	PM8821_SSBI_ADDR_IRQ_ROOT(master, block), &bits);
	206	if (ret) {
	207	pr_err("Reading block %d failed ret=%d", block, ret);
	208	return;
	209	}
	210
	211	/* Convert block offset to global block number */
	212	block += (master * PM8821_BLOCKS_PER_MASTER) - 1;
	213
	214	/* Check IRQ bits */
	215	for (i = 0; i < 8; i++) {
	216	if (bits & BIT(i)) {
	217	pmirq = block * 8 + i;
3b0cccef	218	generic_handle_domain_irq(chip->irqdomain, pmirq);
953f432b SK	219	}
	220	}
	221	}
	222
	223	static inline void pm8821_irq_master_handler(struct pm_irq_chip *chip,
	224	int master, u8 master_val)
	225	{
	226	int block;
	227
	228	for (block = 1; block < 8; block++)
	229	if (master_val & BIT(block))
	230	pm8821_irq_block_handler(chip, master, block);
	231	}
	232
	233	static void pm8821_irq_handler(struct irq_desc *desc)
	234	{
	235	struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
	236	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
	237	unsigned int master;
	238	int ret;
	239
	240	chained_irq_enter(irq_chip, desc);
	241	ret = regmap_read(chip->regmap,
	242	PM8821_SSBI_REG_ADDR_IRQ_MASTER0, &master);
	243	if (ret) {
	244	pr_err("Failed to read master 0 ret=%d\n", ret);
	245	goto done;
	246	}
	247
	248	/* bits 1 through 7 marks the first 7 blocks in master 0 */
	249	if (master & GENMASK(7, 1))
	250	pm8821_irq_master_handler(chip, 0, master);
	251
	252	/* bit 0 marks if master 1 contains any bits */
	253	if (!(master & BIT(0)))
	254	goto done;
	255
	256	ret = regmap_read(chip->regmap,
	257	PM8821_SSBI_REG_ADDR_IRQ_MASTER1, &master);
	258	if (ret) {
	259	pr_err("Failed to read master 1 ret=%d\n", ret);
	260	goto done;
	261	}
	262
	263	pm8821_irq_master_handler(chip, 1, master);
	264
	265	done:
	266	chained_irq_exit(irq_chip, desc);
	267	}
	268
bc866fc7 SB	269	static void pm8xxx_irq_mask_ack(struct irq_data *d)
	270	{
	271	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
dc1a95cc	272	unsigned int pmirq = irqd_to_hwirq(d);
bc866fc7 SB	273	u8 block, config;
	274
	275	block = pmirq / 8;
bc866fc7 SB	276
	277	config = chip->config[pmirq] \| PM_IRQF_MASK_ALL \| PM_IRQF_CLR;
	278	pm8xxx_config_irq(chip, block, config);
	279	}
	280
	281	static void pm8xxx_irq_unmask(struct irq_data *d)
	282	{
	283	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
dc1a95cc	284	unsigned int pmirq = irqd_to_hwirq(d);
bc866fc7 SB	285	u8 block, config;
	286
	287	block = pmirq / 8;
bc866fc7 SB	288
	289	config = chip->config[pmirq];
	290	pm8xxx_config_irq(chip, block, config);
	291	}
	292
	293	static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
	294	{
	295	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
dc1a95cc SB	296	unsigned int pmirq = irqd_to_hwirq(d);
dc1a95cc SB	297	int irq_bit;
bc866fc7 SB	298	u8 block, config;
	299
	300	block = pmirq / 8;
bc866fc7 SB	301	irq_bit = pmirq % 8;
	302
	303	chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
	304	\| PM_IRQF_MASK_ALL;
	305	if (flow_type & (IRQF_TRIGGER_RISING \| IRQF_TRIGGER_FALLING)) {
	306	if (flow_type & IRQF_TRIGGER_RISING)
	307	chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
	308	if (flow_type & IRQF_TRIGGER_FALLING)
	309	chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
	310	} else {
	311	chip->config[pmirq] \|= PM_IRQF_LVL_SEL;
	312
	313	if (flow_type & IRQF_TRIGGER_HIGH)
	314	chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
	315	else
	316	chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
	317	}
	318
	319	config = chip->config[pmirq] \| PM_IRQF_CLR;
	320	return pm8xxx_config_irq(chip, block, config);
	321	}
	322
f1837e4a BA	323	static int pm8xxx_irq_get_irqchip_state(struct irq_data *d,
	324	enum irqchip_irq_state which,
	325	bool *state)
	326	{
	327	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	328	unsigned int pmirq = irqd_to_hwirq(d);
	329	unsigned int bits;
	330	int irq_bit;
	331	u8 block;
	332	int rc;
	333
	334	if (which != IRQCHIP_STATE_LINE_LEVEL)
	335	return -EINVAL;
	336
	337	block = pmirq / 8;
	338	irq_bit = pmirq % 8;
	339
	340	spin_lock(&chip->pm_irq_lock);
	341	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
	342	if (rc) {
	343	pr_err("Failed Selecting Block %d rc=%d\n", block, rc);
	344	goto bail;
	345	}
	346
	347	rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
	348	if (rc) {
	349	pr_err("Failed Reading Status rc=%d\n", rc);
	350	goto bail;
	351	}
	352
	353	*state = !!(bits & BIT(irq_bit));
	354	bail:
	355	spin_unlock(&chip->pm_irq_lock);
	356
	357	return rc;
	358	}
	359
bc866fc7 SB	360	static struct irq_chip pm8xxx_irq_chip = {
	361	.name = "pm8xxx",
	362	.irq_mask_ack = pm8xxx_irq_mask_ack,
	363	.irq_unmask = pm8xxx_irq_unmask,
	364	.irq_set_type = pm8xxx_irq_set_type,
f1837e4a	365	.irq_get_irqchip_state = pm8xxx_irq_get_irqchip_state,
d2d24ad1	366	.flags = IRQCHIP_MASK_ON_SUSPEND \| IRQCHIP_SKIP_SET_WAKE,
bc866fc7 SB	367	};
bc866fc7 SB	368
3324a7c1 BM	369	static void pm8xxx_irq_domain_map(struct pm_irq_chip *chip,
	370	struct irq_domain *domain, unsigned int irq,
	371	irq_hw_number_t hwirq, unsigned int type)
dc1a95cc	372	{
3324a7c1 BM	373	irq_domain_set_info(domain, irq, hwirq, chip->pm_irq_data->irq_chip,
3324a7c1 BM	374	chip, handle_level_irq, NULL, NULL);
dc1a95cc	375	irq_set_noprobe(irq);
3324a7c1 BM	376	}
	377
	378	static int pm8xxx_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
	379	unsigned int nr_irqs, void *data)
	380	{
	381	struct pm_irq_chip *chip = domain->host_data;
	382	struct irq_fwspec *fwspec = data;
	383	irq_hw_number_t hwirq;
	384	unsigned int type;
	385	int ret, i;
	386
	387	ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
	388	if (ret)
	389	return ret;
	390
	391	for (i = 0; i < nr_irqs; i++)
	392	pm8xxx_irq_domain_map(chip, domain, virq + i, hwirq + i, type);
9bd09f34	393
bc866fc7 SB	394	return 0;
	395	}
	396
dc1a95cc	397	static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
3324a7c1 BM	398	.alloc = pm8xxx_irq_domain_alloc,
	399	.free = irq_domain_free_irqs_common,
	400	.translate = irq_domain_translate_twocell,
dc1a95cc SB	401	};
dc1a95cc SB	402
953f432b SK	403	static void pm8821_irq_mask_ack(struct irq_data *d)
	404	{
	405	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	406	unsigned int pmirq = irqd_to_hwirq(d);
	407	u8 block, master;
	408	int irq_bit, rc;
	409
	410	block = pmirq / 8;
	411	master = block / PM8821_BLOCKS_PER_MASTER;
	412	irq_bit = pmirq % 8;
	413	block %= PM8821_BLOCKS_PER_MASTER;
	414
	415	rc = regmap_update_bits(chip->regmap,
	416	PM8821_SSBI_ADDR_IRQ_MASK(master, block),
	417	BIT(irq_bit), BIT(irq_bit));
	418	if (rc) {
	419	pr_err("Failed to mask IRQ:%d rc=%d\n", pmirq, rc);
	420	return;
	421	}
	422
	423	rc = regmap_update_bits(chip->regmap,
	424	PM8821_SSBI_ADDR_IRQ_CLEAR(master, block),
	425	BIT(irq_bit), BIT(irq_bit));
	426	if (rc)
	427	pr_err("Failed to CLEAR IRQ:%d rc=%d\n", pmirq, rc);
	428	}
	429
	430	static void pm8821_irq_unmask(struct irq_data *d)
	431	{
	432	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	433	unsigned int pmirq = irqd_to_hwirq(d);
	434	int irq_bit, rc;
	435	u8 block, master;
	436
	437	block = pmirq / 8;
	438	master = block / PM8821_BLOCKS_PER_MASTER;
	439	irq_bit = pmirq % 8;
	440	block %= PM8821_BLOCKS_PER_MASTER;
	441
	442	rc = regmap_update_bits(chip->regmap,
	443	PM8821_SSBI_ADDR_IRQ_MASK(master, block),
	444	BIT(irq_bit), ~BIT(irq_bit));
	445	if (rc)
	446	pr_err("Failed to read/write unmask IRQ:%d rc=%d\n", pmirq, rc);
	447
	448	}
	449
	450	static int pm8821_irq_get_irqchip_state(struct irq_data *d,
	451	enum irqchip_irq_state which,
	452	bool *state)
	453	{
	454	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	455	int rc, pmirq = irqd_to_hwirq(d);
	456	u8 block, irq_bit, master;
	457	unsigned int bits;
	458
	459	block = pmirq / 8;
	460	master = block / PM8821_BLOCKS_PER_MASTER;
	461	irq_bit = pmirq % 8;
	462	block %= PM8821_BLOCKS_PER_MASTER;
	463
	464	rc = regmap_read(chip->regmap,
	465	PM8821_SSBI_ADDR_IRQ_RT_STATUS(master, block), &bits);
	466	if (rc) {
467	pr_err("Reading Status of IRQ %d failed rc=%d\n", pmirq, rc);
468	return rc;
469	}
470
471	*state = !!(bits & BIT(irq_bit));
472
473	return rc;
474	}
475
476	static struct irq_chip pm8821_irq_chip = {
477	.name = "pm8821",
478	.irq_mask_ack = pm8821_irq_mask_ack,
479	.irq_unmask = pm8821_irq_unmask,
480	.irq_get_irqchip_state = pm8821_irq_get_irqchip_state,
481	.flags = IRQCHIP_MASK_ON_SUSPEND \| IRQCHIP_SKIP_SET_WAKE,
482	};
483
e7b81fca SB	484	static const struct regmap_config ssbi_regmap_config = {
	485	.reg_bits = 16,
	486	.val_bits = 8,
	487	.max_register = 0x3ff,
	488	.fast_io = true,
	489	.reg_read = ssbi_reg_read,
	490	.reg_write = ssbi_reg_write
	491	};
	492
953f432b SK	493	static const struct pm_irq_data pm8xxx_data = {
953f432b SK	494	.num_irqs = PM8XXX_NR_IRQS,
3324a7c1	495	.irq_chip = &pm8xxx_irq_chip,
953f432b SK	496	.irq_handler = pm8xxx_irq_handler,
	497	};
	498
	499	static const struct pm_irq_data pm8821_data = {
	500	.num_irqs = PM8821_NR_IRQS,
3324a7c1	501	.irq_chip = &pm8821_irq_chip,
953f432b SK	502	.irq_handler = pm8821_irq_handler,
	503	};
	504
40a3a0f2	505	static const struct of_device_id pm8xxx_id_table[] = {
953f432b SK	506	{ .compatible = "qcom,pm8018", .data = &pm8xxx_data},
	507	{ .compatible = "qcom,pm8058", .data = &pm8xxx_data},
	508	{ .compatible = "qcom,pm8821", .data = &pm8821_data},
	509	{ .compatible = "qcom,pm8921", .data = &pm8xxx_data},
c5865a53 SB	510	{ }
c5865a53 SB	511	};
40a3a0f2	512	MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
c5865a53	513
40a3a0f2	514	static int pm8xxx_probe(struct platform_device *pdev)
cbdb53e1	515	{
953f432b	516	const struct pm_irq_data *data;
e7b81fca	517	struct regmap *regmap;
202f7680	518	int irq, rc;
e7b81fca	519	unsigned int val;
c013f0a5	520	u32 rev;
dc1a95cc	521	struct pm_irq_chip *chip;
953f432b SK	522
	523	data = of_device_get_match_data(&pdev->dev);
	524	if (!data) {
	525	dev_err(&pdev->dev, "No matching driver data found\n");
	526	return -EINVAL;
	527	}
cbdb53e1	528
dc1a95cc SB	529	irq = platform_get_irq(pdev, 0);
	530	if (irq < 0)
	531	return irq;
cbdb53e1	532
e7b81fca SB	533	regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent,
	534	&ssbi_regmap_config);
	535	if (IS_ERR(regmap))
	536	return PTR_ERR(regmap);
	537
cbdb53e1	538	/* Read PMIC chip revision */
e7b81fca	539	rc = regmap_read(regmap, REG_HWREV, &val);
cbdb53e1 AD	540	if (rc) {
cbdb53e1 AD	541	pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
b2cdcfac	542	return rc;
cbdb53e1 AD	543	}
cbdb53e1 AD	544	pr_info("PMIC revision 1: %02X\n", val);
c013f0a5	545	rev = val;
cbdb53e1 AD	546
cbdb53e1 AD	547	/* Read PMIC chip revision 2 */
e7b81fca	548	rc = regmap_read(regmap, REG_HWREV_2, &val);
cbdb53e1 AD	549	if (rc) {
	550	pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
	551	REG_HWREV_2, rc);
b2cdcfac	552	return rc;
cbdb53e1 AD	553	}
cbdb53e1 AD	554	pr_info("PMIC revision 2: %02X\n", val);
c013f0a5	555	rev \|= val << BITS_PER_BYTE;
cbdb53e1	556
0ed2dd03 KC	557	chip = devm_kzalloc(&pdev->dev,
0ed2dd03 KC	558	struct_size(chip, config, data->num_irqs),
953f432b	559	GFP_KERNEL);
dc1a95cc SB	560	if (!chip)
	561	return -ENOMEM;
	562
3e87933a	563	platform_set_drvdata(pdev, chip);
e7b81fca	564	chip->regmap = regmap;
3324a7c1	565	chip->num_blocks = DIV_ROUND_UP(data->num_irqs, 8);
dc1a95cc	566	chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
3324a7c1	567	chip->pm_irq_data = data;
dc1a95cc SB	568	spin_lock_init(&chip->pm_irq_lock);
dc1a95cc SB	569
953f432b SK	570	chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
953f432b SK	571	data->num_irqs,
3324a7c1	572	&pm8xxx_irq_domain_ops,
dc1a95cc SB	573	chip);
	574	if (!chip->irqdomain)
	575	return -ENODEV;
	576
953f432b	577	irq_set_chained_handler_and_data(irq, data->irq_handler, chip);
dc1a95cc SB	578	irq_set_irq_wake(irq, 1);
	579
	580	rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
c013f0a5	581	if (rc) {
b79f0438	582	irq_set_chained_handler_and_data(irq, NULL, NULL);
dc1a95cc	583	irq_domain_remove(chip->irqdomain);
c013f0a5 AD	584	}
c013f0a5 AD	585
dc1a95cc SB	586	return rc;
dc1a95cc SB	587	}
c013f0a5	588
40a3a0f2	589	static int pm8xxx_remove_child(struct device dev, void unused)
dc1a95cc SB	590	{
dc1a95cc SB	591	platform_device_unregister(to_platform_device(dev));
cbdb53e1	592	return 0;
cbdb53e1 AD	593	}
cbdb53e1 AD	594
40a3a0f2	595	static int pm8xxx_remove(struct platform_device *pdev)
cbdb53e1	596	{
dc1a95cc	597	int irq = platform_get_irq(pdev, 0);
3e87933a	598	struct pm_irq_chip *chip = platform_get_drvdata(pdev);
dc1a95cc	599
40a3a0f2	600	device_for_each_child(&pdev->dev, NULL, pm8xxx_remove_child);
b79f0438	601	irq_set_chained_handler_and_data(irq, NULL, NULL);
dc1a95cc	602	irq_domain_remove(chip->irqdomain);
cbdb53e1 AD	603
	604	return 0;
	605	}
	606
40a3a0f2 LW	607	static struct platform_driver pm8xxx_driver = {
	608	.probe = pm8xxx_probe,
	609	.remove = pm8xxx_remove,
cbdb53e1	610	.driver = {
40a3a0f2 LW	611	.name = "pm8xxx-core",
40a3a0f2 LW	612	.of_match_table = pm8xxx_id_table,
cbdb53e1 AD	613	},
	614	};
	615
40a3a0f2	616	static int __init pm8xxx_init(void)
cbdb53e1	617	{
40a3a0f2	618	return platform_driver_register(&pm8xxx_driver);
cbdb53e1	619	}
40a3a0f2	620	subsys_initcall(pm8xxx_init);
cbdb53e1	621
40a3a0f2	622	static void __exit pm8xxx_exit(void)
cbdb53e1	623	{
40a3a0f2	624	platform_driver_unregister(&pm8xxx_driver);
cbdb53e1	625	}
40a3a0f2	626	module_exit(pm8xxx_exit);
cbdb53e1 AD	627
cbdb53e1 AD	628	MODULE_LICENSE("GPL v2");
40a3a0f2	629	MODULE_DESCRIPTION("PMIC 8xxx core driver");
cbdb53e1	630	MODULE_VERSION("1.0");
40a3a0f2	631	MODULE_ALIAS("platform:pm8xxx-core");