[mirror_ubuntu-jammy-kernel.git] / drivers / mfd / rc5t583.c

/*
 * Core driver access RC5T583 power management chip.
 *
 * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
 * Author: Laxman dewangan <ldewangan@nvidia.com>
 *
 * Based on code
 *	Copyright (C) 2011 RICOH COMPANY,LTD
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 */
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/mfd/core.h>
#include <linux/mfd/rc5t583.h>
#include <linux/regmap.h>

#define RICOH_ONOFFSEL_REG	0x10
#define RICOH_SWCTL_REG		0x5E

struct deepsleep_control_data {
	u8 reg_add;
	u8 ds_pos_bit;
};

#define DEEPSLEEP_INIT(_id, _reg, _pos)		\
	{					\
		.reg_add = RC5T583_##_reg,	\
		.ds_pos_bit = _pos,		\
	}

static struct deepsleep_control_data deepsleep_data[] = {
	DEEPSLEEP_INIT(DC0, SLPSEQ1, 0),
	DEEPSLEEP_INIT(DC1, SLPSEQ1, 4),
	DEEPSLEEP_INIT(DC2, SLPSEQ2, 0),
	DEEPSLEEP_INIT(DC3, SLPSEQ2, 4),
	DEEPSLEEP_INIT(LDO0, SLPSEQ3, 0),
	DEEPSLEEP_INIT(LDO1, SLPSEQ3, 4),
	DEEPSLEEP_INIT(LDO2, SLPSEQ4, 0),
	DEEPSLEEP_INIT(LDO3, SLPSEQ4, 4),
	DEEPSLEEP_INIT(LDO4, SLPSEQ5, 0),
	DEEPSLEEP_INIT(LDO5, SLPSEQ5, 4),
	DEEPSLEEP_INIT(LDO6, SLPSEQ6, 0),
	DEEPSLEEP_INIT(LDO7, SLPSEQ6, 4),
	DEEPSLEEP_INIT(LDO8, SLPSEQ7, 0),
	DEEPSLEEP_INIT(LDO9, SLPSEQ7, 4),
	DEEPSLEEP_INIT(PSO0, SLPSEQ8, 0),
	DEEPSLEEP_INIT(PSO1, SLPSEQ8, 4),
	DEEPSLEEP_INIT(PSO2, SLPSEQ9, 0),
	DEEPSLEEP_INIT(PSO3, SLPSEQ9, 4),
	DEEPSLEEP_INIT(PSO4, SLPSEQ10, 0),
	DEEPSLEEP_INIT(PSO5, SLPSEQ10, 4),
	DEEPSLEEP_INIT(PSO6, SLPSEQ11, 0),
	DEEPSLEEP_INIT(PSO7, SLPSEQ11, 4),
};

#define EXT_PWR_REQ		\
	(RC5T583_EXT_PWRREQ1_CONTROL | RC5T583_EXT_PWRREQ2_CONTROL)

static const struct mfd_cell rc5t583_subdevs[] = {
	{.name = "rc5t583-gpio",},
	{.name = "rc5t583-regulator",},
	{.name = "rc5t583-rtc",      },
	{.name = "rc5t583-key",      }
};

static int __rc5t583_set_ext_pwrreq1_control(struct device *dev,
	int id, int ext_pwr, int slots)
{
	int ret;
	uint8_t sleepseq_val = 0;
	unsigned int en_bit;
	unsigned int slot_bit;

	if (id == RC5T583_DS_DC0) {
		dev_err(dev, "PWRREQ1 is invalid control for rail %d\n", id);
		return -EINVAL;
	}

	en_bit = deepsleep_data[id].ds_pos_bit;
	slot_bit = en_bit + 1;
	ret = rc5t583_read(dev, deepsleep_data[id].reg_add, &sleepseq_val);
	if (ret < 0) {
		dev_err(dev, "Error in reading reg 0x%x\n",
				deepsleep_data[id].reg_add);
		return ret;
	}

	sleepseq_val &= ~(0xF << en_bit);
	sleepseq_val |= BIT(en_bit);
	sleepseq_val |= ((slots & 0x7) << slot_bit);
	ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(1));
	if (ret < 0) {
		dev_err(dev, "Error in updating the 0x%02x register\n",
				RICOH_ONOFFSEL_REG);
		return ret;
	}

	ret = rc5t583_write(dev, deepsleep_data[id].reg_add, sleepseq_val);
	if (ret < 0) {
		dev_err(dev, "Error in writing reg 0x%x\n",
				deepsleep_data[id].reg_add);
		return ret;
	}

	if (id == RC5T583_DS_LDO4) {
		ret = rc5t583_write(dev, RICOH_SWCTL_REG, 0x1);
		if (ret < 0)
			dev_err(dev, "Error in writing reg 0x%x\n",
				RICOH_SWCTL_REG);
	}
	return ret;
}

static int __rc5t583_set_ext_pwrreq2_control(struct device *dev,
	int id, int ext_pwr)
{
	int ret;

	if (id != RC5T583_DS_DC0) {
		dev_err(dev, "PWRREQ2 is invalid control for rail %d\n", id);
		return -EINVAL;
	}

	ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(2));
	if (ret < 0)
		dev_err(dev, "Error in updating the ONOFFSEL 0x10 register\n");
	return ret;
}

int rc5t583_ext_power_req_config(struct device *dev, int ds_id,
	int ext_pwr_req, int deepsleep_slot_nr)
{
	if ((ext_pwr_req & EXT_PWR_REQ) == EXT_PWR_REQ)
		return -EINVAL;

	if (ext_pwr_req & RC5T583_EXT_PWRREQ1_CONTROL)
		return __rc5t583_set_ext_pwrreq1_control(dev, ds_id,
				ext_pwr_req, deepsleep_slot_nr);

	if (ext_pwr_req & RC5T583_EXT_PWRREQ2_CONTROL)
		return __rc5t583_set_ext_pwrreq2_control(dev,
			ds_id, ext_pwr_req);
	return 0;
}
EXPORT_SYMBOL(rc5t583_ext_power_req_config);

static int rc5t583_clear_ext_power_req(struct rc5t583 *rc5t583,
	struct rc5t583_platform_data *pdata)
{
	int ret;
	int i;
	uint8_t on_off_val = 0;

	/*  Clear ONOFFSEL register */
	if (pdata->enable_shutdown)
		on_off_val = 0x1;

	ret = rc5t583_write(rc5t583->dev, RICOH_ONOFFSEL_REG, on_off_val);
	if (ret < 0)
		dev_warn(rc5t583->dev, "Error in writing reg %d error: %d\n",
					RICOH_ONOFFSEL_REG, ret);

	ret = rc5t583_write(rc5t583->dev, RICOH_SWCTL_REG, 0x0);
	if (ret < 0)
		dev_warn(rc5t583->dev, "Error in writing reg %d error: %d\n",
					RICOH_SWCTL_REG, ret);

	/* Clear sleep sequence register */
	for (i = RC5T583_SLPSEQ1; i <= RC5T583_SLPSEQ11; ++i) {
		ret = rc5t583_write(rc5t583->dev, i, 0x0);
		if (ret < 0)
			dev_warn(rc5t583->dev,
				"Error in writing reg 0x%02x error: %d\n",
				i, ret);
	}
	return 0;
}

static bool volatile_reg(struct device *dev, unsigned int reg)
{
	/* Enable caching in interrupt registers */
	switch (reg) {
	case RC5T583_INT_EN_SYS1:
	case RC5T583_INT_EN_SYS2:
	case RC5T583_INT_EN_DCDC:
	case RC5T583_INT_EN_RTC:
	case RC5T583_INT_EN_ADC1:
	case RC5T583_INT_EN_ADC2:
	case RC5T583_INT_EN_ADC3:
	case RC5T583_GPIO_GPEDGE1:
	case RC5T583_GPIO_GPEDGE2:
	case RC5T583_GPIO_EN_INT:
		return false;

	case RC5T583_GPIO_MON_IOIN:
		/* This is gpio input register */
		return true;

	default:
		/* Enable caching in gpio registers */
		if ((reg >= RC5T583_GPIO_IOSEL) &&
				(reg <= RC5T583_GPIO_GPOFUNC))
			return false;

		/* Enable caching in sleep seq registers */
		if ((reg >= RC5T583_SLPSEQ1) && (reg <= RC5T583_SLPSEQ11))
			return false;

		/* Enable caching of regulator registers */
		if ((reg >= RC5T583_REG_DC0CTL) && (reg <= RC5T583_REG_SR3CTL))
			return false;
		if ((reg >= RC5T583_REG_LDOEN1) &&
					(reg <= RC5T583_REG_LDO9DAC_DS))
			return false;

		break;
	}

	return true;
}

static const struct regmap_config rc5t583_regmap_config = {
	.reg_bits = 8,
	.val_bits = 8,
	.volatile_reg = volatile_reg,
	.max_register = RC5T583_MAX_REG,
	.num_reg_defaults_raw = RC5T583_NUM_REGS,
	.cache_type = REGCACHE_RBTREE,
};

static int rc5t583_i2c_probe(struct i2c_client *i2c,
			      const struct i2c_device_id *id)
{
	struct rc5t583 *rc5t583;
	struct rc5t583_platform_data *pdata = dev_get_platdata(&i2c->dev);
	int ret;

	if (!pdata) {
		dev_err(&i2c->dev, "Err: Platform data not found\n");
		return -EINVAL;
	}

	rc5t583 = devm_kzalloc(&i2c->dev, sizeof(*rc5t583), GFP_KERNEL);
	if (!rc5t583)
		return -ENOMEM;

	rc5t583->dev = &i2c->dev;
	i2c_set_clientdata(i2c, rc5t583);

	rc5t583->regmap = devm_regmap_init_i2c(i2c, &rc5t583_regmap_config);
	if (IS_ERR(rc5t583->regmap)) {
		ret = PTR_ERR(rc5t583->regmap);
		dev_err(&i2c->dev, "regmap initialization failed: %d\n", ret);
		return ret;
	}

	ret = rc5t583_clear_ext_power_req(rc5t583, pdata);
	if (ret < 0)
		return ret;

	if (i2c->irq) {
		ret = rc5t583_irq_init(rc5t583, i2c->irq, pdata->irq_base);
		/* Still continue with warning, if irq init fails */
		if (ret)
			dev_warn(&i2c->dev, "IRQ init failed: %d\n", ret);
	}

	ret = devm_mfd_add_devices(rc5t583->dev, -1, rc5t583_subdevs,
				   ARRAY_SIZE(rc5t583_subdevs), NULL, 0, NULL);
	if (ret) {
		dev_err(&i2c->dev, "add mfd devices failed: %d\n", ret);
		return ret;
	}

	return 0;
}

static const struct i2c_device_id rc5t583_i2c_id[] = {
	{.name = "rc5t583", .driver_data = 0},
	{}
};

static struct i2c_driver rc5t583_i2c_driver = {
	.driver = {
		   .name = "rc5t583",
		   },
	.probe = rc5t583_i2c_probe,
	.id_table = rc5t583_i2c_id,
};

static int __init rc5t583_i2c_init(void)
{
	return i2c_add_driver(&rc5t583_i2c_driver);
}
subsys_initcall(rc5t583_i2c_init);
Commit	Line	Data
1b1247dd LD	1	/*
	2	* Core driver access RC5T583 power management chip.
	3	*
	4	* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
	5	* Author: Laxman dewangan <ldewangan@nvidia.com>
	6	*
	7	* Based on code
	8	* Copyright (C) 2011 RICOH COMPANY,LTD
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms and conditions of the GNU General Public License,
	12	* version 2, as published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope it will be useful, but WITHOUT
	15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	17	* more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	21	*
	22	*/
	23	#include <linux/interrupt.h>
	24	#include <linux/irq.h>
	25	#include <linux/kernel.h>
1b1247dd LD	26	#include <linux/init.h>
	27	#include <linux/err.h>
	28	#include <linux/slab.h>
	29	#include <linux/i2c.h>
	30	#include <linux/mfd/core.h>
	31	#include <linux/mfd/rc5t583.h>
	32	#include <linux/regmap.h>
	33
	34	#define RICOH_ONOFFSEL_REG 0x10
	35	#define RICOH_SWCTL_REG 0x5E
	36
	37	struct deepsleep_control_data {
	38	u8 reg_add;
	39	u8 ds_pos_bit;
	40	};
	41
	42	#define DEEPSLEEP_INIT(_id, _reg, _pos) \
	43	{ \
	44	.reg_add = RC5T583_##_reg, \
	45	.ds_pos_bit = _pos, \
	46	}
	47
	48	static struct deepsleep_control_data deepsleep_data[] = {
	49	DEEPSLEEP_INIT(DC0, SLPSEQ1, 0),
	50	DEEPSLEEP_INIT(DC1, SLPSEQ1, 4),
	51	DEEPSLEEP_INIT(DC2, SLPSEQ2, 0),
	52	DEEPSLEEP_INIT(DC3, SLPSEQ2, 4),
	53	DEEPSLEEP_INIT(LDO0, SLPSEQ3, 0),
	54	DEEPSLEEP_INIT(LDO1, SLPSEQ3, 4),
	55	DEEPSLEEP_INIT(LDO2, SLPSEQ4, 0),
	56	DEEPSLEEP_INIT(LDO3, SLPSEQ4, 4),
	57	DEEPSLEEP_INIT(LDO4, SLPSEQ5, 0),
	58	DEEPSLEEP_INIT(LDO5, SLPSEQ5, 4),
	59	DEEPSLEEP_INIT(LDO6, SLPSEQ6, 0),
	60	DEEPSLEEP_INIT(LDO7, SLPSEQ6, 4),
	61	DEEPSLEEP_INIT(LDO8, SLPSEQ7, 0),
	62	DEEPSLEEP_INIT(LDO9, SLPSEQ7, 4),
	63	DEEPSLEEP_INIT(PSO0, SLPSEQ8, 0),
	64	DEEPSLEEP_INIT(PSO1, SLPSEQ8, 4),
	65	DEEPSLEEP_INIT(PSO2, SLPSEQ9, 0),
	66	DEEPSLEEP_INIT(PSO3, SLPSEQ9, 4),
	67	DEEPSLEEP_INIT(PSO4, SLPSEQ10, 0),
	68	DEEPSLEEP_INIT(PSO5, SLPSEQ10, 4),
	69	DEEPSLEEP_INIT(PSO6, SLPSEQ11, 0),
	70	DEEPSLEEP_INIT(PSO7, SLPSEQ11, 4),
	71	};
	72
	73	#define EXT_PWR_REQ \
	74	(RC5T583_EXT_PWRREQ1_CONTROL \| RC5T583_EXT_PWRREQ2_CONTROL)
	75
5ac98553	76	static const struct mfd_cell rc5t583_subdevs[] = {
e1277f45	77	{.name = "rc5t583-gpio",},
1b1247dd LD	78	{.name = "rc5t583-regulator",},
	79	{.name = "rc5t583-rtc", },
	80	{.name = "rc5t583-key", }
	81	};
	82
1b1247dd LD	83	static int __rc5t583_set_ext_pwrreq1_control(struct device *dev,
	84	int id, int ext_pwr, int slots)
	85	{
	86	int ret;
0dd96360	87	uint8_t sleepseq_val = 0;
1b1247dd LD	88	unsigned int en_bit;
	89	unsigned int slot_bit;
	90
	91	if (id == RC5T583_DS_DC0) {
	92	dev_err(dev, "PWRREQ1 is invalid control for rail %d\n", id);
	93	return -EINVAL;
	94	}
	95
	96	en_bit = deepsleep_data[id].ds_pos_bit;
	97	slot_bit = en_bit + 1;
	98	ret = rc5t583_read(dev, deepsleep_data[id].reg_add, &sleepseq_val);
	99	if (ret < 0) {
	100	dev_err(dev, "Error in reading reg 0x%x\n",
	101	deepsleep_data[id].reg_add);
	102	return ret;
	103	}
	104
	105	sleepseq_val &= ~(0xF << en_bit);
	106	sleepseq_val \|= BIT(en_bit);
	107	sleepseq_val \|= ((slots & 0x7) << slot_bit);
	108	ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(1));
	109	if (ret < 0) {
	110	dev_err(dev, "Error in updating the 0x%02x register\n",
	111	RICOH_ONOFFSEL_REG);
	112	return ret;
	113	}
	114
	115	ret = rc5t583_write(dev, deepsleep_data[id].reg_add, sleepseq_val);
	116	if (ret < 0) {
	117	dev_err(dev, "Error in writing reg 0x%x\n",
	118	deepsleep_data[id].reg_add);
	119	return ret;
	120	}
	121
	122	if (id == RC5T583_DS_LDO4) {
	123	ret = rc5t583_write(dev, RICOH_SWCTL_REG, 0x1);
	124	if (ret < 0)
	125	dev_err(dev, "Error in writing reg 0x%x\n",
	126	RICOH_SWCTL_REG);
	127	}
	128	return ret;
	129	}
	130
	131	static int __rc5t583_set_ext_pwrreq2_control(struct device *dev,
	132	int id, int ext_pwr)
	133	{
	134	int ret;
	135
	136	if (id != RC5T583_DS_DC0) {
	137	dev_err(dev, "PWRREQ2 is invalid control for rail %d\n", id);
	138	return -EINVAL;
	139	}
	140
	141	ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(2));
	142	if (ret < 0)
	143	dev_err(dev, "Error in updating the ONOFFSEL 0x10 register\n");
	144	return ret;
	145	}
	146
	147	int rc5t583_ext_power_req_config(struct device *dev, int ds_id,
	148	int ext_pwr_req, int deepsleep_slot_nr)
	149	{
	150	if ((ext_pwr_req & EXT_PWR_REQ) == EXT_PWR_REQ)
	151	return -EINVAL;
152
153	if (ext_pwr_req & RC5T583_EXT_PWRREQ1_CONTROL)
154	return __rc5t583_set_ext_pwrreq1_control(dev, ds_id,
155	ext_pwr_req, deepsleep_slot_nr);
156
157	if (ext_pwr_req & RC5T583_EXT_PWRREQ2_CONTROL)
158	return __rc5t583_set_ext_pwrreq2_control(dev,
159	ds_id, ext_pwr_req);
160	return 0;
161	}
82ea267f	162	EXPORT_SYMBOL(rc5t583_ext_power_req_config);
1b1247dd LD	163
	164	static int rc5t583_clear_ext_power_req(struct rc5t583 *rc5t583,
	165	struct rc5t583_platform_data *pdata)
	166	{
	167	int ret;
	168	int i;
	169	uint8_t on_off_val = 0;
	170
	171	/* Clear ONOFFSEL register */
	172	if (pdata->enable_shutdown)
	173	on_off_val = 0x1;
	174
	175	ret = rc5t583_write(rc5t583->dev, RICOH_ONOFFSEL_REG, on_off_val);
	176	if (ret < 0)
	177	dev_warn(rc5t583->dev, "Error in writing reg %d error: %d\n",
	178	RICOH_ONOFFSEL_REG, ret);
	179
	180	ret = rc5t583_write(rc5t583->dev, RICOH_SWCTL_REG, 0x0);
	181	if (ret < 0)
	182	dev_warn(rc5t583->dev, "Error in writing reg %d error: %d\n",
	183	RICOH_SWCTL_REG, ret);
	184
	185	/* Clear sleep sequence register */
	186	for (i = RC5T583_SLPSEQ1; i <= RC5T583_SLPSEQ11; ++i) {
	187	ret = rc5t583_write(rc5t583->dev, i, 0x0);
	188	if (ret < 0)
	189	dev_warn(rc5t583->dev,
	190	"Error in writing reg 0x%02x error: %d\n",
	191	i, ret);
	192	}
	193	return 0;
	194	}
	195
	196	static bool volatile_reg(struct device *dev, unsigned int reg)
	197	{
	198	/* Enable caching in interrupt registers */
	199	switch (reg) {
	200	case RC5T583_INT_EN_SYS1:
	201	case RC5T583_INT_EN_SYS2:
	202	case RC5T583_INT_EN_DCDC:
	203	case RC5T583_INT_EN_RTC:
	204	case RC5T583_INT_EN_ADC1:
	205	case RC5T583_INT_EN_ADC2:
	206	case RC5T583_INT_EN_ADC3:
	207	case RC5T583_GPIO_GPEDGE1:
	208	case RC5T583_GPIO_GPEDGE2:
	209	case RC5T583_GPIO_EN_INT:
	210	return false;
	211
	212	case RC5T583_GPIO_MON_IOIN:
	213	/* This is gpio input register */
	214	return true;
	215
	216	default:
	217	/* Enable caching in gpio registers */
	218	if ((reg >= RC5T583_GPIO_IOSEL) &&
	219	(reg <= RC5T583_GPIO_GPOFUNC))
	220	return false;
	221
	222	/* Enable caching in sleep seq registers */
	223	if ((reg >= RC5T583_SLPSEQ1) && (reg <= RC5T583_SLPSEQ11))
	224	return false;
	225
	226	/* Enable caching of regulator registers */
227	if ((reg >= RC5T583_REG_DC0CTL) && (reg <= RC5T583_REG_SR3CTL))
228	return false;
229	if ((reg >= RC5T583_REG_LDOEN1) &&
230	(reg <= RC5T583_REG_LDO9DAC_DS))
231	return false;
232
233	break;
234	}
235
236	return true;
237	}
238
239	static const struct regmap_config rc5t583_regmap_config = {
240	.reg_bits = 8,
241	.val_bits = 8,
242	.volatile_reg = volatile_reg,
a862dc3e MS	243	.max_register = RC5T583_MAX_REG,
a862dc3e MS	244	.num_reg_defaults_raw = RC5T583_NUM_REGS,
1b1247dd LD	245	.cache_type = REGCACHE_RBTREE,
	246	};
	247
f791be49	248	static int rc5t583_i2c_probe(struct i2c_client *i2c,
1b1247dd LD	249	const struct i2c_device_id *id)
	250	{
	251	struct rc5t583 *rc5t583;
334a41ce	252	struct rc5t583_platform_data *pdata = dev_get_platdata(&i2c->dev);
1b1247dd	253	int ret;
1b1247dd LD	254
	255	if (!pdata) {
	256	dev_err(&i2c->dev, "Err: Platform data not found\n");
	257	return -EINVAL;
	258	}
	259
d0011174	260	rc5t583 = devm_kzalloc(&i2c->dev, sizeof(*rc5t583), GFP_KERNEL);
6733f64f	261	if (!rc5t583)
1b1247dd	262	return -ENOMEM;
1b1247dd LD	263
	264	rc5t583->dev = &i2c->dev;
	265	i2c_set_clientdata(i2c, rc5t583);
	266
f8dddc0c	267	rc5t583->regmap = devm_regmap_init_i2c(i2c, &rc5t583_regmap_config);
1b1247dd LD	268	if (IS_ERR(rc5t583->regmap)) {
	269	ret = PTR_ERR(rc5t583->regmap);
	270	dev_err(&i2c->dev, "regmap initialization failed: %d\n", ret);
	271	return ret;
	272	}
	273
	274	ret = rc5t583_clear_ext_power_req(rc5t583, pdata);
	275	if (ret < 0)
f8dddc0c	276	return ret;
1b1247dd LD	277
	278	if (i2c->irq) {
	279	ret = rc5t583_irq_init(rc5t583, i2c->irq, pdata->irq_base);
5a4432b9	280	/* Still continue with warning, if irq init fails */
1b1247dd LD	281	if (ret)
1b1247dd LD	282	dev_warn(&i2c->dev, "IRQ init failed: %d\n", ret);
1b1247dd LD	283	}
1b1247dd LD	284
b36c8272 LD	285	ret = devm_mfd_add_devices(rc5t583->dev, -1, rc5t583_subdevs,
b36c8272 LD	286	ARRAY_SIZE(rc5t583_subdevs), NULL, 0, NULL);
1b1247dd LD	287	if (ret) {
1b1247dd LD	288	dev_err(&i2c->dev, "add mfd devices failed: %d\n", ret);
b36c8272	289	return ret;
1b1247dd LD	290	}
	291
	292	return 0;
1b1247dd LD	293	}
	294
	295	static const struct i2c_device_id rc5t583_i2c_id[] = {
	296	{.name = "rc5t583", .driver_data = 0},
	297	{}
	298	};
	299
1b1247dd LD	300	static struct i2c_driver rc5t583_i2c_driver = {
	301	.driver = {
	302	.name = "rc5t583",
1b1247dd LD	303	},
1b1247dd LD	304	.probe = rc5t583_i2c_probe,
1b1247dd LD	305	.id_table = rc5t583_i2c_id,
	306	};
	307
	308	static int __init rc5t583_i2c_init(void)
	309	{
	310	return i2c_add_driver(&rc5t583_i2c_driver);
	311	}
	312	subsys_initcall(rc5t583_i2c_init);