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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-bionic-kernel.git] / drivers / mfd / rts5249.c
CommitLineData
4c4b8c10
WW		 1/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
4c4b8c10
WW		 20 */
21
22#include <linux/module.h>
23#include <linux/delay.h>
24#include <linux/mfd/rtsx_pci.h>
25
26#include "rtsx_pcr.h"
27
28static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
29{
30 u8 val;
31
32 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
33 return val & 0x0F;
34}
35
773ccdfd
WW		 36static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
37{
38 u8 driving_3v3[4][3] = {
e89f2318 39 {0x11, 0x11, 0x18},
773ccdfd 40 {0x55, 0x55, 0x5C},
e89f2318
MC		 41 {0xFF, 0xFF, 0xFF},
42 {0x96, 0x96, 0x96},
773ccdfd
WW		 43 };
44 u8 driving_1v8[4][3] = {
e89f2318 45 {0xC4, 0xC4, 0xC4},
773ccdfd 46 {0x3C, 0x3C, 0x3C},
773ccdfd 47 {0xFE, 0xFE, 0xFE},
e89f2318 48 {0xB3, 0xB3, 0xB3},
773ccdfd
WW		 49 };
50 u8 (*driving)[3], drive_sel;
51
52 if (voltage == OUTPUT_3V3) {
53 driving = driving_3v3;
54 drive_sel = pcr->sd30_drive_sel_3v3;
55 } else {
56 driving = driving_1v8;
57 drive_sel = pcr->sd30_drive_sel_1v8;
58 }
59
60 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
61 0xFF, driving[drive_sel][0]);
62 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
63 0xFF, driving[drive_sel][1]);
64 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
65 0xFF, driving[drive_sel][2]);
66}
67
663c425f 68static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
773ccdfd
WW		 69{
70 u32 reg;
71
72 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
0523b8f4 73 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
773ccdfd 74
663c425f
MC		 75 if (!rtsx_vendor_setting_valid(reg)) {
76 pcr_dbg(pcr, "skip fetch vendor setting\n");
773ccdfd 77 return;
663c425f 78 }
773ccdfd
WW		 79
80 pcr->aspm_en = rtsx_reg_to_aspm(reg);
81 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
82 pcr->card_drive_sel &= 0x3F;
83 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
84
85 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
0523b8f4 86 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
773ccdfd
WW		 87 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
88 if (rtsx_reg_check_reverse_socket(reg))
89 pcr->flags |= PCR_REVERSE_SOCKET;
90}
91
663c425f 92static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
5947c167
WW		 93{
94 /* Set relink_time to 0 */
95 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
96 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
97 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
98
eb891c65 99 if (pm_state == HOST_ENTER_S3)
663c425f
MC		 100 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
101 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
eb891c65 102
5947c167
WW		 103 rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
104}
105
8275b77a
RF		 106static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
107{
108 struct rtsx_cr_option *option = &(pcr->option);
109 u32 lval;
110
111 if (CHK_PCI_PID(pcr, PID_524A))
112 rtsx_pci_read_config_dword(pcr,
113 PCR_ASPM_SETTING_REG1, &lval);
114 else
115 rtsx_pci_read_config_dword(pcr,
116 PCR_ASPM_SETTING_REG2, &lval);
117
118 if (lval & ASPM_L1_1_EN_MASK)
119 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
120
121 if (lval & ASPM_L1_2_EN_MASK)
122 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
123
124 if (lval & PM_L1_1_EN_MASK)
125 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
126
127 if (lval & PM_L1_2_EN_MASK)
128 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
129
130 if (option->ltr_en) {
131 u16 val;
132
133 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
134 if (val & PCI_EXP_DEVCTL2_LTR_EN) {
135 option->ltr_enabled = true;
136 option->ltr_active = true;
137 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
138 } else {
139 option->ltr_enabled = false;
140 }
141 }
142}
143
144static int rts5249_init_from_hw(struct rtsx_pcr *pcr)
145{
146 struct rtsx_cr_option *option = &(pcr->option);
147
148 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
149 | PM_L1_1_EN | PM_L1_2_EN))
150 option->force_clkreq_0 = false;
151 else
152 option->force_clkreq_0 = true;
153
154 return 0;
155}
156
4c4b8c10
WW		 157static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
158{
8275b77a
RF		 159 struct rtsx_cr_option *option = &(pcr->option);
160
161 rts5249_init_from_cfg(pcr);
162 rts5249_init_from_hw(pcr);
163
4c4b8c10
WW		 164 rtsx_pci_init_cmd(pcr);
165
663c425f
MC		 166 /* Rest L1SUB Config */
167 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
4c4b8c10
WW		 168 /* Configure GPIO as output */
169 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
7140812c
WW		 170 /* Reset ASPM state to default value */
171 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
4c4b8c10
WW		 172 /* Switch LDO3318 source from DV33 to card_3v3 */
173 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
174 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
175 /* LED shine disabled, set initial shine cycle period */
176 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
773ccdfd
WW		 177 /* Configure driving */
178 rts5249_fill_driving(pcr, OUTPUT_3V3);
179 if (pcr->flags & PCR_REVERSE_SOCKET)
9e33ce79 180 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
773ccdfd 181 else
9e33ce79 182 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
4c4b8c10 183
8275b77a
RF		 184 /*
185 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
186 * to drive low, and we forcibly request clock.
187 */
188 if (option->force_clkreq_0)
189 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
190 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
191 else
192 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
193 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
194
195 return rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
4c4b8c10
WW		 196}
197
198static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
199{
200 int err;
201
19f3bd54 202 err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
5cb5d961
MC		 203 if (err < 0)
204 return err;
205
b0385381
MC		 206 err = rtsx_pci_write_phy_register(pcr, PHY_REV,
207 PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED |
208 PHY_REV_P1_EN | PHY_REV_RXIDLE_EN |
209 PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST |
210 PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD |
211 PHY_REV_STOP_CLKWR);
4c4b8c10
WW		 212 if (err < 0)
213 return err;
214
215 msleep(1);
216
26b81851
WW		 217 err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
218 PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
219 PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
220 if (err < 0)
221 return err;
b0385381 222
26b81851
WW		 223 err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
224 PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
225 PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
b0385381 226 PHY_PCR_RSSI_EN | PHY_PCR_RX10K);
26b81851
WW		 227 if (err < 0)
228 return err;
b0385381 229
26b81851
WW		 230 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
231 PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR |
b0385381
MC		 232 PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 |
233 PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE);
26b81851
WW		 234 if (err < 0)
235 return err;
b0385381 236
26b81851
WW		 237 err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
238 PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF |
239 PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA |
240 PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER |
241 PHY_FLD4_BER_CHK_EN);
242 if (err < 0)
243 return err;
b0385381
MC		 244 err = rtsx_pci_write_phy_register(pcr, PHY_RDR,
245 PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD);
26b81851
WW		 246 if (err < 0)
247 return err;
248 err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
b0385381 249 PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE);
26b81851
WW		 250 if (err < 0)
251 return err;
252 err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
253 PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 |
254 PHY_FLD3_RXDELINK);
255 if (err < 0)
256 return err;
b0385381 257
26b81851
WW		 258 return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
259 PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 |
260 PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 |
b0385381 261 PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
4c4b8c10
WW		 262}
263
663c425f 264static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)
4c4b8c10
WW		 265{
266 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
267}
268
663c425f 269static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)
4c4b8c10
WW		 270{
271 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
272}
273
663c425f 274static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
4c4b8c10
WW		 275{
276 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
277}
278
663c425f 279static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
4c4b8c10
WW		 280{
281 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
282}
283
663c425f 284static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
4c4b8c10
WW		 285{
286 int err;
287
288 rtsx_pci_init_cmd(pcr);
289 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
290 SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
291 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
292 LDO3318_PWR_MASK, 0x02);
293 err = rtsx_pci_send_cmd(pcr, 100);
294 if (err < 0)
295 return err;
296
297 msleep(5);
298
299 rtsx_pci_init_cmd(pcr);
300 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
301 SD_POWER_MASK, SD_VCC_POWER_ON);
302 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
303 LDO3318_PWR_MASK, 0x06);
b158b69a 304 return rtsx_pci_send_cmd(pcr, 100);
4c4b8c10
WW		 305}
306
663c425f 307static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
4c4b8c10
WW		 308{
309 rtsx_pci_init_cmd(pcr);
310 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
311 SD_POWER_MASK, SD_POWER_OFF);
312 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
313 LDO3318_PWR_MASK, 0x00);
314 return rtsx_pci_send_cmd(pcr, 100);
315}
316
663c425f 317static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
4c4b8c10
WW		 318{
319 int err;
663c425f 320 u16 append;
4c4b8c10 321
663c425f
MC		 322 switch (voltage) {
323 case OUTPUT_3V3:
324 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
325 PHY_TUNE_VOLTAGE_3V3);
4c4b8c10
WW		 326 if (err < 0)
327 return err;
663c425f
MC		 328 break;
329 case OUTPUT_1V8:
330 append = PHY_TUNE_D18_1V8;
331 if (CHK_PCI_PID(pcr, 0x5249)) {
332 err = rtsx_pci_update_phy(pcr, PHY_BACR,
333 PHY_BACR_BASIC_MASK, 0);
334 if (err < 0)
335 return err;
336 append = PHY_TUNE_D18_1V7;
337 }
338
339 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
340 append);
4c4b8c10
WW		 341 if (err < 0)
342 return err;
663c425f
MC		 343 break;
344 default:
345 pcr_dbg(pcr, "unknown output voltage %d\n", voltage);
4c4b8c10
WW		 346 return -EINVAL;
347 }
348
349 /* set pad drive */
350 rtsx_pci_init_cmd(pcr);
773ccdfd 351 rts5249_fill_driving(pcr, voltage);
4c4b8c10
WW		 352 return rtsx_pci_send_cmd(pcr, 100);
353}
354
8275b77a
RF		 355static void rts5249_set_aspm(struct rtsx_pcr *pcr, bool enable)
356{
357 struct rtsx_cr_option *option = &pcr->option;
358 u8 val = 0;
359
360 if (pcr->aspm_enabled == enable)
361 return;
362
363 if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) {
364 if (enable)
365 val = pcr->aspm_en;
366 rtsx_pci_update_cfg_byte(pcr,
367 pcr->pcie_cap + PCI_EXP_LNKCTL,
368 ASPM_MASK_NEG, val);
369 } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) {
370 u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0;
371
372 if (!enable)
373 val = FORCE_ASPM_CTL0;
374 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
375 }
376
377 pcr->aspm_enabled = enable;
378}
379
4c4b8c10 380static const struct pcr_ops rts5249_pcr_ops = {
663c425f 381 .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
4c4b8c10
WW		 382 .extra_init_hw = rts5249_extra_init_hw,
383 .optimize_phy = rts5249_optimize_phy,
663c425f
MC		 384 .turn_on_led = rtsx_base_turn_on_led,
385 .turn_off_led = rtsx_base_turn_off_led,
386 .enable_auto_blink = rtsx_base_enable_auto_blink,
387 .disable_auto_blink = rtsx_base_disable_auto_blink,
388 .card_power_on = rtsx_base_card_power_on,
389 .card_power_off = rtsx_base_card_power_off,
390 .switch_output_voltage = rtsx_base_switch_output_voltage,
391 .force_power_down = rtsx_base_force_power_down,
8275b77a 392 .set_aspm = rts5249_set_aspm,
4c4b8c10
WW		 393};
394
395/* SD Pull Control Enable:
396 * SD_DAT[3:0] ==> pull up
397 * SD_CD ==> pull up
398 * SD_WP ==> pull up
399 * SD_CMD ==> pull up
400 * SD_CLK ==> pull down
401 */
402static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
403 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
404 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
405 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
406 RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
407 0,
408};
409
410/* SD Pull Control Disable:
411 * SD_DAT[3:0] ==> pull down
412 * SD_CD ==> pull up
413 * SD_WP ==> pull down
414 * SD_CMD ==> pull down
415 * SD_CLK ==> pull down
416 */
417static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
418 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
419 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
420 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
421 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
422 0,
423};
424
425/* MS Pull Control Enable:
426 * MS CD ==> pull up
427 * others ==> pull down
428 */
429static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
430 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
431 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
432 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
433 0,
434};
435
436/* MS Pull Control Disable:
437 * MS CD ==> pull up
438 * others ==> pull down
439 */
440static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
441 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
442 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
443 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
444 0,
445};
446
447void rts5249_init_params(struct rtsx_pcr *pcr)
448{
8275b77a
RF		 449 struct rtsx_cr_option *option = &(pcr->option);
450
4c4b8c10
WW		 451 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
452 pcr->num_slots = 2;
453 pcr->ops = &rts5249_pcr_ops;
454
773ccdfd
WW		 455 pcr->flags = 0;
456 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
e89f2318 457 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
773ccdfd
WW		 458 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
459 pcr->aspm_en = ASPM_L1_EN;
84d72f9c
WW		 460 pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
461 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
773ccdfd 462
4c4b8c10
WW		 463 pcr->ic_version = rts5249_get_ic_version(pcr);
464 pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
465 pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
466 pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
467 pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
663c425f
MC		 468
469 pcr->reg_pm_ctrl3 = PM_CTRL3;
8275b77a
RF		 470
471 option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
472 | LTR_L1SS_PWR_GATE_EN);
473 option->ltr_en = true;
474
475 /* Init latency of active, idle, L1OFF to 60us, 300us, 3ms */
476 option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
477 option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
478 option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
479 option->dev_aspm_mode = DEV_ASPM_DYNAMIC;
480 option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
481 option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF;
482 option->ltr_l1off_snooze_sspwrgate =
483 LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF;
663c425f
MC		 484}
485
486static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
487{
488 addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
489
490 return __rtsx_pci_write_phy_register(pcr, addr, val);
4c4b8c10 491}
663c425f
MC		 492
493static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)
494{
495 addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
496
497 return __rtsx_pci_read_phy_register(pcr, addr, val);
498}
499
500static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
501{
502 int err;
503
504 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
505 D3_DELINK_MODE_EN, 0x00);
506 if (err < 0)
507 return err;
508
509 rtsx_pci_write_phy_register(pcr, PHY_PCR,
510 PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
511 PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN);
512 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
513 PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
514
515 if (is_version(pcr, 0x524A, IC_VER_A)) {
516 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
517 PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
518 rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
519 PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 |
520 PHY_SSCCR2_TIME2_WIDTH);
521 rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
522 PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST |
523 PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV);
524 rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
525 PHY_ANA1D_DEBUG_ADDR);
526 rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
527 PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 |
528 PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST |
529 PHY_DIG1E_RCLK_TX_EN_KEEP |
530 PHY_DIG1E_RCLK_TX_TERM_KEEP |
531 PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP |
532 PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP |
533 PHY_DIG1E_RX_EN_KEEP);
534 }
535
536 rtsx_pci_write_phy_register(pcr, PHY_ANA08,
537 PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN |
538 PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI);
539
540 return 0;
541}
542
543static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)
544{
545 rts5249_extra_init_hw(pcr);
546
547 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
548 FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN);
549 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
550 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,
551 LDO_VCC_LMT_EN);
552 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
553 if (is_version(pcr, 0x524A, IC_VER_A)) {
554 rtsx_pci_write_register(pcr, LDO_DV18_CFG,
555 LDO_DV18_SR_MASK, LDO_DV18_SR_DF);
556 rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
557 LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2);
558 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
559 LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2);
560 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
561 LDO_VIO_SR_MASK, LDO_VIO_SR_DF);
562 rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
563 LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF);
564 rtsx_pci_write_register(pcr, SD40_LDO_CTL1,
565 SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7);
566 }
567
568 return 0;
569}
570
8275b77a
RF		 571static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
572{
573 struct rtsx_cr_option *option = &(pcr->option);
574
575 u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
576 int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST);
577 int aspm_L1_1, aspm_L1_2;
578 u8 val = 0;
579
580 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
581 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
582
583 if (active) {
584 /* Run, latency: 60us */
585 if (aspm_L1_1)
586 val = option->ltr_l1off_snooze_sspwrgate;
587 } else {
588 /* L1off, latency: 300us */
589 if (aspm_L1_2)
590 val = option->ltr_l1off_sspwrgate;
591 }
592
593 if (aspm_L1_1 || aspm_L1_2) {
594 if (rtsx_check_dev_flag(pcr,
595 LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {
596 if (card_exist)
597 val &= ~L1OFF_MBIAS2_EN_5250;
598 else
599 val |= L1OFF_MBIAS2_EN_5250;
600 }
601 }
602 rtsx_set_l1off_sub(pcr, val);
603}
604
663c425f
MC		 605static const struct pcr_ops rts524a_pcr_ops = {
606 .write_phy = rts524a_write_phy,
607 .read_phy = rts524a_read_phy,
608 .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
609 .extra_init_hw = rts524a_extra_init_hw,
610 .optimize_phy = rts524a_optimize_phy,
611 .turn_on_led = rtsx_base_turn_on_led,
612 .turn_off_led = rtsx_base_turn_off_led,
613 .enable_auto_blink = rtsx_base_enable_auto_blink,
614 .disable_auto_blink = rtsx_base_disable_auto_blink,
615 .card_power_on = rtsx_base_card_power_on,
616 .card_power_off = rtsx_base_card_power_off,
617 .switch_output_voltage = rtsx_base_switch_output_voltage,
618 .force_power_down = rtsx_base_force_power_down,
8275b77a
RF		 619 .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
620 .set_aspm = rts5249_set_aspm,
663c425f
MC		 621};
622
623void rts524a_init_params(struct rtsx_pcr *pcr)
624{
625 rts5249_init_params(pcr);
8275b77a
RF		 626 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
627 pcr->option.ltr_l1off_snooze_sspwrgate =
628 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
663c425f
MC		 629
630 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
631 pcr->ops = &rts524a_pcr_ops;
632}
633
41bc2334
MC		 634static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)
635{
636 rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
637 LDO_VCC_TUNE_MASK, LDO_VCC_3V3);
638 return rtsx_base_card_power_on(pcr, card);
639}
640
641static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
642{
643 switch (voltage) {
644 case OUTPUT_3V3:
645 rtsx_pci_write_register(pcr, LDO_CONFIG2,
646 LDO_D3318_MASK, LDO_D3318_33V);
647 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
648 break;
649 case OUTPUT_1V8:
650 rtsx_pci_write_register(pcr, LDO_CONFIG2,
651 LDO_D3318_MASK, LDO_D3318_18V);
652 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
653 SD_IO_USING_1V8);
654 break;
655 default:
656 return -EINVAL;
657 }
658
659 rtsx_pci_init_cmd(pcr);
660 rts5249_fill_driving(pcr, voltage);
661 return rtsx_pci_send_cmd(pcr, 100);
662}
663
664static int rts525a_optimize_phy(struct rtsx_pcr *pcr)
665{
666 int err;
667
668 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
669 D3_DELINK_MODE_EN, 0x00);
670 if (err < 0)
671 return err;
672
673 rtsx_pci_write_phy_register(pcr, _PHY_FLD0,
674 _PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN |
675 _PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT |
676 _PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN);
677
678 rtsx_pci_write_phy_register(pcr, _PHY_ANA03,
679 _PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN |
680 _PHY_CMU_DEBUG_EN);
681
682 if (is_version(pcr, 0x525A, IC_VER_A))
683 rtsx_pci_write_phy_register(pcr, _PHY_REV0,
684 _PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD |
685 _PHY_REV0_CDR_RX_IDLE_BYPASS);
686
687 return 0;
688}
689
690static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)
691{
692 rts5249_extra_init_hw(pcr);
693
694 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
695 if (is_version(pcr, 0x525A, IC_VER_A)) {
696 rtsx_pci_write_register(pcr, L1SUB_CONFIG2,
697 L1SUB_AUTO_CFG, L1SUB_AUTO_CFG);
698 rtsx_pci_write_register(pcr, RREF_CFG,
699 RREF_VBGSEL_MASK, RREF_VBGSEL_1V25);
700 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
701 LDO_VIO_TUNE_MASK, LDO_VIO_1V7);
702 rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
703 LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF);
704 rtsx_pci_write_register(pcr, LDO_AV12S_CFG,
705 LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF);
706 rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
707 LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A);
708 rtsx_pci_write_register(pcr, OOBS_CONFIG,
709 OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89);
710 }
711
712 return 0;
713}
714
715static const struct pcr_ops rts525a_pcr_ops = {
716 .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
717 .extra_init_hw = rts525a_extra_init_hw,
718 .optimize_phy = rts525a_optimize_phy,
719 .turn_on_led = rtsx_base_turn_on_led,
720 .turn_off_led = rtsx_base_turn_off_led,
721 .enable_auto_blink = rtsx_base_enable_auto_blink,
722 .disable_auto_blink = rtsx_base_disable_auto_blink,
723 .card_power_on = rts525a_card_power_on,
724 .card_power_off = rtsx_base_card_power_off,
725 .switch_output_voltage = rts525a_switch_output_voltage,
726 .force_power_down = rtsx_base_force_power_down,
8275b77a
RF		 727 .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
728 .set_aspm = rts5249_set_aspm,
41bc2334
MC		 729};
730
731void rts525a_init_params(struct rtsx_pcr *pcr)
732{
733 rts5249_init_params(pcr);
8275b77a
RF		 734 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
735 pcr->option.ltr_l1off_snooze_sspwrgate =
736 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
41bc2334
MC		 737
738 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
739 pcr->ops = &rts525a_pcr_ops;
740}
741
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