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Merge branch 'work.splice_read' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-zesty-kernel.git] / drivers / mfd / sm501.c
CommitLineData
b6d6454f
BD		 1/* linux/drivers/mfd/sm501.c
2 *
3 * Copyright (C) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * Vincent Sanders <vince@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * SM501 MFD driver
12*/
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/delay.h>
17#include <linux/init.h>
18#include <linux/list.h>
19#include <linux/device.h>
20#include <linux/platform_device.h>
21#include <linux/pci.h>
42cd2366 22#include <linux/i2c-gpio.h>
5a0e3ad6 23#include <linux/slab.h>
b6d6454f
BD		 24
25#include <linux/sm501.h>
26#include <linux/sm501-regs.h>
61711f8f 27#include <linux/serial_8250.h>
b6d6454f 28
f77401d4 29#include <linux/io.h>
b6d6454f
BD		 30
31struct sm501_device {
32 struct list_head list;
33 struct platform_device pdev;
34};
35
f61be273
BD		 36struct sm501_gpio;
37
f2999209
BD		 38#ifdef CONFIG_MFD_SM501_GPIO
39#include <linux/gpio.h>
40
f61be273
BD		 41struct sm501_gpio_chip {
42 struct gpio_chip gpio;
43 struct sm501_gpio *ourgpio; /* to get back to parent. */
44 void __iomem *regbase;
98325f8f 45 void __iomem *control; /* address of control reg. */
f61be273
BD		 46};
47
48struct sm501_gpio {
49 struct sm501_gpio_chip low;
50 struct sm501_gpio_chip high;
51 spinlock_t lock;
52
53 unsigned int registered : 1;
54 void __iomem *regs;
55 struct resource *regs_res;
56};
f2999209
BD		 57#else
58struct sm501_gpio {
59 /* no gpio support, empty definition for sm501_devdata. */
60};
61#endif
f61be273 62
b6d6454f
BD		 63struct sm501_devdata {
64 spinlock_t reg_lock;
65 struct mutex clock_lock;
66 struct list_head devices;
f61be273 67 struct sm501_gpio gpio;
b6d6454f
BD		 68
69 struct device *dev;
70 struct resource *io_res;
71 struct resource *mem_res;
72 struct resource *regs_claim;
73 struct sm501_platdata *platdata;
74
f61be273 75
331d7475
BD		 76 unsigned int in_suspend;
77 unsigned long pm_misc;
78
b6d6454f
BD		 79 int unit_power[20];
80 unsigned int pdev_id;
81 unsigned int irq;
82 void __iomem *regs;
3149be50 83 unsigned int rev;
b6d6454f
BD		 84};
85
f61be273 86
b6d6454f
BD		 87#define MHZ (1000 * 1000)
88
89#ifdef DEBUG
245904a4 90static const unsigned int div_tab[] = {
b6d6454f
BD		 91 [0] = 1,
92 [1] = 2,
93 [2] = 4,
94 [3] = 8,
95 [4] = 16,
96 [5] = 32,
97 [6] = 64,
98 [7] = 128,
99 [8] = 3,
100 [9] = 6,
101 [10] = 12,
102 [11] = 24,
103 [12] = 48,
104 [13] = 96,
105 [14] = 192,
106 [15] = 384,
107 [16] = 5,
108 [17] = 10,
109 [18] = 20,
110 [19] = 40,
111 [20] = 80,
112 [21] = 160,
113 [22] = 320,
114 [23] = 604,
115};
116
117static unsigned long decode_div(unsigned long pll2, unsigned long val,
118 unsigned int lshft, unsigned int selbit,
245904a4 119 unsigned long mask)
b6d6454f
BD		 120{
121 if (val & selbit)
122 pll2 = 288 * MHZ;
123
245904a4 124 return pll2 / div_tab[(val >> lshft) & mask];
b6d6454f
BD		 125}
126
127#define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
128
129/* sm501_dump_clk
130 *
131 * Print out the current clock configuration for the device
132*/
133
134static void sm501_dump_clk(struct sm501_devdata *sm)
135{
bf5f0019
HS		 136 unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING);
137 unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
138 unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
139 unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
b6d6454f
BD		 140 unsigned long sdclk0, sdclk1;
141 unsigned long pll2 = 0;
142
143 switch (misct & 0x30) {
144 case 0x00:
145 pll2 = 336 * MHZ;
146 break;
147 case 0x10:
148 pll2 = 288 * MHZ;
149 break;
150 case 0x20:
151 pll2 = 240 * MHZ;
152 break;
153 case 0x30:
154 pll2 = 192 * MHZ;
155 break;
156 }
157
158 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
245904a4 159 sdclk0 /= div_tab[((misct >> 8) & 0xf)];
b6d6454f
BD		 160
161 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
245904a4 162 sdclk1 /= div_tab[((misct >> 16) & 0xf)];
b6d6454f
BD		 163
164 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
165 misct, pm0, pm1);
166
167 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
168 fmt_freq(pll2), sdclk0, sdclk1);
169
170 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
171
172 dev_dbg(sm->dev, "PM0[%c]: "
173 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
48986f06 174 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
b6d6454f 175 (pmc & 3 ) == 0 ? '*' : '-',
245904a4
VS		 176 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
177 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
178 fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)),
179 fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15)));
b6d6454f
BD		 180
181 dev_dbg(sm->dev, "PM1[%c]: "
182 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
183 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
184 (pmc & 3 ) == 1 ? '*' : '-',
245904a4
VS		 185 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
186 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
187 fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)),
188 fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15)));
b6d6454f 189}
331d7475
BD		 190
191static void sm501_dump_regs(struct sm501_devdata *sm)
192{
193 void __iomem *regs = sm->regs;
194
195 dev_info(sm->dev, "System Control %08x\n",
bf5f0019 196 smc501_readl(regs + SM501_SYSTEM_CONTROL));
331d7475 197 dev_info(sm->dev, "Misc Control %08x\n",
bf5f0019 198 smc501_readl(regs + SM501_MISC_CONTROL));
331d7475 199 dev_info(sm->dev, "GPIO Control Low %08x\n",
bf5f0019 200 smc501_readl(regs + SM501_GPIO31_0_CONTROL));
331d7475 201 dev_info(sm->dev, "GPIO Control Hi %08x\n",
bf5f0019 202 smc501_readl(regs + SM501_GPIO63_32_CONTROL));
331d7475 203 dev_info(sm->dev, "DRAM Control %08x\n",
bf5f0019 204 smc501_readl(regs + SM501_DRAM_CONTROL));
331d7475 205 dev_info(sm->dev, "Arbitration Ctrl %08x\n",
bf5f0019 206 smc501_readl(regs + SM501_ARBTRTN_CONTROL));
331d7475 207 dev_info(sm->dev, "Misc Timing %08x\n",
bf5f0019 208 smc501_readl(regs + SM501_MISC_TIMING));
331d7475
BD		 209}
210
211static void sm501_dump_gate(struct sm501_devdata *sm)
b6d6454f 212{
331d7475 213 dev_info(sm->dev, "CurrentGate %08x\n",
bf5f0019 214 smc501_readl(sm->regs + SM501_CURRENT_GATE));
331d7475 215 dev_info(sm->dev, "CurrentClock %08x\n",
bf5f0019 216 smc501_readl(sm->regs + SM501_CURRENT_CLOCK));
331d7475 217 dev_info(sm->dev, "PowerModeControl %08x\n",
bf5f0019 218 smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL));
b6d6454f 219}
331d7475
BD		 220
221#else
222static inline void sm501_dump_gate(struct sm501_devdata *sm) { }
223static inline void sm501_dump_regs(struct sm501_devdata *sm) { }
224static inline void sm501_dump_clk(struct sm501_devdata *sm) { }
b6d6454f
BD		 225#endif
226
227/* sm501_sync_regs
228 *
229 * ensure the
230*/
231
232static void sm501_sync_regs(struct sm501_devdata *sm)
233{
bf5f0019 234 smc501_readl(sm->regs);
b6d6454f
BD		 235}
236
331d7475
BD		 237static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
238{
239 /* during suspend/resume, we are currently not allowed to sleep,
240 * so change to using mdelay() instead of msleep() if we
241 * are in one of these paths */
242
243 if (sm->in_suspend)
244 mdelay(delay);
245 else
246 msleep(delay);
247}
248
b6d6454f
BD		 249/* sm501_misc_control
250 *
331d7475 251 * alters the miscellaneous control parameters
b6d6454f
BD		 252*/
253
254int sm501_misc_control(struct device *dev,
255 unsigned long set, unsigned long clear)
256{
257 struct sm501_devdata *sm = dev_get_drvdata(dev);
258 unsigned long misc;
259 unsigned long save;
260 unsigned long to;
261
262 spin_lock_irqsave(&sm->reg_lock, save);
263
bf5f0019 264 misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
b6d6454f
BD		 265 to = (misc & ~clear) | set;
266
267 if (to != misc) {
bf5f0019 268 smc501_writel(to, sm->regs + SM501_MISC_CONTROL);
b6d6454f
BD		 269 sm501_sync_regs(sm);
270
271 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
272 }
273
274 spin_unlock_irqrestore(&sm->reg_lock, save);
275 return to;
276}
277
278EXPORT_SYMBOL_GPL(sm501_misc_control);
279
280/* sm501_modify_reg
281 *
282 * Modify a register in the SM501 which may be shared with other
283 * drivers.
284*/
285
286unsigned long sm501_modify_reg(struct device *dev,
287 unsigned long reg,
288 unsigned long set,
289 unsigned long clear)
290{
291 struct sm501_devdata *sm = dev_get_drvdata(dev);
292 unsigned long data;
293 unsigned long save;
294
295 spin_lock_irqsave(&sm->reg_lock, save);
296
bf5f0019 297 data = smc501_readl(sm->regs + reg);
b6d6454f
BD		 298 data |= set;
299 data &= ~clear;
300
bf5f0019 301 smc501_writel(data, sm->regs + reg);
b6d6454f
BD		 302 sm501_sync_regs(sm);
303
304 spin_unlock_irqrestore(&sm->reg_lock, save);
305
306 return data;
307}
308
309EXPORT_SYMBOL_GPL(sm501_modify_reg);
310
b6d6454f
BD		 311/* sm501_unit_power
312 *
313 * alters the power active gate to set specific units on or off
314 */
315
316int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
317{
318 struct sm501_devdata *sm = dev_get_drvdata(dev);
319 unsigned long mode;
320 unsigned long gate;
321 unsigned long clock;
322
323 mutex_lock(&sm->clock_lock);
324
bf5f0019
HS		 325 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
326 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
327 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
b6d6454f
BD		 328
329 mode &= 3; /* get current power mode */
330
bf703c3f 331 if (unit >= ARRAY_SIZE(sm->unit_power)) {
145980a0 332 dev_err(dev, "%s: bad unit %d\n", __func__, unit);
b6d6454f
BD		 333 goto already;
334 }
335
145980a0 336 dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
b6d6454f
BD		 337 sm->unit_power[unit], to);
338
339 if (to == 0 && sm->unit_power[unit] == 0) {
340 dev_err(sm->dev, "unit %d is already shutdown\n", unit);
341 goto already;
342 }
343
344 sm->unit_power[unit] += to ? 1 : -1;
345 to = sm->unit_power[unit] ? 1 : 0;
346
347 if (to) {
348 if (gate & (1 << unit))
349 goto already;
350 gate |= (1 << unit);
351 } else {
352 if (!(gate & (1 << unit)))
353 goto already;
354 gate &= ~(1 << unit);
355 }
356
357 switch (mode) {
358 case 1:
bf5f0019
HS		 359 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
360 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
b6d6454f
BD		 361 mode = 0;
362 break;
363 case 2:
364 case 0:
bf5f0019
HS		 365 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
366 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
b6d6454f
BD		 367 mode = 1;
368 break;
369
370 default:
992bb253
JS		 371 gate = -1;
372 goto already;
b6d6454f
BD		 373 }
374
bf5f0019 375 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
b6d6454f
BD		 376 sm501_sync_regs(sm);
377
378 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
379 gate, clock, mode);
380
331d7475 381 sm501_mdelay(sm, 16);
b6d6454f
BD		 382
383 already:
384 mutex_unlock(&sm->clock_lock);
385 return gate;
386}
387
388EXPORT_SYMBOL_GPL(sm501_unit_power);
389
b6d6454f
BD		 390/* clock value structure. */
391struct sm501_clock {
392 unsigned long mclk;
393 int divider;
394 int shift;
3149be50 395 unsigned int m, n, k;
b6d6454f
BD		 396};
397
3149be50
VS		 398/* sm501_calc_clock
399 *
400 * Calculates the nearest discrete clock frequency that
401 * can be achieved with the specified input clock.
402 * the maximum divisor is 3 or 5
403 */
404
405static int sm501_calc_clock(unsigned long freq,
406 struct sm501_clock *clock,
407 int max_div,
408 unsigned long mclk,
409 long *best_diff)
410{
411 int ret = 0;
412 int divider;
413 int shift;
414 long diff;
415
416 /* try dividers 1 and 3 for CRT and for panel,
417 try divider 5 for panel only.*/
418
419 for (divider = 1; divider <= max_div; divider += 2) {
420 /* try all 8 shift values.*/
421 for (shift = 0; shift < 8; shift++) {
422 /* Calculate difference to requested clock */
829ecbcb 423 diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq;
3149be50
VS		 424 if (diff < 0)
425 diff = -diff;
426
427 /* If it is less than the current, use it */
428 if (diff < *best_diff) {
429 *best_diff = diff;
430
431 clock->mclk = mclk;
432 clock->divider = divider;
433 clock->shift = shift;
434 ret = 1;
435 }
436 }
437 }
438
439 return ret;
440}
441
442/* sm501_calc_pll
443 *
444 * Calculates the nearest discrete clock frequency that can be
445 * achieved using the programmable PLL.
446 * the maximum divisor is 3 or 5
447 */
448
449static unsigned long sm501_calc_pll(unsigned long freq,
450 struct sm501_clock *clock,
451 int max_div)
452{
453 unsigned long mclk;
454 unsigned int m, n, k;
455 long best_diff = 999999999;
456
457 /*
458 * The SM502 datasheet doesn't specify the min/max values for M and N.
459 * N = 1 at least doesn't work in practice.
460 */
461 for (m = 2; m <= 255; m++) {
462 for (n = 2; n <= 127; n++) {
463 for (k = 0; k <= 1; k++) {
464 mclk = (24000000UL * m / n) >> k;
465
466 if (sm501_calc_clock(freq, clock, max_div,
467 mclk, &best_diff)) {
468 clock->m = m;
469 clock->n = n;
470 clock->k = k;
471 }
472 }
473 }
474 }
475
476 /* Return best clock. */
477 return clock->mclk / (clock->divider << clock->shift);
478}
479
b6d6454f
BD		 480/* sm501_select_clock
481 *
3149be50
VS		 482 * Calculates the nearest discrete clock frequency that can be
483 * achieved using the 288MHz and 336MHz PLLs.
b6d6454f
BD		 484 * the maximum divisor is 3 or 5
485 */
3149be50 486
b6d6454f
BD		 487static unsigned long sm501_select_clock(unsigned long freq,
488 struct sm501_clock *clock,
489 int max_div)
490{
491 unsigned long mclk;
b6d6454f
BD		 492 long best_diff = 999999999;
493
494 /* Try 288MHz and 336MHz clocks. */
495 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
3149be50 496 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
b6d6454f
BD		 497 }
498
499 /* Return best clock. */
500 return clock->mclk / (clock->divider << clock->shift);
501}
502
503/* sm501_set_clock
504 *
505 * set one of the four clock sources to the closest available frequency to
506 * the one specified
507*/
508
509unsigned long sm501_set_clock(struct device *dev,
510 int clksrc,
511 unsigned long req_freq)
512{
513 struct sm501_devdata *sm = dev_get_drvdata(dev);
bf5f0019
HS		 514 unsigned long mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
515 unsigned long gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
516 unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
3149be50 517 unsigned int pll_reg = 0;
3ad2f3fb 518 unsigned long sm501_freq; /* the actual frequency achieved */
5f114ebc 519 u64 reg;
b6d6454f
BD		 520
521 struct sm501_clock to;
522
523 /* find achivable discrete frequency and setup register value
524 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
525 * has an extra bit for the divider */
526
527 switch (clksrc) {
528 case SM501_CLOCK_P2XCLK:
3ad2f3fb 529 /* This clock is divided in half so to achieve the
b6d6454f
BD		 530 * requested frequency the value must be multiplied by
531 * 2. This clock also has an additional pre divisor */
532
3149be50
VS		 533 if (sm->rev >= 0xC0) {
534 /* SM502 -> use the programmable PLL */
535 sm501_freq = (sm501_calc_pll(2 * req_freq,
536 &to, 5) / 2);
537 reg = to.shift & 0x07;/* bottom 3 bits are shift */
538 if (to.divider == 3)
539 reg |= 0x08; /* /3 divider required */
540 else if (to.divider == 5)
541 reg |= 0x10; /* /5 divider required */
542 reg |= 0x40; /* select the programmable PLL */
543 pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
544 } else {
545 sm501_freq = (sm501_select_clock(2 * req_freq,
546 &to, 5) / 2);
547 reg = to.shift & 0x07;/* bottom 3 bits are shift */
548 if (to.divider == 3)
549 reg |= 0x08; /* /3 divider required */
550 else if (to.divider == 5)
551 reg |= 0x10; /* /5 divider required */
552 if (to.mclk != 288000000)
553 reg |= 0x20; /* which mclk pll is source */
554 }
b6d6454f
BD		 555 break;
556
557 case SM501_CLOCK_V2XCLK:
3ad2f3fb 558 /* This clock is divided in half so to achieve the
b6d6454f
BD		 559 * requested frequency the value must be multiplied by 2. */
560
561 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
562 reg=to.shift & 0x07; /* bottom 3 bits are shift */
563 if (to.divider == 3)
564 reg |= 0x08; /* /3 divider required */
565 if (to.mclk != 288000000)
566 reg |= 0x10; /* which mclk pll is source */
567 break;
568
569 case SM501_CLOCK_MCLK:
570 case SM501_CLOCK_M1XCLK:
571 /* These clocks are the same and not further divided */
572
573 sm501_freq = sm501_select_clock( req_freq, &to, 3);
574 reg=to.shift & 0x07; /* bottom 3 bits are shift */
575 if (to.divider == 3)
576 reg |= 0x08; /* /3 divider required */
577 if (to.mclk != 288000000)
578 reg |= 0x10; /* which mclk pll is source */
579 break;
580
581 default:
582 return 0; /* this is bad */
583 }
584
585 mutex_lock(&sm->clock_lock);
586
bf5f0019
HS		 587 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
588 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
589 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
b6d6454f
BD		 590
591 clock = clock & ~(0xFF << clksrc);
592 clock |= reg<<clksrc;
593
594 mode &= 3; /* find current mode */
595
596 switch (mode) {
597 case 1:
bf5f0019
HS		 598 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
599 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
b6d6454f
BD		 600 mode = 0;
601 break;
602 case 2:
603 case 0:
bf5f0019
HS		 604 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
605 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
b6d6454f
BD		 606 mode = 1;
607 break;
608
609 default:
610 mutex_unlock(&sm->clock_lock);
611 return -1;
612 }
613
bf5f0019 614 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
3149be50
VS		 615
616 if (pll_reg)
bf5f0019
HS		 617 smc501_writel(pll_reg,
618 sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
3149be50 619
b6d6454f
BD		 620 sm501_sync_regs(sm);
621
80e74a80
BD		 622 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
623 gate, clock, mode);
b6d6454f 624
331d7475 625 sm501_mdelay(sm, 16);
b6d6454f
BD		 626 mutex_unlock(&sm->clock_lock);
627
628 sm501_dump_clk(sm);
629
630 return sm501_freq;
631}
632
633EXPORT_SYMBOL_GPL(sm501_set_clock);
634
635/* sm501_find_clock
636 *
637 * finds the closest available frequency for a given clock
638*/
639
3149be50
VS		 640unsigned long sm501_find_clock(struct device *dev,
641 int clksrc,
b6d6454f
BD		 642 unsigned long req_freq)
643{
3149be50 644 struct sm501_devdata *sm = dev_get_drvdata(dev);
3ad2f3fb 645 unsigned long sm501_freq; /* the frequency achieveable by the 501 */
b6d6454f
BD		 646 struct sm501_clock to;
647
648 switch (clksrc) {
649 case SM501_CLOCK_P2XCLK:
3149be50
VS		 650 if (sm->rev >= 0xC0) {
651 /* SM502 -> use the programmable PLL */
652 sm501_freq = (sm501_calc_pll(2 * req_freq,
653 &to, 5) / 2);
654 } else {
655 sm501_freq = (sm501_select_clock(2 * req_freq,
656 &to, 5) / 2);
657 }
b6d6454f
BD		 658 break;
659
660 case SM501_CLOCK_V2XCLK:
661 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
662 break;
663
664 case SM501_CLOCK_MCLK:
665 case SM501_CLOCK_M1XCLK:
666 sm501_freq = sm501_select_clock(req_freq, &to, 3);
667 break;
668
669 default:
670 sm501_freq = 0; /* error */
671 }
672
673 return sm501_freq;
674}
675
676EXPORT_SYMBOL_GPL(sm501_find_clock);
677
678static struct sm501_device *to_sm_device(struct platform_device *pdev)
679{
680 return container_of(pdev, struct sm501_device, pdev);
681}
682
683/* sm501_device_release
684 *
685 * A release function for the platform devices we create to allow us to
686 * free any items we allocated
687*/
688
689static void sm501_device_release(struct device *dev)
690{
691 kfree(to_sm_device(to_platform_device(dev)));
692}
693
694/* sm501_create_subdev
695 *
696 * Create a skeleton platform device with resources for passing to a
697 * sub-driver
698*/
699
700static struct platform_device *
61711f8f
MD		 701sm501_create_subdev(struct sm501_devdata *sm, char *name,
702 unsigned int res_count, unsigned int platform_data_size)
b6d6454f
BD		 703{
704 struct sm501_device *smdev;
705
706 smdev = kzalloc(sizeof(struct sm501_device) +
61711f8f
MD		 707 (sizeof(struct resource) * res_count) +
708 platform_data_size, GFP_KERNEL);
b6d6454f
BD		 709 if (!smdev)
710 return NULL;
711
712 smdev->pdev.dev.release = sm501_device_release;
713
714 smdev->pdev.name = name;
715 smdev->pdev.id = sm->pdev_id;
b6d6454f
BD		 716 smdev->pdev.dev.parent = sm->dev;
717
61711f8f
MD		 718 if (res_count) {
719 smdev->pdev.resource = (struct resource *)(smdev+1);
720 smdev->pdev.num_resources = res_count;
721 }
722 if (platform_data_size)
723 smdev->pdev.dev.platform_data = (void *)(smdev+1);
724
b6d6454f
BD		 725 return &smdev->pdev;
726}
727
728/* sm501_register_device
729 *
730 * Register a platform device created with sm501_create_subdev()
731*/
732
733static int sm501_register_device(struct sm501_devdata *sm,
734 struct platform_device *pdev)
735{
736 struct sm501_device *smdev = to_sm_device(pdev);
737 int ptr;
738 int ret;
739
740 for (ptr = 0; ptr < pdev->num_resources; ptr++) {
3f3d4310
JP		 741 printk(KERN_DEBUG "%s[%d] %pR\n",
742 pdev->name, ptr, &pdev->resource[ptr]);
b6d6454f
BD		 743 }
744
745 ret = platform_device_register(pdev);
746
747 if (ret >= 0) {
748 dev_dbg(sm->dev, "registered %s\n", pdev->name);
749 list_add_tail(&smdev->list, &sm->devices);
750 } else
751 dev_err(sm->dev, "error registering %s (%d)\n",
752 pdev->name, ret);
753
754 return ret;
755}
756
757/* sm501_create_subio
758 *
759 * Fill in an IO resource for a sub device
760*/
761
762static void sm501_create_subio(struct sm501_devdata *sm,
763 struct resource *res,
764 resource_size_t offs,
765 resource_size_t size)
766{
767 res->flags = IORESOURCE_MEM;
768 res->parent = sm->io_res;
769 res->start = sm->io_res->start + offs;
770 res->end = res->start + size - 1;
771}
772
773/* sm501_create_mem
774 *
775 * Fill in an MEM resource for a sub device
776*/
777
778static void sm501_create_mem(struct sm501_devdata *sm,
779 struct resource *res,
780 resource_size_t *offs,
781 resource_size_t size)
782{
783 *offs -= size; /* adjust memory size */
784
785 res->flags = IORESOURCE_MEM;
786 res->parent = sm->mem_res;
787 res->start = sm->mem_res->start + *offs;
788 res->end = res->start + size - 1;
789}
790
791/* sm501_create_irq
792 *
793 * Fill in an IRQ resource for a sub device
794*/
795
796static void sm501_create_irq(struct sm501_devdata *sm,
797 struct resource *res)
798{
799 res->flags = IORESOURCE_IRQ;
800 res->parent = NULL;
801 res->start = res->end = sm->irq;
802}
803
804static int sm501_register_usbhost(struct sm501_devdata *sm,
805 resource_size_t *mem_avail)
806{
807 struct platform_device *pdev;
808
61711f8f 809 pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0);
b6d6454f
BD		 810 if (!pdev)
811 return -ENOMEM;
812
813 sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
814 sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
815 sm501_create_irq(sm, &pdev->resource[2]);
816
817 return sm501_register_device(sm, pdev);
818}
819
61711f8f
MD		 820static void sm501_setup_uart_data(struct sm501_devdata *sm,
821 struct plat_serial8250_port *uart_data,
822 unsigned int offset)
823{
824 uart_data->membase = sm->regs + offset;
825 uart_data->mapbase = sm->io_res->start + offset;
826 uart_data->iotype = UPIO_MEM;
827 uart_data->irq = sm->irq;
828 uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
829 uart_data->regshift = 2;
830 uart_data->uartclk = (9600 * 16);
831}
832
833static int sm501_register_uart(struct sm501_devdata *sm, int devices)
834{
835 struct platform_device *pdev;
836 struct plat_serial8250_port *uart_data;
837
838 pdev = sm501_create_subdev(sm, "serial8250", 0,
839 sizeof(struct plat_serial8250_port) * 3);
840 if (!pdev)
841 return -ENOMEM;
842
334a41ce 843 uart_data = dev_get_platdata(&pdev->dev);
61711f8f
MD		 844
845 if (devices & SM501_USE_UART0) {
846 sm501_setup_uart_data(sm, uart_data++, 0x30000);
847 sm501_unit_power(sm->dev, SM501_GATE_UART0, 1);
848 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0);
849 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0);
850 }
851 if (devices & SM501_USE_UART1) {
852 sm501_setup_uart_data(sm, uart_data++, 0x30020);
853 sm501_unit_power(sm->dev, SM501_GATE_UART1, 1);
854 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0);
855 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0);
856 }
857
858 pdev->id = PLAT8250_DEV_SM501;
859
860 return sm501_register_device(sm, pdev);
861}
862
b6d6454f
BD		 863static int sm501_register_display(struct sm501_devdata *sm,
864 resource_size_t *mem_avail)
865{
866 struct platform_device *pdev;
867
61711f8f 868 pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0);
b6d6454f
BD		 869 if (!pdev)
870 return -ENOMEM;
871
872 sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
873 sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
874 sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
875 sm501_create_irq(sm, &pdev->resource[3]);
876
877 return sm501_register_device(sm, pdev);
878}
879
f61be273
BD		 880#ifdef CONFIG_MFD_SM501_GPIO
881
f61be273
BD		 882static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio)
883{
884 return container_of(gpio, struct sm501_devdata, gpio);
885}
886
887static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset)
888
889{
3a504105 890 struct sm501_gpio_chip *smgpio = gpiochip_get_data(chip);
f61be273
BD		 891 unsigned long result;
892
bf5f0019 893 result = smc501_readl(smgpio->regbase + SM501_GPIO_DATA_LOW);
f61be273
BD		 894 result >>= offset;
895
896 return result & 1UL;
897}
898
98325f8f
BD		 899static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip,
900 unsigned long bit)
901{
902 unsigned long ctrl;
903
904 /* check and modify if this pin is not set as gpio. */
905
bf5f0019 906 if (smc501_readl(smchip->control) & bit) {
98325f8f
BD		 907 dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev,
908 "changing mode of gpio, bit %08lx\n", bit);
909
bf5f0019 910 ctrl = smc501_readl(smchip->control);
98325f8f 911 ctrl &= ~bit;
bf5f0019 912 smc501_writel(ctrl, smchip->control);
98325f8f
BD		 913
914 sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio));
915 }
916}
917
f61be273
BD		 918static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
919
920{
3a504105 921 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
f61be273
BD		 922 struct sm501_gpio *smgpio = smchip->ourgpio;
923 unsigned long bit = 1 << offset;
924 void __iomem *regs = smchip->regbase;
925 unsigned long save;
926 unsigned long val;
927
928 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
929 __func__, chip, offset);
930
931 spin_lock_irqsave(&smgpio->lock, save);
932
bf5f0019 933 val = smc501_readl(regs + SM501_GPIO_DATA_LOW) & ~bit;
f61be273
BD		 934 if (value)
935 val |= bit;
bf5f0019 936 smc501_writel(val, regs);
f61be273
BD		 937
938 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
98325f8f
BD		 939 sm501_gpio_ensure_gpio(smchip, bit);
940
f61be273
BD		 941 spin_unlock_irqrestore(&smgpio->lock, save);
942}
943
944static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset)
945{
3a504105 946 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
f61be273
BD		 947 struct sm501_gpio *smgpio = smchip->ourgpio;
948 void __iomem *regs = smchip->regbase;
949 unsigned long bit = 1 << offset;
950 unsigned long save;
951 unsigned long ddr;
952
98325f8f
BD		 953 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
954 __func__, chip, offset);
f61be273
BD		 955
956 spin_lock_irqsave(&smgpio->lock, save);
957
bf5f0019
HS		 958 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
959 smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW);
f61be273
BD		 960
961 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
98325f8f
BD		 962 sm501_gpio_ensure_gpio(smchip, bit);
963
f61be273
BD		 964 spin_unlock_irqrestore(&smgpio->lock, save);
965
966 return 0;
967}
968
969static int sm501_gpio_output(struct gpio_chip *chip,
970 unsigned offset, int value)
971{
3a504105 972 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
f61be273
BD		 973 struct sm501_gpio *smgpio = smchip->ourgpio;
974 unsigned long bit = 1 << offset;
975 void __iomem *regs = smchip->regbase;
976 unsigned long save;
977 unsigned long val;
978 unsigned long ddr;
979
980 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n",
981 __func__, chip, offset, value);
982
983 spin_lock_irqsave(&smgpio->lock, save);
984
bf5f0019 985 val = smc501_readl(regs + SM501_GPIO_DATA_LOW);
f61be273
BD		 986 if (value)
987 val |= bit;
988 else
989 val &= ~bit;
bf5f0019 990 smc501_writel(val, regs);
f61be273 991
bf5f0019
HS		 992 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
993 smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW);
f61be273
BD		 994
995 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
bf5f0019 996 smc501_writel(val, regs + SM501_GPIO_DATA_LOW);
f61be273
BD		 997
998 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
999 spin_unlock_irqrestore(&smgpio->lock, save);
1000
1001 return 0;
1002}
1003
7e94e515 1004static const struct gpio_chip gpio_chip_template = {
f61be273
BD		 1005 .ngpio = 32,
1006 .direction_input = sm501_gpio_input,
1007 .direction_output = sm501_gpio_output,
1008 .set = sm501_gpio_set,
1009 .get = sm501_gpio_get,
1010};
1011
f791be49 1012static int sm501_gpio_register_chip(struct sm501_devdata *sm,
f61be273
BD		 1013 struct sm501_gpio *gpio,
1014 struct sm501_gpio_chip *chip)
1015{
1016 struct sm501_platdata *pdata = sm->platdata;
1017 struct gpio_chip *gchip = &chip->gpio;
60e540d6 1018 int base = pdata->gpio_base;
f61be273 1019
28130bea 1020 chip->gpio = gpio_chip_template;
f61be273
BD		 1021
1022 if (chip == &gpio->high) {
60e540d6
AP		 1023 if (base > 0)
1024 base += 32;
f61be273 1025 chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;
98325f8f 1026 chip->control = sm->regs + SM501_GPIO63_32_CONTROL;
f61be273
BD		 1027 gchip->label = "SM501-HIGH";
1028 } else {
1029 chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;
98325f8f 1030 chip->control = sm->regs + SM501_GPIO31_0_CONTROL;
f61be273
BD		 1031 gchip->label = "SM501-LOW";
1032 }
1033
1034 gchip->base = base;
1035 chip->ourgpio = gpio;
1036
3a504105 1037 return gpiochip_add_data(gchip, chip);
f61be273
BD		 1038}
1039
f791be49 1040static int sm501_register_gpio(struct sm501_devdata *sm)
f61be273
BD		 1041{
1042 struct sm501_gpio *gpio = &sm->gpio;
1043 resource_size_t iobase = sm->io_res->start + SM501_GPIO;
1044 int ret;
f61be273
BD		 1045
1046 dev_dbg(sm->dev, "registering gpio block %08llx\n",
1047 (unsigned long long)iobase);
1048
1049 spin_lock_init(&gpio->lock);
1050
1051 gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio");
1052 if (gpio->regs_res == NULL) {
1053 dev_err(sm->dev, "gpio: failed to request region\n");
1054 return -ENXIO;
1055 }
1056
1057 gpio->regs = ioremap(iobase, 0x20);
1058 if (gpio->regs == NULL) {
1059 dev_err(sm->dev, "gpio: failed to remap registers\n");
1060 ret = -ENXIO;
28130bea 1061 goto err_claimed;
f61be273
BD		 1062 }
1063
1064 /* Register both our chips. */
1065
1066 ret = sm501_gpio_register_chip(sm, gpio, &gpio->low);
1067 if (ret) {
1068 dev_err(sm->dev, "failed to add low chip\n");
1069 goto err_mapped;
1070 }
1071
1072 ret = sm501_gpio_register_chip(sm, gpio, &gpio->high);
1073 if (ret) {
1074 dev_err(sm->dev, "failed to add high chip\n");
1075 goto err_low_chip;
1076 }
1077
1078 gpio->registered = 1;
1079
1080 return 0;
1081
1082 err_low_chip:
88d5e520 1083 gpiochip_remove(&gpio->low.gpio);
f61be273
BD		 1084
1085 err_mapped:
28130bea
BD		 1086 iounmap(gpio->regs);
1087
1088 err_claimed:
f61be273
BD		 1089 release_resource(gpio->regs_res);
1090 kfree(gpio->regs_res);
1091
1092 return ret;
1093}
1094
1095static void sm501_gpio_remove(struct sm501_devdata *sm)
1096{
28130bea 1097 struct sm501_gpio *gpio = &sm->gpio;
f61be273 1098
f2999209
BD		 1099 if (!sm->gpio.registered)
1100 return;
1101
88d5e520 1102 gpiochip_remove(&gpio->low.gpio);
1103 gpiochip_remove(&gpio->high.gpio);
28130bea
BD		 1104
1105 iounmap(gpio->regs);
1106 release_resource(gpio->regs_res);
1107 kfree(gpio->regs_res);
f61be273
BD		 1108}
1109
28130bea 1110static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
42cd2366
BD		 1111{
1112 struct sm501_gpio *gpio = &sm->gpio;
53a9600c
BD		 1113 int base = (pin < 32) ? gpio->low.gpio.base : gpio->high.gpio.base;
1114
1115 return (pin % 32) + base;
42cd2366 1116}
f2999209
BD		 1117
1118static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1119{
1120 return sm->gpio.registered;
1121}
f61be273 1122#else
28130bea 1123static inline int sm501_register_gpio(struct sm501_devdata *sm)
f61be273
BD		 1124{
1125 return 0;
1126}
1127
28130bea 1128static inline void sm501_gpio_remove(struct sm501_devdata *sm)
f61be273
BD		 1129{
1130}
42cd2366 1131
28130bea 1132static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
42cd2366
BD		 1133{
1134 return -1;
1135}
f2999209
BD		 1136
1137static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1138{
1139 return 0;
1140}
f61be273
BD		 1141#endif
1142
42cd2366
BD		 1143static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
1144 struct sm501_platdata_gpio_i2c *iic)
1145{
1146 struct i2c_gpio_platform_data *icd;
1147 struct platform_device *pdev;
1148
1149 pdev = sm501_create_subdev(sm, "i2c-gpio", 0,
1150 sizeof(struct i2c_gpio_platform_data));
1151 if (!pdev)
1152 return -ENOMEM;
1153
334a41ce 1154 icd = dev_get_platdata(&pdev->dev);
42cd2366
BD		 1155
1156 /* We keep the pin_sda and pin_scl fields relative in case the
1157 * same platform data is passed to >1 SM501.
1158 */
1159
1160 icd->sda_pin = sm501_gpio_pin2nr(sm, iic->pin_sda);
1161 icd->scl_pin = sm501_gpio_pin2nr(sm, iic->pin_scl);
1162 icd->timeout = iic->timeout;
1163 icd->udelay = iic->udelay;
1164
1165 /* note, we can't use either of the pin numbers, as the i2c-gpio
1166 * driver uses the platform.id field to generate the bus number
1167 * to register with the i2c core; The i2c core doesn't have enough
1168 * entries to deal with anything we currently use.
1169 */
1170
1171 pdev->id = iic->bus_num;
1172
1173 dev_info(sm->dev, "registering i2c-%d: sda=%d (%d), scl=%d (%d)\n",
1174 iic->bus_num,
1175 icd->sda_pin, iic->pin_sda, icd->scl_pin, iic->pin_scl);
1176
1177 return sm501_register_device(sm, pdev);
1178}
1179
1180static int sm501_register_gpio_i2c(struct sm501_devdata *sm,
1181 struct sm501_platdata *pdata)
1182{
1183 struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c;
1184 int index;
1185 int ret;
1186
1187 for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) {
1188 ret = sm501_register_gpio_i2c_instance(sm, iic);
1189 if (ret < 0)
1190 return ret;
1191 }
1192
1193 return 0;
1194}
1195
b6d6454f
BD		 1196/* sm501_dbg_regs
1197 *
1198 * Debug attribute to attach to parent device to show core registers
1199*/
1200
1201static ssize_t sm501_dbg_regs(struct device *dev,
1202 struct device_attribute *attr, char *buff)
1203{
1204 struct sm501_devdata *sm = dev_get_drvdata(dev) ;
1205 unsigned int reg;
1206 char *ptr = buff;
1207 int ret;
1208
1209 for (reg = 0x00; reg < 0x70; reg += 4) {
1210 ret = sprintf(ptr, "%08x = %08x\n",
bf5f0019 1211 reg, smc501_readl(sm->regs + reg));
b6d6454f
BD		 1212 ptr += ret;
1213 }
1214
1215 return ptr - buff;
1216}
1217
1218
8a8320c2 1219static DEVICE_ATTR(dbg_regs, 0444, sm501_dbg_regs, NULL);
b6d6454f
BD		 1220
1221/* sm501_init_reg
1222 *
1223 * Helper function for the init code to setup a register
5136237b
BD		 1224 *
1225 * clear the bits which are set in r->mask, and then set
1226 * the bits set in r->set.
b6d6454f
BD		 1227*/
1228
1229static inline void sm501_init_reg(struct sm501_devdata *sm,
1230 unsigned long reg,
1231 struct sm501_reg_init *r)
1232{
1233 unsigned long tmp;
1234
bf5f0019 1235 tmp = smc501_readl(sm->regs + reg);
b6d6454f 1236 tmp &= ~r->mask;
5136237b 1237 tmp |= r->set;
bf5f0019 1238 smc501_writel(tmp, sm->regs + reg);
b6d6454f
BD		 1239}
1240
1241/* sm501_init_regs
1242 *
1243 * Setup core register values
1244*/
1245
1246static void sm501_init_regs(struct sm501_devdata *sm,
1247 struct sm501_initdata *init)
1248{
1249 sm501_misc_control(sm->dev,
1250 init->misc_control.set,
1251 init->misc_control.mask);
1252
1253 sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
1254 sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
1255 sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
1256
b6d6454f
BD		 1257 if (init->m1xclk) {
1258 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
1259 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
1260 }
b5913bbd
BD		 1261
1262 if (init->mclk) {
1263 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
1264 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
1265 }
81906221
BD		 1266
1267}
1268
1269/* Check the PLL sources for the M1CLK and M1XCLK
1270 *
1271 * If the M1CLK and M1XCLKs are not sourced from the same PLL, then
1272 * there is a risk (see errata AB-5) that the SM501 will cease proper
1273 * function. If this happens, then it is likely the SM501 will
1274 * hang the system.
1275*/
1276
1277static int sm501_check_clocks(struct sm501_devdata *sm)
1278{
bf5f0019 1279 unsigned long pwrmode = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
81906221
BD		 1280 unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);
1281 unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);
1282
1283 return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));
b6d6454f
BD		 1284}
1285
1286static unsigned int sm501_mem_local[] = {
1287 [0] = 4*1024*1024,
1288 [1] = 8*1024*1024,
1289 [2] = 16*1024*1024,
1290 [3] = 32*1024*1024,
1291 [4] = 64*1024*1024,
1292 [5] = 2*1024*1024,
1293};
1294
1295/* sm501_init_dev
1296 *
1297 * Common init code for an SM501
1298*/
1299
f791be49 1300static int sm501_init_dev(struct sm501_devdata *sm)
b6d6454f 1301{
61711f8f 1302 struct sm501_initdata *idata;
42cd2366 1303 struct sm501_platdata *pdata;
b6d6454f
BD		 1304 resource_size_t mem_avail;
1305 unsigned long dramctrl;
1e27dbe7 1306 unsigned long devid;
b6d6454f
BD		 1307 int ret;
1308
1309 mutex_init(&sm->clock_lock);
1310 spin_lock_init(&sm->reg_lock);
1311
1312 INIT_LIST_HEAD(&sm->devices);
1313
bf5f0019 1314 devid = smc501_readl(sm->regs + SM501_DEVICEID);
b6d6454f 1315
1e27dbe7
BD		 1316 if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {
1317 dev_err(sm->dev, "incorrect device id %08lx\n", devid);
1318 return -EINVAL;
1319 }
1320
61711f8f 1321 /* disable irqs */
bf5f0019 1322 smc501_writel(0, sm->regs + SM501_IRQ_MASK);
61711f8f 1323
bf5f0019 1324 dramctrl = smc501_readl(sm->regs + SM501_DRAM_CONTROL);
b6d6454f
BD		 1325 mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
1326
1e27dbe7
BD		 1327 dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
1328 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
b6d6454f 1329
3149be50
VS		 1330 sm->rev = devid & SM501_DEVICEID_REVMASK;
1331
331d7475 1332 sm501_dump_gate(sm);
b6d6454f
BD		 1333
1334 ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
1335 if (ret)
1336 dev_err(sm->dev, "failed to create debug regs file\n");
1337
1338 sm501_dump_clk(sm);
1339
1340 /* check to see if we have some device initialisation */
1341
42cd2366
BD		 1342 pdata = sm->platdata;
1343 idata = pdata ? pdata->init : NULL;
1344
61711f8f
MD		 1345 if (idata) {
1346 sm501_init_regs(sm, idata);
b6d6454f 1347
61711f8f
MD		 1348 if (idata->devices & SM501_USE_USB_HOST)
1349 sm501_register_usbhost(sm, &mem_avail);
1350 if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1))
1351 sm501_register_uart(sm, idata->devices);
f61be273
BD		 1352 if (idata->devices & SM501_USE_GPIO)
1353 sm501_register_gpio(sm);
b6d6454f
BD		 1354 }
1355
4295f9bf 1356 if (pdata && pdata->gpio_i2c != NULL && pdata->gpio_i2c_nr > 0) {
f2999209
BD		 1357 if (!sm501_gpio_isregistered(sm))
1358 dev_err(sm->dev, "no gpio available for i2c gpio.\n");
42cd2366
BD		 1359 else
1360 sm501_register_gpio_i2c(sm, pdata);
1361 }
1362
81906221
BD		 1363 ret = sm501_check_clocks(sm);
1364 if (ret) {
1365 dev_err(sm->dev, "M1X and M clocks sourced from different "
1366 "PLLs\n");
1367 return -EINVAL;
1368 }
1369
b6d6454f
BD		 1370 /* always create a framebuffer */
1371 sm501_register_display(sm, &mem_avail);
1372
1373 return 0;
1374}
1375
f791be49 1376static int sm501_plat_probe(struct platform_device *dev)
b6d6454f
BD		 1377{
1378 struct sm501_devdata *sm;
7cf5244c 1379 int ret;
b6d6454f
BD		 1380
1381 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1382 if (sm == NULL) {
1383 dev_err(&dev->dev, "no memory for device data\n");
7cf5244c 1384 ret = -ENOMEM;
b6d6454f
BD		 1385 goto err1;
1386 }
1387
1388 sm->dev = &dev->dev;
1389 sm->pdev_id = dev->id;
334a41ce 1390 sm->platdata = dev_get_platdata(&dev->dev);
b6d6454f 1391
7cf5244c
RK		 1392 ret = platform_get_irq(dev, 0);
1393 if (ret < 0) {
b6d6454f 1394 dev_err(&dev->dev, "failed to get irq resource\n");
b6d6454f
BD		 1395 goto err_res;
1396 }
7cf5244c 1397 sm->irq = ret;
b6d6454f 1398
7cf5244c
RK		 1399 sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
1400 sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
4295f9bf 1401
b6d6454f
BD		 1402 if (sm->io_res == NULL || sm->mem_res == NULL) {
1403 dev_err(&dev->dev, "failed to get IO resource\n");
7cf5244c 1404 ret = -ENOENT;
b6d6454f
BD		 1405 goto err_res;
1406 }
1407
1408 sm->regs_claim = request_mem_region(sm->io_res->start,
a5300dcb 1409 0x100, "sm501");
b6d6454f
BD		 1410
1411 if (sm->regs_claim == NULL) {
1412 dev_err(&dev->dev, "cannot claim registers\n");
7cf5244c 1413 ret = -EBUSY;
b6d6454f
BD		 1414 goto err_res;
1415 }
1416
1417 platform_set_drvdata(dev, sm);
1418
311e54c0 1419 sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res));
b6d6454f
BD		 1420
1421 if (sm->regs == NULL) {
1422 dev_err(&dev->dev, "cannot remap registers\n");
7cf5244c 1423 ret = -EIO;
b6d6454f
BD		 1424 goto err_claim;
1425 }
1426
1427 return sm501_init_dev(sm);
1428
1429 err_claim:
1430 release_resource(sm->regs_claim);
1431 kfree(sm->regs_claim);
1432 err_res:
1433 kfree(sm);
1434 err1:
7cf5244c 1435 return ret;
b6d6454f
BD		 1436
1437}
1438
331d7475 1439#ifdef CONFIG_PM
472dba7d 1440
331d7475
BD		 1441/* power management support */
1442
472dba7d
BD		 1443static void sm501_set_power(struct sm501_devdata *sm, int on)
1444{
1445 struct sm501_platdata *pd = sm->platdata;
1446
1447 if (pd == NULL)
1448 return;
1449
1450 if (pd->get_power) {
1451 if (pd->get_power(sm->dev) == on) {
1452 dev_dbg(sm->dev, "is already %d\n", on);
1453 return;
1454 }
1455 }
1456
1457 if (pd->set_power) {
1458 dev_dbg(sm->dev, "setting power to %d\n", on);
1459
1460 pd->set_power(sm->dev, on);
1461 sm501_mdelay(sm, 10);
1462 }
1463}
1464
331d7475
BD		 1465static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)
1466{
1467 struct sm501_devdata *sm = platform_get_drvdata(pdev);
1468
1469 sm->in_suspend = 1;
bf5f0019 1470 sm->pm_misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
331d7475
BD		 1471
1472 sm501_dump_regs(sm);
472dba7d
BD		 1473
1474 if (sm->platdata) {
1475 if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF)
1476 sm501_set_power(sm, 0);
1477 }
1478
331d7475
BD		 1479 return 0;
1480}
1481
1482static int sm501_plat_resume(struct platform_device *pdev)
1483{
1484 struct sm501_devdata *sm = platform_get_drvdata(pdev);
1485
472dba7d
BD		 1486 sm501_set_power(sm, 1);
1487
331d7475
BD		 1488 sm501_dump_regs(sm);
1489 sm501_dump_gate(sm);
1490 sm501_dump_clk(sm);
1491
1492 /* check to see if we are in the same state as when suspended */
1493
bf5f0019 1494 if (smc501_readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {
331d7475 1495 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");
bf5f0019 1496 smc501_writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);
331d7475
BD		 1497
1498 /* our suspend causes the controller state to change,
1499 * either by something attempting setup, power loss,
1500 * or an external reset event on power change */
1501
1502 if (sm->platdata && sm->platdata->init) {
1503 sm501_init_regs(sm, sm->platdata->init);
1504 }
1505 }
1506
1507 /* dump our state from resume */
1508
1509 sm501_dump_regs(sm);
1510 sm501_dump_clk(sm);
1511
1512 sm->in_suspend = 0;
1513
1514 return 0;
1515}
1516#else
1517#define sm501_plat_suspend NULL
1518#define sm501_plat_resume NULL
1519#endif
1520
b6d6454f
BD		 1521/* Initialisation data for PCI devices */
1522
1523static struct sm501_initdata sm501_pci_initdata = {
1524 .gpio_high = {
1525 .set = 0x3F000000, /* 24bit panel */
1526 .mask = 0x0,
1527 },
1528 .misc_timing = {
1529 .set = 0x010100, /* SDRAM timing */
1530 .mask = 0x1F1F00,
1531 },
1532 .misc_control = {
1533 .set = SM501_MISC_PNL_24BIT,
1534 .mask = 0,
1535 },
1536
1537 .devices = SM501_USE_ALL,
81906221
BD		 1538
1539 /* Errata AB-3 says that 72MHz is the fastest available
1540 * for 33MHZ PCI with proper bus-mastering operation */
1541
1542 .mclk = 72 * MHZ,
1543 .m1xclk = 144 * MHZ,
b6d6454f
BD		 1544};
1545
1546static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
1547 .flags = (SM501FB_FLAG_USE_INIT_MODE |
1548 SM501FB_FLAG_USE_HWCURSOR |
1549 SM501FB_FLAG_USE_HWACCEL |
1550 SM501FB_FLAG_DISABLE_AT_EXIT),
1551};
1552
1553static struct sm501_platdata_fb sm501_fb_pdata = {
1554 .fb_route = SM501_FB_OWN,
1555 .fb_crt = &sm501_pdata_fbsub,
1556 .fb_pnl = &sm501_pdata_fbsub,
1557};
1558
1559static struct sm501_platdata sm501_pci_platdata = {
1560 .init = &sm501_pci_initdata,
1561 .fb = &sm501_fb_pdata,
60e540d6 1562 .gpio_base = -1,
b6d6454f
BD		 1563};
1564
f791be49 1565static int sm501_pci_probe(struct pci_dev *dev,
158abca5 1566 const struct pci_device_id *id)
b6d6454f
BD		 1567{
1568 struct sm501_devdata *sm;
1569 int err;
1570
1571 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1572 if (sm == NULL) {
1573 dev_err(&dev->dev, "no memory for device data\n");
1574 err = -ENOMEM;
1575 goto err1;
1576 }
1577
1578 /* set a default set of platform data */
1579 dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
1580
1581 /* set a hopefully unique id for our child platform devices */
1582 sm->pdev_id = 32 + dev->devfn;
1583
1584 pci_set_drvdata(dev, sm);
1585
1586 err = pci_enable_device(dev);
1587 if (err) {
1588 dev_err(&dev->dev, "cannot enable device\n");
1589 goto err2;
1590 }
1591
1592 sm->dev = &dev->dev;
1593 sm->irq = dev->irq;
1594
1595#ifdef __BIG_ENDIAN
1596 /* if the system is big-endian, we most probably have a
1597 * translation in the IO layer making the PCI bus little endian
1598 * so make the framebuffer swapped pixels */
1599
1600 sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
1601#endif
1602
1603 /* check our resources */
1604
1605 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
1606 dev_err(&dev->dev, "region #0 is not memory?\n");
1607 err = -EINVAL;
1608 goto err3;
1609 }
1610
1611 if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
1612 dev_err(&dev->dev, "region #1 is not memory?\n");
1613 err = -EINVAL;
1614 goto err3;
1615 }
1616
1617 /* make our resources ready for sharing */
1618
1619 sm->io_res = &dev->resource[1];
1620 sm->mem_res = &dev->resource[0];
1621
1622 sm->regs_claim = request_mem_region(sm->io_res->start,
a5300dcb 1623 0x100, "sm501");
b6d6454f
BD		 1624 if (sm->regs_claim == NULL) {
1625 dev_err(&dev->dev, "cannot claim registers\n");
1626 err= -EBUSY;
1627 goto err3;
1628 }
1629
7ab18995 1630 sm->regs = pci_ioremap_bar(dev, 1);
b6d6454f
BD		 1631
1632 if (sm->regs == NULL) {
1633 dev_err(&dev->dev, "cannot remap registers\n");
1634 err = -EIO;
1635 goto err4;
1636 }
1637
1638 sm501_init_dev(sm);
1639 return 0;
1640
1641 err4:
1642 release_resource(sm->regs_claim);
1643 kfree(sm->regs_claim);
1644 err3:
1645 pci_disable_device(dev);
1646 err2:
b6d6454f
BD		 1647 kfree(sm);
1648 err1:
1649 return err;
1650}
1651
1652static void sm501_remove_sub(struct sm501_devdata *sm,
1653 struct sm501_device *smdev)
1654{
1655 list_del(&smdev->list);
1656 platform_device_unregister(&smdev->pdev);
1657}
1658
1659static void sm501_dev_remove(struct sm501_devdata *sm)
1660{
1661 struct sm501_device *smdev, *tmp;
1662
1663 list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
1664 sm501_remove_sub(sm, smdev);
1665
1666 device_remove_file(sm->dev, &dev_attr_dbg_regs);
f61be273 1667
f2999209 1668 sm501_gpio_remove(sm);
b6d6454f
BD		 1669}
1670
4740f73f 1671static void sm501_pci_remove(struct pci_dev *dev)
b6d6454f
BD		 1672{
1673 struct sm501_devdata *sm = pci_get_drvdata(dev);
1674
1675 sm501_dev_remove(sm);
1676 iounmap(sm->regs);
1677
1678 release_resource(sm->regs_claim);
1679 kfree(sm->regs_claim);
1680
b6d6454f
BD		 1681 pci_disable_device(dev);
1682}
1683
1684static int sm501_plat_remove(struct platform_device *dev)
1685{
1686 struct sm501_devdata *sm = platform_get_drvdata(dev);
1687
1688 sm501_dev_remove(sm);
1689 iounmap(sm->regs);
1690
1691 release_resource(sm->regs_claim);
1692 kfree(sm->regs_claim);
1693
1694 return 0;
1695}
1696
36fcd06c 1697static const struct pci_device_id sm501_pci_tbl[] = {
b6d6454f
BD		 1698 { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1699 { 0, },
1700};
1701
1702MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
1703
158abca5 1704static struct pci_driver sm501_pci_driver = {
b6d6454f
BD		 1705 .name = "sm501",
1706 .id_table = sm501_pci_tbl,
1707 .probe = sm501_pci_probe,
84449216 1708 .remove = sm501_pci_remove,
b6d6454f
BD		 1709};
1710
4f46d6e7
KS		 1711MODULE_ALIAS("platform:sm501");
1712
ae6eee3c 1713static const struct of_device_id of_sm501_match_tbl[] = {
4295f9bf
HS		 1714 { .compatible = "smi,sm501", },
1715 { /* end */ }
1716};
327cc18e 1717MODULE_DEVICE_TABLE(of, of_sm501_match_tbl);
4295f9bf 1718
158abca5 1719static struct platform_driver sm501_plat_driver = {
b6d6454f
BD		 1720 .driver = {
1721 .name = "sm501",
4295f9bf 1722 .of_match_table = of_sm501_match_tbl,
b6d6454f
BD		 1723 },
1724 .probe = sm501_plat_probe,
1725 .remove = sm501_plat_remove,
331d7475
BD		 1726 .suspend = sm501_plat_suspend,
1727 .resume = sm501_plat_resume,
b6d6454f
BD		 1728};
1729
1730static int __init sm501_base_init(void)
1731{
158abca5
AD		 1732 platform_driver_register(&sm501_plat_driver);
1733 return pci_register_driver(&sm501_pci_driver);
b6d6454f
BD		 1734}
1735
1736static void __exit sm501_base_exit(void)
1737{
158abca5
AD		 1738 platform_driver_unregister(&sm501_plat_driver);
1739 pci_unregister_driver(&sm501_pci_driver);
b6d6454f
BD		 1740}
1741
1742module_init(sm501_base_init);
1743module_exit(sm501_base_exit);
1744
1745MODULE_DESCRIPTION("SM501 Core Driver");
1746MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
1747MODULE_LICENSE("GPL v2");
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